TPS51716RUKT - Texas Instruments

V5IN

TPS51716

VREF

VBST

DRVH

DRVL

REFIN

PGND

GND

MODE

18 TRIP

PGOOD

VDDQSNS

VLDOIN

VTT

VTTSNS

VTTGND

VTTREF

UDG-12146

VDDQ

VTT

PGND

5VIN

PGND

VIN

VTTREF

AGNDAGND

Powergood

PGND

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

Reference

Design

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS51716

SLUSB94A –OCTOBER 2012–REVISED SEPTEMBER 2016

TPS51716 Complete DDR2, DDR3, DDR3L, LPDDR3, and DDR4 Memory Power Solution

Synchronous Buck Controller, 2-A LDO, With Buffered Reference

1 Features

1• Synchronous Buck Controller (VDDQ)

– Conversion Voltage Range: 3 to 28 V

– Output Voltage Range: 0.7 to 1.8 V

– 0.8% VREF Accuracy

– D-CAP2™ Mode for Ceramic Output

Capacitors

– Selectable 500-kHz/670-kHz Switching

Frequencies

– Optimized Efficiency at Light and Heavy Loads

With Auto-Skip Function

– Supports Soft-Off in S4/S5 States

– OCL/OVP/UVP/UVLO Protections

– Powergood Output

• 2-A LDO (VTT), Buffered Reference (VTTREF)

– 2-A (Peak) Sink and Source Current

– Requires Only 10-μF of Ceramic Output

Capacitance

– Buffered, Low Noise, 10-mA VTTREF Output

– 0.8% VTTREF, 20-mV VTT Accuracy

– Support High-Z in S3 and Soft-Off in S4/S5

• Thermal Shutdown

• 20-Pin, 3 mm × 3 mm, WQFN Package

2 Applications

• DDR2, DDR3, DDR3L, LPDDR3, and DDR4

Memory Power Supplies

• SSTL_18, SSTL_15, SSTL_135, and HSTL

Termination

3 Description

The TPS51716 provides a complete power supply for

DDR2, DDR3, DDR3L, LPDDR3, and DDR4 memory

systems in the lowest total cost and minimum space.

It integrates a synchronous buck regulator controller

(VDDQ) with a 2-A sink/source tracking LDO (VTT)

and buffered low noise reference (VTTREF). The

TPS51716 employs D-CAP2 mode coupled with

500 kHz or 670 kHz operating frequencies that

supports ceramic output capacitors without an

external compensation circuit. The VTTREF tracks

VDDQ/2 with excellent 0.8% accuracy. The VTT,

which provides 2-A sink/source peak current

capabilities, requires only 10 μF of ceramic

capacitance. In addition, the device features a

dedicated LDO supply input.

The TPS51716 provides rich, useful functions as well

as excellent power supply performance. It supports

flexible power state control, placing VTT at high-Z in

S3 and discharging VDDQ, VTT and VTTREF (soft-

off) in S4/S5 state. It includes programmable OCL

with low-side MOSFET RDS(on) sensing,

OVP/UVP/UVLO and thermal shutdown protections.

TI offers the TPS51716 in a 20-pin, 3 mm × 3 mm,

WQFN package and specifies it for an ambient

temperature range between –40°C and 85°C.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

TPS51716 WQFN (20) 3.00 mm × 3.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Block Diagram

TPS51716

SLUSB94A –OCTOBER 2012–REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: TPS51716

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 6

6.6 Typical Characteristics.............................................. 8

7 Detailed Description............................................ 12

7.1 Overview................................................................. 12

7.2 Functional Block Diagram....................................... 12

7.3 Feature Description................................................. 13

7.4 Device Functional Modes........................................ 16

8 Application and Implementation ........................ 18

8.1 Application Information............................................ 18

8.2 Typical Application ................................................. 18

9 Power Supply Recommendations...................... 22

10 Layout................................................................... 23

10.1 Layout Guidelines ................................................. 23

10.2 Layout Example .................................................... 24

11 Device and Documentation Support................. 25

11.1 Device Support...................................................... 25

11.2 Documentation Support ........................................ 25

11.3 Trademarks........................................................... 25

11.4 Electrostatic Discharge Caution............................ 25

11.5 Glossary................................................................ 25

12 Mechanical, Packaging, and Orderable

Information........................................................... 25

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (October 2012) to Revision A Page

• Added ESD Ratings table, Detailed Description section, Application and Implementation section, Power Supply

Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,

Packaging, and Orderable Information section ...................................................................................................................... 1

• Updated the Title From: Complete DDR2, DDR3, DDR3L, and LPDDR3 Memory Power Solution To: Complete

DDR2, DDR3, DDR3L, LPDDR3, and DDR4 Memory Power ............................................................................................... 1

• Changed Applications list From: DDR2/DDR3/DDR3L/LPDDR3 Memory Power Supplies To: DDR2, DDR3, DDR3L,

LPDDR3, and DDR4 Memory Power Supplies ...................................................................................................................... 1

Thermal

Pad

PGOOD

VREF

VTTSNS 15 VBST

MODE

GND

VLDOIN 14 DRVH

TRIP

REFIN

VTT 13 SW

VDDQSNS

VTTGND 12 V5IN

PGND

VTTREF 11 DRVL

TPS51716

www.ti.com

SLUSB94A –OCTOBER 2012–REVISED SEPTEMBER 2016

Product Folder Links: TPS51716

5 Pin Configuration and Functions

RUK Package

20-Pin WQFN

Top View

Pin Functions

PIN I/O DESCRIPTION

NAME NO.

DRVH 14 O High-side MOSFET gate driver output.

DRVL 11 O Low-side MOSFET gate driver output.

GND 7 — Signal ground.

MODE 19 I Connect resistor to GND to configure switching frequency, control mode and discharge mode. (See Table 2)

PGND 10 — Gate driver power ground. RDS(on) current sensing input(+).

PGOOD 20 O Powergood signal open drain output. PGOOD goes high when VDDQ output voltage is within the target range.

REFIN 8 I Reference input for VDDQ. Connect to the midpoint of a resistor divider from VREF to GND. Add a capacitor for

stable operation.

SW 13 I/O High-side MOSFET gate driver return. RDS(on) current sensing input(–).

S3 17 I S3 signal input. (See Table 1)

S5 16 I S5 signal input. (See Table 1)

TRIP 18 I Connect resistor to GND to set OCL at VTRIP/8. Output 10-μA current at room temperature, TC= 4700 ppm/°C.

VBST 15 I High-side MOSFET gate driver bootstrap voltage input. Connect a capacitor from the VBST pin to the SW pin.

VDDQSNS 9 I VDDQ output voltage feedback. Reference input for VTTREF. Also serves as power supply for VTTREF.

VLDOIN 2 I Power supply input for VTT LDO. Connect VDDQ in typical application.

VREF 6 O 1.8-V reference output

VTT 3 O VTT 2-A LDO output. Need to connect 10 μF or larger capacitance for stability.

VTTGND 4 — Power ground for VTT LDO

VTTREF 5 O Buffered VTT reference output. Need to connect 0.22 μF or larger capacitance for stability.

VTTSNS 1 I VTT output voltage feedback.

V5IN 12 I 5-V power supply input for internal circuits and MOSFET gate drivers.

Thermal

pad — — Thermal pad. Connect directly to system GND plane with multiple vias.

TPS51716

SLUSB94A –OCTOBER 2012–REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: TPS51716

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to the network ground terminal unless otherwise noted.

(3) Voltage values are with respect to the SW terminal.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

Input voltage(2)

VBST –0.3 36

VBST(3) –0.3 6

SW –5 30

VLDOIN, VDDQSNS, REFIN –0.3 3.6

VTTSNS –0.3 3.6

PGND, VTTGND –0.3 0.3

V5IN, S3, S5, TRIP, MODE –0.3 6

Output voltage(2)

DRVH –5 36

DRVH(3) –0.3 6

VTTREF, VREF –0.3 3.6

VTT –0.3 3.6

DRVL –0.3 6

PGOOD –0.3 6

Junction temperature, TJ125 °C

Storage temperature, Tstg –55 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic

discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V

Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500

TPS51716

www.ti.com

SLUSB94A –OCTOBER 2012–REVISED SEPTEMBER 2016

Product Folder Links: TPS51716

(1) Voltage values are with respect to the SW terminal.

(2) This voltage should be applied for less than 30% of the repetitive period.

6.3 Recommended Operating Conditions MIN NOM MAX UNIT

Supply voltage V5IN 4.5 5.5 V

Input voltage range

VBST –0.1 33.5

VBST(1) –0.1 5.5

SW –3 28

SW(2) –4.5 28

VLDOIN, VDDQSNS, REFIN –0.1 3.5

VTTSNS –0.1 3.5

PGND, VTTGND –0.1 0.1

S3, S5, TRIP, MODE –0.1 5.5

Output voltage range

DRVH –3 33.5

DRVH(1) –0.1 5.5

DRVH(2) –4.5 33.5

VTTREF, VREF –0.1 3.5

VTT –0.1 3.5

DRVL –0.1 5.5

PGOOD –0.1 5.5

TAOperating free-air temperature –40 85 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.4 Thermal Information

THERMAL METRIC(1) TPS51716

UNITRUK (WQFN)

20 PINS

RθJA Junction-to-ambient thermal resistance 94.1 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 58.1 °C/W

RθJB Junction-to-board thermal resistance 64.3 °C/W

ψJT Junction-to-top characterization parameter 31.8 °C/W

ψJB Junction-to-board characterization parameter 58.0 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance 5.9 °C/W

TPS51716

SLUSB94A –OCTOBER 2012–REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: TPS51716

(1) Specified by design. Not production tested.

6.5 Electrical Characteristics

over operating free-air temperature range, VV5IN = 5 V, VLDOIN is connected to VDDQ output, VMODE= 0 V, VS3= VS5= 5 V

(unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY CURRENT

IV5IN(S0) V5IN supply current, in S0 TA= 25°C, No load, VS3 = VS5 = 5 V 590 μA

IV5IN(S3) V5IN supply current, in S3 TA= 25°C, No load, VS3 = 0 V, VS5 = 5 V 500 μA

IV5INSDN V5IN shutdown current TA= 25°C, No load, VS3 = VS5 = 0 V 1 μA

IVLDOIN(S0) VLDOIN supply current, in S0 TA= 25°C, No load, VS3 = VS5 = 5 V 5 μA

IVLDOIN(S3) VLDOIN supply current, in S3 TA= 25°C, No load, VS3 = 0 V, VS5 = 5 V 5 μA

IVLDOINSDN VLDOIN shutdown current TA= 25°C, No load, VS3 = VS5 = 0 V 5 μA

VREF OUTPUT

VVREF Output voltage

IVREF = 30 μA, TA= 25°C 1.8000

V0 μA≤IVREF <300 μA, TA= –10°C to 85°C 1.7856 1.8144

0μA≤IVREF <300 μA, TA= –40°C to 85°C 1.7820 1.8180

IVREFOCL Current limit VVREF = 1.7 V 0.4 0.8 mA

VTTREF OUTPUT

VVTTREF Output voltage VVDDQSNS / 2 V

VVTTREF Output voltage tolerance to VVDDQ |IVTTREF| <100 μA, 1.2 V ≤VVDDQSNS ≤1.8 V 49.2% 50.8%

|IVTTREF| <10 mA, 1.2 V ≤VVDDQSNS ≤1.8 V 49% 51%

IVTTREFOCLSRC Source current limit VVDDQSNS = 1.8 V, VVTTREF= 0 V 10 18 mA

IVTTREFOCLSNK Sink current limit VVDDQSNS = 1.8 V, VVTTREF = 1.8 V 10 17 mA

IVTTREFDIS VTTREF discharge current TA= 25°C, VS3 = VS5 = 0 V, VVTTREF = 0.5 V 0.8 1.3 mA

VTT OUTPUT

VVTT Output voltage VVTTREF V

VVTTTOL Output voltage tolerance to VTTREF

|IVTT|≤10 mA, 1.2 V ≤VVDDQSNS ≤1.8 V,

IVTTREF= 0 A –20 20

|IVTT|≤1 A, 1.2 ≤VVDDQSNS ≤1.8 V,

IVTTREF= 0 A –30 30

|IVTT|≤2 A, 1.4 V ≤VVDDQSNS ≤1.8 V,

IVTTREF= 0 A –40 40

|IVTT|≤1.5 A, 1.2 V ≤VVDDQSNS ≤1.4 V,

IVTTREF= 0 A –40 40

IVTTOCLSRC Source current limit VVDDQSNS = 1.8 V, VVTT = VVTTSNS = 0.7 V,

IVTTREF= 0 A 2 3 A

IVTTOCLSNK Sink current limit VVDDQSNS = 1.8V, VVTT = VVTTSNS = 1.1 V,

IVTTREF= 0 A 2 3 A

IVTTLK Leakage current TA= 25°C , VS3 = 0 V, VS5 = 5 V, VVTT = VVTTREF 5μA

IVTTSNSBIAS VTTSNS input bias current VS3 = 5 V, VS5 = 5 V, VVTTSNS = VVTTREF –0.5 0.0 0.5 μA

IVTTSNSLK VTTSNS leakage current VS3 = 0 V, VS5 = 5 V, VVTTSNS = VVTTREF –1 0 1 μA

IVTTDIS VTT Discharge current TA= 25°C, VS3 = VS5 = 0 V, VVDDQSNS = 1.8 V,

VVTT = 0.5 V, IVTTREF= 0 A 7.8 mA

VDDQ OUTPUT

VVDDQSNS VDDQ sense voltage VREFIN

IVDDQSNS VDDQSNS input current VVDDQSNS = 1.8 V 39 μA

IREFIN REFIN input current VREFIN = 1.8 V –0.1 0.0 0.1 μA

IVDDQDIS VDDQ discharge current VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V, non-tracking discharge

mode 12 mA

IVLDOINDIS VLDOIN discharge current VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V, tracking discharge mode 1.2 A

SWITCH MODE POWER SUPPLY (SMPS) FREQUENCY

fSW VDDQ switching frequency VIN = 12 V, VVDDQSNS = 1.8 V, RMODE = 1 kΩ500 kHz

VIN = 12 V, VVDDQSNS = 1.8 V, RMODE = 12 kΩ670

tON(min) Minimum on time DRVH rising to falling(1) 60 ns

tOFF(min) Minimum off time DRVH falling to rising 200 320 450 ns

VDDQ MOSFET DRIVER

RDRVH DRVH resistance Source, IDRVH = –50 mA 1.6 3 Ω

Sink, IDRVH = 50 mA 0.6 1.5

RDRVL DRVL resistance Source, IDRVL = –50 mA 0.9 2 Ω

Sink, IDRVL = 50 mA 0.5 1.2

TPS51716

www.ti.com

SLUSB94A –OCTOBER 2012–REVISED SEPTEMBER 2016

Product Folder Links: TPS51716

Electrical Characteristics (continued)

over operating free-air temperature range, VV5IN = 5 V, VLDOIN is connected to VDDQ output, VMODE= 0 V, VS3= VS5= 5 V

(unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tDEAD Dead time DRVH-off to DRVL-on 10 ns

DRVL-off to DRVH-on 20

INTERNAL BOOT STRAP SW

VFBST Forward voltage VV5IN-VBST, TA= 25°C, IF= 10 mA 0.1 0.2 V

IVBSTLK VBST leakage current TA= 25°C, VVBST = 33 V, VSW = 28 V 0.01 1.5 μA

LOGIC THRESHOLD

IMODE MODE source current 14 15 16 μA

VTHMODE MODE threshold voltage

MODE 0-1 109 129 149

mVMODE 1-2 235 255 275

MODE 2-3 392 412 432

VIL S3/S5 low-level voltage 0.5 V

VIH S3/S5 high-level voltage 1.8 V

VIHYST S3/S5 hysteresis voltage 0.25 V

IILK S3/S5 input leak current –1 0 1 μA

SOFT START

tSS VDDQ soft-start time Internal soft-start time, CVREF = 0.1 μF,

S5 rising to VVDDQSNS > 0.99 × VREFIN 1.1 ms

PGOOD COMPARATOR

VTHPG VDDQ PGOOD threshold

PGOOD in from higher 106% 108% 110%

PGOOD in from lower 90% 92% 94%

PGOOD out to higher 114% 116% 118%

PGOOD out to lower 82% 84% 86%

IPG PGOOD sink current VPGOOD = 0.5 V 3 5.9 mA

tPGDLY PGOOD delay time Delay for PGOOD in 0.8 1 1.2 ms

Delay for PGOOD out, with 100 mV over drive 330 ns

tPGSSDLY PGOOD start-up delay CVREF = 0.1 μF, S5 rising to PGOOD rising 2.5 ms

PROTECTIONS

ITRIP TRIP source current TA= 25°C, VTRIP = 0.4 V 9 10 11 μA

TCITRIP TRIP source current temperature

coefficient(1) 4700 ppm/°C

VTRIP VTRIP voltage range 0.2 3 V

VOCL Current limit threshold

VTRIP = 3.0 V 360 375 390

mVVTRIP = 1.6 V 190 200 210

VTRIP = 0.2 V 20 25 30

VOCLN Negative current limit threshold

VTRIP = 3.0 V –390 –375 –360

mVVTRIP = 1.6 V –210 –200 –190

VTRIP = 0.2 V –30 –25 –20

VZC Zero cross detection offset 0 mV

VUVLO V5IN UVLO threshold voltage Wake-up 4.2 4.4 4.5 V

Shutdown 3.7 3.9 4.1

VOVP VDDQ OVP threshold voltage OVP detect voltage 118% 120% 122%

tOVPDLY VDDQ OVP propagation delay With 100 mV over drive 430 ns

VUVP VDDQ UVP threshold voltage UVP detect voltage 66% 68% 70%

tUVPDLY VDDQ UVP delay 1 ms

tUVPENDLY VDDQ UVP enable delay 1.2 ms

VOOB OOB Threshold voltage 108%

THERMAL SHUTDOWN

TSDN Thermal shutdown threshold Shutdown temperature(1) 140 °C

Hysteresis(1) 10

100

110

120

130

140

150

−50 −25 0 25 50 75 100 125

Junction Temperature (°C)

OVP/UVP Threshold (%)

OVP

UVP

−50 −25 0 25 50 75 100 125

Junction Temperature (°C)

VDDQSNS Discharge Current (mA)

−50 −25 0 25 50 75 100 125

Junction Temperature (°C)

VLDOIN Suppy Current (µA)

−50 −25 0 25 50 75 100 125

Junction Temperature (°C)

TRIP Source Current (µA)

200

400

600

800

1000

−50 −25 0 25 50 75 100 125

Junction Temperature (°C)

V5IN Suppy Current (µA)

−50 −25 0 25 50 75 100 125

Junction Temperature (°C)

V5IN Shutdown Current (µA)

TPS51716

SLUSB94A –OCTOBER 2012–REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: TPS51716

6.6 Typical Characteristics

Figure 1. V5IN Supply Current vs Junction Temperature Figure 2. V5IN Shutdown Current vs Junction Temperature

Figure 3. VLDOIN Supply Current vs Junction Temperature Figure 4. Current Sense Current vs Junction Temperature

Figure 5. OVP/UVP Threshold vs Junction Temperature Figure 6. VDDQSNS Discharge Current vs Junction

Temperature

1.45

1.46

1.47

1.48

1.49

1.50

1.51

1.52

1.53

1.54

1.55

0 2 4 6 8 10

VDDQ Output Current (A)

VDDQ Output Voltage (V)

VIN = 3 V

VIN = 5 V

VIN = 8 V

VIN = 12 V

VIN = 20 V

RMODE = 1 kΩ

G000

100

200

300

400

500

600

700

800

0 2 4 6 8 10

VDDQ Output Current (A)

Switching Frequency (kHz)

VVDDQ = 1.20 V

VVDDQ = 1.35 V

VVDDQ = 1.50 V

RMODE = 12 kΩ

VIN = 12 V

G000

200

300

400

500

600

700

800

6 8 10 12 14 16 18 20 22

Input Voltage (V)

Switching Frequency (kHz)

VVDDQ = 1.20 V

VVDDQ = 1.35 V

VVDDQ = 1.50 V

RMODE = 12 kΩ

IVDDQ = 5 A

100

200

300

400

500

600

700

800

0 2 4 6 8 10

VDDQ Output Current (A)

Switching Frequency (kHz)

VVDDQ = 1.20 V

VVDDQ = 1.35 V

VVDDQ = 1.50 V

RMODE = 1 kΩ

VIN = 12 V

−50 −25 0 25 50 75 100 125

Junction Temperature (°C)

VTT Discharge Current (mA)

200

300

400

500

600

700

800

6 8 10 12 14 16 18 20 22

Input Voltage (V)

Switching Frequency (kHz)

VVDDQ = 1.20 V

VVDDQ = 1.35 V

VVDDQ = 1.50 V

RMODE = 1 kΩ

IVDDQ = 5 A

TPS51716

www.ti.com

SLUSB94A –OCTOBER 2012–REVISED SEPTEMBER 2016

Product Folder Links: TPS51716

Typical Characteristics (continued)

Figure 7. VTT Discharge Current vs Junction Temperature Figure 8. Switching Frequency vs Input Voltage

Figure 9. Switching Frequency vs Input Voltage Figure 10. Switching Frequency vs Load Current

Figure 11. Switching Frequency vs Load Current Figure 12. Load Regulation

0.710

0.720

0.730

0.740

0.750

0.760

0.770

0.780

0.790

−2.0 −1.5 −1.0 −0.5 0.0 0.5 1.0 1.5 2.0

VTT Current (A)

VTT Voltage (V)

VVDDQ = 1.5 V

0.635

0.645

0.655

0.665

0.675

0.685

0.695

0.705

0.715

−2.0 −1.5 −1.0 −0.5 0.0 0.5 1.0 1.5 2.0

VTT Current (A)

VTT Voltage (V)

VVDDQ = 1.35 V

0.650

0.655

0.660

0.665

0.670

0.675

0.680

0.685

0.690

0.695

−10 −5 0 5 10

VTTREF Current (mA)

VTTREF Voltage (V)

VVDDQ = 1.35 V

0.580

0.585

0.590

0.595

0.600

0.605

0.610

0.615

0.620

−10 −5 0 5 10

VTTREF Current (mA)

VTTREF Voltage (V)

VVDDQ = 1.2 V

0.730

0.735

0.740

0.745

0.750

0.755

0.760

0.765

0.770

−10 −5 0 5 10

VTTREF Current (mA)

VTTREF Voltage (V)

VVDDQ = 1.5 V

1.45

1.46

1.47

1.48

1.49

1.50

1.51

1.52

1.53

1.54

1.55

2 4 6 8 10 12 14 16 18 20 22 24 26

Input Voltage (V)

VDDQ Output Voltage (V)

IOUT = 0 A

IOUT =10 A

RMODE = 1 kΩ

fSW = 1 kHz

G000

TPS51716

SLUSB94A –OCTOBER 2012–REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: TPS51716

Typical Characteristics (continued)

Figure 13. Line Regulation Figure 14. VTTREF Load Regulation

Figure 15. VTTREF Load Regulation Figure 16. VTTREF Load Regulation

Figure 17. VTT Load Regulation Figure 18. VTT Load Regulation

100

0.001 0.01 0.1 1 10

VDDQ Output Current (A)

Efficiency (%)

VIN = 5 V

VIN = 7.4 V

VIN = 12 V

VIN = 20 V

VVDDQ = 1.2 V

RMODE = 1 kΩ

fSW = 500 kHz

L: GLMCR470A/ALPS

HS−FET: CSD17308/TI

LS−FET: CSD17309/TI

G000

100

0.001 0.01 0.1 1 10

VDDQ Output Current (A)

Efficiency (%)

VIN = 3 V

VIN = 5 V

VIN = 8 V

VIN = 12 V

VIN = 20 V

VVDDQ = 1.5 V

fSW = 500 kHz

G000

0.560

0.570

0.580

0.590

0.600

0.610

0.620

0.630

0.640

−2.0 −1.5 −1.0 −0.5 0.0 0.5 1.0 1.5 2.0

VTT Current (A)

VTT Voltage (V)

VVDDQ = 1.2 V

TPS51716

www.ti.com

SLUSB94A –OCTOBER 2012–REVISED SEPTEMBER 2016

Product Folder Links: TPS51716

Typical Characteristics (continued)

Figure 19. VTT Load Regulation Figure 20. Efficiency

Figure 21. Efficiency

PGND

TPS51716

XCON

15 VBST

12 V5IN

PWM

REFIN

TRIP

Delay

20 PGOOD

Control Logic

UDG-12151

10 mA

VREFIN +20%

VDDQSNS

14 DRVH

11 DRVL

tON

One-

Shot

VREFIN –32%

16S5

Soft-Start

NOC

8 R

6VREF

7GND

17S3

5VTTREF

1VTTSNS

4 VTTGND

3 VTT

+2 VLDOIN

7 R

VTT Discharge

VTTREF Discharge

Mode

Selection

15 mA

19 MODE

VREFIN +8/16 %

VREFIN –8/16 %

VDDQ

Discharge V5OK

4.4 V/3.9 V

UVP

OVP

+1.8 V

TPS51716

SLUSB94A –OCTOBER 2012–REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: TPS51716

7 Detailed Description

7.1 Overview

The TPS51716 provides a complete power supply for DDR2, DDR3, DDR3L, LPDDR3, and DDR4 memory

systems in the lowest total cost and minimum space. It integrates a synchronous buck regulator controller

(VDDQ) with a 2-A sink/source tracking LDO (VTT) and buffered low noise reference (VTTREF). The TPS51716

employs D-CAP2 mode coupled with 500 kHz or 670 kHz operating frequencies that supports ceramic output

capacitors without an external compensation circuit. The VTTREF tracks VDDQ/2 with excellent 0.8% accuracy.

The VTT, which provides 2-A sink/source peak current capabilities, requires only 10-μF of ceramic capacitance.

In addition, the device features a dedicated LDO supply input.

7.2 Functional Block Diagram

700 ms400 ms 1.4 ms

VREF

VDDQ

PGOOD

UDG-10137

TPS51716

www.ti.com

SLUSB94A –OCTOBER 2012–REVISED SEPTEMBER 2016

Product Folder Links: TPS51716

7.3 Feature Description

7.3.1 VDDQ Switch Mode Power Supply Control

The TPS51716 supports D-CAP2 mode, which does not require complex external compensation networks and

are suitable for designs with small external components counts. The D-CAP2 mode is dedicated for a

configuration with very low ESR output capacitors such as multi-layer ceramic capacitors (MLCC). An adaptive

on-time control scheme is used to achieve pseudo-constant frequency. The TPS51716 adjusts the on-time (tON )

to be inversely proportional to the input voltage (VIN) and proportional to the output voltage (VVDDQ). This

produces a switching frequency that is approximately constant over the variation of input voltage at the steady

state condition.

7.3.2 VREF and REFIN, VDDQ Output Voltage

The part provides a 1.8-V, ±0.8% accurate, voltage reference from VREF. This output has a 300-μA (max)

current capability to drive the REFIN input voltage through a voltage divider circuit. A capacitor with a value of

0.1-μF or larger should be attached close to the VREF terminal.

The VDDQ switch-mode power supply (SMPS) output voltage is defined by REFIN voltage, within the range

between 0.7 V and 1.8 V, programmed by the resister-divider connected between VREF and GND. (See External

Components Selection section.) A few nano farads of capacitance from REFIN to GND is recommended for

stable operation.

7.3.3 Soft-Start and Powergood

Provide a voltage supply to VIN and V5IN before asserting S5 to high. TPS51716 provides integrated VDDQ

soft-start functions to suppress in-rush current at start-up. The soft-start is achieved by controlling internal

reference voltage ramping up. Figure 22 shows the start-up waveforms. The switching regulator waits for 400μs

after S5 assertion. The MODE pin voltage is read in this period. A typical VDDQ ramp up duration is 700μs.

TPS51716 has a powergood open-drain output that indicates the VDDQ voltage is within the target range. The

target voltage window and transition delay times of the PGOOD comparator are ±8% (typ) and 1-ms delay for

assertion (low to high), and ±16% (typ) and 330-ns delay for de-assertion (high to low) during running. The

PGOOD start-up delay is 2.5 ms after S5 is asserted to high. Note that the time constant which is composed of

the REFIN capacitor and a resistor divider needs to be short enough to reach the target value before PGOOD

comparator enabled.

Figure 22. Typical Start-Up Waveforms

= ´ TRIP

OCTRIP TRIP

V R

TPS51716

SLUSB94A –OCTOBER 2012–REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: TPS51716

Feature Description (continued)

7.3.4 Power State Control

The TPS51716 has two input pins, S3 and S5, to provide simple control scheme of power state. All of VDDQ,

VTTREF and VTT are turned on at S0 state (S3=S5=high). In S3 state (S3=low, S5=high), VDDQ and VTTREF

voltages are kept on while VTT is turned off and left at high impedance state (high-Z). The VTT output floats and

does not sink or source current in this state. In S4/S5 states (S3=S5=low), all of the three outputs are turned off

and discharged to GND according to the discharge mode selected by MODE pin. Each state code represents as

follow; S0 = full ON, S3 = suspend to RAM (STR), S4 = suspend to disk (STD), S5 = soft OFF. (See Table 1.)

Table 1. S3/S5 Power State Control

STATE S3 S5 VREF VDDQ VTTREF VTT

S0 HI HI ON ON ON ON

S3 LO HI ON ON ON OFF (High-Z)

S4/S5 LO LO OFF OFF (Discharge) OFF (Discharge) OFF (Discharge)

7.3.5 VDDQ Overvoltage and Undervoltage Protection

The TPS51716 sets the overvoltage protection (OVP) when VDDQSNS voltage reaches a level 20% (typ) higher

than the REFIN voltage. When an OV event is detected, the controller changes the output target voltage to 0 V.

This usually turns off DRVH and forces DRVL to be on. When the inductor current begins to flow through the

low-side MOSFET and reaches the negative OCL, DRVL is turned off and DRVH is turned on, for a minimum on-

time.

After the minimum on-time expires, DRVH is turned off and DRVL is turned on again. This action minimizes the

output node undershoot due to LC resonance. When the VDDQSNS reaches 0 V, the driver output is latched as

DRVH off, DRVL on. VTTREF and VTT are turned off and discharged using the non-tracking discharge

MOSFETs regardless of the tracking mode.

The undervoltage protection (UVP) latch is set when the VDDQSNS voltage remains lower than 68% (typ) of the

REFIN voltage for 1 ms or longer. In this fault condition, the controller latches DRVH low and DRVL low and

discharges the VDDQ, VTT and VTTREF outputs. UVP detection function is enabled after 1.2 ms of SMPS

operation to ensure startup.

To release the OVP and UVP latches, toggle S5 or adjust the V5IN voltage down and up beyond the

undervoltage lockout threshold.

7.3.6 VDDQ Out-of-Bound Operation

When the output voltage rises to 8% above the target value, the out-of-bound operation starts. During the out-of-

bound condition, the controller operates in forced PWM-only mode. Turning on the low-side MOSFET beyond the

zero inductor current quickly discharges the output capacitor. During this operation, the cycle-by-cycle negative

overcurrent limit is also valid. Once the output voltage returns to within regulation range, the controller resumes

to auto-skip mode.

7.3.7 VDDQ Overcurrent Protection

The VDDQ SMPS has cycle-by-cycle overcurrent limiting protection. The inductor current is monitored during the

off-state using the low-side MOSFET RDS(on), and the controller maintains the off-state when the inductor current

is larger than the overcurrent trip level. The current monitor circuit inputs are PGND and SW pins so that those

should be properly connected to the source and drain terminals of low-side MOSFET. The overcurrent trip level,

VOCTRIP, is determined by Equation 1, where RTRIP is the value of the resistor connected between the TRIP pin

and GND, and ITRIP is the current sourced from the TRIP pin. ITRIP is 10 μA typically at room temperature, and

has 4700ppm/°C temperature coefficient to compensate the temperature dependency of the low-side MOSFET

RDS(on).

(1)

Because the comparison is done during the off-state, VOCTRIP sets the valley level of the inductor current. The

load current OCL level, IOCL, can be calculated by considering the inductor ripple current as shown in Equation 2.

V5IN

TPS51716

VREF

VBST

DRVH

DRVL

REFIN

PGND

GND

MODE

18 TRIP

PGOOD

VDDQSNS

VLDOIN

VTT

VTTSNS

VTTGND

VTTREF

UDG-12152

VDDQ

PGND

5VIN

PGND

VIN

AGND

Powergood

PGND

1 kW

PGND

0.22 mF

AGND

( ) ( )

æ ö æ ö -

ç ÷ ç ÷

= + = + ´ ´

ç ÷ ç ÷ ´

è ø è ø

IND(ripple)

OCTRIP OCTRIP IN OUT OUT

OCL

X SW IN

DS on DS on

V V V V V

IR 2 R 2 L f V

TPS51716

www.ti.com

SLUSB94A –OCTOBER 2012–REVISED SEPTEMBER 2016

Product Folder Links: TPS51716

where

• IIND(ripple) is inductor ripple current (2)

In an overcurrent condition, the current to the load exceeds the current to the output capacitor, thus the output

voltage tends to fall down. Eventually, it crosses the undervoltage protection threshold and shuts down.

7.3.8 VTT and VTTREF

TPS51716 integrates two high performance, low-dropout linear regulators, VTT and VTTREF, to provide

complete DDR2, DDR3, DDR3L, LPDDR3, and DDR4 power solutions. The VTTREF has a 10-mA sink/source

current capability, and tracks ½ of VDDQSNS with ±1% accuracy using an on-chip ½ divider. A 0.22-μF (or

larger) ceramic capacitor must be connected close to the VTTREF terminal to ensure stable operation. The VTT

responds quickly to track VTTREF within ±40 mV at all conditions, and the current capability is 2 A for both sink

and source. A 10-μF (or larger) ceramic capacitor(s) need to be connected close to the VTT terminal for stable

operation. To achieve tight regulation with minimum effect of wiring resistance, a remote sensing terminal,

VTTSNS, should be connected to the positive node of VTT output capacitor(s) as a separate trace from the high-

current line to the VTT pin. (Refer to the Layout Guidelines section for details.)

When VTT is not required in the design, the following treatment is strongly recommended.

• Connect VLDOIN to VDDQ.

• Tie VTTSNS to VTT, and remove capacitors from VTT to float.

• Connect VTTGND to GND.

• Select MODE2, 3, 4, or 5 shown in Table 2 (Select Non-tracking discharge mode).

• Maintain a 0.22-µF capacitor connected at VTTREF.

• Pull down S3 to GND with 1-kΩresistance.

Figure 23. Application Circuit When VTT is not Required

TPS51716

SLUSB94A –OCTOBER 2012–REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: TPS51716

7.3.9 VTT Overcurrent Protection

The LDO has an internally fixed constant overcurrent limiting of 3-A (typ) for both sink and source operation.

7.3.10 V5IN Undervoltage Lockout (UVLO) Protection

The TPS51716 has a 5-V supply UVLO protection threshold. When the V5IN voltage is lower than UVLO

threshold voltage, typically 3.9 V, VDDQ, VTT, and VTTREF are shut off. This is a non-latch protection.

7.3.11 Thermal Shutdown

The TPS51716 includes an internal temperature monitor. If the temperature exceeds the threshold value, 140°C

(typ), VDDQ, VTT, and VTTREF are shut off. The state of VDDQ is open, and that of VTT and VTTREF are high

impedance (high-Z) at thermal shutdown. The discharge functions of all outputs are disabled. This is a non-latch

protection and the operation is restarted with soft-start sequence when the device temperature is reduced by

10°C (typ).

7.4 Device Functional Modes

7.4.1 MODE Pin Configuration

The TPS51716 reads the MODE pin voltage when the S5 signal is raised high and stores the status in a register.

A 15-μA current is sourced from the MODE pin during this time to read the voltage across the resistor connected

between the pin and GND. Table 2 shows resistor values, corresponding control mode, switching frequency and

discharge mode configurations.

Table 2. MODE Selection

MODE NO. RESISTANCE BETWEEN

MODE AND GND (kΩ)CONTROL

MODE SWITCHING

FREQUENCY (kHz) DISCHARGE MODE

3 33

D-CAP2

500 Non-Tracking

2 22 670

1 12 670 Tracking

0 1 500

7.4.2 Discharge Control

In S4/S5 state, VDDQ, VTT, and VTTREF outputs are discharged based on the respective discharge mode

selected above. The tracking discharge mode discharges VDDQ output through the internal VTT regulator

transistors enabling quick 13 ms discharge operation. The VTT output maintains tracking of the VTTREF voltage

in this mode. (Please refer to Figure 28) After 4 ms of tracking discharge operation, the mode changes to non-

tracking discharge. The VDDQ output must be connected to the VLDOIN pin in this mode. The non-tracking

mode discharges the VDDQ and VTT pins using internal MOSFETs that are connected to corresponding output

terminals. The non-tracking discharge is slow compared with the tracking discharge due to the lower current

capability of these MOSFETs. Refer to Figure 29.

( )

= ´ ´

IN OUT OUT

LOAD(LL)

X IN SW

V V V1

I2 L V f

= £

p ´ ´ ´

C C SW

X OUT

R C f

2 G L C 3

Control

Logic

and

Driver

COUT RLOAD

CC1

VIN

DRVH

DRVL

VDDQSNS

REFIN

VREF

+1.8 V

RC1

CC2 RC2

TPS51716

VDDQ

PWM

TPS51716

www.ti.com

SLUSB94A –OCTOBER 2012–REVISED SEPTEMBER 2016

Product Folder Links: TPS51716

7.4.3 D-CAP2 Mode Operation

Figure 24 shows simplified model of D-CAP2 architecture.

Figure 24. Simplified Modulator Using D-CAP2 Mode

The D-CAP2 mode in the TPS51716 includes an internal feedback network enabling the use of very low ESR

output capacitor(s) such as multi-layer ceramic capacitors. The role of the internal network is to sense the ripple

component of the inductor current information and combine it with voltage feedback signal. Using RC1 = RC2 ≡RC

and CC1 = CC2 ≡CC, 0-dB frequency of the D-CAP2 mode is given by Equation 3. It is recommended that the 0-

dB frequency (f0) be lower than 1/3 of the switching frequency to secure the proper phase margin.

where

• G is gain of the amplifier which amplifies the ripple current information generated by the compensation

circuit (3)

The typical G value is 0.25, and typical RCCCtime constant values for 500 kHz and 670 kHz operation are 23 µs

and 14.6 µs, respectively.

For example, when fSW=500 kHz and LX=1 µH, COUT should be larger than 88 µF.

When selecting the capacitor, pay attention to its characteristics. For MLCC use X5R or better dielectric and

consider the derating of the capacitance by both DC bias and AC bias. When derating by DC bias and AC bias

are 80% and 50%, respectively, the effective derating is 40% because 0.8 x 0.5 = 0.4. The capacitance of

specialty polymer capacitors may change depending on the operating frequency. Consult capacitor

manufacturers for specific characteristics.

7.4.4 Light-Load Operation

In auto-skip mode, the TPS51716 SMPS control logic automatically reduces its switching frequency to improve

light-load efficiency. To achieve this intelligence, a zero cross detection comparator is used to prevent negative

inductor current by turning off the low-side MOSFET. Equation 4 shows the boundary load condition of this skip

mode and continuous conduction operation.

(4)

VTTSNS

TPS51716RUK

VLDOIN

VTT

VTTGND

VBST

DRVH

V5IN

5 11VTTREF DRVL

10987

PGND

VDDQSNS

REFIN

GND

VREF

16171819

TRIP

MODE

PGOOD

PwPad

1mF

UDG-12148

0.1 mF

10 mF

VIN

8 V to 20 V

PGND

0.1 mF

R7 0 WL1

1mH

FDMS8670AS(1)

C10

4 x 47 mF

VDDQ_GND

PGND

49.9 kW

10 kW

0.1 mF

10 nF

0.22 mF

10 mF

C12

10 mF

PGND

VTT

0.75 V/2 A

VTTREF

0.75 V

VTTGND

100 kW

R2 1 kW

R3 36 kW

V5IN

4.5 V to 5.5 V

FDMS8680(1)

VDDQ

1.5 V/10 A

AGND

PGND

AGND PGND

TPS51716

SLUSB94A –OCTOBER 2012–REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: TPS51716

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

TPS51716 is typically used as step down converters, which converts a voltage from 3V- 28V to 0.7 V to 1.8 V

output voltage and provide a total solution to memory system.

8.2 Typical Application

(1) TI NexFET™ power MOSFETs are available and can be used in this application. Please contact your local TI

representative.

Figure 25. DDR3, DCAP-2 500-kHz Application Circuit, Tracking Discharge

Table 3. DDR3, DCAP-2 500-kHz Application Circuit, List of Materials

REFERENCE DESIGNATOR QTY SPECIFICATION MANUFACTURE PART NUMBER

C8, C9 2 10 µF, 25 V Taiyo Yuden TMK325BJ106MM

C10 4 47 µF, 6.3 V TDK C2012X5R0J476M

L1 1 1 µH, 18.5 A, 2.3 mΩNEC Tokin MPC1055L1R0C

Q1 1 30 V, 35 A, 8.5 mΩFairchild FDMS8680

Q2 1 30 V, 42 A, 3.5 mΩFairchild FDMS8670AS

( ) ( )

( )

()

( )

- ´

= + ´

´ ´

IN OUT OUT

max

TRIP TRIP

IND peak SW IN

DS on max

V V V

R I 1

I8 R L f V

( )

()

( ) ( )

( )

()

( )

- ´ - ´

= ´ = ´

´ ´

IN OUT OUT IN OUT OUT

max max

SW IN O SW IN

IND ripple max max max

V V V V V V

1 3

LI f V I f V

IND(ripple)

OUT(ripple)

OUT SW

V8 C f

´ ´

OUT(ripple) IND(ripple)

V I ESR= ´

OUT(ripple)

OUT

1.8 1

=æ ö

ç ÷

ç ÷ -

ç ÷

è ø

TPS51716

www.ti.com

SLUSB94A –OCTOBER 2012–REVISED SEPTEMBER 2016

Product Folder Links: TPS51716

8.2.1 Design Requirements

To begin the design process, the user must know a few application parameters (see Table 4).

Table 4. Design Parameters

PARAMETER EXAMPLE VALUE

Input voltage range 8 to 20 V

Output voltage 1. 5 V

Transient response, 1.5-A load step ΔVout = ±5%

Input ripple voltage 400 mV

Output ripple voltage 40 mV

Output current rating 10A

Operating frequency 670 kHz/ 500 kHz

8.2.2 Detailed Design Procedure

The following design procedure can be used to select component values for the TPS51716.

8.2.2.1 External Components Selection

The external components selection is a simple process.

1. Determine the value of R1 and R2

The output voltage is determined by the value of the voltage-divider resistor, R1 and R2. R1 is connected

between VREF and REFIN pins, and R2 is connected between the REFIN pin and GND. Setting R1 to 10-kΩ

is a good starting point. Determine R2 using Equation 5.

(5)

For an application using organic semiconductor capacitor(s) or specialty polymer capacitor(s) for the output

capacitor(s), the output voltage ripple can be calculated as shown in Equation 6.

(6)

For an application using ceramic capacitor(s) as the output capacitor(s), the output voltage ripple can be

calculated as shown in Equation 7.

(7)

2. Choose the inductor

The inductance value should be determined to yield a ripple current of approximately ¼ to ½ of maximum

output current. Larger ripple current increases output ripple voltage and improves the signal-to-noise ratio

and helps stable operation.

(8)

The inductor needs a low direct current resistance (DCR) to achieve good efficiency, as well as enough room

above peak inductor current before saturation. The peak inductor current can be estimated in Equation 9.

(9)

p ´ ´ ´

C C SW

X OUT

R C f

2 G L C 3

( )

( ) ( )

æ ö

ç ÷

´ - ´ ´

ç ÷

´´

è ø

IN OUT OUT

OCL DS(on)

XSW IN

TRIP

V V V

8 I R

2 L f V

TPS51716

SLUSB94A –OCTOBER 2012–REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: TPS51716

3. Choose the OCL setting resistance, RTRIP

Combining Equation 1 and Equation 2, RTRIP can be obtained using Equation 10.

(10)

4. Choose the output capacitors

Determine output capacitance to meet small signal stability as shown in Equation 11.

where

• RC× CCtime constant is 23 µs for 500 kHz operation (or 14.6 µs for 670-kHz operation)

• G = 0.25 (11)

TPS51716

www.ti.com

SLUSB94A –OCTOBER 2012–REVISED SEPTEMBER 2016

Product Folder Links: TPS51716

8.2.3 Application Curves

Figure 26. 1.5-V Startup Waveforms Figure 27. 1.5-V Startup Waveforms (0.5-V Pre-Biased)

Figure 28. 1.5-V Soft-Stop Waveforms (Tracking

Discharge) Figure 29. 1.5-V Soft-Stop Waveforms (Non-Tracking

Discharge)

10000 100000 1000000 10000000

−80

−60

−40

−20

−180

−135

−90

−45

135

180

Frequency (Hz)

Gain (dB)

Phase (°)

Gain

Phase

IVTT = 1 A

100 1000 10000 100000 1000000

−80

−60

−40

−20

−180

−135

−90

−45

135

180

Frequency (Hz)

Gain (dB)

Phase (°)

Gain

Phase

VIN = 12 V

IVDDQ = 10 A

10000 100000 1000000 10000000

−80

−60

−40

−20

−180

−135

−90

−45

135

180

Frequency (Hz)

Gain (dB)

Phase (°)

Gain

Phase

IVTT = −1 A

TPS51716

SLUSB94A –OCTOBER 2012–REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: TPS51716

Figure 30. VDDQ Bode Plot Figure 31. VTT Bode Plot (Sink)

Figure 32. VTT Bode Plot (Source)

9 Power Supply Recommendations

The TPS51367 is designed to operate from input supply voltage in the range of 3 V to 28 V. Buck converters

require the input voltage to be higher than the output voltage for proper operation. The maximum recommended

operating duty cycle is 75%. Using that criteria, the minimum recommended input voltage is VO/ 0.75.

TPS51716

www.ti.com

SLUSB94A –OCTOBER 2012–REVISED SEPTEMBER 2016

Product Folder Links: TPS51716

10 Layout

10.1 Layout Guidelines

Certain issues must be considered before designing a layout using the TPS51716.

• VIN capacitor(s), VOUT capacitor(s) and MOSFETs are the power components and should be placed on one

side of the PCB (solder side). Other small signal components should be placed on another side (component

side). At least one inner system GND plane should be inserted, in order to shield and isolate the small signal

traces from noisy power lines.

• All sensitive analog traces and components such as VDDQSNS, VTTSNS, MODE, REFIN, VREF and TRIP

should be placed away from high-voltage switching nodes such as SW, DRVL, DRVH or VBST to avoid

coupling. Use internal layer(s) as system GND plane(s) and shield feedback trace from power traces and

components.

• The DC/DC converter has several high-current loops. The area of these loops should be minimized in order to

suppress generating switching noise.

– The most important loop to minimize the area of is the path from the VIN capacitor(s) through the high and

low-side MOSFETs, and back to the negative node of the VIN capacitor(s). Connect the negative node of

the VIN capacitor(s) and the source of the low-side MOSFET as close as possible. (Refer to loop #1 of

Figure 33)

– The second important loop is the path from the low-side MOSFET through inductor and VOUT

capacitor(s), and back to source of the low-side MOSFET. Connect the source of the low-side MOSFET

and negative node of VOUT capacitor(s) as close as possible. (Refer to loop #2 of Figure 33)

– The third important loop is of gate driving system for the low-side MOSFET. To turn on the low-side

MOSFET, high current flows from V5IN capacitor through gate driver and the low-side MOSFET, and back

to negative node of the capacitor. To turn off the low-side MOSFET, high current flows from gate of the

low-side MOSFET through the gate driver and PGND pin, and back to source of the low-side MOSFET.

Connect negative node of V5IN capacitor, source of the low-side MOSFET and PGND pin as close as

possible. (Refer to loop #3 of Figure 33)

• Connect negative nodes of the VTTREF output capacitor, VREF capacitor and REFIN capacitor and bottom-

side resistance of VREF voltage-divider to GND pin as close as possible. The negative node of the VTT

output capacitor(s), VTTGND, GND and PGND pins should be connected to system GND plane near the

device as shown in Figure 33.

• Because the TPS51716 controls output voltage referring to voltage across VOUT capacitor, VDDQSNS

should be connected to the positive node of VOUT capacitor using different trace from that for VLDOIN.

Remember that this sensing potential is the reference voltage of VTTREF. Avoid any noise generative lines.

GND pin refers to the negative node of VOUT capacitor.

• Connect the overcurrent setting resistor from TRIP pin to GND pin and make the connections as close as

possible to the device to avoid coupling from a high-voltage switching node.

• Connect the frequency and mode setting resistor from MODE pin to GND pin ground, and make the

connections as close as possible to the device to avoid coupling from a high-voltage switching node.

• Connections from gate drivers to the respective gate of the high-side or the low-side MOSFET should be as

short as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider trace and via(s) of at least 0.5

mm (20 mils) diameter along this trace.

• The PCB trace defined as SW node, which connects to the source of the high-side MOSFET, the drain of the

low-side MOSFET and the high-voltage side of the inductor, should be as short and wide as possible.

• VLDOIN should be connected to VOUT with short and wide traces. An input bypass capacitor should be

placed as close as possible to the pin with short and wide connections. The negative node of the capacitor

should be connected to system GND plane.

• The output capacitor for VTT should be placed close to the pins with a short and wide connection in order to

avoid additional ESR and/or ESL of the trace.

• VTTSNS should be connected to the positive node of the VTT output capacitor(s) using a separate trace from

the high-current power line. When remote sensing is required attach the output capacitor(s) at that point.

Also, it is recommended to minimize any additional ESR and/or ESL of ground trace between GND pin and

the output capacitor(s).

• Consider adding a low pass filter (LPF) at VTTSNS in case the ESR of the VTT output capacitor(s) is larger

than 2 mΩ.

TPS51716

DRVL

VIN

REFIN GND

V5IN

12 VOUT

TRIP

MODE

PGND

VREF

VTT

UDG-12149

VTTGND

0.22 ?F

VTTREF

10 ?F

10 nF

0.1 ?F

VTT

VTTGND

VLDOIN

1?F

PGND

AGND

TPS51716

SLUSB94A –OCTOBER 2012–REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: TPS51716

Layout Guidelines (continued)

• In order to effectively remove heat from the package, prepare a thermal land and solder to the package

thermal pad. Wide trace of the component-side copper, connected to this thermal land, helps heat spreading.

Numerous vias with a 0.3-mm diameter connected from the thermal land to the internal/solder-side ground

plane(s) should be used to help dissipation. The thermal land can be connected to either AGND or PGND but

is recommended to be connected to PGND, the system GND plane(s), which has better heat radiation.

10.2 Layout Example

Figure 33. DC/DC Converter Ground System

TPS51716

www.ti.com

SLUSB94A –OCTOBER 2012–REVISED SEPTEMBER 2016

Product Folder Links: TPS51716

11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 Documentation Support

11.2.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.2.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.3 Trademarks

D-CAP2, NexFET, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 7-Jan-2016

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

TPS51716RUKR ACTIVE WQFN RUK 20 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 51716

TPS51716RUKT ACTIVE WQFN RUK 20 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 51716

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

PACKAGE OPTION ADDENDUM

www.ti.com 7-Jan-2016

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TPS51716RUKR WQFN RUK 20 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

TPS51716RUKT WQFN RUK 20 250 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Nov-2017

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS51716RUKR WQFN RUK 20 3000 338.0 355.0 50.0

TPS51716RUKT WQFN RUK 20 250 338.0 355.0 50.0

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Nov-2017

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its

semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers

should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated

circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and

services.

Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is

accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced

documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements

different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the

associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers

remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have

full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products

used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with

respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous

consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and

take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will

thoroughly test such applications and the functionality of such TI products as used in such applications.

TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,

including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to

assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any

way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource

solely for this purpose and subject to the terms of this Notice.

TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI

products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,

enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically

described in the published documentation for a particular TI Resource.

Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that

include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE

TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY

RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information

regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or

endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR

REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO

ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF

MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL

PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,

INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF

PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,

DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN

CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN

ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949

and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.

Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such

products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards

and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must

ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in

life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.

Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life

support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all

medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.

TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).

Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications

and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory

requirements in connection with such selection.

Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-

compliance with the terms and provisions of this Notice.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Texas Instruments:

TPS51716RUKT TPS51716RUKR