INTEGRATED CIRCUITS DATA SHEET For a compicte data sheet, please also download: es The iOO8 7ahC/NCT/NCU/NCMOS Logic Farnly Specifications | s The [006 74NC/CTYMCLYHCMOS Logic Package Information | | s The IC08 T4HC/HCT/NCLYHCMOS Logic Package Quilines | 74HC/HCT595 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state Product specification 1998 Jun 04 Supersedes data of September 1993 File under Integrated Circuits, ICO6 CAE ctor & PHILIPSPhilips Semiconductors Product specification | 8-bit serial-in/serial or parallel-out shift 74HC/HCT595 register with output latches; 3-state ee FEATURES DESCRIPTION 8-bit serial input The 74HC/HCT595 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL . . (LSTTL}. They are specified in compliance with JEDEC Storage register with 3-state outputs standard no. 7A. 8-bit serial or parallel output Shift register with direct clear . . . . . The 595 is an 8-stage serial shift register with a storage register and 3-state outputs. The shift register and storage 100 MHz (typ) shift out frequency @ Output capability: register have separate clocks. parallel outputs; bus driver Data is shifted on the positive-going transitions of the serial output; standard SHep input. The data in each register is transferred to the storage register on a positive-going transition of the STcp input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the log category: MSI. APPLICATIONS storage register. Serial-to-parallel data conversion The shift register has a serial input (Ds) and a serial * Remote control holding register. standard output (Q;) for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. QUICK REFERENCE DATA GND = 0 V; Tamp = 25 C; th = ty = 6 ns. SYMBOL | PARAMETER CONDITIONS nr UNIT HC HCT tpHU/tpLH =| propagation delay CL=15pF; Voc =5V SHcp to Q; 16 21 ns STcp to Qh 17 20 ns MR to Q,' 14 19 ns Frmax maximum clock frequency SHcp, STep 100 57 MHz C, input capacitance 3.5 3.5 pF Crp power dissipation capacitance per package [notes 1 and 2 115 130 pF Notes 1. Cpp is used to determine the dynamic power dissipation (Pp in uW): Pp = Cpp x Voc? xA+E (CL x Vac? x fo) where: fi = input frequency in MHz fy = output frequency in MHz E(CL * Veo? x fp} = sum of outputs C_ = output load capacitance in pF Voc = supply voltage in V 2. For HC the condition is V; = GND to Vee; for HCT the condition is V) = GND to Veg 1.5 V. 1998 Jun 04 2Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift | | 74HC/HCT595 register with output latches; 3-state ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION 74HC595N DIP16 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 74HC595D S016 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HC595DB SSOP16 | plastic shrink small outline package; 16 leads; body width 5.38 mm SOT338-1 74HC595PW TSSOP 16 | plastic thin shrink small outline package; 16 leads; body width 4.4 mm | SOT403-1 74HCT595N DIP16 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 74HCTS95D $016 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 PINNING SYMBOL PIN DESCRIPTION Qo to Q; 15,1to7 parallel data output GND 8 ground (0 V) Q; g serial data output MR 10 master reset (active LOW) SHcp 11 shift register clock input STocp 12 storage register clock input OE 13 output enable (active LOW) Dg 14 serial data input Voc 16 positive supply voltage | 11 12 a U 16] Voc SHop STcp g Q;' a [2 15] Q oO Tis. Q3 [3 14] Dg a, a4 [4 13] OE = i 595 14 ve 3 Qs [5] h2] Stop Ds Q3 - 4 Qg [6] 13] SHop Ts ora al 10] MR o. 6 3 - ono [a ra] 0, oy [2 MLAGO? MR OE | 10 [13 MLAOd2 Fig.1 Pin configuration. Fig.2 Logic symbol. 1998 Jun 04 3Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift 74HC/HCT595 register with output latches; 3-state uw ols a foe fo fe fa MSA6&8 Fig.8 IEC logic symbol. 8-STAGE SHIFT REGISTER 8-BIT STORAGE REGISTER 3-STATE OUTPUTS ~fofoao fo te fw dn f= MLAOOZ Fig.4 Functional diagram. 1998 Jun 04 4Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74HC/HCT595 STAGE 0 cP | Ls dD. FFO STAGES 1TO6 STAGE 7 re FF7 cP | Cs cp LATCH LATCH Qy Qs Qz Qy As Ay Fig.6 Logic diagram. Q> MLAOTO 1998 Jun 04Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift . , 74HC/HCT595 register with output latches; 3-state FUNCTION TABLE INPUTS OUTPUTS = FUNCTON SHcp | STcp | OE MR Ds Q, Qu xX Xx L L x L NC |aLOW level on MR only affects the shift registers x tT L L x L L | empty shift register loaded into storage register x x H L x L Z | shift register clear. Parallel outputs in high-impedance OF F-state t x L H H Qe. NG | logic high level shifted into shift register stage 0. Contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q,) appears on the serial output (Q7) x tT L H x NC Q, | contents of shift register stages (internal Q,) are transferred to the storage register and parallel output stages t T L H x Qs Qn, | contents of shift register shifted through. Previous contents of the shift register is transferred to the storage register and the parallel output stages. Notes 1. H = HIGH voltage level; L = LOW voltage level T = LOW-to-HIGH transition; J = HIGH-to-LOW transition Z = high-impedance OFF-state; NC = no change X = don't care. 1998 Jun 04 6Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift 74HC/HCT595 register with output latches; 3-state 0. [| stor PLLA LEELA mL] Li oW-4---- aan high-impedance OFF-state a ST ITIIE aT TTTI 4 o 72427277 Pou oy 77 Po Fig.6 Timing diagram. 1998 Jun 04 7Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift 74HC/HCT595 register with output latches; 3-state DC CHARACTERISTICS FOR 74HC For the DC characteristics see chapter 74HC/HCT/HCU/HCMOS Logic Family Specifications. Output capability: parallel outputs, bus driver, serial output, standard lcg category: MSI. AC CHARACTERISTICS FOR 74HC GND =0 V; t =t =6 ns; C, = 50 pF. Tamb (C) TEST CONDITION SYMBOL | PARAMETER +25 40 to +85 | 40 to +125 | UNIT | y,, WAVEFORMS min | typ | max | min | max | min | max (V) tpyi/tpty | propagation delay - 52 160 |- 200 = |- 240 | ns 2.0 | Fig.7 SHep to Q7 - 19 |32 - 40 - 48 45 15 27 34 4] 6.0 tpuitpty =| propagation delay 55 175 |- 220) | - 265 ns 2.0 | Fig.8 STcp to Qn |20 |35 | |44 |- [53 45 16 30 37 45 6.0 tPHL propagation delay - 47 175 | - 220 | - 265 [ns 2.0 | Fig.19 MR to Q; - 17 |35 - 44 - 53 45 14 |30 |- 37. |= 45 6.0 tpzy/tpz_ | 3-state output 47 |150 |- 190 | 225 |ns |20 |Fig.11 enable time 17 |30) |= cn 45 45 OE to Qn |14 |26 |- [33 |- {a8 6.0 tpyzitpLz | 3-state output 41 150 190 225 ns 2.0 | Fig.11 disable time - 15/30 |- 38s - 45 45 OE to Qn |12 |26 |- a3 |- {as 6.0 tw shift clock pulse Fis) 17 |- 95 |- 110 ns 2.0 | Fig.7 width HIGH or 15 6 _ 19 _ 22 45 LOW 13 5 16 19 6.0 tw storage clock 75 11 - 95 |- 110 ns 2.0 | Fig.8 pulse width HIGH is |4 _ ig |- 22 _ 45 or LOW 13 |3 |- 16 |- 19 |- 6.0 tw master reset 75 en 95 |- 110 ns 2.0 | Fig.10 pulse width LOW 1s |60 |- 19 |- 22 45 13 5.0 |- 16 19 6.0 tsu set-up time Ds to 50 11 65 75 ns 2.0 | Fig.9 SHep 10 |40 |- 13 |- 15 45 990 |30 |- 11 13 6.0 tsu set-up time SHep 75 22 - 95 - 110 |- ns 2.0 | Fig.8 to STop 15 |8 19 |- 22 45 13 7 16 19 6.0 1998 Jun 04 8Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state (AHCIHCTS9S Tamb (C) TEST CONDITION SYMBOL | PARAMETER +25 40 to +85 | 40 to +125 | UNIT Voc WAVEFORMS min | typ | max | min | max | min | max (V) th hold time Dg to 3 6 3 ns 2.0 | Fig.9 SHop 3 |2 |- - 3 - 45 2 6.0 trem removal time MR 50 19 |- 65 75 ns 2.0 | Fig.10 to SHcp 10 |7 |- 13 |- 15 |- 45 9 6 11 13 6.0 fax maximum clock 9 30 48 |- 4 MHz |2.0 | Figs 7 and8 pulse frequency 30 |91 |- 24 |- 20. |- 45 SHop or STcp 35 |108 |- 28 |- 24 |- 6.0 1998 Jun 04 9Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift FAHC/HCT595 register with output latches; 3-state DC CHARACTERISTICS FOR 74HCT For the DC characteristics see chapter 74HC/HCT/HCU/HCMOS Logic Family Specifications. Output capability: parallel outputs, bus driver; serial output, standard log category: MSI. Note to HCT types The value of additional quiescent supply current (Alcc) for a unit load of 1 is given in the family specifications. To determine Alec per input, multiply this value by the unit load coefficient shown in the table below. GND =0V;t,==6 ns; C_ = 50 pF. INPUT UNIT LOAD COEFFICIENT Ds 0.25 1.50 SHep 1.50 1.50 OE 1.50 1998 Jun 04 10Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift ; ,; 74HC/HCT595 register with output latches; 3-state AC CHARACTERISTICS FOR 74HCT GND =0 V; tt =t =6 ns; CL = 50 pF. Tamb (C) TEST CONDITION SYMBOL | PARAMETER +25 40 to +85 | -40 to +125 | UNIT | y y)_| WAVEFORMS min | typ | max | min | max | min | max (V) tpHL/ tpLH | propagation delay 25 42 - 53 - 63 ns 4.5 | Fig.7 SHep to Q; tpu/ tpLy | propagation delay 24 40 50 60 ns 45 |Fig.8 STop to Qn tPHL propagation delay - 23 40 - 50 - 60 ns 45 | Fig.10 MR to Q, tpzH/ tpz7 3-state output enable 21 35 44 53 ns 45 | Fig.11 time CE to Qh tpyz/ tpiz 3-state output disable - 18 30 38 45 ns 45 | Fig.11 time OE to Q, tw shift clock pulse 16 6 - 20 |- 24 - ns 45 |Fig.7 width HIGH or LOW tw storage clock pulse width | 16 5 - 20 |- 24 - ns 45 |Fig.8 HIGH or LOW tw master reset 20 8 - 25 |- 30 - ns 45 | Fig.10 pulse width LOW tsu set-up time Dg to 16 5 - 20 |- 24 - ns 45 |Fig.9 SHgp tsu set-up time SHcp 16 8 20) |- 24 ns 4.5 | Fig.8 to STecp th hold time Dg to SHep 3 -2 = 3 = 3 = ns 4.5 | Fig.9 trem removal time MR 10 |-7 | - 13 |- 15 |- ns |4.5 |Fig.10 to SHocp fax maximum clock 30 52 24 |- 20 MHz |4.5 | Figs 7 and 8 pulse frequency SHep or STop 1998 Jun 04 11Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift 74HC/HCT595 register with output latches; 3-state AC WAVEFORMS SHop INPUT ] _| Qy' OUTPUT (1) HG: Vu = 50%; Vi = GND to Veco HCT: Vy = 1.3 V; V) = GND to 3 V. Fig.f Waveforms showing the clock (SHgp) to output (Q;') propagation delays, the shift clock pulse width and maximum shift clock frequency. SHgp INPUT STcp INPUT Q,, OUTPUT MSA700 (1) HO: Vy = 50%: Vi = GND to Voc HCT: Vy = 1.3 V; V) = GND to 3 V. Fig.8 Waveforms showing the storage clock (STp) to output (Q,) propagation delays, the storage clock pulse width and the shift clock to storage clock set-up time. 1998 Jun 04 12Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift 74HC/HCT595 register with output latches; 3-state SHop INPUT Dg INPUT Qy! OUTPUT vu? MLBI96 (1) HG: Vy = 50%; V)= GND to Voc HOT: Vy = 1.3 V; V) = GND to 3V. Fig.9 Waveforms showing the data set-up and hold times for the Dg input. MR INPUT \ SHcp INPUT Qz' OUTPUT MLBIS7 (1) HO: Vy = 50%: V) = GND to Voo HCT: Vy = 1.3 V; V) = GND to 3 V. Fig.10 Waveforms showing the master reset (MR) pulse width, the master reset to output (Q,) propagation delay and the master reset to shift clock (SHcp) removal time. 1998 Jun 04 13Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74HC/HCT595 OE INPUT Q, OUTPUT LOW-10-OFF OFF-to-LOW es Q, OUTPUT K90% HIGH-to-OFF vu OFF-to-HIGH outputs outputs outputs enabled disabled wis enabled MSA697 (1) HG: Vu = 50%; vi = GND to Vee HCT: Vy = 1.3 V; V| = GND to 3 V. Fig.11 Waveforms showing the 3-state enable and disable times for input OE. 1998 Jun 04 14Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74HC/HCT595 PACKAGE OUTLINES DIP16: plastic dual in-line package; 16 leads (300 mil); long body SoTs8-1 . P - +~___Mp + i == i re nd pin 1 index 1 8 0 5 10mm daa scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A Ay Ao 43 1} zy UNIT | ay | omin. | mie b by c pi E! e e L Me | My w ex. 140 | 053 | 0.32 | 21.8 | 648 39 8.25 95 mm 47) O51 37 | 444 | o38 | o23 | 214 | 620 | 254 | 782 | 34 | 790 | 33 | 0754 |) 22 . 0.055 | 0.021 | 0.013 | o86 | o26 015 | 0.32 | 0.37 inches | 0.19 | 0.020] 0.15 | Kare | gois | ooog | os4 | ona | 219 | 939 | ys | ost | ggg | 201 | 0.087 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION PROJECTION ISSUE DATE IEC JEDEC EIAJ SOT36-1 050G09 MO-001 AE on seat 1998 Jun 04 15Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift FAHC/HCT595 register with output latches; 3-state $016: plastic small outline package; 16 leads; body width 3.9 mm $OT109-1 EAS |? "AR AAAAAR Vovvnas I f pin 1 index > ho -2 <_ <__ > lel ole fl HORBEOEE. me -w! [e] | Lee bp 0 2.5 5mm bee scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT | waax. | 4 Ap | Ag bp c Do) | EM) | He L Lp Q v w y z | 9 0.25 | 1.45 0.49 | 0.25 | 10.0] 4.0 6.2 1.0 | 07 0.7 mm} 1-75 | gia] 1.25] % |oas|oi9| 98 | a8 | '*7 | 58 1 | oa | os | 979] 775) OT | gg | Qo 0.010 | 0.057 0.019 [0.0100] 0.39 | 0.16 0.244 0.039 | 0.028 o.o2z8| 0 inches | 0.089 9 494 | 0.049| 9! | o.014|0.0075| 0.38 | 0.15 | 9959] 9.298 | 41 | go16 | o.020| 201 | 0.01 | 0.004) Ani, Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES VERSION provecrion | SUE DATE IEC JEDEC EIAJ S5-O+-23- SOT109-1 076E07S MS-012AG EI} 97-05-22 1998 Jun 04 16Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift ; ,; 74HC/HCT595 register with output latches; 3-state SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm $0OT338-1 * D jE yoo - i \ rInnnAnAnAnAh f y | LA ot Ly (Oly J, ; [=] v t/a | 7 a AAARA AAA | I t | : ! fot 0 A p---|----}- Ay \ (As) A : 14 pin 1 index _ t q Yy roe | be l | | yu | OHEHOH OL: elke s Eww Qo 2.5 5mm scale DIMENSIONS (mm are the original dimensions) UNIT mo A, | A> | Ag | bp | c | DS) EM | @ | He | L | bp | a v w y | 2M) 9 0.21 | 1.80 0.38 | 0.20 | 64 | 54 79 1.03 | 09 1.00 | 9 mm |) 20 | gos | 165) | 025 009} 60 | 52 | %88 |) 76 | 178] oss | o7 | OF | O13) OT | ges | ge Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC FIAJ PROJECTION SOT338-1 MO-150AC iO} on opin 1998 Jun 04 17Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift .; , 74HC/HCT595 register with output latches; 3-state TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 t DB -~t E +p{a] | _ a : __ Ag | Sa | | r i] y| He fev Al HARA AAG | PT fe fd Ag \ (Ag) A Yt mp RS) \ 4 t 44 | Loe \ | __ 1 8 | detail X wl +) ele o 2.5 5mm ee scale DIMENSIONS (mm are the original dimensions) UNIT mae. Ar | Az | As | bp | ec | DM | E) e@ | He | L | bp | @ v w y | z) 4 0.15 | 0.95 030] 02 | 541) 45 6.6 0.75 | 04 0.40) 3 mm |} 119) go5 080 | 925] aig} ot | 49 | 43 | 28] go | 12 | oso] o3 | 2% | 213 | Ot | goog | ge Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC FIAJ PROJECTION SOT403-1 MO-153 E} oe oho ISSUE DATE 1998 Jun 04 18Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74HC/HCT595 SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook 1C26; Integrated Circuit Packages (order code 9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (T sig max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. 1998 Jun 04 19 SO, SSOP and TSSOP REFLOW SOLDERING Reflow soldering techniques are suitable for all SO, SSOP and TSSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. WAVE SOLDERING Wave soldering can be used for all SO packages. Wave soldering is not recommended for SSOP and TSSOP packages, because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering is used - and cannot be avoided for SSOP and TSSOP packages - the following conditions must be observed: e A double-wave (a turbulent wave with high upward pressure follawed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end.Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift . , 74HC/HCT595 register with output latches; 3-state Even with these conditions: REPAIRING SOLDERED JOINTS * Only consider wave soldering SSOP packages that Fix the component by first soldering two diagonally- have a body width of 4.4 mm, that is opposite end leads. Use only a low voltage soldering iron SSOP16 (SOT369-1) or SSOP20 (SOT266-1). (less than 24 V) applied to the flat part of the lead. Contact Do not consider wave soldering TSSOP packages time must be limited to 10 seconds at up to 300 C. When with 48 leads or more, that is TSSOP48 (SOT362-1) using a dedicated tool, all other leads can be soldered in and TSSOP56 (SOT364-1). one operation within 2 to 5 seconds between During placement and before soldering, the package must 270 and 320 C. be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1998 Jun 04 20