[AK4393]
M0039-E-03 2012/01
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GENERAL DESCRIPTION
The AK4393 is a high performance stereo DAC for the 96kHz sampling mode of DAT, DVD including a
24bit digital filter. The AK4393 introduces the advanced multi-bit system for ΔΣ modulator. This new
architecture achieves the wider dynamic range, while keeping much the same superior distortion
characteristics as conventional Single-Bit way. In the AK4393, the analog outputs are filtered in the
analog domain by switched-capacitor filter (SCF) with high tolerance to clock jitter. The analog outputs
are full differential output, so the device is suitable for hi-end applications. The operating voltages support
analog 5V and digital 3.3V, so it is easy to I/F with 3.3V logic IC.
FEATURES
• 128x Oversampling
• Sampling Rate up to 108kHz
• 24Bit 8x Digital Filter
Ripple: ±0.005dB, Attenuation: 75dB
• High Tolerance to Clock Jitter
• Low Distortion Differential Output
• Digital de-emphasis for 32, 44.1, 48 & 96kHz sampling
• Soft Mute
• THD+N: -100dB
• DR, S/N: 120dB
• I/F format: MSB justified, 16/20/24bit LSB justified, I2S
• Master Clock: Normal Speed: 256fs, 384fs, 512fs or 768fs
Double Speed: 128fs, 192fs, 256fs or 384fs
• Pow er Supply: 4.75 to 5.25V (Analog), 3 to 5.25V (Digital)
• Small Package: 28pin SSOP
DEM1
LRCK
BICK
SDAT
A
Audio Data
Interface
DEM0DVDD
CSN
AVDD
AOUTR+
8x
Interpolator SCF
ΔΣ
Modulator
AOUTR-
SCF
De-emphasis
Soft Mute
Control Regist er Clock Divider
De-emphasis
Control
PDN
CCLK CDTI P/S MCLK CKS0 CKS1 CKS2
V
REFH
V
REFL
AOUTL+
AOUTL-
V
COM
BVSS
AVSSDVSS
DIF2DIF1DIF0
SMUTE De-emphasis
Soft Mute 8x
Interpolator ΔΣ
Modulator
DFS
Advanced Multi-Bit 96kHz 24-Bit ΔΣ DAC
AK4393
[AK4393]
M0039-E-03 2012/01
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Ordering Guide
AK4393VM -40 ~ +85 °C 28pin SSOP (0.65mm pitch)
Pin Layout
6
5
4
3
2
1
DVSS
DVDD
PDN
MCLK
BICK
SDATA
LRCK 7
SMUTE/CSN 8
CKS2
CKS1
CKS0
P/S
VCOM
A
OUTL+
A
OUTL-
A
OUTR+
Top
View
10
9
DFS
DEM0/CCLK
DEM1/CDTI 11
DIF0 12
A
OUTR-
VSS
A
VDD
VREFH
23
24
25
26
27
28
22
21
19
20
18
17
13
14
16
15
DIF1
DIF2
VREFL
BVSS
[AK4393]
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PIN/FUNCTION
No. Pin Name I/O Function
1 DVSS - Digital Ground Pin
2 DVDD - Digital Power Supply Pin, 3.3V or 5.0V
3 MCLK I Master Clock Input Pin
4
PDN
I
Power-Down Mode Pin
When at “L”, the AK4393 is in power-down mode and is held in reset.
The AK4393 should always be reset upon power-up.
5 BICK
I
Audio Serial Data Clock Pin
The clock of 64fs or more than is recommended to be input on this pin.
6 SDATA
I
Audio Serial Data Input Pin
2’s complement MSB-first data is input on this pin.
7 LRCK I L/R Clock Pin
SMUTE
I
Soft Mute Pin in parallel mode
When this p in goes "H", soft mute cycle is initiated.
When returning “L”, the output mute releases.
8
CSN I Chip Select Pin in serial mode
9 DFS
I
Double Speed Sampling Mode Pin (Internal pull-down pin)
“L”: Normal Speed , “H”: Double Speed
DEM0 I De-emphasis Enable Pin in parallel mode
10 CCLK I Control Data Clock Pin in serial mode
DEM1 I De-emphasis Enable Pin in parallel mode
11 CDTI I Control Data Input Pin in serial mode
12 DIF0 I Digital Input Format Pin
13 DIF1 I Digital Input Format Pin
14 DIF2 I Digital Input Format Pin
15 BVSS - Substrate Ground Pin, 0V
16 VREFL I Low Level Voltage Reference Input Pin
17 VREFH I High Level Voltage Reference Input Pin
18 AVDD - Analog Power Supply Pin, 5.0V
19 AVSS - Analog Ground Pin, 0V
20 AOUTR- O Rch Negative analog output Pin
21 AOUTR+ O Rch Positive analog output Pin
22 AOUTL- O Lch Negative analog output Pin
23 AOUTL+ O Lch Positive analog outp ut Pin
24 VCOM O Common Voltage Output Pin, 2.6V
25 P/S I Parallel/Serial Select Pin (Internal pull-up pin)
“L”: Serial control mode, “H”: Parallel control mode
26 CKS0 I Master Clock Select Pin
27 CKS1 I Master Clock Select Pin
28 CKS2 I Master Clock Select Pin
Note: All input pins except internal pull-up/down pins should not be left floating.
[AK4393]
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ABSOLUTE MAXIMUM RATINGS
(AVSS, BVSS, DVSS = 0V; Note 1)
Parameter Symbol min max Unit
Power Supplies:
Analog
Digital
| BVSS-DVSS | (Note 2)
AVDD
DVDD
Δ GND
-0.3
-0.3
-
6.0
6.0
0.3
V
V
V
Input Current , Any pin Except Supplies IIN - ±10 mA
Input Voltage VIND -0.3 DVDD+0.3 V
Ambient Operating Temperature Ta -40 85 °C
Storage Temperature Tstg -65 150 °C
Notes: 1. All voltages with respect to ground.
2. AVSS, BVSS and DVSS must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, BVSS, DVSS=0V; Note 1)
Parameter Symbol min typ max Unit
Power Supplies:
(Note 3) Analog
Digital AVDD
DVDD 4.75
3.0 5.0
3.3 5.25
5.25 V
V
Voltage Reference
(Note 4) “H” voltage reference
“L” voltage reference
VREFH-VREFL
VREFH
VREFL
Δ VREF
AVDD-0.5
AVSS
3.0
-
-
-
AVDD
-
AVDD
V
V
V
Notes: 3. The power up sequence between AVDD and DVDD is not critical.
4. Analog output voltage scales with the voltage of (VREFH-VREFL).
AOUT (typ.@0dB) = (AOUT+) - (AOUT-) = ±2.4Vpp×(VREFH-VREFL)/5.
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
[AK4393]
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ANALOG CHARACTERISTICS
(Ta = 25°C; AVDD = 5V, DVDD = 3.3V; AVSS, BVSS, DVSS = 0V, VREFH = AVDD, VREFL = AVSS;
fs = 44.1kHz; BICK = 64fs; Signal Frequency = 1kHz; 24bit Input Data; Measurement Bandwidth = 20Hz~20kHz;
RL ≥ 600Ω; External circuit: Figure 11; unless o th erwise specified)
Parameter min typ max Unit
Resolution 24 Bits
Dynamic Characteristics (Note 5)
fs=44.1kHz
BW=20kHz 0dBFS
-60dBFS
-100
-53 -90
- dB
dB
THD+N
fs=96kHz
BW=40kHz 0dBFS
-60dBFS -97
-51 -86
- dB
dB
fs=44.1kHz (Note 6)
(Note 7) 112
- 117
120
dB
dB
Dynamic Range
(-60dBFS with A-weighted)
fs=96kHz
(Note 7) 111
- 116
118
dB
dB
fs=44.1kHz (Note 8)
(Note 7) 112
- 117
120
dB
dB
S/N (A-weighted
fs=96kHz
(Note 7) 111
- 116
118
dB
dB
Interchannel Isolation (1kHz) 100 120 dB
DC Accuracy
Interchannel Gain Mismatch 0.15 0.3 dB
Gain Drift (Note 9) 20 - ppm/°C
Output Voltage (Note 10) ±2.25 ±2.4 ±2.55 Vpp
Load Resistance (Note 11) 600 Ω
Output Current 3.5 mA
Power Supplies
Power Supply Current
Normal Operation (PDN = “H”)
AVDD
DVDD(fs=44.1kHz)
DVDD(fs=96kHz)
AVDD + DVDD
60
3
5
-
-
-
90
mA
mA
mA
mA
Power-Down Mode (PDN = “L”)
AVDD + DVDD (Note 12)
10
50
µA
Power Supply Rejection (Note 13) 50 dB
Notes: 5. At 44.1kHz, measured by Audio Precision, System Two. Averaging mode.
At 96kHz, measured by ROHDE & SCHWARZ, UPD. Averaging mode.
Refer to the eva board manual.
6. 101dB at 16bit data and 116dB at 20bit data.
7. By Figure12. External LPF Circuit Example 2.
8. S/N does not depend on input bit length.
9. The voltage on (VREFH-VREFL) is held +5V externally.
10. Full-scale voltage (0dB). Output voltage scales with the voltage of (VREFH-VREFL).
AOUT (typ.@0dB) = (AOUT+) - (AOUT-) = ±2.4Vpp×(VREFH-VREFL)/5.
11. For AC-load. 1kΩ for DC-load.
12. In the power-down mode. P/S = DVDD, and all other digital input pins including clock pins (MCLK, BICK
and LRCK) are held DVSS.
13. PSR is applied to AVDD, DVDD with 1kHz, 100mVpp. VREFH pin is held +5V.
[AK4393]
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FILTER CHARACTERISTICS (fs = 44.1kHz)
(Ta = 25°C; AVDD = 4.75~5.25V; DVDD = 3.0~5.25V; fs = 44.1kHz; Normal Speed Mode; DEM = OFF)
Parameter Symbol min typ max Unit
Digital Filter
Passband ±0.01dB (Note 14)
-6.0dB PB
0
-
22.05 20.0
- kHz
kHz
Stopband (Note 14) SB 24.1 kHz
Passband Ripple PR ± 0.005 dB
Stopband Attenuation SA 75 dB
Group Delay (Note 15) GD - 28 - 1/fs
Digital Filter + SCF
Frequency Response 0 ∼ 20.0kHz - ± 0.2 - dB
Note: 14. The passband and stopband frequencies scale with fs.
For example, PB = 0.4535×fs (@±0.01dB), SB = 0.546×fs.
15. The calculating delay time which occurred by digital filtering. This time is from setting the 16/20/24bit data of
both channels to input register to the output of analog signal.
FILTER CHARACTERISTICS (fs = 96kHz)
(Ta = 25°C; AVDD = 4.75~5.25V; DVDD = 3.0~5.25V; fs = 96kHz; Double Speed Mode; DEM = OFF)
Parameter Symbol min typ max Unit
Digital Filter
Passband ±0.01dB (Note 14)
-6.0dB PB
0
-
48.0 43.5
- kHz
kHz
Stopband (Note 14) SB 52.5 kHz
Passband Ripple PR ± 0.005 dB
Stopband Attenuation SA 75 dB
Group Delay (Note 15) GD - 28 - 1/fs
Digital Filter + SCF
Frequency Response 0 ∼ 40.0kHz - ± 0.3 - dB
DC CHARACTERISTICS
(Ta = 25°C; AVDD = 4.75~5.25V; DVDD = 3.0~5.25V)
Parameter Symbol min typ max Unit
High-Level Input Voltage
Low-Level Input Voltage VIH
VIL 70%DVDD
- -
- -
30%DVDD V
V
Input Leakage Current (Note 16) Iin - - ± 10 µA
Note: 16. DFS and P/S pins have internal pull-down or pull-up devices, nominally 100kΩ.
[AK4393]
M0039-E-03 2012/01
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SWITCHING CHARACTERISTICS
(Ta = 25°C; AVDD = 4.75~5.25V; DVDD = 3.0~5.25V; CL = 20pF)
Parameter Symbol min typ max Unit
Master Clock Timing (Note 17)
Normal Speed: 256fs, Double Speed: 128fs
Pulse Width Low
Pulse Width High
fCLK
tCLKL
tCLKH
7.7
28
28 13.824 MHz
ns
ns
Normal Speed: 384fs, Double Speed: 192fs
Pulse Width Low
Pulse Width High
fCLK
tCLKL
tCLKH
11.5
20
20 20.736 MHz
ns
ns
Normal Speed: 512fs, Double Speed: 256fs
Normal Speed: 768fs, Double Speed: 384fs
Pulse Width Low
Pulse Width High
fCLK
fCLK
tCLKL
tCLKH
15.4
23.0
7
7
27.648
41.472 MHz
MHz
ns
ns
LRCK Frequency (Note 18)
Normal Speed Mode (DFS = “L”)
Double Speed Mode (DFS = “H”)
Duty Cycle
fsn
fsd
Duty
30
60
45
44.1
88.2
54
108
55
kHz
kHz
%
Serial Interface Timing
BICK Period
BICK Pulse Width Low
Pulse Width High
BICK “↑” to LRCK Edge (Note 19)
LRCK Edge to BICK “↑” (Note 19)
SDATA Hold Time
SDATA Setup Time
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
140
60
60
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN High Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200
80
80
50
50
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
Reset Timing
PDN Pulse Width (Note 20)
tPW
150
ns
Notes: 17. For Double Speed mode please see Appendix A for relationship of MCLK and BCLK/LRCK.
18. When the normal and double speed modes are switched, AK4393 should be reset by PDN pin or RSTN bit.
19. BICK rising edge must not occur at the same time as LRCK edge.
20. The AK4393 can be reset by bringing PDN “L” to “H”.
When the states of CKS2-0 or DFS change, the AK4393 should be reset by PDN pin or RSTN bit.
[AK4393]
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Timing Diagram
1/fCLK
tCLKL
50%DVDD
tCLKH
MCLK
1/fns,1/fds
50%DVDD
LRCK
tBCK
tBCKL
50%DVDD
tBCKH
BICK
Clock Timing
For Double Speed mode timing please see Appendix A for relationship of MCLK and BCLK/LRCK.
tLRB
LRCK
BICK
tSDS
SDATA
tSDH
50%DVDD
tBLR
50%DVDD
50%DVDD
Audio Interface Timing
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tCSS
CSN
CCLK
CDTI
50%DVDD
C1 C0 R/W A4
tCCKL tCCKH
tCDS tCDH
50%DVDD
50%DVDD
WRITE Command Input Timing
CSN
CCLK
CDTI
50%DVDD
D3 D2 D1 D0
tCSW
tCSH
50%DVDD
50%DVDD
WRITE Data Input Timing
tPW
30%DVDD
PDN
Power-down Timing
[AK4393]
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OPERATION OVERVIEW
System Clock
The external clocks, which are required t o operate the AK4393, are MCLK, LRCK and BICK. The mast er clock (MCLK)
should be synchronized with LRCK but the phase is not critical. However, in Double Speed Mode, the phase
relationship between MCLK and LRCK/BICK is limited. (Refer to Appendix A). The MCLK is used to operate the
digital interpolation filter and the delta-sigma m odulator. The sam pling speed is set by DFS (Table 1). The sam pling rate
(LRCK), CKS0/1/2 and DFS determine the frequency of MCLK (Table 2).
All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4393 is in normal operation
mode (PDN = “H”). If these clocks are not provided, the AK4393 may draw excess current because the device utilizes
dynamic refreshed l ogic internally. If the external clocks are not present, the AK4393 should be in the power-down m ode
(PDN = “L”) or in the reset mode (RSTN = “0”). After exiting reset at power-up etc., the AK4393 is in power-down mode
until MCLK and LRCK are input.
DFS Sampling Rate (fs)
0 Normal Speed Mode 30kHz~54kHz Default
1 Double Speed Mode 60kHz~108kHz
Table 1. Sampling Speed
Mode CKS2 CKS1 CKS0 Normal Double
0 0 0 0 256fs 128fs
Default
1 0 0 1 256fs
256fs
2 0 1 0 384fs 192fs
3 0 1 1 384fs
384fs
4 1 0 0 512fs 256fs
5 1 0 1 512fs
N/A
6 1 1 0 768fs 384fs
7 1 1 1 768fs N/A
Table 2. System Clocks
LRCK MCLK BICK
fs 256fs 384fs 512fs 768fs 64fs
32.0kHz 8.1920MHz 12.2880MHz 16.3840MHz 24.5760MHz 2.0480MHz
44.1kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz 2.8224MHz
48.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz 3.0720MHz
Table 3. System clock example (Normal Speed Mode)
LRCK MCLK BICK
fs 128fs 192fs 256fs 384fs 64fs
88.2kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz 5.6448MHz
96.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz 6.1440MHz
Table 4. System clock example (Double Speed Mode)
[AK4393]
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Audio Serial Interface Format
Data is shifted in vi a the SDATA pin usi ng BICK and LR CK input s. Five dat a form ats are support ed and select ed by the
DIF0-2 as shown in Table 5. In all formats the serial data is MSB-first, 2's compliment format and is latched on the rising
edge of BICK. Mode 2 can be used for 20 and 16 MSB justified formats by zeroing the unused LSBs.
Mode DIF2 DIF1 DIF0 Mode BICK Figure
0 0 0 0 0: 16bit LSB Justified ≥32fs Figure 1
1 0 0 1 1: 20bit LSB Justified ≥40fs Figure 2
2 0 1 0 2: 24bit MSB Justified ≥48fs Figure 3
3 0 1 1 3: I2S Compatible ≥48fs Figure 4
4 1 0 0 4: 24bit LSB Justified ≥48fs Figure 2
Table 5. Audio Data Formats
SDAT
A
BICK
LRCK
SDAT
A
15 14 6 5 4
BICK
0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1
3210 1514
(
32fs
)
(
64fs
)
014
115 16 17 31 0 1 14 15 16 17 31 0 1
15 14 0 15 14 0
Mode 0 Don’t care Don’t care
15:MSB, 0:LSB
Mode 0 15 14 6 5 4 3 2 1 0
Lch Data Rch Data
Figure 1. Mode 0 Timing
SDAT
A
LRCK
BICK
(
64fs
)
091 10 11 12 31 0 1 9 10 11 12 31 0 1
19 0 19 0
Mode 1 Don’t care Don’t care
19:MSB, 0:LSB
SDAT
A
Mode 4 23:MSB, 0:LSB
20 19 0 20 19 0
Don’t care Don’t care
22 21 22 21
Lch Data Rch Data
8
23 23
8
Figure 2. Mode 1,4 Timing
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LRCK
BICK
(
64fs
)
SDAT
A
0221 2 24 31 0 1 31 0 1
23:MSB, 0:LSB
22 1 0 Don’t care23
Lch Data Rch Data
23 30 2222423 30
22 1 0 Don’t care
23 2223
Figure 3. Mode 2 Timing
LRCK
BICK
(
64fs
)
SDAT
A
031 2 24 31 0 1 31 0 1
23:MSB, 0:LSB
22 10Don’t care
23
Lch Data Rch Data
23 25 322423 25
22 1 0Don’t care23 23
Figure 4. Mode 3 Timing
De-emphasis filter
A digital de-emphasis filter is available for 32, 44.1, 48 or 96kHz sampling rates (tc = 50/15µs) and is enabled or disabled
with the DEM0, DEM1 and DFS input pins.
DEM1 DEM0 DFS Mode
0 0 0 44.1kHz Default
0 1 0 OFF
1 0 0 48kHz
1 1 0 32kHz
0 0 1 OFF
0 1 1 OFF
1 0 1 96kHz
1 1 1 OFF
Table 6. De-emphasis filter control
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Soft mute operation
Soft mute operation is performed at digital domain. When SMUTE goes to “H”, the output signal is attenuated by -∞
during 1024 LRCK cycles. When SMUTE is returned to “L”, the mute is cancelled and the output attenuation gradually
changes to 0dB during 1024 LRCK cycles. If the soft mute is cancelled within 1024 LRCK cycles after starting the
operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for changing the signal source
without stopping the signal transmission.
SMUTE
A
ttenuation
1024/fs
0dB
-∞
A
OUT
1024/fs
GD GD
(1)
(2)
(3)
Notes:
(1) The output signal is attenuated by -∞ during 1024 LRCK cycles (1024/fs).
(2) Analog output corresponding to digital input has the group delay (GD).
(3) If the soft mute is cancelled within 1024 LRCK cycles, the attenuation is discontinued and returned to 0dB.
Figure 5. Soft mute operation
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System Reset
The AK4393 should be reset once by bringing PDN = “L” upon power-up. The AK4393 is powered up and the internal
timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4393 is in the
power-down mode until MCLK and LRCK are input.
Power-Down
The AK4393 is placed in the power-down mode by bringing PDN pin “L” and the anlog outputs are floating (Hi-Z).
Figure 6 shows an example of the system timing at the power-down and power-up.
Normal Operation
Internal
State
PDN
Power-down Normal Op eration
GD GD
“0” data
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCLK, LRCK, BICK
(1) (3)
External
MUTE (5)
(3) (1)
Mute ON
(2)
(4)
Don’t care
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are floating (Hi -Z) at the power-down mode.
(3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”).
(5) Please mute the analog output externally if the click noise (3) influences system application.
The timing example is shown in this figure.
Figure 6. Power-down/up sequence example
Click Noise from analog output
Click noise occurs from analog output in the following cases.
1) When switching de-emphasis mode by DEM0, DEM1 and DFS pins,
2) When switching serial data mode by DIF0, DIF1 and DIF2 pins,
3) When going and exiting power down mode by PDN pin,
4) W h e n switching normal speed and double speed by DFS pin,
However in case of 1) & 2), If the input data is “0” or the soft mute is enabl ed (aft er 1024 LR C K cycl es from SMUTE =
“H”), no click noise occur except for switching DFS pin.
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Mode Control Interface
Pins (parallel control mode) or registers (serial control mode) can control each functions of the AK4393. For DIF2-0,
CKS2-0 and DFS, the setting of pin and regi ster are “ORed” int ernally . So, even serial control mode, pi n setting can also
control these functions.
The serial control interface is enabled by the P/S pin = “L”. In this mode, pin setting must be all “L”. Internal registers
may be written by 3-wire µP interface pins: CSN, CCLK and CDTI. The data on this interface consists of Chip address
(2bits, C1/0; fixed to “01”), Read/Write (1bit; fixed to “1”), Register add r ess (MSB first, 5bits) and Control data (MSB
first, 8bits). The AK4393 latches the data on the rising edge of CCLK, so data should be clocked in on the falling edge.
The writing of data becom es val id by C SN “↑”. The clock speed of CCLK is 5MHz(max). The CSN and CCLK must be
fixed to “H” when the register does not be accessed.
PDN = “L” resets the registers to their default values. When the state of P/S pin is changed, the AK4393 should be reset
by PDN = “L”. In serial mode, the internal timing circuit is reset by RSTN bit, but the registers are not initialized .
CDTI
CCLK
C1
012345678 9 10 11 12 13 14 15
D4D5D6D7A1A2A3A4R/WC0 A0 D0D1D2D3
CSN
C1-C0: Chip Address (Fixed to “01”)
R/W: READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 7. Control I/F Timing
*The AK4393 does not support the read command and chip address. C1/0 and R/W are fixed to “011”
*When the AK4393 is in the power down mode (PDN = “L”) or the MCLK is not provided, writing into the control
register is inhibited.
*For setting the registers, the following sequence is recommended.
y Control 1 register
(1) Writing RSTN = “0” and other bits (D6-D1) to the register at the same time.
(2) Writing RSTN = “1” to the register. The other bits are no change.
y Control 2 register
This writing sequence has no limitation like control 1 register.
*When RSTN = “0”, the click noise is output from AOUT pins.
*If the mode setting is done without setting RSTN = “0”, large noise may be output from AOUT pins. (Especially when
CKS0/1/2 are changed.)
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Register Map
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control 1 0 CKS2 CKS1 CKS0 DIF2 DIF1 DIF0 RSTN
01H Control 2 0 0 0 0 DFS DEM1 DEM0 SMUTE
02H Test TEST7 TEST6 TEST5 TEST4 TEST3 TEST2 TEST1 TEST0
Notes:
For addresses from 03H to 1FH, data must not be written.
When PDN pin goes to “L”, the registers are initialized to their default values. When RSTN bit goes to “0”, the only
internal timing is reset and the registers are not initialized to their default values. DIF2-0, CKS2-0 and DFS bits are
ORed with pins respectively.
Register Definitions
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control 1 0 CKS2 CKS1 CKS0 DIF2 DIF1 DIF0 RSTN
default 0 0 0 0 0 0 0 1
RSTN: Internal timing reset
0: Reset. All registers are not initialized.
1: Normal Operation
When the states of CKS2-0 or DFS change, the AK4393 should be reset by PDN pin or RSTN bit.
DIF2-0: Audio data interface modes (see Table 5)
Initial: “000”, Mode 0
Register bits are ORed with DIF2-0 pins if P/S = “L”.
CKS2-0: Master Clock Frequency Select (see Table 2)
Initial: “000”, Mode 0
Register bits are ORed with CKS2-0 pins if P/S = “L”.
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
01H Control 2 0 0 0 0 DFS DEM1 DEM0 SMUTE
default 0 0 0 0 0 0 0 0
SMUTE: Soft Mute Enable
0: Normal operation
1: DAC outputs soft-muted
DEM1-0: De-emphasis response (see Table 6)
Initial: “00”, 44.1 kHz
DFS: Sampling speed control (see Table 1)
0: Normal speed
1: Double speed
Register bit is ORed with DFS pin if P/S = “L”.
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
02H Test TEST7 TEST6 TEST5 TEST4 TEST3 TEST2 TEST1 TEST0
default 0 0 0 0 0 0 0 0
TEST7-0: Test mode. Do not write any data to 02H.
[AK4393]
M0039-E-03 2012/01
- 17 -
SYSTEM DESIGN
Figure 8 and 9 show the system connection diagram. An evaluation board (AKD4393) is available which demonstrates
the optimum layout, power supply arrangements and measurement results.
DVSS
1
DVDD
2
MCLK
3
PDN
4
BICK
5
SDATA
6
LRCK
7
CSN
8
DFS9
CCLK10
CDTI
11
DIF0
12
CKS2 28
CKS1 27
CKS0 26
P/S 25
VCOM 24
AOUTL+ 23
AOUTL- 22
AOUTR+ 21
AOUTR- 20
AVSS 19
AVDD 18
VREFH 17
Master Clock
Micro-
controller
0.1u10u
+
10u
0.1u +
10u
+Supply 5V
AK4393
0.1u
Digital
Supply
13
14
16
15
DIF1
DIF2
VREFL
BVSS
fs
24bit Audio Data
Reset & Power down
64fs 10u
0.1u +
Lch
LPF
Rch
LPF
Lch Out
Analog GroundDigital Ground
A
nalog
Rch Out
Figure 8. Typical Connection Diagram (Serial mode)
Notes:
- LRCK = fs, BICK = 64fs.
- Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of
regulator etc.
- AVSS, BVSS and DVSS must be connected to the same analog ground plane.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and
capacitive load.
- All input pins except pull-down/pull-up pins should not be left floating.
[AK4393]
M0039-E-03 2012/01
- 18 -
DVSS
1
DVDD
2
MCLK
3
PDN
4
BICK
5
SDATA
6
LRCK
7
SMUTE
8
DFS9
DEM010
DEM1
11
DIF0
12
CKS2 28
CKS1 27
CKS0 26
P/S 25
VCOM 24
AOUTL+ 23
AOUTL- 22
AOUTR+ 21
AOUTR- 20
AVSS 19
AVDD 18
VREFH 17
Master Clock
Mode
setting
0.1u10u
+
10u
0.1u +
10u
+Supply 5V
AK4393
0.1u
Digital
Supply
13
14
16
15
DIF1
DIF2
VREFL
BVSS
fs
24bit Audio Data
Reset & Power down
64fs 10u
0.1u +
Lch
LPF
Rch
LPF Rch Out
Lch Out
Master
Clock
Select
A
nalog
Analog GroundDigital Ground
Figure 9. Typical Connection Diagram (Parallel mode)
Notes:
- LRCK = fs, BICK = 64fs.
- Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of
regulator etc.
- AVSS, BVSS and DVSS must be connected to the same analog ground plane.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive
load.
- All input pins except pull-down/pull-up pins should not be left floating.
Analog GroundDigital Ground
System
Controller
DVSS
1
DVDD
2
MCLK
3
PDN
4
BICK
5
SDATA
6
LRCK
7
SMUTE
8
DFS9
DEM010
DEM1
11
DIF0
12
CKS2 28
CKS1 27
CKS0 26
P/S 25
VCOM 24
AOUTL+ 23
AOUTL- 22
AOUTR+ 21
AOUTR- 20
AVSS 19
AVDD 18
VREFH
AK4393
17
13
14
16
15
DIF1
DIF2
VREFR
BVSS
Figure 10. Ground Layout
[AK4393]
M0039-E-03 2012/01
- 19 -
1. Grounding and Power Supply Decoupling
To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD and DVDD, respectively.
AVDD is supplied from analog supply in system and DVDD is supplied from digital supply in system. If AVDD and
DVDD are supplied separately, the power up sequence is not critical. AVSS, BVSS and DVSS must be connected
to analog ground plane. System analog ground and digital ground should be connected together near to where the
supplies are brought onto the printed circuit board. Decoupling capacitors for high frequency should be placed as near as
possible.
2. Voltage Reference
The differential Voltage between VREFH and VREFL set the analog output range. VREFH pin is norm all y connected to
AVDD and VREFL pin is normal ly connected to AVSS. VREFH and VREFL should be connected wit h a 0.1µF ceramic
capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 10µF parallel with a 0.1µF ceramic capacitor
attached to VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. All
signals, especially clocks, should be kept away from the VREFH, VREFL and VCOM pins in order to avoid unwanted
coupling into the AK4393.
3. Analog Outputs
The analog outputs are full differential outputs and 2.4Vpp (typ@VREF=5V) centered around VCOM. The differential
outputs are summed externally, VAOUT = (AOUT+) - (AOUT-) between AOUT+ and AOUT-. If the summing gain is 1,
the output range i s 4.8Vpp (typ@VREF=5V). The bias voltage of the external sum ming circuit is supplied externally. The
input data format is 2's complement. The output voltage (VAOUT) is a positive full scale for 7FFFFFH (@24bit) and a
negative full scale for 800000H (@24bit). The ideal VAOUT is 0V for 000000H(@24bit).
The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond the audio
passband.
Figure 11 shows an example of external LPF circuit summing the differential outputs by an op-amp.
Figure 12 shows an example of differential outputs and LPF circuit example by three op-amps.
1k 1k
1k
1k 1k
1k 1n
+Vop
1n
-Vop
AOUT-
AOUT+
3.3n Analog
Out
AK4393
Figure 11. External LPF Circuit Example 1
[AK4393]
M0039-E-03 2012/01
- 20 -
300
47u 300
A
OUTL-
620
10n
300
220
10n
6
4
3
2710u
0.1u
0.1u 10u
10u
NJM5534D
300
47u
300
A
OUTL+
620
10n
300
220
10n
6
4
3
2710u
0.1u
0.1u 10u
NJM5534D
32
1
100
100
0.1u +
NJM5534D
0.1u 10u
100
4
3
2
4.7n
620
620
430
7
+
+
++
-
+
-
+
+
+
-
+
+
4.7n
Lch
-15
+15
6
430
Figure 12. External LPF Circuit Example 2
[AK4393]
M0039-E-03 2012/01
- 21 -
PACKAGE
1.30
0.1±0.1
0-8°
Detail A
Seating Plane
NOTE: Dimension "*" does not include mold flash.
0.10
0.22±0.05
0.32±0.08 0.65
10.40MAX 2.1MAX
A
114
15
28
28pin SSOP (Unit: mm)
5.30
7.90±0.20
0.60±0.15
Material & Lead finish
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder plate
[AK4393]
M0039-E-03 2012/01
- 22 -
MARKING
AK4393VM
XXXBYYYYC
XXXXBYYYYC: data code identifier
XXXB: Lot number (X: Digit number, B: Alpha character)
YYYYC: Assembly date (Y: Digit number C: Alpha character)
Date (Y/M/D) Revision Reason Page Contents
98/11/11 00 First Edition
00/06/02 01 Format
Change No specification has been changed.
03/08/29 02 Specification
Change 7
8
10/2
23
SWITCHING CHARACTERISTICS
Note 17 → Added
Timing Diagram
“For Double Speed modes timing please see Appendix A
for relationship of MCLK and BCLK/LRCK” → Added
OPERATION OVERVIEW
System Clock
“However, in Double Speed Mode, the phase relationship
between MCLK and LRCK/BICK is limited. (Refer to
Appendix A).” → Added
“Appendix A” → Added
12/01/24 03 Specification
Change 1, 2,
21, 22 AK4393VF was deleted. (28pin VSOP)
AK4393VM was added. (28pin SSOP)
Ordering Guide was changed.
PACKAGE was changed.
MARKING was changed.
REVISION HISTORY
[AK4393]
M0039-E-03 2012/01
- 23 -
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assum es no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any p atent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulati ons of the country of export pertai ning to customs and t ariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform ma y reasonably be expected t o result,
whether directly or indi rectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or m aintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
[AK4393]
M0039-E-03 2012/01
- 24 -
Appendix A
In Double Speed Mode, the phase relationship between MCLK and LRCK/BICK is limited (Table 7). If the phase
relationship happens during this prohibited period, it is possible to occur the inverse of output channel. The phase
relationship m ust be set to avoid the prohibit ed period when the AK4393 operates at Doubl e Speed Mode. The prohibited
period is specified by t he combination of digital power supply voltage (DVDD), M CLK frequency and audio data form at
(Table 5). When the audio data formats are 16/20/24bit LSB Just ified (Mode 0,1,4) and 24bit MSB Justified (M ode 2), the
phase relationship (tLR M: Fi gure 11) between the ri sing edge of LR C K and t he risi ng edge of M C LK has t he prohi bi t ed
period of min to max in Table 7. In case of I2S Compatible (Mode 3), the relationship between the falling edge of BICK
and the rising edge of MCLK has the prohibited period (tBCM: Figure 12)
Mode Setting Prohibited Period
Sampling
Mode Digital Power
Supply, DVDD
MCLK
Frequenc
y CKS2 CKS1 CKS0 DFS min max
Units
Double Speed 3.0 to 5.25V 128fs 0 0 0 1 0.4 1.7 ns
Double Speed 3.0 to 5.25V 192fs 0 1 0 1 -0.5 0.8 ns
Double Speed 3.0 to 5.25V 256fs 0 0 1 1 -0.7 0.7 ns
Double Speed 3.0 to 5.25V 256fs 1 0 0 1 -0.7 0.7 ns
Double Speed 3.0 to 5.25V 384fs 0 1 1 1 -1.7 -0.3 ns
Double Speed 3.0 to 5.25V 384fs 1 1 0 1 -1.7 -0.3 ns
Double Speed 4.75 to 5.25V 128fs 0 0 0 1 0.8 1.5 ns
Double Speed 4.75 to 5.25V 192fs 0 1 0 1 -0.2 0.5 ns
Double Speed 4.75 to 5.25V 256fs 0 0 1 1 -0.3 0.4 ns
Double Speed 4.75 to 5.25V 256fs 1 0 0 1 -0.3 0.4 ns
Double Speed 4.75 to 5.25V 384fs 0 1 1 1 -1.0 -0.3 ns
Double Speed 4.75 to 5.25V 384fs 1 1 0 1 -1.0 -0.3 ns
Table 7. Prohibited Period
Figure 11. 16/20/24bit LSB Justified, 24bit MSB Justified
Figure 12. I2S Compatible
tLRM
LRCK
MCLK
50%DVDD
50%DVDD
tBCM
BICK
MCLK
50%DVDD
50%DVDD