IMAGE SENSOR CCD area image sensor S7963, S7964, S7965 Small area, back-thinned FFT-CCD S7963, S7964 and S7965 are a family of FFT-CCD image sensors with small active area and feature low noise and low dark current (MPP mode operation). This enables low-light-level detection and long integration time, thus achieving a wide dynamic range. Binning operation and/or summing operation offers significant improvement in S/N. Due to the low noise amprifier on a CCD chip, a combination of full binning and full summing operation makes CCD as a very low noise photodiode. S7963 has an effective pixel size of 24 x 24 m and is available in image areas of 1.536 (H) x 1.536 (V) mm2. S7965 has relatively large image area of 5.184 (H) x 1.152 (V) mm2. Two-stage TE-cooler is built into the package for thermoelectric cooling. At room temperature operation, the device can be cooled down to -20 C without using any other cooling technique. In addition, since both the CCD chip and the TE-cooler are hermetically sealed, no dry air is required, thus allowing easy handling. Features Applications l Small area l Pixel size: 24 x 24 m l Line, pixel binning l Two-stage TE-cooled l Line, pixel binning l Greater than 90 % quantum efficiency l Low readout noise l MPP operation l Low price l Low-light-level detection l Small area, high-speed imaging l UV detection l Industrial inspection Selection guide Type No. S7963 S7964 S7965 General ratings Parameter Pixel size Vertical clock phase Horizontal clock phase Output circuit Package Cooling Window Cooling Number of total pixels Number of active pixels Two-stage TE cooled 80 x 72 124 x 56 232 x 56 64 x 64 108 x 48 216 x 48 Active area [mm (H) x mm (V)] 1.536 x 1.536 2.592 x 1.152 5.184 x 1.152 Specification 24 (H) x 24 (V) m 2 phase 2 phase One-stage MOSFET source follower 16-pin metal package Two-stage TE-cooler Hermetically sealed quartz 1 CCD area image sensor Absolute maximum ratings Parameter Operating temperature Storage temperature OD voltage RD voltage SG voltage OG voltage RG voltage All vertical clock All horizontal clock Note) All voltage are respect to the SS terminal. Operating conditions (MPP mode) Parameter Output transistor drain voltage Reset drain voltage Output gate voltage Substrate voltage Vertical shift register clock voltage Horizontal shift register clock voltage Summing gate voltage Reset gate voltage High Low High Low High Low High Low S7963, S7964, S7965 Symbol Topr Tstg VOD VRD VSG VOG VRG VP1V, VP2V VP1H, VP2H Min. -50 -50 -0.5 -0.5 -10 -10 -10 -10 -10 Typ. - Max. +30 +70 +25 +18 +15 +15 +15 +15 +15 Unit C C V V V V V V V Symbol VOD VRD VOG Vss VP1VH, VP2VH VP1VL, VP2VL VP1HH, VP2HH VP1HL, VP2HL VSGH VSGL VRGH VRGL Min. 18 11.5 1 4 -9 4 -9 4 -9 4 -9 Typ. 20 12 3 0 6 -8 6 -8 6 -8 6 -8 Max. 22 12.5 5 8 -7 8 -7 8 -7 8 -7 Unit V V V V Typ. 80 k 80 k 300 100 7 7 0.99999 15 3k 15 Max. 1M 1M 18 - Unit Hz Hz pF pF pF pF V W mW Typ. Fw x Sv 300 3,000 0.6 4,000 200 30 (TBD) 10,000 100,000 3 200 to 1100 Max. Unit V Electrical characteristics (Ta=25 C) Parameter Symbol Min. Signal output frequency fc Reset clock frequency frg Vertical shift register capacitance (S7965) CP1V, CP2V Horizontal shift register capacitance (S7965) CP1H, CP2H Summing gate capacitance CSG Reset gate capacitance CRG Charge transfer efficiency *1 CTE 0.99995 DC output level *2 Vout 12 Output impedance *2 Zo Power consumption *2, *3 P *1: Charge transfer efficiency per pixel, measured at half of the full well capacity. *2: VOD=20 V, Load resistance=22 kW *3: Power consumption of the on chip amplifier. Electrical and optical characteristics (Ta =0 C, unless otherwise noted) Parameter Symbol Min. Saturation output voltage Vsat Vertical 150 Full well capacity Fw Horizontal (Summing) 1,500 CCD node sensitivity Sv Dark current *4 25 C DS 0 C (MPP mode) Readout noise *5 Nr Area scanning 2,500 Dynamic range DR Line binning 25,000 6 Photo response non-uniformity * PRNU Spectral response range *7 l *4: Dark current nearly doubles for every 5 to 7 C increase in temperature. *5: -40 C, Readout frequency is 80 kHz. *6: Measured at the half of the full well capacity output. *7: No window material below 200 nm 2 12,000 600 60 10 - V V V V keV / ee- /pixel/s e-rms % nm CCD area image sensor Spectral response (without window) Dark current vs. temperature (Typ. Ta=25 C) 100 (Typ.) 10000 BACK-THINNED 80 DARK CURRENT (e-/pixel/s) QUANTUM EFFICIENCY (%) 90 70 60 50 40 30 20 S7963, S7964, S7965 FRONT-SIDED (UV COAT) 1000 100 10 1 FRONT-SIDED 10 0 200 400 600 800 1000 0.1 -50 1200 -40 -30 WAVELENGTH (nm) -20 -10 0 10 20 30 TEMPERATURE (C) KMPDB0058EA KMPDB0037EB Device structure THINNING P1V P2V 11 10 N 4 3 2 1234 M 4 BEVEL RG 1 TOTAL PIXEL ACTIVE PIXEL THINNING 4 BEVEL SS 13 RD 12 OD 3 2 14 4 OS OG SG 4 BLANK 6 5 P1H P2H BEVEL ACTIVE PIXEL BEVEL 4 BLANK TOTAL PIXEL KMPDC0134EA 3 CCD area image sensor S7963, S7964, S7965 Timing chart Area scanning 1 (low dark current mode) INTEGRATION PERIOD (Shutter must be open) READOUT PERIOD (Shutter must be closed) Tpwv P1V P2V P1H P2H, SG RG OS Tovr P2V ENLARGED VIEW Tpwh, Tpws P1H P2H, SG Tpwr RG OS KMPDC0131EA Parameter Pulse width P1V, P2V Rise and fall time Pulse width P1H, P2H Rise and fall time Duty ratio Pulse width SG Rise and fall time Duty ratio Pulse width RG Rise and fall time P2V - P1H Overlap time 4 Symbol Tpwv Tprv, Tpfv Tpwh Tprh, Tpfh Tpws Tprs, Tpfs Tpwr Tprr, Tpfr Tovr Min. 1 50 500 10 500 10 100 5 3 Typ. 50 50 - Max - Unit s ns ns ns % ns ns % ns ns s CCD area image sensor S7963, S7964, S7965 Area scanning 2 (large full well mode) INTEGRATION PERIOD (Shutter must be open) READOUT PERIOD (Shutter must be closed) Tpwv P1V P2V P1H P2H, SG RG OS Tovr P2V ENLARGED VIEW Tpwh, Tpws P1H P2H, SG Tpwr RG OS KMPDC0132EA Parameter Pulse width P1V, P2V Rise time, fall time Pulse width P1H, P2H Rise and fall time Duty ratio Pulse width SG Rise and fall time Duty ratio Pulse width RG Rise and fall time P2V - P1H Overlap time Symbol Tpwv Tprv, Tpfv Tpwh Tprh, Tpfh Tpws Tprs, Tpfs Tpwr Tprr, Tpfr Tovr Min. 1 50 500 10 500 10 100 5 3 Typ. 50 50 - Max - Unit s ns ns ns % ns ns % ns ns s 5 CCD area image sensor S7963, S7964, S7965 Line binning INTEGRATION PERIOD VERTICAL BINNING PERIOD READOUT PERIOD INTEGRATION PERIOD Tpwv P1V Tovr P2V Tpwh, Tpws P1H P2H SG Tpwr RG Vos KMPDC0133EA Parameter Pulse width P1V, P2V Rise and fall time Pulse width P1H, P2H Rise and fall time Duty ratio Pulse width SG Rise and fall time Duty ratio Pulse width RG Rise and fall time P2V - P1H Overlap time 6 Symbol Tpwv Tprv, Tpfv Tpwh Tprh, Tpfh Tpws Tprs, Tpfs Tpwr Tprr, Tpfr Tovr Min. 1 50 500 10 500 10 100 5 3 Typ. 50 50 - Max - Unit s ns ns ns % ns ns % ns ns s CCD area image sensor Dimensional outline (unit: mm) S7963, S7964, S7965 12 26.0 23.0 5.5 WINDOW 7.0 3.2 7.62 12.7 17.0 2.0 18.0 WINDOW 2.54 7.0 PIN No.16 PIN No.1 10.8 10.5 3.8 4.7 1.2 6.3 PHOTOSENSITIVE SURFACE (16 x) 0.45 KMPDA0134EC Pin connection Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol RG OS OD SG P2H P1H PP+ NC P2V P1V RD SS OG Th1 Th2 Function Reset gate Output transistor source Output transistor drain Summing gate CCD horizontal register clock-2 CCD horizontal register clock-1 TE-cooler (-) TE-cooler (+) Remark +6/-8 V Output +20 V same pulse as P2H +6/-8 V +6/-8 V CCD vertical register clock-2 CCD vertical register clock-1 Reset drain Substrate Output gate Thermister Thermister +6/-8 V +6/-8 V +12 V GND +3 V Specifications of built-in TE-cooler Parameter Internal resistance Symbol Rint Maximum current * & Imax Maximum voltage Vmax Maximum heat absorption * Qmax Condition Ta=27 C Th * ' =27 C ,T * =,Tmax Th* ' =27 C Min. - Typ. 3.0 Max. - Unit 9 - - 1.3 A ,T=,Tmax I=Imax Tc * =Th * ' =27 C - - 3.5 V - - 1.4 W I=Imax Maximum temperature at hot side 50 C CCD temperature Ta=25 C -20 C *8: If the current is greater than Imax, the heat absorption begins to decrease due to the Joule heat. It should be noted that this value is not a damage threshold. To protect the thermoelectric cooler and maintain stable operation, the supply current should be less than 60 % of this maximum current. *9: Temperature at hot side of thermoelectric cooler. *10: ,T=Th - Tc *11: This is a theoretical heat absorption level that offsets the temperature difference in the thermoelectric cooler element when the maximum current is supplied to the unit. *12: Temperature at cool side of thermoelectric cooler. 7 CCD area image sensor S7963, S7964, S7965 Specifications of built-in TE-cooler (TBD) (Typ. Th *=25 C) 3.0 VOLTAGE - CURRENT CCD TEMPERATURE CURRENT 20 2.0 10 1.5 0 1.0 -10 0.5 -20 0 0 0.2 0.4 0.6 0.8 1.0 1.2 CCD TEMPERATURE (C) VOLTAGE (V) 2.5 30 -30 1.4 CURRENT (A) * Temperature at hot side of TE-cooler KMPDB0181EB Specifications of built-in temperature sensor A chip thermistor is built in the same package with a CCD chip, and the CCD chip temperature can be monitored with it. A relation between the thermistor resistance and absolute temperature is expressed by the following equation. R1 = R2 x expB (1 / T1 1 / T2) where R1 is the resistance at absolute temperature T1 (K) R2 is the resistance at absolute temperature T2 (K) B is so-called the B constant (K) RESISTANCE The characteristics of the thermistor used are as follows. R (298 K)=10 kW B (298 K / 323 K)=3450 K. (Typ. Ta=25 C) 1 M 100 k 10 k 220 Precaution for use (electrostatic countermeasures) 240 260 280 300 TEMPERATURE (K) KMPDB0111EA Handle these sensors with bare hands or wearing cotton gloves. In addition, wear anti-static clothing or use a wrist band with an earth ring, in order to prevent electrostatic damage due to electrical charges from friction. Avoid directly placing these sensors on a work-desk or work-bench that may carry an electrostatic charge. Provide ground lines or ground connection with the work-floor, work-desk and work-bench to allow static electricity to discharge. Ground the tools used to handle these sensors, such as tweezers and soldering irons. It is not always necessary to provide all the electrostatic measures stated above. Implement these measures according to the amount of damage that occurs. Element cooling/heating temperature incline rate Element cooling/heating temperature incline rate should be set at less than 5 K/min. Information furnished by HAMAMATSU is believed to be reliable. However, no responsibility is assumed for possible inaccuracies or omissions. Specifications are subject to change without notice. No patent rights are granted to any of the circuits described herein. (c)2003 Hamamatsu Photonics K.K. HAMAMATSU PHOTONICS K.K., Solid State Division 1126-1 Ichino-cho, Hamamatsu City, 435-8558 Japan, Telephone: (81) 053-434-3311, Fax: (81) 053-434-5184, http://www.hamamatsu.com U.S.A.: Hamamatsu Corporation: 360 Foothill Road, P.O.Box 6910, Bridgewater, N.J. 08807-0910, U.S.A., Telephone: (1) 908-231-0960, Fax: (1) 908-231-1218 Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 08152-3750, Fax: (49) 08152-2658 France: Hamamatsu Photonics France S.A.R.L.: 8, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10 United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777 North Europe: Hamamatsu Photonics Norden AB: Smidesvagen 12, SE-171 41 Solna, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01 Cat. No. KMPD1051E05 Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, 1/E, 20020 Arese, (Milano), Italy, Telephone: (39) 02-935-81-733, Fax: (39) 02-935-81-741 Feb. 2003 DN 8