89HPES24T6G2 Data Sheet 24-Lane 6-Port Gen2 PCI Express(R) Switch (R) Device Overview The 89HPES24T6G2 is a member of IDT's PRECISETM family of PCI Express(R) switching solutions. The PES24T6G2 is a 24-lane, 6-port Gen2 peripheral chip that performs PCI Express base switching with a feature set optimized for high performance applications such as servers, storage, and communications systems. It provides connectivity and switching functions between a PCI Express upstream port and up to five downstream ports and supports switching between downstream ports. Features High Performance PCI Express Switch - Twenty-four 5 Gbps Gen2 PCI Express lanes supporting 5 Gbps and 2.5 Gbps operation - Up to six switch ports - Support for Max Payload Size up to 2048 bytes - Supports one virtual channel and eight traffic classes - Fully compliant with PCI Express base specification Revision 2.0 Flexible Architecture with Numerous Configuration Options - Automatic per port link width negotiation to x8, x4, x2, or x1 - Automatic lane reversal on all ports - Automatic polarity inversion - Supports in-band hot-plug presence detect capability - Supports external signal for hot plug event notification allowing SCI/SMI generation for legacy operating systems - Dynamic link width reconfiguration for power/performance optimization - Configurable downstream port PCI-to-PCI bridge device numbering - Crosslink support - Supports ARI forwarding defined in the Alternative Routing-ID Interpretation (ARI) ECN for virtualized and non-virtualized environments - Ability to load device configuration from serial EEPROM Legacy Support - PCI compatible INTx emulation - Supports bus locked transactions, allowing use of PCI Express with legacy software Highly Integrated Solution - Requires no external components - Incorporates on-chip internal memory for packet buffering and queueing - Integrates twenty-four 5 Gbps / 2.5 Gbps embedded SerDes, 8B/10B encoder/decoder (no separate transceivers needed) Reliability, Availability, and Serviceability (RAS) Features - Ability to disable peer-to-peer communications - Supports ECRC and Advanced Error Reporting - All internal data and control RAMs are SECDED ECC protected - Supports PCI Express hot-plug on all downstream ports - Supports upstream port hot-plug Block Diagram 6-Port Switch Core / 24 Gen2 PCI Express Lanes Frame Buffer Port Arbitration Route Table Scheduler Transaction Layer Transaction Layer Transaction Layer Data Link Layer Data Link Layer Data Link Layer Multiplexer / Demultiplexer Multiplexer / Demultiplexer Multiplexer / Demultiplexer Phy Logical Layer Phy Logical Layer Phy Logical Layer Phy Logical Layer Phy Logical Layer Phy Logical Layer Phy Logical Layer Phy Logical Layer Phy Logical Layer Phy Logical Layer Phy Logical Layer SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes (Port 0) (Port 1) Phy Logical Layer (Port 5) Figure 1 Internal Block Diagram IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 50 (c) 2009 Integrated Device Technology, Inc. February 11, 2009 DSC 6930 IDT 89HPES24T6G2 Data Sheet - - - - Hot-swap capable I/O External Serial EEPROM contents are checksum protected Supports PCI Express Device Serial Number Capability Capability to monitor link reliability and autonomously change link speed to prevent link instability Power Management - Utilizes advanced low-power design techniques to achieve low typical power consumption - Support PCI Power Management Interface specification (PCIPM 1.1) * Supports device power management states: D0, D3hot and D3cold - Support for PCI Express Active State Power Management (ASPM) link state * Supports link power management states: L0, L0s, L1, L2/L3 Ready and L3 - Supports PCI Express Power Budgeting Capability - Configurable SerDes power consumption * Supports optional PCI-Express SerDes Transmit Low-Swing Voltage Mode * Supports numerous SerDes Transmit Voltage Margin settings - Unused SerDes are disabled Testability and Debug Features - Per port link up and activity status outputs available on I/O expander outputs - Built in SerDes 8-bit and 10-bit pseudo-random bit stream (PRBS) generators - Numerous SerDes test modes, including a PRBS Master Loopback mode for in-system link testing - Ability to read and write any internal register via SMBus and JTAG interfaces, including SerDes internal controls - Per port statistics and performance counters, as well as proprietary link status registers Eleven General Purpose Input/Output Pins - Each pin may be individually configured as an input or output - Each pin may be individually configured as an interrupt input - Some pins have selectable alternate functions Option A Package: 19mm x 19mm 324-ball Flip Chip BGA with 1mm ball spacing Option B Package: 27mm x 27mm 676-ball Flip Chip BGA with 1mm ball spacing Product Description Revision 2.0. The PES24T6G2 can operate either as a store and forward or cut-through switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource management to enable efficient switching and I/O connectivity for servers, storage, and embedded processors with limited connectivity. Processor Processor Memory Memory Memory Memory North Bridge x8 PES24T6G2 x4 x4 PCI Express Slots x4 x4 I/O 10GbE I/O 10GbE I/O SATA I/O SATA Figure 2 I/O Expansion Application SMBus Interface The PES24T6G2 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES24T6G2, allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration register values of the PES24T6G2 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug I/O expander. Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In the slave interface, these address pins allow the SMBus address to which the device responds to be configured. In the master interface, these address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up on negation of PERSTN by sampling the corresponding address pins. When the pins are sampled, the resulting address is assigned as shown in Table 1. Utilizing standard PCI Express interconnect, the PES24T6G2 provides the most efficient I/O connectivity solution for applications requiring high throughput, low latency, and simple board layout with a minimum number of board layers. It provides connectivity for up to 6 ports across 24 integrated serial lanes. Each lane provides 5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base Specification, Revision 2.0, including operation in 5 Gbps, 2.5 Gbps, and mixed 5 Gbps / 2.5Gbps modes. Note: MSMBADDR and SSMBADDR address pins are not available in the 19mm package. The MSMBADDR address is hardwired to 0x50, and the SSMBADDR address is hardwired to 0x77. The PES24T6G2 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification 2 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Bit Slave SMBus Address Master SMBus Address 1 SSMBADDR[1] MSMBADDR[1] 2 SSMBADDR[2] MSMBADDR[2] 3 SSMBADDR[3] MSMBADDR[3] 4 0 MSMBADDR[4] 5 SSMBADDR[5] 1 6 1 0 7 1 1 Table 1 Master and Slave SMBus Address Assignment for 27x27mm Package As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure 3(a), the master and slave SMBuses are tied together and the PES24T6G2 acts both as a SMBus master as well as a SMBus slave on this bus. This requires that the SMBus master or processor that has access to PES24T6G2 registers supports SMBus arbitration. In some systems, this SMBus master interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To support these systems, the PES24T6G2 may be configured to operate in a split configuration as shown in Figure 3(b). In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required. The PES24T6G2 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of the serial EEPROM. PES24T6G2 Processor SMBus Master Serial EEPROM ... Other SMBus Devices PES24T6G2 SSMBCLK SSMBDAT SSMBCLK SSMBDAT MSMBCLK MSMBCLK MSMBDAT MSMBDAT Processor SMBus Master ... Other SMBus Devices Serial EEPROM (b) Split Configuration and Management Buses (a) Unified Configuration and Management Bus Figure 3 SMBus Interface Configuration Examples Hot-Plug Interface The PES24T6G2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES24T6G2 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES24T6G2 generates an SMBus transaction to the I/O expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate function of GPIO) of the PES24T6G2. In response to an I/O expander interrupt, the PES24T6G2 generates an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander. General Purpose Input/Output The PES24T6G2 provides General Purpose Input/Output (GPIO) pins (7 pins in the 19mm package and 11 pins in the 27mm package) that may be used by the system designer as bit I/O ports. Each GPIO pin may be configured independently as an input or output through software control. Many GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM. 3 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Pin Description The following tables list the functions of the pins provided on the PES24T6G2. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an "N" are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Signal Type Name/Description PE0RP[3:0] PE0RN[3:0] I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pairs for port 0. Port 0 is the upstream port. PE0TP[3:0] PE0TN[3:0] O PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pairs for port 0. Port 0 is the upstream port. PE1RP[3:0] PE1RN[3:0] I PCI Express Port 1 Serial Data Receive. Differential PCI Express receive pairs for port 1. PE1TP[3:0] PE1TN[3:0] O PCI Express Port 1 Serial Data Transmit. Differential PCI Express transmit pairs for port 1. PE2RP[3:0] PE2RN[3:0] I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pairs for port 2. PE2TP[3:0] PE2TN[3:0] O PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit pairs for port 2. PE3RP[3:0] PE3RN[3:0] I PCI Express Port 3 Serial Data Receive. Differential PCI Express receive pairs for port 3. PE3TP[3:0] PE3TN[3:0] O PCI Express Port 3 Serial Data Transmit. Differential PCI Express transmit pairs for port 3. PE4RP[3:0] PE4RN[3:0] I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive pairs for port 4. PE4TP[3:0] PE4TN[3:0] O PCI Express Port 4 Serial Data Transmit. Differential PCI Express transmit pairs for port 4. PE5RP[3:0] PE5RN[3:0] I PCI Express Port 5 Serial Data Receive. Differential PCI Express receive pairs for port 5. PE5TP[3:0] PE5TN[3:0] O PCI Express Port 5 Serial Data Transmit. Differential PCI Express transmit pairs for port 5. PEREFCLKP PEREFCLKN I PCI Express Reference Clock. Differential reference clock pair input. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip SerDes. The frequency of the differential reference clock is determined by the REFCLKM signal. REFCLKM1 I PCI Express Reference Clock Mode Select. This signal selects the frequency of the reference clock input. 0x0 - 100 MHz 0x1 - 125 MHz This pin should be static and not change following the negation of PERSTN. Table 2 PCI Express Interface Pins 1. REFCLKM is not available in the 19mm package and frequency is set at 100MHz. Signal Type Name/Description MSMBADDR[4:1]1 I Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. Table 3 SMBus Interface Pins (Part 1 of 2) 4 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Signal Type Name/Description MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the master SMBus. SSMBADDR[5,3:1]2 I Slave SMBus Address. These pins determine the SMBus address to which the slave SMBus interface responds. SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize transfers on the slave SMBus. SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus. Table 3 SMBus Interface Pins (Part 2 of 2) 1. MSMBADDR pins are not available in the 19mm package. Address hardwired to 0x50. 2. SSMBADDR pins are not available in the 19mm package. Address hardwired to 0x77. Signal Type Name/Description GPIO[0] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2 GPIO[1] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P4RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 4 GPIO[2] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN0 Alternate function pin type: Input Alternate function: I/O Expander interrupt 0 input GPIO[3]1 I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN1 Alternate function pin type: Input Alternate function: I/O Expander interrupt 1 input GPIO[4]1 I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN2 Alternate function pin type: Input Alternate function: I/O Expander interrupt 2 input GPIO[5]1 I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN3 Alternate function pin type: Input Alternate function: I/O Expander interrupt 3 input GPIO[6]1 I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[7] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: GPEN Alternate function pin type: Output Alternate function: General Purpose Event (GPE) output Table 4 General Purpose I/O Pins (Part 1 of 2) 5 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Signal Type Name/Description GPIO[8] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P1RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 1 GPIO[9] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P3RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 3 GPIO[10] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P5RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 5 Table 4 General Purpose I/O Pins (Part 2 of 2) 1. GPIO pins 3, 4, 5, 6 are not available in the 19mm package. Signal Type Name/Description CCLKDS I Common Clock Downstream. The assertion of this pin indicates that all downstream ports are using the same clock source as that provided to downstream devices.This bit is used as the initial value of the Slot Clock Configuration bit in all of the Link Status Registers for downstream ports. The value may be overridden by modifying the SCLK bit in each downstream port's PCIELSTS register. CCLKUS I Common Clock Upstream. The assertion of this pin indicates that the upstream port is using the same clock source as the upstream device. This bit is used as the initial value of the Slot Clock Configuration bit in the Link Status Register for the upstream port. The value may be overridden by modifying the SCLK bit in the P0_PCIELSTS register. MSMBSMODE1 I Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus should operate at 100 KHz instead of 400 KHz. This value may not be overridden. P01MERGEN I Port 0 and 1 Merge. P01MERGEN is an active low signal. It is pulled low internally via a 90K ohm resistor. When this pin is low, port 0 is merged with port 1 to form a single x8 port. The Serdes lanes associated with port 1 become lanes 4 through 7 of port 0. When this pin is high, port 0 and port 1 are not merged, and each operates as a single x4 port. P23MERGEN I Port 2 and 3 Merge. P23MERGEN is an active low signal. It is pulled low internally via a 90K ohm resistor. When this pin is low, port 2 is merged with port 3 to form a single x8 port. The Serdes lanes associated with port 3 become lanes 4 through 7 of port 2. When this pin is high, port 2 and port 3 are not merged, and each operates as a single x4 port. P45MERGEN I Port 4 and 5 Merge. P45MERGEN is an active low signal. It is pulled low internally via a 90K ohm resistor. When this pin is low, port 4 is merged with port 5 to form a single x8 port. The Serdes lanes associated with port 5 become lanes 4 through 7 of port 4. When this pin is high, port 4 and port 5 are not merged, and each operates as a single x4 port. PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside PES24T6G2 and initiates a PCI Express fundamental reset. Table 5 System Pins (Part 1 of 2) 6 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Signal Type Name/Description RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental reset, PES24T6G2 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device operation begins. The device exits the reset state when the RSTHALT bit is cleared in the SWCTL register by an SMBus master. SWMODE[2:0] I Switch Mode. These configuration pins determine the PES24T6G2 switch operating mode. 0x0 -Normal switch mode 0x1 -Normal switch mode with Serial EEPROM initialization 0x2 - through 0x7 Reserved These pins should be static and not change following the negation of PERSTN. 2 Table 5 System Pins (Part 2 of 2) 1. MSMBSMODE is not available in the 19mm package, resulting in the master SMBus operating only at 400 KHz. 2. RSTHALT is not available in the 19mm package. Signal Type Name/Description JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle. JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG Controller. JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated. JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board Table 6 Test Pins 7 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Signal Type Name/Description REFRES0 I/O Port 0 External Reference Resistor. Provides a reference for the Port 0 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be connected from this pin to ground. REFRES1 I/O Port 1 External Reference Resistor. Provides a reference for the Port 1 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be connected from this pin to ground. REFRES2 I/O Port 2 External Reference Resistor. Provides a reference for the Port 2 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be connected from this pin to ground. REFRES3 I/O Port 3 External Reference Resistor. Provides a reference for the Port 3 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be connected from this pin to ground. REFRES4 I/O Port 4 External Reference Resistor. Provides a reference for the Port 4 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be connected from this pin to ground. REFRES5 I/O Port 5 External Reference Resistor. Provides a reference for the Port 5 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be connected from this pin to ground. VDDCORE I Core VDD. Power supply for core logic. VDDI/O I I/O VDD. LVTTL I/O buffer power supply. VDDPEA I PCI Express Analog Power. Serdes analog power supply (1.0V). VDDPEHA I PCI Express Analog High Power. Serdes analog power supply (2.5V). VDDPETA I PCI Express Transmitter Analog Voltage. Serdes transmitter analog power supply (1.0V). VSS I Ground. Table 7 Power, Ground, and SerDes Resistor Pins 8 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Pin Characteristics Note: Some input pads of the PES24T6G2 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption. Function PCI Express Interface Type Buffer I/O Type PE0RN[3:0] I CML Serial Link PE0RP[3:0] I PE0TN[3:0] O PE0TP[3:0] O PE1RN[3:0] I PE1RP[3:0] I PE1TN[3:0] O PE1TP[3:0] O PE2RN[3:0] I PE2RP[3:0] I PE2TN[3:0] O PE2TP[3:0] O PE3RN[3:0] I PE3RP[3:0] I PE3TN[3:0] O PE3TP[3:0] O PE4RN[3:0] I PE4RP[3:0] I PE4TN[3:0] O PE4TP[3:0] O PE5RN[3:0] I PE5RP[3:0] I PE5TN[3:0] O PE5TP[3:0] O PEREFCLKN I PEREFCLKP I Pin Name REFCLKM SMBus 2 3 MSMBADDR[4:1] Diff. Clock Input Notes Refer to Table 9 I LVTTL Input pull-down I LVTTL Input pull-down I/O STI4 pull-up on board I/O STI pull-up on board I Input SSMBCLK I/O STI pull-up on board SSMBDAT I/O STI pull-up on board MSMBCLK MSMBDAT SSMBADDR[5,3:1] General Purpose I/O Internal Resistor1 GPIO[10:0] 5 3 I/O LVTTL STI, High Drive pull-up pull-up Table 8 Pin Characteristics (Part 1 of 2) 9 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Type Buffer I/O Type Internal Resistor1 I LVTTL Input pull-up I Input pull-up MSMBSMODE I Input pull-down P01MERGEN I pull-down P23MERGEN I pull-down P45MERGEN I pull-down PERSTN I Function System Pins Pin Name CCLKDS CCLKUS 6 6 EJTAG / JTAG SerDes Reference Resistors STI RSTHALT I Input pull-down SWMODE[2:0] I Input pull-down JTAG_TCK I STI pull-up JTAG_TDI I STI pull-up JTAG_TDO O JTAG_TMS I STI pull-up JTAG_TRST_N I STI pull-up REFRES0 I/O REFRES1 I/O REFRES2 I/O REFRES3 I/O REFRES4 I/O REFRES5 I/O Notes LVTTL Analog Table 8 Pin Characteristics (Part 2 of 2) 1. Internal resistor values under typical operating conditions are 92K for pull-up and 90K for pull-down. 2. REFCLKM is not available in the 19mm package. 3. SMBus address pins are not available in the 19mm package. 4. Schmitt Trigger Input (STI). 5. GPIO pins 3, 4, 5, 6 are not available in the 19mm package. 6. MSMBSMODE and RSTHALT are not available in the 19mm package. 10 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Logic Diagram -- PES24T6G2 Reference Clocks Reference Clock Frequency Selection PEREFCLKP PEREFCLKN REFCLKM PE0TP[0] PE0TN[0] PE0RP[0] PE0RN[0] PCI Express Switch SerDes Input Port 1 PE1RP[0] PE1RN[0] PCI Express Switch SerDes Input Port 2 PE2RP[0] PE2RN[0] PE2RP[3] PE2RN[3] PE2TP[3] PE2TN[3] PCI Express Switch SerDes Input Port 3 PE3RP[0] PE3RN[0] PE3TP[0] PE3TN[0] PCI Express Switch SerDes Input Port 4 PE4RP[0] PE4RN[0] PE4RP[3] PE4RN[3] PE4TP[3] PE4TN[3] PCI Express Switch SerDes Input Port 5 PE5RP[0] PE5RN[0] PE5TP[0] PE5TN[0] ... PE0TP[3] PE0TN[3] PE0RP[3] PE0RN[3] ... ... PE1TP[0] PE1TN[0] PE1TP[3] PE1TN[3] PE1RP[3] PE1RN[3] PE2TP[0] PE2TN[0] ... ... ... ... PE3RP[3] PE3RN[3] PE3TP[3] PE3TN[3] PES24T6G2 ... ... PE4TP[0] PE4TN[0] ... ... PE5TP[3] PE5TN[3] PE5RP[3] PE5RN[3] Master SMBus Interface MSMBADDR[4:1] MSMBCLK MSMBDAT Slave SMBus Interface SSMBADDR[5,3:1] SSMBCLK SSMBDAT System Pins ... PCI Express Switch SerDes Input Port 0 MSMBSMODE CCLKDS CCLKUS RSTHALT PERSTN SWMODE[2:0] P01MERGEN P23MERGEN P45MERGEN 11 4 GPIO[10:0] JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N 4 REFRES0 REFRES1 REFRES2 REFRES3 REFRES4 REFRES5 PCI Express Switch SerDes Output Port 0 PCI Express Switch SerDes Output Port 1 PCI Express Switch SerDes Output Port 2 PCI Express Switch SerDes Output Port 3 PCI Express Switch SerDes Output Port 4 PCI Express Switch SerDes Output Port 5 General Purpose I/O JTAG Pins SerDes Reference Resistors VDDCORE 3 VDDI/O VDDPEA VDDPEHA Power/Ground VDDPETA VSS Figure 4 PES24T6G2 Logic Diagram Note: The following pins are not available in the 19mm package: REFCLKM, MSMBADDR, SSMBADDR, MSMBSMODE, RSTHALT, GPIO[6:3]. 11 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14. Parameter Description RefclkFREQ Input reference clock frequency range TC-RISE Rising edge rate TC-FALL Condition Min Typical Max Unit 1 100 125 MHz Differential 0.6 4 V/ns Falling edge rate Differential 0.6 4 V/ns VIH Differential input high voltage Differential +150 VIL Differential input low voltage Differential VCROSS Absolute single-ended crossing point voltage Single-ended VCROSS-DELTA Variation of VCROSS over all rising clock edges Single-ended VRB Ring back voltage margin Differential -100 TSTABLE Time before VRB is allowed Differential 500 TPERIOD-AVG Average clock period accuracy -300 2800 ppm TPERIOD-ABS Absolute period, including spread-spectrum and jitter 9.847 10.203 ns TCC-JITTER Cycle to cycle jitter 150 ps VMAX Absolute maximum input voltage +1.15 V VMIN Absolute minimum input voltage -0.3 Duty Cycle Duty cycle 40 Rise/Fall Matching Single ended rising Refclk edge rate versus falling Refclk edge rate ZC-DC Clock source output DC impedance mV +250 -150 mV +550 mV +140 mV +100 mV ps V 60 % 20 % 40 60 Table 9 Input Clock Requirements 1. The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM. Frequency is set at 100 MHz in the 19mm package. AC Timing Characteristics Parameter Gen 1 Description Gen 2 Min1 Typ1 Max1 Min1 Typ1 Max1 399.88 400 400.12 199.94 200 200.06 Units PCIe Transmit UI Unit Interval TTX-EYE Minimum Tx Eye Width TTX-EYE-MEDIAN-toMAX-JITTER Maximum time between the jitter median and maximum deviation from the median TTX-RISE, TTX-FALL TX Rise/Fall Time: 20% - 80% TTX- IDLE-MIN Minimum time in idle 0.75 0.75 ps UI 0.125 UI 0.125 0.15 UI 20 20 UI TTX-IDLE-SET-TO-IDLE Maximum time to transition to a valid Idle after sending an Idle ordered set 8 8 ns Table 10 PCIe AC Timing Characteristics (Part 1 of 2) 12 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Parameter TTX-IDLE-TO-DIFF- Gen 1 Description 1 Min 1 Typ Gen 2 1 Max Maximum time to transition from valid idle to diff data 1 Min Typ1 Max1 Units 8 8 ns 1.3 1.3 ns DATA TTX-SKEW Transmitter data skew between any 2 lanes TMIN-PULSED Minimum Instantaneous Lone Pulse Width NA TTX-HF-DJ-DD Transmitter Deterministic Jitter > 1.5MHz Bandwidth NA 0.15 UI TRF-MISMATCH Rise/Fall Time Differential Mismatch NA 0.1 UI 200.06 ps 0.9 UI PCIe Receive UI Unit Interval 399.88 400 400.12 TRX-EYE (with jitter) Minimum Receiver Eye Width (jitter tolerance) TRX-EYE-MEDIUM TO Max time between jitter median & max deviation 0.3 TRX-SKEW Lane to lane input skew 20 TRX-HF-RMS 1.5 -- 100 MHz RMS jitter (common clock) TRX-HF-DJ-DD 0.4 199.94 0.4 UI UI MAX JITTER 8 ns NA 3.4 ps Maximum tolerable DJ by the receiver (common clock) NA 88 ps TRX-LF-RMS 10 KHz to 1.5 MHz RMS jitter (common clock) NA 4.2 ps TRX-MIN-PULSE Minimum receiver instantaneous eye width NA 0.6 UI Table 10 PCIe AC Timing Characteristics (Part 2 of 2) 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 2.0 Signal Symbol Referenc e Edge Tpw2 None Min Max Unit Timing Diagram Reference GPIO GPIO[10:0]1 50 -- ns Table 11 GPIO AC Timing Characteristics 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. Note that GPIO{6:3} pins are not available in the 19mm package. 2. The values for this symbol were determined by calculation, not by testing. 13 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference Tper_16a none 50.0 -- ns See Figure 5. 10.0 25.0 ns 2.4 -- ns 1.0 -- ns -- 20 ns -- 20 ns 25.0 -- ns JTAG JTAG_TCK Thigh_16a, Tlow_16a JTAG_TMS1, JTAG_TDI Tsu_16b JTAG_TCK rising Thld_16b JTAG_TDO Tdo_16c JTAG_TCK falling Tdz_16c2 JTAG_TRST_N Tpw_16d2 none Table 12 JTAG AC Timing Characteristics 1. The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state. 2. The values for this symbol were determined by calculation, not by testing. Tlow_16a Tper_16a Thigh_16a JTAG_TCK Thld_16b Tsu_16b JTAG_TDI Thld_16b Tsu_16b JTAG_TMS Tdo_16c Tdz_16c JTAG_TDO Tpw_16d JTAG_TRST_N Figure 5 JTAG AC Timing Waveform 14 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Recommended Operating Supply Voltages Symbol Parameter Minimum Typical Maximum Unit 0.9 1.0 1.1 V VDDCORE Internal logic supply VDDI/O I/O supply except for SerDes LVPECL/CML 3.135 3.3 3.465 V VDDPEA1 PCI Express Analog Power 0.95 1.0 1.1 V VDDPEHA2 PCI Express Analog High Power 2.25 2.5 2.75 V VDDPETA PCI Express Transmitter Analog Voltage 0.95 1.0 1.1 V VSS Common ground 0 0 0 V Table 13 PES24T6G2 Operating Voltages 1. V PEA should have no more than 25mV DD peak-peak AC power supply noise superimposed on the 1.0V nominal DC value. 2. V PEHA should have no more than 50mV DD peak-peak AC power supply noise superimposed on the 2.5V nominal DC value. Power-Up/Power-Down Sequence During power supply ramp-up, VDDCORE must remain at least 1.0V below VDDI/O at all times. There are no other power-up sequence requirements for the various operating supply voltages. The power-down sequence can occur in any order. Recommended Operating Temperature Grade Temperature Commercial 0C to +70C Ambient Table 14 PES24T6G2 Operating Temperatures Power Consumption Typical power is measured under the following conditions: 25C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13 (and also listed below). Maximum power is measured under the following conditions: 70C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 13 (and also listed below). Core Supply PCIe Analog Supply PCIe Analog High Supply PCIe Termination Supply Typ 1.0V Max 1.1V Typ 1.0V Max 1.1V Typ 2.5V Max 2.75V Typ 1.0V Max 1.15V Typ 3.3V Max 3.465V mA 1010 1260 1384 1600 161 176 541 600 3 5 Watts 1.01 1.39 1.38 1.76 0.40 0.48 0.54 0.66 0.010 0.017 mA 1010 1260 1190 1376 161 176 281 312 3 5 Watts 1.01 1.39 1.19 1.51 0.40 0.48 0.28 0.34 0.010 0.017 Number of active Lanes per Port 8/4/4/4/4 (Full Swing) 8/4/4/4/4 (Half swing) I/O Supply Total Typ Power Max Power 3.35 4.31 2.89 3.74 Table 15 PES24T6G2 Power Consumption 15 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Thermal Considerations -- Option A Package This section describes thermal considerations for the PES24T6G2 (19mm2 FCBGA324 package). The data in Table 16 below contains information that is relevant to the thermal performance of the PES24T6G2 switch. Symbol Parameter Value TJ(max) Junction Temperature 125 o Maximum 70 o TA(max) JA(effective) JB Ambient Temperature Effective Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Board Units C Conditions C Maximum 16.8 o C/W Zero air flow 10.1 o 1 m/S air flow 9.2 o 2 m/S air flow 4.1 o C/W C/W C/W JC Thermal Resistance, Junction-to-Case 0.3 oC/W P Power Dissipation of the Device 4.31 Watts Maximum Table 16 Thermal Specifications for PES24T6G2, 19x19 mm FCBGA324 Package Thermal Considerations -- Option B Package This section describes thermal considerations for the PES24T6G2 (27mm2 FCBGA676 package). The data in Table 17 below contains information that is relevant to the thermal performance of the PES24T6G2 switch. Symbol Parameter Value Units Conditions TJ(max) Junction Temperature 125 oC Maximum 70 oC Maximum 14.6 oC/W Zero air flow 8.2 oC/W 1 m/S air flow 7.2 oC/W 2 m/S air flow TA(max) JA(effective) Ambient Temperature Effective Thermal Resistance, Junction-to-Ambient JB Thermal Resistance, Junction-to-Board 3.1 oC/W JC Thermal Resistance, Junction-to-Case 0.3 oC/W P Power Dissipation of the Device 4.31 Watts Maximum Table 17 Thermal Specifications for PES24T6G2, 27x27 mm FCBGA676 Package Note: It is important for the reliability of this device in any user environment that the junction temperature not exceed the TJ(max) value specified in Table 16. Consequently, the effective junction to ambient thermal resistance (JA) for the worst case scenario must be maintained below the value determined by the formula: JA = (TJ(max) - TA(max))/P Given that the values of TJ(max), TA(max), and P are known, the value of desired JA becomes a known entity to the system designer. How to achieve the desired JA is left up to the board or system designer, but in general, it can be achieved by adding the effects of JC (value provided in Table 16), thermal resistance of the chosen adhesive (CS), that of the heat sink (SA), amount of airflow, and properties of the circuit board (number of layers and size of the board). As a general guideline, this device will not need a heat sink if the board has 8 or more layers AND the board size is larger than 4"x12" AND airflow in excess of 0.5 m/s is available. It is strongly recommended that users perform their own thermal analysis for their own board and system design scenarios. 16 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing. I/O Type Serial Link Parameter Description Gen1 Min1 Typ1 Gen2 Max1 Min1 Typ1 Unit Conditions Max1 PCIe Transmit VTX-DIFFp-p Differential peak-to-peak output voltage 800 1200 800 1200 mV VTX-DIFFp-p-LOW Low-Drive Differential Peak to Peak Output Voltage 400 1200 400 1200 mV VTX-DE-RATIO- De-emphasized differential output voltage -3 -4 -3.0 -3.5 -4.0 dB -5.5 -6.0 -6.5 dB 3.6 V 3.5dB 6.0dB De-emphasized differential output voltage VTX-DC-CM DC Common mode voltage VTX-CM-ACP RMS AC peak common mode output voltage VTX-DE-RATIO- NA 0 3.6 0 20 mV VTX-CM-DC-active- Abs delta of DC common mode voltage between L0 and idle idle-delta 100 100 mV Abs delta of DC common mode voltage between D+ and D- 25 25 mV delta VTX-Idle-DiffP Electrical idle diff peak output 20 20 mV RLTX-DIFF Transmitter Differential Return loss 10 10 dB 0.05 - 1.25GHz 8 dB 1.25 - 2.5GHz RLTX-CM Transmitter Common Mode Return loss 6 6 dB ZTX-DIFF-DC DC Differential TX impedance 80 120 VTX-CM-ACpp Peak-Peak AC Common 100 mV VTX-DC-CM Transmit Driver DC Common Mode Voltage 3.6 V 600 mV VTX-CM-DC-line- 100 NA 0 3.6 VTX-RCV-DETECT The amount of voltage change allowed during Receiver Detection ITX-SHORT Transmitter Short Circuit Current Limit 120 0 600 0 90 90 mA Table 18 DC Electrical Characteristics (Part 1 of 2) 17 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet I/O Type Serial Link (cont.) Parameter Description Gen1 Min1 Typ1 Gen2 Max1 Min1 1200 120 Typ1 Unit Conditions Max1 PCIe Receive VRX-DIFFp-p Differential input voltage (peak-topeak) 175 RLRX-DIFF Receiver Differential Return Loss 10 1200 mV 10 dB 8 RLRX-CM Receiver Common Mode Return Loss 6 ZRX-DIFF-DC Differential input impedance (DC) 80 100 ZRX--DC DC common mode impedance 40 50 ZRX-COMM-DC Powered down input common mode impedance (DC) 200k 350k 1.25 - 2.5GHz 6 dB 120 Refer to return loss spec 60 40 60 50k ZRX-HIGH-IMP-DC- DC input CM input impedance for V>0 during reset or power down POS 50k 50k ZRX-HIGH-IMP-DC- DC input CM input impedance for V<0 during reset or power down NEG 1.0k 1.0k 175 mV 150 mV VRX-IDLE-DET- Electrical idle detect threshold 65 175 65 0.05 - 1.25GHz DIFFp-p VRX-CM-ACp Receiver AC common-mode peak voltage 150 VRX-CM-ACp PCIe REFCLK CIN Input Capacitance 1.5 -- 1.5 -- IOL -- 2.5 IOH -- IOL pF -- -- 2.5 -- mA VOL = 0.4v -5.5 -- -- -5.5 -- mA VOH = 1.5V -- 12.0 -- -- 12.0 -- mA VOL = 0.4v IOH -- -20.0 -- -- -20.0 -- mA VOH = 1.5V Other I/Os LOW Drive Output High Drive Output Schmitt Trigger Input (STI) VIL -0.3 -- 0.8 -0.3 -- 0.8 V -- VIH 2.0 -- VDDI/O + 0.5 2.0 -- VDDI/O + 0.5 V -- Input VIL -0.3 -- 0.8 -0.3 -- 0.8 V -- VIH 2.0 -- VDDI/O + 0.5 2.0 -- VDDI/O + 0.5 V -- CIN -- -- 8.5 -- -- 8.5 pF -- Inputs -- -- + 10 -- -- + 10 A VDDI/O (max) I/OLEAK W/O Pull-ups/downs -- -- + 10 -- -- + 10 A VDDI/O (max) I/OLEAK WITH Pull-ups/downs -- -- + 80 -- -- + 80 A VDDI/O (max) Capacitance Leakage Table 18 DC Electrical Characteristics (Part 2 of 2) 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 2.0. 18 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet PES24T6G2 Package Options Package Option Package Size A 19x19 mm B 27x27 mm Table 19 PES24T6G2 Package Options 19 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Option A Package Pinout, 19x19mm 324-BGA Signal Pinout The following table lists the pin numbers and signal names for the PES24T6G2 device. Pin Function Alt Pin Function Alt Pin Function Alt Pin Function A1 VSS B17 PE4TN00 D15 VDDCORE F13 VSS A2 VDDI/O B18 PE4TP00 D16 VSS F14 PE4RN03 A3 P01MERGEN C1 PE3TP02 D17 VSS F15 PE4RP03 A4 P23MERGEN C2 PE3TN02 D18 VSS F16 VSS A5 P45MERGEN C3 VSS E1 PE3TP01 F17 PE4TN03 A6 VDDI/O C4 PE3RP02 E2 PE3TN01 F18 PE4TP03 A7 VSS C5 PE3RN02 E3 VSS G1 VSS A8 JTAG_TDI C6 VSS E4 PE3RP01 G2 VSS A9 MSMBDAT C7 JTAG_TCK E5 PE3RN01 G3 VSS A10 VDDI/O C8 JTAG_TRST_N E6 VDDCORE G4 VDDCORE A11 VSS C9 SSMBDAT E7 VDDCORE G5 VDDCORE A12 GPIO_00 C10 CCLKDS E8 VDDCORE G6 VDDPEA A13 VDDI/O C11 SWMODE_2 E9 VSS G7 VDDPEA A14 VDDI/O C12 GPIO_02 1 E10 VDDCORE G8 VDDCORE A15 VSS C13 GPIO_09 1 E11 VDDCORE G9 VDDCORE A16 VSS C14 PE4RN01 E12 VDDCORE G10 VDDCORE A17 VDDI/O C15 PE4RP01 E13 VDDCORE G11 VSS A18 VDDI/O C16 VSS E14 PE4RN02 G12 VDDPEA B1 PE3TP03 C17 PE4TN01 E15 PE4RP02 G13 VDDPEA B2 PE3TN03 C18 PE4TP01 E16 VSS G14 VDDCORE B3 VSS D1 VSS E17 PE4TN02 G15 VDDCORE B4 PE3RP03 D2 VSS E18 PE4TP02 G16 VSS B5 PE3RN03 D3 VSS F1 PE3TP00 G17 VSS B6 VDDI/O D4 VDDCORE F2 PE3TN00 G18 VSS B7 VDDI/O D5 VDDCORE F3 VSS H1 PE2TP03 B8 JTAG_TMS D6 VDDI/O F4 PE3RP00 H2 PE2TN03 B9 SSMBCLK D7 JTAG_TDO F5 PE3RN00 H3 VSS B10 VDDI/O D8 MSMBCLK F6 VSS H4 PE2RP03 B11 SWMODE_1 D9 CCLKUS F7 VSS H5 PE2RN03 B12 GPIO_01 1 D10 SWMODE_0 F8 VDDCORE H6 VDDPEA B13 GPIO_10 1 D11 PERSTN F9 VSS H7 VDDPEA B14 PE4RN00 D12 GPIO_07 F10 VDDCORE H8 VDDCORE B15 PE4RP00 D13 GPIO_08 F11 VSS H9 VDDCORE B16 VSS D14 VDDCORE F12 VSS H10 VDDCORE 1 1 Alt Table 20 PES24T6G2 (19x19mm 324-pin) Signal Pin-Out (Part 1 of 3) 20 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Pin Function Alt Pin Function Alt Pin Function Alt Pin Function H11 VSS K13 VDDPETA M15 PE5RP03 P17 VDDCORE H12 VDDPEA K14 VDDCORE M16 VSS P18 VSS H13 VDDPEA K15 NC M17 PE5TN03 R1 VSS H14 PE5RN00 K16 VSS M18 PE5TP03 R2 VDDCORE H15 PE5RP00 K17 REFRES5 N1 VSS R3 VDDCORE H16 VSS K18 REFRES4 N2 VSS R4 PE1RP03 H17 PE5TN00 L1 PE2TP01 N3 VSS R5 PE1RP02 H18 PE5TP00 L2 PE2TN01 N4 VDDCORE R6 NC J1 PE2TP02 L3 VSS N5 VDDCORE R7 PE1RP01 J2 PE2TN02 L4 PE2RP01 N6 VSS R8 PE1RP00 J3 VSS L5 PE2RN01 N7 VSS R9 VDDCORE J4 PE2RP02 L6 VDDPETA N8 VDDPEA R10 PE0RP03 J5 PE2RN02 L7 VDDPETA N9 VDDPEHA R11 PE0RP02 J6 VDDPEHA L8 VDDPEA N10 VDDPETA R12 VDDCORE J7 VDDPEHA L9 VDDPEHA N11 VDDPEA R13 PE0RP01 J8 VDDCORE L10 VDDPETA N12 VDDPEHA R14 PE0RP00 J9 VSS L11 VDDPEA N13 VSS R15 VDDCORE J10 VDDCORE L12 VDDPEHA N14 VSS R16 VDDCORE J11 VSS L13 VDDPETA N15 VDDCORE R17 VDDCORE J12 VDDPEHA L14 PE5RN02 N16 VSS R18 VSS J13 VDDPEHA L15 PE5RP02 N17 VSS T1 VSS J14 PE5RN01 L16 VSS N18 VSS T2 VSS J15 PE5RP01 L17 PE5TN02 P1 VSS T3 VSS J16 VSS L18 PE5TP02 P2 VDDCORE T4 VSS J17 PE5TN01 M1 PE2TP00 P3 VDDCORE T5 VSS J18 PE5TP01 M2 PE2TN00 P4 PE1RN03 T6 VSS K1 REFRES2 M3 VSS P5 PE1RN02 T7 VSS K2 REFRES3 M4 PE2RP00 P6 VDDCORE T8 VSS K3 VSS M5 PE2RN00 P7 PE1RN01 T9 VSS K4 VDDCORE M6 VDDPETA P8 PE1RN00 T10 VSS K5 VDDCORE M7 VDDPETA P9 VDDCORE T11 VSS K6 VDDPETA M8 VDDPEA P10 PE0RN03 T12 VSS K7 VDDPETA M9 VDDPEHA P11 PE0RN02 T13 VSS K8 VDDCORE M10 VDDPETA P12 VDDCORE T14 VSS K9 VSS M11 VDDPEA P13 PE0RN01 T15 VSS K10 VDDCORE M12 VDDPEHA P14 PE0RN00 T16 VSS K11 VSS M13 VSS P15 VDDCORE T17 VSS Alt Table 20 PES24T6G2 (19x19mm 324-pin) Signal Pin-Out (Part 2 of 3) 21 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Pin Function Alt Pin Function Alt Pin Function Alt Pin Function K12 VDDPETA M14 PE5RN03 P16 VDDCORE T18 VSS U1 VSS U10 PE0TN03 V1 VSS V10 PE0TP03 U2 PEREFCLKN U11 PE0TN02 V2 PEREFCLKP V11 PE0TP02 U3 VSS U12 VSS V3 VSS V12 VSS U4 PE1TN03 U13 PE0TN01 V4 PE1TP03 V13 PE0TP01 U5 PE1TN02 U14 PE0TN00 V5 PE1TP02 V14 PE0TP00 U6 REFRES1 U15 VSS V6 REFRES0 V15 VSS U7 PE1TN01 U16 VSS V7 PE1TP01 V16 VSS U8 PE1TN00 U17 VSS V8 PE1TP00 V17 VSS U9 VSS U18 VSS V9 VSS V18 VSS Alt Table 20 PES24T6G2 (19x19mm 324-pin) Signal Pin-Out (Part 3 of 3) Option A Package -- Alternate Signal Functions Pin GPIO Alternate A12 GPIO_00 P2RSTN B12 GPIO_01 P4RSTN C12 GPIO_02 IOEXPINTN0 D12 GPIO_07 GPEN D13 GPIO_08 P1RSTN C13 GPIO_09 P3RSTN B13 GPIO_10 P5RSTN Table 21 PES24T6G2 (19x19mm 324-Pin) Alternate Signal Functions 22 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Option A Package -- Power Pins VDDCore VDDCore VDDCore VDDI/O VDDPEA VDDPEHA VTTPETA D4 G9 N15 A2 G6 J6 K6 D5 G10 P2 A6 G7 J7 K7 D14 G14 P3 A10 G12 J12 K12 D15 G15 P6 A13 G13 J13 K13 E6 H8 P9 A14 H6 L9 L6 E7 H9 P12 A17 H7 L12 L7 E8 H10 P15 A18 H12 M9 L10 E10 J8 P16 B6 H13 M12 L13 E11 J10 P17 B7 L8 N9 M6 E12 K4 R2 B10 L11 N12 M7 E13 K5 R3 D6 M8 M10 F8 K8 R9 M11 N10 F10 K10 R12 N8 G4 K14 R15 N11 G5 N4 R16 G8 N5 R17 Table 22 PES24T6G2 (19x19mm 324-pin) Power Pins 23 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Option A Package -- Ground Pins VSS VSS VSS VSS VSS VSS A1 E9 H3 N2 T5 U12 A7 E16 H11 N3 T6 U15 A11 F3 H16 N6 T7 U16 A15 F6 J3 N7 T8 U17 A16 F7 J9 N13 T9 U18 B3 F9 J11 N14 T10 V1 B16 F11 J16 N16 T11 V3 C3 F12 K3 N17 T12 V9 C6 F13 K9 N18 T13 V12 C16 F16 K11 P1 T14 V15 D1 G1 K16 P18 T15 V16 D2 G2 L3 R1 T16 V17 D3 G3 L16 R18 T17 V18 D16 G11 M3 T1 T18 D17 G16 M13 T2 U1 D18 G17 M16 T3 U3 E3 G18 N1 T4 U9 Table 23 PES24T6G2 (19x19mm 324-pin) Ground Pins 24 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Option A Package -- Signals Listed Alphabetically Signal Name I/O Type Location Signal Category CCLKDS I C10 System CCLKUS I D9 GPIO_00 I/O A12 GPIO_01 I/O B12 GPIO_02 I/O C12 GPIO_07 I/O D12 GPIO_08 I/O D13 GPIO_09 I/O C13 GPIO_10 I/O B13 JTAG_TCK I C7 JTAG_TDI I A8 JTAG_TDO O D7 JTAG_TMS I B8 JTAG_TRST_N I C8 MSMBCLK I/O D8 MSMBDAT I/O A9 NO CONNECTION General Purpose Input/Output JTAG SMBus K15, R6 P01MERGEN I A3 P23MERGEN I A4 P45MERGEN I A5 PE0RN00 I P14 PE0RN01 I P13 PE0RN02 I P11 PE0RN03 I P10 PE0RP00 I R14 PE0RP01 I R13 PE0RP02 I R11 PE0RP03 I R10 PE0TN00 O U14 PE0TN01 O U13 PE0TN02 O U11 PE0TN03 O U10 PE0TP00 O V14 PE0TP01 O V13 PE0TP02 O V11 PE0TP03 O V10 System PCI Express Table 24 PES24T6G2 (19x19mm 324-pin) Alphabetical Signal List (Part 1 of 4) 25 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Signal Name I/O Type Location Signal Category PE1RN00 I P8 PCI Express PE1RN01 I P7 PE1RN02 I P5 PE1RN03 I P4 PE1RP00 I R8 PE1RP01 I R7 PE1RP02 I R5 PE1RP03 I R4 PE1TN00 O U8 PE1TN01 O U7 PE1TN02 O U5 PE1TN03 O U4 PE1TP00 O V8 PE1TP01 O V7 PE1TP02 O V5 PE1TP03 O V4 PE2RN00 I M5 PE2RN01 I L5 PE2RN02 I J5 PE2RN03 I H5 PE2RP00 I M4 PE2RP01 I L4 PE2RP02 I J4 PE2RP03 I H4 PE2TN00 O M2 PE2TN01 O L2 PE2TN02 O J2 PE2TN03 O H2 PE2TP00 O M1 PE2TP01 O L1 PE2TP02 O J1 PE2TP03 O H1 PE3RN00 I F5 PE3RN01 I E5 PE3RN02 I C5 PE3RN03 I B5 PE3RP00 I F4 PCI Express (cont.) Table 24 PES24T6G2 (19x19mm 324-pin) Alphabetical Signal List (Part 2 of 4) 26 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Signal Name I/O Type Location PE3RP01 I E4 PE3RP02 I C4 PE3RP03 I B4 PE3TN00 O F2 PE3TN01 O E2 PE3TN02 O C2 PE3TN03 O B2 PE3TP00 O F1 PE3TP01 O E1 PE3TP02 O C1 PE3TP03 O B1 PE4RN00 I B14 PE4RN01 I C14 PE4RN02 I E14 PE4RN03 I F14 PE4RP00 I B15 PE4RP01 I C15 PE4RP02 I E15 PE4RP03 I F15 PE4TN00 O B17 PE4TN01 O C17 PE4TN02 O E17 PE4TN03 O F17 PE4TP00 O B18 PE4TP01 O C18 PE4TP02 O E18 PE4TP03 O F18 PE5RN00 I H14 PE5RN01 I J14 PE5RN02 I L14 PE5RN03 I M14 PE5RP00 I H15 PE5RP01 I J15 PE5RP02 I L15 PE5RP03 I M15 PE5TN00 O H17 PE5TN01 O J17 Signal Category PCI Express (cont.) Table 24 PES24T6G2 (19x19mm 324-pin) Alphabetical Signal List (Part 3 of 4) 27 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Signal Name I/O Type Location Signal Category PE5TN02 O L17 PE5TN03 O M17 PE5TP00 O H18 PE5TP01 O J18 PE5TP02 O L18 PE5TP03 O M18 PEREFCLKN I U2 PEREFCLKP I V2 PERSTN I D11 System REFRES0 I/O V6 SerDes Reference Resistors REFRES1 I/O U6 REFRES2 I/O K1 REFRES3 I/O K2 REFRES4 I/O K18 REFRES5 I/O K17 SSMBCLK I/O B9 SSMBDAT I/O C9 SWMODE_0 I D10 SWMODE_1 I B11 SWMODE_2 I C11 SMBus System VDDCORE, VDDI/O, VDDPEA, VDDPEHA, VDDPETA See Table 26 for a listing of power pins. VSS See Table 23 for a listing of ground pins. Table 24 PES24T6G2 (19x19mm 324-pin) Alphabetical Signal List (Part 4 of 4) 28 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Option A Package Pinout -- Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A A B B C C D D E E F F G G H H J J K X X L X X X M X X X M X N X N X K X L P P R R T T U U V V 1 2 3 4 VDDCore (Power) VDDI/O (Power) 5 x 6 7 8 9 10 VDDPETA (Power) VDDPEA (Power) 11 12 13 Vss (Ground) 14 15 16 17 18 Signals No Connect VDDPEHA (Power) 29 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Option A Package Drawing -- 324-Pin AL324/ALG324 30 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Option A Package Drawing -- Page Two 31 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Option B Package Pinout, 27x27mm 676-BGA Signal Pinout The following table lists the pin numbers and signal names for the PES24T6G2 (27x27mm) device. Pin Function Alt Pin Function Alt Pin Function Alt Pin Function A1 VSS B9 MSMBDAT C17 VDDI/O D25 VSS A2 VSS B10 SSMBADDR_2 C18 VSS D26 NC A3 VDDI/O B11 SSMBADDR_5 C19 VDDI/O E1 VSS A4 JTAG_TDI B12 SSMBDAT C20 VSS E2 VSS A5 JTAG_TMS B13 VSS C21 VDDI/O E3 VSS A6 MSMBADDR_1 B14 SWMODE_0 C22 GPIO_10 E4 VSS A7 MSMBADDR_3 B15 SWMODE_2 C23 VDDI/O E5 P01MERGEN A8 MSMBCLK B16 VSS C24 VSS E6 VDDCORE A9 SSMBADDR_1 B17 VDDI/O C25 VSS E7 VDDCORE A10 SSMBADDR_3 B18 GPIO_00 1 C26 NC E8 VSS A11 SSMBCLK B19 GPIO_02 1 D1 PEREFCLKP1 E9 VDDCORE A12 CCLKUS B20 GPIO_04 1 D2 VSS E10 VSS A13 CCLKDS B21 GPIO_06 D3 VSS E11 VDDCORE A14 VSS B22 MSMBSMODE D4 P45MERGEN E12 VSS A15 SWMODE_1 B23 REFCLKM D5 VDDCORE E13 VDDCORE A16 NC B24 VDDI/O D6 VDDCORE E14 VSS A17 PERSTN B25 VSS D7 VSS E15 VDDCORE A18 RSTHALT B26 VSS D8 VDDCORE E16 VSS A19 GPIO_01 1 C1 PEREFCLKN1 D9 VSS E17 VDDCORE A20 GPIO_03 1 C2 VSS D10 VDDCORE E18 VSS A21 GPIO_05 1 C3 P23MERGEN D11 VSS E19 VDDCORE A22 GPIO_07 1 C4 VDDCORE D12 VDDCORE E20 VDDCORE A23 VSS C5 VDDI/O D13 VDDCORE E21 VDDCORE A24 GPIO_09 C6 VSS D14 VSS E22 VSS A25 VSS C7 VDDI/O D15 VDDCORE E23 VSS A26 VSS C8 VSS D16 VSS E24 VSS B1 VSS C9 VDDI/O D17 VDDCORE E25 VSS B2 VSS C10 VSS D18 VDDCORE E26 VSS B3 VDDI/O C11 VDDI/O D19 VDDCORE F1 VDDCORE B4 JTAG_TCK C12 VSS D20 VSS F2 VDDCORE B5 JTAG_TDO C13 VDDI/O D21 VDDCORE F3 VDDPEA B6 JTAG_TRST_N C14 VDDCORE D22 VDDCORE F4 VSS B7 MSMBADDR_2 C15 VDDI/O D23 GPIO_08 F5 VSS B8 MSMBADDR_4 C16 VDDCORE D24 VSS F6 VDDI/O 1 1 1 Alt Table 25 PES24T6G2 (27x27mm 676-Pin) Signal Pin-Out (Part 1 of 5) 32 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Pin Function Alt Pin Function Alt Pin Function Alt Pin Function F7 VSS G18 VSS J3 VDDPETA K14 VSS F8 VSS G19 VSS J4 PE3RN02 K15 VDDCORE F9 VSS G20 VSS J5 PE3RP02 K16 VDDCORE F10 VSS G21 VSS J6 VSS K17 VSS F11 VSS G22 PE4RP00 J7 VDDCORE K18 VSS F12 NC G23 PE4RN00 J8 VDDCORE K19 VDDCORE F13 VSS G24 VDDPETA J9 VSS K20 VDDCORE F14 VSS G25 PE4TP00 J10 VSS K21 VSS F15 VSS G26 PE4TN00 J11 VDDCORE K22 VDDPEA F16 NC H1 VSS J12 VDDCORE K23 VDDPEA F17 VSS H2 VSS J13 VSS K24 VDDPEA F18 VSS H3 VDDPEHA J14 VSS K25 VSS F19 VSS H4 VDDPEHA J15 VDDCORE K26 REFRES4 F20 VSS H5 VSS J16 VDDCORE L1 PE3TN01 F21 VSS H6 VSS J17 VSS L2 PE3TP01 F22 VSS H7 VDDCORE J18 VSS L3 VDDPETA F23 VSS H8 VDDCORE J19 VDDCORE L4 PE3RN01 F24 VDDPEA H9 VSS J20 VDDCORE L5 PE3RP01 F25 VDDCORE H10 VSS J21 VSS L6 VSS F26 VDDCORE H11 VDDCORE J22 PE4RP01 L7 VDDCORE G1 PE3TN03 H12 VDDCORE J23 PE4RN01 L8 VDDCORE G2 PE3TP03 H13 VSS J24 VDDPETA L9 VSS G3 VDDPETA H14 VSS J25 PE4TP01 L10 VSS G4 PE3RN03 H15 VDDCORE J26 PE4TN01 L11 VDDCORE G5 PE3RP03 H16 VDDCORE K1 REFRES3 L12 VDDCORE G6 VSS H17 VSS K2 VSS L13 VSS G7 VSS H18 VSS K3 VDDPEA L14 VSS G8 VSS H19 VDDCORE K4 VDDPEA L15 VDDCORE G9 VSS H20 VDDCORE K5 VDDPEA L16 VDDCORE G10 VSS H21 VSS K6 VSS L17 VSS G11 VSS H22 VSS K7 VDDCORE L18 VSS G12 VSS H23 VDDPEHA K8 VDDCORE L19 VDDCORE G13 VSS H24 VDDPEHA K9 VSS L20 VDDCORE G14 VSS H25 VSS K10 VSS L21 VSS G15 VSS H26 VSS K11 VDDCORE L22 PE4RP02 G16 VSS J1 PE3TN02 K12 VDDCORE L23 PE4RN02 G17 VSS J2 PE3TP02 K13 VSS L24 VDDPETA Alt Table 25 PES24T6G2 (27x27mm 676-Pin) Signal Pin-Out (Part 2 of 5) 33 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Pin Function Alt Pin Function Alt Pin Function Alt Pin Function L25 PE4TP02 N10 VSS P21 VSS T6 NC L26 PE4TN02 N11 VDDCORE P22 VSS T7 VDDCORE M1 VDDCORE N12 VDDCORE P23 VDDPEHA T8 VDDCORE M2 VSS N13 VSS P24 VDDPEHA T9 VSS M3 VDDPEHA N14 VSS P25 VSS T10 VSS M4 VDDPEHA N15 VDDCORE P26 VDDCORE T11 VDDCORE M5 VSS N16 VDDCORE R1 PE2TN03 T12 VDDCORE M6 NC N17 VSS R2 PE2TP03 T13 VSS M7 VDDCORE N18 VSS R3 VDDPETA T14 VSS M8 VDDCORE N19 VDDCORE R4 PE2RN03 T15 VDDCORE M9 VSS N20 VDDCORE R5 PE2RP03 T16 VDDCORE M10 VSS N21 VSS R6 VSS T17 VSS M11 VDDCORE N22 PE4RP03 R7 VDDCORE T18 VSS M12 VDDCORE N23 PE4RN03 R8 VDDCORE T19 VDDCORE M13 VSS N24 VDDPETA R9 VSS T20 VDDCORE M14 VSS N25 PE4TP03 R10 VSS T21 NC M15 VDDCORE N26 PE4TN03 R11 VDDCORE T22 VSS M16 VDDCORE P1 VDDCORE R12 VDDCORE T23 VDDPEA M17 VSS P2 VSS R13 VSS T24 VDDPEA M18 VSS P3 VDDPEHA R14 VSS T25 VSS M19 VDDCORE P4 VDDPEHA R15 VDDCORE T26 VDDCORE M20 VDDCORE P5 VSS R16 VDDCORE U1 PE2TN02 M21 NC P6 VSS R17 VSS U2 PE2TP02 M22 VSS P7 VDDCORE R18 VSS U3 VDDPETA M23 VDDPEHA P8 VDDCORE R19 VDDCORE U4 PE2RN02 M24 VDDPEHA P9 VSS R20 VDDCORE U5 PE2RP02 M25 VSS P10 VSS R21 VSS U6 VSS M26 VDDCORE P11 VDDCORE R22 PE5RP00 U7 VDDCORE N1 PE3TN00 P12 VDDCORE R23 PE5RN00 U8 VDDCORE N2 PE3TP00 P13 VSS R24 VDDPETA U9 VSS N3 VDDPETA P14 VSS R25 PE5TP00 U10 VSS N4 PE3RN00 P15 VDDCORE R26 PE5TN00 U11 VDDCORE N5 PE3RP00 P16 VDDCORE T1 VDDCORE U12 VDDCORE N6 VSS P17 VSS T2 VSS U13 VSS N7 VDDCORE P18 VSS T3 VDDPEA U14 VSS N8 VDDCORE P19 VDDCORE T4 VDDPEA U15 VDDCORE N9 VSS P20 VDDCORE T5 VSS U16 VDDCORE Alt Table 25 PES24T6G2 (27x27mm 676-Pin) Signal Pin-Out (Part 3 of 5) 34 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Pin Function Alt Pin Function Alt Pin Function Alt Pin Function U17 VSS W2 PE2TP01 Y13 VSS AA24 VDDPETA U18 VSS W3 VDDPETA Y14 VSS AA25 PE5TP03 U19 VDDCORE W4 PE2RN01 Y15 VDDCORE AA26 PE5TN03 U20 VDDCORE W5 PE2RP01 Y16 VDDCORE AB1 VSS U21 VSS W6 VSS Y17 VSS AB2 VSS U22 PE5RP01 W7 VDDCORE Y18 VSS AB3 VDDCORE U23 PE5RN01 W8 VDDCORE Y19 VDDCORE AB4 VDDCORE U24 VDDPETA W9 VSS Y20 VDDCORE AB5 VDDCORE U25 PE5TP01 W10 VSS Y21 VSS AB6 VSS U26 PE5TN01 W11 VDDCORE Y22 VSS AB7 PE1RP03 V1 VDDCORE W12 VDDCORE Y23 VDDPEHA AB8 VSS V2 VSS W13 VSS Y24 VDDPEHA AB9 PE1RP02 V3 VDDPEA W14 VSS Y25 VSS AB10 VDDPEA V4 VDDPEA W15 VDDCORE Y26 REFRES5 AB11 PE1RP01 V5 VDDPEA W16 VDDCORE AA1 PE2TN00 AB12 VSS V6 VSS W17 VSS AA2 PE2TP00 AB13 PE1RP00 V7 VDDCORE W18 VSS AA3 VDDPETA AB14 VDDPEA V8 VDDCORE W19 VDDCORE AA4 PE2RN00 AB15 PE0RP03 V9 VSS W20 VDDCORE AA5 PE2RP00 AB16 VSS V10 VSS W21 VSS AA6 VSS AB17 PE0RP02 V11 VDDCORE W22 PE5RP02 AA7 VSS AB18 VDDPEA V12 VDDCORE W23 PE5RN02 AA8 VSS AB19 PE0RP01 V13 VSS W24 VDDPETA AA9 VSS AB20 VSS V14 VSS W25 PE5TP02 AA10 VSS AB21 PE0RP00 V15 VDDCORE W26 PE5TN02 AA11 VSS AB22 VSS V16 VDDCORE Y1 REFRES2 AA12 NC AB23 VDDCORE V17 VSS Y2 VSS AA13 VSS AB24 VDDCORE V18 VSS Y3 VDDPEHA AA14 VSS AB25 VSS V19 VDDCORE Y4 VDDPEHA AA15 VSS AB26 VSS V20 VDDCORE Y5 VSS AA16 NC AC1 VSS V21 VSS Y6 VSS AA17 VSS AC2 VSS V22 VDDPEA Y7 VDDCORE AA18 VSS AC3 VDDCORE V23 VDDPEA Y8 VDDCORE AA19 VSS AC4 VDDCORE V24 VDDPEA Y9 VSS AA20 VSS AC5 VDDCORE V25 VSS Y10 VSS AA21 VSS AC6 VDDPEHA V26 VDDCORE Y11 VDDCORE AA22 PE5RP03 AC7 PE1RN03 W1 PE2TN01 Y12 VDDCORE AA23 PE5RN03 AC8 VDDPEA Alt Table 25 PES24T6G2 (27x27mm 676-Pin) Signal Pin-Out (Part 4 of 5) 35 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Pin Function Alt Pin Function Alt Pin Function Alt Pin Function AC9 PE1RN02 AD7 VSS AE5 VSS AF3 VDDCORE AC10 VDDPEA AD8 VDDPETA AE6 VSS AF4 VDDCORE AC11 PE1RN01 AD9 VSS AE7 PE1TP03 AF5 VDDCORE AC12 VDDPEHA AD10 VDDPETA AE8 VSS AF6 VSS AC13 PE1RN00 AD11 VDDPETA AE9 PE1TP02 AF7 PE1TN03 AC14 VDDPEHA AD12 VDDPEHA AE10 VSS AF8 REFRES1 AC15 PE0RN03 AD13 VDDPETA AE11 PE1TP01 AF9 PE1TN02 AC16 VDDPEA AD14 VDDPEHA AE12 VSS AF10 VDDCORE AC17 PE0RN02 AD15 VDDPETA AE13 PE1TP00 AF11 PE1TN01 AC18 VDDPEA AD16 VDDPEA AE14 VSS AF12 VDDCORE AC19 PE0RN01 AD17 VSS AE15 PE0TP03 AF13 PE1TN00 AC20 VDDPEHA AD18 VDDPETA AE16 VSS AF14 VDDCORE AC21 PE0RN00 AD19 VDDPETA AE17 PE0TP02 AF15 PE0TN03 AC22 VSS AD20 VDDPEHA AE18 VSS AF16 VDDCORE AC23 VDDCORE AD21 VDDPETA AE19 PE0TP01 AF17 PE0TN02 AC24 VDDCORE AD22 VSS AE20 VSS AF18 REFRES0 AC25 VSS AD23 VDDCORE AE21 PE0TP00 AF19 PE0TN01 AC26 VSS AD24 VDDCORE AE22 VSS AF20 VSS AD1 VSS AD25 VSS AE23 VDDCORE AF21 PE0TN00 AD2 VSS AD26 VSS AE24 VDDCORE AF22 VSS AD3 VDDCORE AE1 VSS AE25 VSS AF23 VDDCORE AD4 VDDCORE AE2 VSS AE26 VSS AF24 VDDCORE AD5 VDDCORE AE3 VDDCORE AF1 VSS AF25 VSS AD6 VDDPEHA AE4 VDDCORE AF2 VSS AF26 VSS Alt Table 25 PES24T6G2 (27x27mm 676-Pin) Signal Pin-Out (Part 5 of 5) 36 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Option B Package -- Core Power Pins VDDCore VDDCore VDDCore VDDCore VDDCore C4 H16 M19 T15 Y12 C14 H19 M20 T16 Y15 C16 H20 M26 T19 Y16 D5 J7 N7 T20 Y19 D6 J8 N8 T26 Y20 D8 J11 N11 U7 AB3 D10 J12 N12 U8 AB4 D12 J15 N15 U11 AB5 D13 J16 N16 U12 AB23 D15 J19 N19 U15 AB24 D17 J20 N20 U16 AC3 D18 K7 P1 U19 AC4 D19 K8 P7 U20 AC5 D21 K11 P8 V1 AC23 D22 K12 P11 V7 AC24 E6 K15 P12 V8 AD3 E7 K16 P15 V11 AD4 E9 K19 P16 V12 AD5 E11 K20 P19 V15 AD23 E13 L7 P29 V16 AD24 E15 L8 P26 V19 AE3 E17 L11 R7 V20 AE4 E19 L12 R8 V26 AE23 E20 L15 R11 W7 AE24 E21 L16 R12 W8 AF3 F1 L19 R15 W11 AF4 F2 L20 R16 W12 AF5 F25 M1 R19 W15 AF10 F26 M7 R20 W16 AF12 H7 M8 T1 W19 AF14 H8 M11 T7 W20 AF16 H11 M12 T8 Y7 AF23 H12 M15 T11 Y8 AF24 H15 M16 T12 Y11 Table 26 PES24T6G2 (27x27mm 676-Pin) Core Power Pins 37 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Option B Package -- I/O, PCIe, and Transmitter Power Pins VDDI/O VDDPEA VDDPEHA VDDPETA A3 F3 H3 G3 B3 F24 H4 G24 B17 K3 H23 J3 B24 K4 H24 J24 C5 K5 M3 L3 C7 K22 M4 L24 C9 K23 M23 N3 C11 K24 M24 N24 C13 T3 P3 R3 C15 T4 P4 R24 C17 T23 P23 U3 C19 T24 P24 U24 C21 V3 Y3 W3 C23 V4 Y4 W24 F6 V5 Y23 AA3 V22 Y24 AA24 V23 AC6 AD8 V24 AC12 AD10 AB10 AC14 AD11 AB14 AC20 AD13 AB18 AD6 AD15 AC8 AD12 AD18 AC10 AD14 AD19 AC16 AD20 AD21 1. AC18 AD16 Table 27 PES24T6G2 (27x27mm 676-Pin) I/O, PCIe, and Transmitter Power Pins 38 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Option B Package -- Ground Pins Vss Vss Vss Vss Vss Vss Vss Vss A1 E3 G9 J18 N13 T22 Y13 AC22 A2 E4 G10 J21 N14 T25 Y14 AC25 A14 E8 G11 K2 N17 U6 Y17 AC26 A23 E10 G12 K6 N18 U9 Y18 AD1 A25 E12 G13 K9 N21 U10 Y21 AD2 A26 E14 G14 K10 P2 U13 Y22 AD7 B1 E16 G15 K13 P5 U14 Y25 AD9 B2 E18 G16 K14 P6 U17 AA6 AD17 B13 E22 G17 K17 P9 U18 AA7 AD22 B16 E23 G18 K18 P10 U21 AA8 AD25 B25 E24 G19 K21 P13 V2 AA9 AD26 B26 E25 G20 K25 P14 V6 AA10 AE1 C2 E26 G21 L6 P17 V9 AA11 AE2 C6 F4 H1 L9 P18 V10 AA13 AE5 C8 F5 H2 L10 P21 V13 AA14 AE6 C10 F7 H5 L13 P22 V14 AA15 AE8 C12 F8 H6 L14 P25 V17 AA17 AE10 C18 F9 H9 L17 R6 V18 AA18 AE12 C20 F10 H10 L18 R9 V21 AA19 AE14 C24 F11 H13 L21 R10 V25 AA20 AE16 C25 F13 H14 M2 R13 W6 AA21 AE18 D2 F14 H17 M5 R14 W9 AB1 AE20 D3 F15 H18 M9 R17 W10 AB2 AE22 D7 F17 H21 M10 R18 W13 AB6 AE25 D9 F18 H22 M13 R21 W14 AB8 AE26 D11 F19 H25 M14 T2 W17 AB12 AF1 D14 F20 H26 M17 T5 W18 AB16 AF2 D16 F21 J6 M18 T9 W21 AB20 AF6 D20 F22 J9 M22 T10 Y2 AB22 AF20 D24 F23 J10 M25 T13 Y5 AB25 AF22 D25 G6 J13 N6 T14 Y6 AB26 AF25 E1 G7 J14 N9 T17 Y9 AC1 AF26 E2 G8 J17 N10 T18 Y10 AC2 Table 28 PES24T6G2 (27x27mm 676-Pin) Ground Pins 39 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Option B Package -- Alternate Signal Functions Pin GPIO Alternate B18 GPIO[0] P2RSTN A19 GPIO[1] P4RSTN B19 GPIO[2] IOEXPINTN0 A20 GPIO[3] IOEXPINTN1 B20 GPIO[4] IOEXPINTN2 A21 GPIO[5] IOEXPINTN3 A22 GPIO[7] GPEN D23 GPIO[8] P1RSTN A24 GPIO[9] P3RSTN C22 GPIO[10] P5RSTN Table 29 PES24T6G2 (27x27mm 676-Pin) Alternate Signal Functions Option B Package -- No Connection Pins NC Pins A16 C26 D26 F12 F16 M6 M21 T6 T21 AA12 AA16 Table 30 PES24T6G2 (27x27mm 676-Pin) No Connection Pins 40 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Option B Package -- Signals Listed Alphabetically Signal Name I/O Type Location Signal Category CCLKDS I A13 System CCLKUS I A12 GPIO_00 I/O B18 GPIO_01 I/O A19 GPIO_02 I/O B19 GPIO_03 I/O A20 GPIO_04 I/O B20 GPIO_05 I/O A21 GPIO_06 I/O B21 GPIO_07 I/O A22 GPIO_08 I/O D23 GPIO_09 I/O A24 GPIO_10 I/O C22 JTAG_TCK I B4 JTAG_TDI I A4 JTAG_TDO O B5 JTAG_TMS I A5 JTAG_TRST_N I B6 MSMBADDR_1 I A6 MSMBADDR_2 I B7 MSMBADDR_3 I A7 MSMBADDR_4 I B8 MSMBCLK I/O A8 MSMBDAT I/O B9 I B22 MSMBSMODE NO CONNECTION General Purpose Input/Output JTAG SMBus System See Table 30 for a list of No Connect pins. P01MERGEN I E5 P23MERGEN I C3 P45MERGEN I D4 System Table 31 PES24T6G2 (27x27mm 676-Pin) Alphabetical Signal List (Part 1 of 5) 41 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Signal Name I/O Type Location Signal Category PE0RN00 I AC21 PCI Express PE0RN01 I AC19 PE0RN02 I AC17 PE0RN03 I AC15 PE0RP00 I AB21 PE0RP01 I AB19 PE0RP02 I AB17 PE0RP03 I AB15 PE0TN00 O AF21 PE0TN01 O AF19 PE0TN02 O AF17 PE0TN03 O AF15 PE0TP00 O AE21 PE0TP01 O AE19 PE0TP02 O AE17 PE0TP03 O AE15 PE1RN00 I AC13 PE1RN01 I AC11 PE1RN02 I AC9 PE1RN03 I AC7 PE1RP00 I AB13 PE1RP01 I AB11 PE1RP02 I AB9 PE1RP03 I AB7 PE1TN00 O AF13 PE1TN01 O AF11 PE1TN02 O AF9 PE1TN03 O AF7 PE1TP00 O AE13 PE1TP01 O AE11 PE1TP02 O AE9 PE1TP03 O AE7 PE2RN00 I AA4 PE2RN01 I W4 PE2RN02 I U4 PE2RN03 I R4 Table 31 PES24T6G2 (27x27mm 676-Pin) Alphabetical Signal List (Part 2 of 5) 42 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Signal Name I/O Type Location Signal Category PE2RP00 I AA5 PCI Express (cont.) PE2RP01 I W5 PE2RP02 I U5 PE2RP03 I R5 PE2TN00 O AA1 PE2TN01 O W1 PE2TN02 O U1 PE2TN03 O R1 PE2TP00 O AA2 PE2TP01 O W2 PE2TP02 O U2 PE2TP03 O R2 PE3RN00 I N4 PE3RN01 I L4 PE3RN02 I J4 PE3RN03 I G4 PE3RP00 I N5 PE3RP01 I L5 PE3RP02 I J5 PE3RP03 I G5 PE3TN00 O N1 PE3TN01 O L1 PE3TN02 O J1 PE3TN03 O G1 PE3TP00 O N2 PE3TP01 O L2 PE3TP02 O J2 PE3TP03 O G2 PE4RN00 I G23 PE4RN01 I J23 PE4RN02 I L23 PE4RN03 I N23 PE4RP00 I G22 PE4RP01 I J22 PE4RP02 I L22 PE4RP03 I N22 Table 31 PES24T6G2 (27x27mm 676-Pin) Alphabetical Signal List (Part 3 of 5) 43 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Signal Name I/O Type Location Signal Category PE4TN00 O G26 PCI Express (cont.) PE4TN01 O J26 PE4TN02 O L26 PE4TN03 O N26 PE4TP00 O G25 PE4TP01 O J25 PE4TP02 O L25 PE4TP03 O N25 PE5RN00 I R23 PE5RN01 I U23 PE5RN02 I W23 PE5RN03 I AA23 PE5RP00 I R22 PE5RP01 I U22 PE5RP02 I W22 PE5RP03 I AA22 PE5TN00 O R26 PE5TN01 O U26 PE5TN02 O W26 PE5TN03 O AA26 PE5TP00 O R25 PE5TP01 O U25 PE5TP02 O W25 PE5TP03 O AA25 PEREFCLKN I C1 PEREFCLKP I D1 PERSTN I A17 System REFCLKM I B23 PCI Express REFRES0 I/O AF18 SerDes Reference Resistors REFRES1 I/O AF8 REFRES2 I/O Y1 REFRES3 I/O K1 REFRES4 I/O K26 REFRES5 I/O Y26 RSTHALT I A18 System Table 31 PES24T6G2 (27x27mm 676-Pin) Alphabetical Signal List (Part 4 of 5) 44 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Signal Name I/O Type Location Signal Category SSMBADDR_1 I A9 SMBus SSMBADDR_2 I B10 SSMBADDR_3 I A10 SSMBADDR_5 I B11 SSMBCLK I/O A11 SSMBDAT I/O B12 SWMODE_0 I B14 SWMODE_1 I A15 SWMODE_2 I B15 VDDCORE, VDDI/O, VDDPEA, VDDPEHA, VDDPETA VSS System See Tables 26 and 27 for a listing of power pins. See Table 28 for a listing of ground pins. Table 31 PES24T6G2 (27x27mm 676-Pin) Alphabetical Signal List (Part 5 of 5) 45 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Option B Package Pinout -- Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A A B B C C D D E E F F X X G G H H X J X J K K X X L L M M X X N N P P X X R R T T X X U U V V W X X W Y Y X X AA AA AB AB AC AC X AD X X X X X X X AD AE AE AF AF 1 2 3 4 5 6 7 8 X 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 VDDPETA (Transmitter Power) Signals VDDI/O (Power) VDDPEA (Analog Power) No Connect Vss (Ground) VDDPEHA (High Analog Power) VDDCore (Power) 46 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Option B Package Drawing -- 676-Pin BL676/BLG676 47 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Option B Package Drawing -- Page Two 48 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Revision History January 15, 2009: Publication of final data sheet. February 11, 2009: Revised AC Timing Characteristics table and DC Electrical Characteristics table to correct typos. 49 of 50 February 11, 2009 IDT 89HPES24T6G2 Data Sheet Ordering Information NN A AAA NNAN Product Family Operating Voltage Device Family Product Detail AN AA AA Generation Device Revision Series A Package Temp Range Legend A = Alpha Character N = Numeric Character Blank Commercial Temperature (0C to +70C Ambient) AL ALG BL BLG 324-ball FCBGA 324-ball FCBGA, Green 676-ball FCBGA 676-ball FCBGA, Green ZB ZC ZB revision ZC revision G2 PCIe Gen 2 24T6 24-lane, 6-port PES PCI Express Switch H 1.0V +/- 0.1V Core Voltage 89 Serial Switching Product Valid Combinations Option A (19x19mm) 89HPES24T6G2ZBAL 324-ball FCBGA package, Commercial Temperature 89HPES24T6G2ZBALG 324-ball Green FCBGA package, Commercial Temperature 89HPES24T6G2ZCAL 324-ball FCBGA package, Commercial Temperature 89HPES24T6G2ZCALG 324-ball Green FCBGA package, Commercial Temperature Option B (27x27mm) 89HPES24T6G2ZBBL 676-ball FCBGA package, Commercial Temperature 89HPES24T6G2ZBBLG 676-ball Green FCBGA package, Commercial Temperature 89HPES24T6G2ZCBL 676-ball FCBGA package, Commercial Temperature 89HPES24T6G2ZCBLG 676-ball Green FCBGA package, Commercial Temperature (R) CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 50 of 50 for Tech Support: email: ssdhelp@idt.com phone: 408-284-8208 February 11, 2009