9-203
DISPLAYS
LTM-8647AY
LTM-8647AE
SymbolParameter
Average Luminous Intensity
Peak Emission Wavelength
Spectral Line Half-Width
Dominant Wavelength
Luminous Intensity Matching Ratio
IV
P
d
IV-m
Min.
800
Typ.
2300
585
35
588
Max.
2:1
Unit
cd
nm
nm
nm
Test
Condition
IB=0.4mA
IB=0.4mA
IB=0.4mA
IF=20mA
IB=0.4mA
LTM-8647AHR
SymbolParameter
Average Luminous Intensity
Peak Emission Wavelength
Spectral Line Half-Width
Dominant Wavelength
Luminous Intensity Matching Ratio
IV
P
d
IV-m
Min.
800
Typ.
2300
630
40
621
Max.
2:1
Unit
cd
nm
nm
nm
Test
Condition
IB=0.4mA
IB=0.4mA
IB=0.4mA
IF=20mA
IB=0.4mA
SymbolParameter
Average Luminous Intensity
Peak Emission Wavelength
Spectral Line Half-Width
Dominant Wavelength
Luminous Intensity Matching Ratio
IV
P
d
IV-m
Min.
800
Typ.
2300
635
40
623
Max.
2:1
Unit
cd
nm
nm
nm
Test
Condition
IB=0.4mA
IB=0.4mA
IB=0.4mA
IF=20mA
IB=0.4mA
Notes: Luminous intensity is measured with a light sensor and filter combination that appoximates the CIE (Commision
Internationale De L'Eclairage)eye-response curve.
Functional Description
Serial data transfer from the data source to the display driver is accomplished with 2 signals serial data and clock.
Using a format of a leading "1" followed by the 35 data bits allows data transfer without an additional load signal.
The 35 data bits are latched after the 36th bit is completed, thus provding non multiplexed, direct drive to the display.
Output change only if the serial data bits differ from the previous time.
Brightness of display is determined by control the output current of LED display. A 1nF capacitor Should be connected
to brightness control, Pin 7 to prevent possible oscillations. The output current is typically 25 times greater than the
current into Pin 7 which is set by an external variable resistor. There is an internal limiting resistor of 400 nominal
value.
Figure 1 shows the input data format. A start bit of logical "1" preceed the 35 bits of data. At the 36th clock, a LOAD
signal is generated synchronously with the high state of the clock, which loads the 35 bits of the shift registers into
the latches. At the low state of the clock a RESET signal is generated which clears all the shift registers for the next
set of data . The shift registers are static master-salve configuration. There is no clear for master portion of the first
register, thus allowing continuous operation.
There must be a complete set of 36 clocks or the shift registers won't clear. When power is first applied to the chip,
an internal power ON, a reset signal is generated which reset all registers and all latches. The START bit and first
clock return the chip on its normal operation. Bit 1 is the first following the start bit and it will appear on the segment
A of the digit 1. A logical "1" at the input will turn on the appropriate LED. Figure 2 shows the timing relationship between
data, clock, and DATA ENABLE. A max. clock frequency of0.5MHz is assumed.