DM74LS164MX - Fairchild Semiconductor

August 1986

Revised April 2000

DM74LS164 8-Bit Serial In/Parallel Out Shift Register

DM74LS164

8-Bit Serial In/Parallel Out Shift Register

General Descript ion

These 8-bit shift registers feature gated serial inputs and

an asynchronous clear. A low logic level at either input

inhibits entry of the new data, and resets the first flip-flop to

the low level at the next clock pulse, thus providing com-

plete control over incoming data. A high logic level on

either input enables the other input, which will then deter-

mine the stat e of the first f lip-flop. Data a t the serial inp uts

may be changed w hile th e cloc k is HIG H or LOW, but only

informati on meeting th e setup and hol d time require ments

will be entered. Clocking occurs on the LOW-to-HIGH level

transition of the clock input. All inputs are diode-clamped to

minimize transmission-line effects.

Features

■Gated (enable/disable) serial inputs

■Fully buffered clock and serial inputs

■Asynchronous clear

■Typical clock frequency 36 MHz

■Typical power dissipation 80 mW

Ordering Code:

Devices also available in Tape and R eel. Speci fy by appending the s uffix let t er “X” to the o rdering c ode.

Connection Diagram Function Table

H = HIGH Level (steady state)

L = LOW Level (steady state)

X = Don't Care (a ny input, inc luding transition s )

↑ = Transition from LOW-to-HIGH level

QA0, QB0, QH0 = The level o f QA, QB, or QH, res pec t iv ely, before the

indica t ed s t eady-st at e input co nditions w ere estab lis hed.

QAn, QGn = The level of QA or QG before the most recent ↑ transition of the

clock ; in dic ates a one-bit sh ift.

Order Number Package Number Package Description

DM74LS164M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

DM74LS164N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Inputs Outputs

Clear Clock A B QAQB... QH

LXXXLL...L

HLXXQ

A0 QB0 ... QH0

H↑HHHQ

An ... QGn

H↑LX L Q

An ... QGn

H↑XL L Q

An ... QGn

www.fairchildsemi.com 2

DM74LS164

Logic Diagram

Timing Diagr am

3 www.fairchildsemi.com

DM74LS164

Absolute Maximum Ratings(Note 1) Note 1: The “Abso lute Maximum Ratings” ar e those value s beyond which

the safety of the device cannot be guaranteed. The device should not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum ratings.

The “Rec ommended Ope rating Conditions ” t ables will def ine the cond it ions

for actu al device operation.

Recommended Operating Conditions

Note 2: TA = 25°C and VCC = 5V.

Electri cal Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Note 3: All typicals are at VCC = 5V, TA = 25 °C.

Note 4: N ot m ore than one output sh ould be sh orted at a tim e, and the duration sh ould not ex c eed one sec ond.

Note 5: ICC is mea sure d w ith al l ou tputs OPE N, th e S ERIAL in put g round ed , the C LOC K in put a t 2. 4V, and a mo men tary grou nd , then 4 .5V, app lied to the

CLEAR input.

Switching Characteristics

at VCC = 5V and TA = 25°C

Supply Voltage 7V

Input Voltage 7V

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range −65°C to +150°C

Symbol Parameter Min Nom Max Units

VCC Supply Voltage 4.75 5 5.25 V

VIH HIGH Level Input Voltage 2 V

VIL LOW Level Input Voltage 0.8 V

IOH HIGH Level Output Current −0.4 mA

IOL LOW Level Output Current 8 mA

fCLK Clock Frequency (Note 2) 0 25 MHz

tWPulse Width Clock 20 ns

(Note 2) Clear 20

tSU Data Setup Time (Note 2) 17 ns

tHData Hold Time (Note 2) 5 ns

tREL Clear Release Time (Note 2) 30 ns

TAFree Air Operating Temperature 0 70 °C

Symbol Parameter Conditions Min Typ

(Note 3) Max Units

VIInput Clamp Voltage VCC = Min, II = −18 mA −1.5 V

VOH HIGH Level VCC = Min, IOH = Max 2.7 3.4 V

Output Voltage VIL = Max, VIH = Min

VOL LOW Level VCC = Min, IOL = Max 0.35 0.5

Output Voltage VIL = Max, VIH = Min V

IOL = 4 mA, VCC = Min 0.25 0.4

IIInput Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 mA

IIH HIGH Level Input Current VCC = Max, VI = 2.7V 20 µA

IIL LOW Level Input Current VCC = Max, VI = 0.4V −0.4 mA

IOS Short Circuit Output Current VCC = Max (Note 4) −20 −100 mA

ICC Supply Current VCC = Max (Note 5) 16 27 mA

From (Input) RL = 2 kΩ

Symbol Parameter To (Output) CL = 15 pF CL = 50 pF Units

MinMaxMinMax

fMAX Maximum Clock Frequency 25 MHz

tPLH Propagation Delay Time Clock to Output 27 30 ns

LOW-to-HIGH Level Output

tPHL Propagation Delay Time Clock to Output 32 40 ns

HIGH-to-LOW Level Output

tPHL Propagation Delay Time Clear to Output 36 45 ns

HIGH-to-LOW Level Output

www.fairchildsemi.com 4

DM74LS164

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

Package Number M14A

5 www.fairchildsemi.com

DM74LS164 8-Bit Serial In/Parallel Out Shift Register

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Packag e Num be r N14A

Fairchild does not assume any responsibility for use of any circu itry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life sup por t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the labe l ing, can be re a-

sonably expected to result in a significant injury to the

user.

2. A c ritica l com ponen t in any compo nent o f a lif e supp ort

device or system whose failure to perform can be rea-

sonabl y e xpec ted to c ause th e fa i lure of the li fe s upp or t

device or system, or to affect its safety or effectiveness.