Am188EM-40KCW - Advanced Micro Devices

PRELIMINARY

This document contains information on a product under development at Advanced Micro Devices. The information

is intended to h elp you evaluate t his product. AMD reserves t he right to cha nge or discontinue work o n this proposed

product without notice.

Publication# 19168 Re v: EAmendment/0

Issue Date: February 1997

Am186TMEM/EMLV and Am188TMEM/EMLV

High Performance, 80C186-/80C188-Compatible and

80L186-/80L188-Compatib le, 16-Bit Embedded Microcontrollers

DISTINCTIVE CHARACTERISTICS

nE86TM family 80C186- and 80C188-compatible

microcontrollers with enhanced bus interface

— Lower system cost with higher performance

— 3.3-V ±.3-V operation (Am186EMLV and

Am188EMLV microcontrollers)

nHigh performance

— 20-, 25-, 33-, and 40-MHz operating frequencies

— Supports zero-wait-state operation at 25 MHz

with 110-ns static memory (Am186TMEMLV and

Am188TMEMLV microcontrollers) and 40 MHz

with 70-ns static memory (Am186TMEM and

Am188TMEM microcontrollers)

— 1-Mbyte memory address space

— 64-Kbyte I/O space

nNew features provide faster access to memory and

remove the requirement for a 2x clock input

— Nonmultiplexed address bus

— Phase-locked loop (PLL) allows processor to

operate at the clock input frequency

nNew integrated peripherals provide increased

functionality while reducing system cost

— Thirty-two programmable I/O (PIO) pins

— Asynchr onous serial port a llows full-duplex , 7-bit

or 8-bit data transfers

— Synchronous serial interface allows half-duplex,

bidirectional data transfer to and from ASICs

— Pseudo static RAM (PSRAM) controller includes

auto refresh capability

— Reset configuration register

nFamiliar 80C186/80L186 peripherals

— Two independent DMA channels

— Programmable interrupt controller with six

external interrupts

— Three programmable 16-bit timers—timer 1 can

be used as a watchdog interrupt timer

— Programmable memory and peripheral

chip-select logic

— Programmable wait state generator

— Power- sav e cloc k div id er

nSoftware-compatible with the 80C186/80C188

and 80L186 /80L188 microcontrollers

nWidely available native development tools,

applications, and system software

nAvailable in the following packages:

— 100-pin, thin quad flat pack (TQFP)

— 100-pin, plastic quad flat pack (PQFP)

GENERAL DESCRIPTION

The Am186 TMEM/EMLV and Am188TMEM/EMLV micro-

controllers are the ideal upgrade for 80C186/188 and

80L186/188 microcontroller designs requiring 80C186/

188 and 80L186/188 microcontroller compatibility, in-

crease d per forman ce, s erial c ommun icati ons, a nd a d i-

rect bus interface. The Am186EM/EMLV and

Am188EM/EMLV microcontrollers increase the perfor-

mance of existing 80C186/188 and 80L186/188 sys-

tems while decreasing their cost.

The Am186EM/EMLV and Am188EM/EMLV microcon-

tr o ll er s ar e p ar t o f th e AM D E86 family of embedded mi-

crocontrollers and microprocessors based on the x86

architecture. The E86 family includes the 16- and 32-bit mi-

crocon trollers and micro processors descr ibed on page 8

The Am186EM/EMLV and Am188EM/EMLV microcon-

trollers integrate the functions of the CPU, nonmulti-

plexed address bus, timers, chip selects, interrupt

controller, DMA controller, PSRAM controller, asynchro-

nous s erial port, synchronous s erial interf ace, and pr o-

grammable I/O (PIO) pins on one chip. Compared to the

80C186/188 and 80L186/188 microcontrollers, the

Am186EM/EMLV and Am188EM/EMLV microcontrol-

lers enable designers to reduce the size, power con-

sumption, and cost of embedded systems, while

increasing functionality and performance.

The Am186EM/EMLV and Am188EM/EMLV microcon-

trollers have been desig ned to meet the mo st common

requirements of embedded products developed for the

office automation, mass storage, communications, and

general embedded markets. Specific applications in-

clude di sk driv es, hand-he ld termi nals and desktop ter-

minals, fax machines, printers, photocopiers, feature

phones, cellular phones, PBXs, multiplexers, modems,

and industrial controls.

2 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

Am186EM MICROCONTROLLER BLOCK DIAGRAM

Note:

* All PIO s ignals are shar ed with othe r physi cal pin s. See the pin desc riptio ns begi nning o n page 25 and Tabl e 2 on page 30 for

information on shared functions.

Control

S2–S0

Interrupt

Control Unit

Timer Control

Unit DMA

Unit

Bus

Interface

Unit

Execution

Unit Chip-Select

Unit

Clock and

Power

Managem ent

Unit

Control

Registers

16-Bit Count

Registers

Max Count A

Registers 16-Bit Count

Registers

20-Bit Destination

Pointers

20-Bit Source

Pointers

Control

Registers

Control

Registers

Control

Registers

01 (WDT)2 0 1

Max Count B

Registers

Refresh

Control

Unit

Control

Registers Control

Registers

CLKOUTB

CLKOUTA INT4

INT3/INTA1/IRQ

INT2/INTA0

INT1/SELECT

INT0 TMROUT0 TMROUT1

DRQ0 DRQ1

VCC

GND

TMRIN0 TMRIN1

ARDY

SRDY

DT/R

DEN

HOLD

HLDA

Asynchronous

Serial Port

Synchronous Serial

Interface

TXD

RXD

SCLK SDATA

SDEN0 SDEN1

NMI

A19–A0

AD15–AD0

ALE

BHE/ADEN

WLB

WHB

RES

LCS/ONCE0

MCS2–MCS0

PCS6/A2

PCS3–PCS0

PCS5/A1

UCS/ONCE1

Control

Registers

PSRAM

Control

Unit

MCS3/RFSH

PIO

Unit PIO31–

PIO0*

Registers

S6/

UZI

CLKDIV2

Am186/188EM and Am186/188EMLV Microcontrollers 3

PRELIMINARY

Am188EM MICROCONTROLLER BLOCK DIAGRAM

Note:

* All PIO s ignals are shar ed with othe r physi cal pin s. See the pin desc riptio ns begi nning o n page 25 and Tabl e 2 on page 30 for

information on shared functions.

20-Bit Source

Pointers

S2–S0

Interrupt

Control Unit

Timer Control

Unit DMA

Unit

Bus

Interface

Unit

Execution

Unit Chip-Select

Unit

Clock and

Power

Manage men t

Unit

Control

Registers

16-Bit Count

Registers

Max Count A

Registers 16-Bit Count

Registers

20-Bit Destination

Pointers

Control

Registers

Control

Registers

Control

Registers

01 (WDT)2 0 1

Max Count B

Registers

Refresh

Control

Unit

Control

Registers Control

Registers

CLKOUTB

CLKOUTA INT4

INT3/INTA1/IRQ

INT2/INTA0

INT1/SELECT

INT0 TMROUT0 TMROUT1

DRQ0 DRQ1

VCC

GND

TMRIN0 TMRIN1

ARDY

SRDY

DT/R

DEN

HOLD

HLDA

Asynchronous

Serial Port

Synchronous Serial

Interface

TXD

RXD

SCLK SDATA

SDEN0 SDEN1

NMI

S6/

A19–A0

AD7–AD0

ALE

RES

LCS/ONCE0

MCS2–MCS0

PCS6/A2

PCS3–PCS0

PCS5/A1

UCS/ONCE1

UZI

Control

Registers

PSRAM

Control

Unit

MCS3/RFSH

PIO

Unit PIO31–

PIO0*

Control

Registers

AO15–AO8

RFSH2/ADEN

CLKDIV2

4 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

ORDERING INFORMATION

Standard Products

AMD standard pr oducts ar e availa ble in sev eral pa cka ges an d o pe rat ing ra nge s. The ord er n um be rs (v al id com binat ion s) ar e

form ed by a combina tion o f the element s below .

–40Am186EM

–20 = 20 MHz

–25 = 25 MHz

–33 = 33 MHz

–40 = 40 MHz

TEMPERATURE RANGE

C=EMLV Commercial (TA=0°C to +70°C)

SPEED OPTION

DEVICE NUMBER/DESCRIPTION

Am186EM High-Performance, 80C186-Compatible,

16-Bit Embedded Microcontroller

Am188EM High-Performance, 80C188-Compatible,

16-Bit Embedded Microcontroller

Am186EMLV High-Performance, 80L186-Compatible,

Low-Voltage, 16-Bit Embedded Microcontroller

Am188EMLV High-Performance, 80L188-Compatible,

Low-Voltage, 16-Bit Embedded Microcontroller

LEAD FORMING

\W=Trimmed and Formed

Valid combinations list configurations planned to be

supported in volume for this device. Consult the local

AMD sales office to confirm availability of specific valid

combin ations an d to check o n newly relea sed comb i-

nations.

Notes:

1. The Am186EM and Am188EM industrial

microcontrollers, as well as the Am186EMLV and

Am188EMLV commercial microcontrollers, are

available in 20- and 25-MHz operating

frequencies only.

2. The Am186EM and Am188EM industrial

microcontrollers are not offered in a low-voltage

operating range.

3. The Am186EM, Am188EM, Am186EMLV, and

Am188EM LV microco ntrollers a re all functi onally

the same except for their DC characteristics and

available frequencies.

Valid Combinations

Am186EMLV–25

Valid Combinations

PACKAGE TYPE

V=100-pin, thin quad flat pack (TQFP)

K=100-pin, plastic quad flat pack (PQFP)

Am188EMLV–25

Am188EMLV–20

Am186EMLV–20

VC\W or

KC\W

Am186EM–25

Am186EM–33

Am186EM–40

Am188EM–25

Am188EM–33

Am188EM–40

VC\W or

KC\W

Am188EM–20

Am186EM–20

KI\W

Am186EM–25

Am188EM–25 KI\W

Am188EM–20

Am186EM–20

I=EM Industrial (TA=–40°C to +85°C) (5-V only)

Where: TC = case temperature

C=EM Commercial (TC=0°C to +100°C)

TA = ambient temperature

VC\W or

KC\W

VC\W or

KC\W

Am186/188EM and Am186/188EMLV Microcontrollers 5

PRELIMINARY

TABLE OF CONTENTS

Distinctive Characteristics ............................................................................................................ 1

General Description ..................................................................................................................... 1

Am186EM Microcontroller Block Diagram.................................................................................... 2

Am188EM Microcontroller Block Diagram.................................................................................... 3

Ordering Information .................................................................................................................... 4

Related AMD Products ................................................................................................................ 8

Key Features and Benefits ........................................................................................................ 10

TQFP Connection Diagra ms and Pinouts .............. ............................................. .. ......... .. .......... 11

PQFP Connection Diagrams and Pinouts ................................................. .. ......... .. .................. . 17

Logic Symbol—Am186EM Microcontroller ................................................................................ 23

Logic Symbol—Am188EM Microcontroller ................................................................................ 24

Pin Descriptions

Pins that Are Used by Emulators ................................................................................... 25

A19–A0 ........................................................................................................................... 25

AD7–AD0 ....................................................................................................................... 25

AD15–AD8 (Am186EM Microcontroll er)..................... .. .. .. ............ .. .. .. .. .............. .. .. .. .. .... 25

AO15–AO8 (Am188EM Microcontrolle r) ..... .. .. .. .. .. ............ .. .. .. .. .............. .. .. .. .. ............ .. . 25

ALE ................................................................................................................................ 25

ARDY ............................................................................................................................. 25

BHE/ADEN (Am186EM Microcontrolle r Only) .. ............. .............. ............... ....... ............ 26

CLKOUTA ...................................................................................................................... 26

CLKOUTB ...................................................................................................................... 26

DEN/PIO5 ...................................................................................................................... 26

DRQ1–DRQ0.................................................................................................................. 26

DT/R/PIO4 ..................................................................................................................... 26

GND ............................................................................................................................... 27

HLDA ............................................................................................................................. 27

HOLD ............................................................................................................................. 27

INT0 ............................................................................................................................... 27

INT1/SELECT ................................................................................................................ 27

INT2/INTA0/PIO31 ......................................................................................................... 27

INT3/INTA1/IRQ ... ......... ........ ....... ......... ......... ......... ...... ......... ......... ......... ...... ......... ....... 27

INT4/PIO30 .................................................................................................................... 28

LCS/ONCE0 .... ......... ....... ......... ......... ........ ....... ......... ......... ......... ...... ......... ......... ...... ..... 28

MCS3/RFSH/PIO25 ....................................................................................................... 28

MCS2–MCS0.................................................................................................................. 28

NMI ................................................................................................................................ 28

PCS3–PCS0 ................................................................................................................... 29

PCS5/A1/PIO3 ............................................................................................................... 29

PCS6/A2/PIO2 ............................................................................................................... 29

PIO31–PIO0 (Shared) .......................... .. .. .. .............. .. .. .. .. ............ .. .. .. .. .............. .. .. .. .. .... 29

RD .................................................................................................................................. 31

RES .... ......... ......... ......... ...... ......... ......... ......... ...... ......... ......... ....... ......... ........ ......... ....... 31

RFSH2/ADEN (Am188EM Microcontroller Only) ... .. .................. .. .................................. 31

RXD/PIO28 .................................................................................................................... 31

S2–S0 ............................................................................................................................ 31

S6/CLKDIV2/PIO29 ....................................................................................................... 31

SCLK/PIO20 .................................................................................................................. 32

SDATA/PIO21 ................................................................................................................ 32

SDEN1/PIO23, SDEN0/PIO22 ....................................................................................... 32

SRDY/PIO6 .................................................................................................................... 32

TMRIN0/PIO11 .............................................................................................................. 32

6 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

TMRIN1/PIO0 ................................................................................................................ 32

TMROUT0/PIO10 .......................................................................................................... 32

TMROUT1/PIO1 ............................................................................................................ 32

TXD/P IO27 .... ....... ......... ........ ......... ....... ......... ......... ........ ....... ......... ......... ...... ......... ....... 32

UCS/ONCE1 .................................................................................................................. 32

UZI/PIO26 ...................................................................................................................... 33

VCC ................................................................................................................................. 33

WHB (Am186EM Microcontroller Only) ......................................................................... 33

WLB (Am186EM Microcontroller Only)........................................................................... 33

WB (Am188EM Microcontroller Only) ............................................................................ 33

WR ................................................................................................................................. 33

X1 . ...... ....... ...... ..... ...... ....... .... ....... ....... ...... ..... ...... ....... ....... .... ....... ...... ..... ...... ....... ....... .. 3 3

X2 . ...... ....... ...... ..... ...... ....... .... ....... ....... ...... ..... ...... ....... ....... .... ....... ...... ..... ...... ....... ....... .. 3 3

Functional Descriptio n . .................................... .. .................. .. ......... .. .................. .. .................. .. . 34

Bus Ope ra t io n .. ... .. ........... ...... ....... ........... ....... ...... ........... ....... ....... ........... ...... ........... ....... ....... .. 35

Bus Interf ac e Un it .. .. ....... ...... ........... ....... ....... ........... ...... ....... ........... ....... ........... ...... ....... ........... 37

Peripheral Control Block (PCB) ....................... .. .. .. ............ .. .. .. .. .. .............. .. .. .. ............ .. .. .. .. .. .... 38

Clock and Power Management ............... ......... .. .................. .. .................. .. ......... .. .................. .. . 41

Chip-Select Unit.......................................................................................................................... 43

Refresh Control Unit .................................................................................................................. 45

Interrupt Control Unit ................................................................................................................. 45

Timer Control Unit ...................................................................................................................... 46

Direct Memory Access (DMA) ................................................................................................... 46

Asynchronous Serial Port ..... .................................... .. .................. .. ......... .. .................. .. ............ 48

Synchro nous Se rial Interface ............................................ ......... .. ......... ........... ......... .. ............... 48

Programmable I/O (PIO) Pins .................................................................................................... 50

Absolute Maximum Ratings ....................................................................................................... 51

Operating Ranges .............................. .................. .. .................. .. .................. .. .................. .. ........ 51

DC Characteristics Over Comme rci al Operating Range ................ .. .. .. .............. .. .. .. .. ............ .. . 51

Commercial Swit ching Characteristics and Waveforms ........ ........................... .. ....................... 60

Am186/188EM and Am186/188EMLV Microcontrollers 7

PRELIMINARY

LIST OF FIGURES

Figure 1. Example System Design ........................................................................................ 10

Figure 2. Two-Component Address ...................................................................................... 34

Figure 3. Am186EM Microcontroller Address Bus—Normal Read and Write Operation ...... 35

Figure 4. Am186EM Microcontroller—Read and Write with Address Bus

Disable In Effect ..................................................................................................... 36

Figure 5. Am188EM Microcontroller Address Bus—Normal Read and Write Operation ...... 36

Figure 6. Am188EM Microcontroller—Read and Write with Address Bus

Disable In Effect ..................................................................................................... 37

Figure 7. Peripheral Control Block Register Map .................................................................. 39

Figure 8. Am186EM and Am188EM Microcontrollers Oscillator Configurations ................... 41

Figure 9. Clock Organization ................................................................................................ 42

Figure 10. DMA Unit Block Diagram ....................................................................................... 47

Figure 11. Synchronous Serial Interface Multiple Write .......................................................... 49

Figure 12. Synchronous Serial Interface Multiple Read .......................................................... 49

Figure 13. Typical ICC Versus Frequency for the Am186EMLV and Am188EMLV .. .. .. .. .. .. .... 53

Figure 14. Typical ICC Versus Frequency fo r the Am186EM and Am188EM .......... ............... 53

Figure 15. Thermal Resistance(°C/Watt) ................................................................................ 54

Figure 16 . Therm al Ch a ra c te r istics E q uat io n s ... ... ...... ........... ....... ....... ........... ...... ....... ........... 54

Figure 17. Typical Ambient Temperatures for PQFP with 2-Layer Board ............................... 56

Figure 18. Typical Ambient Temperatures for TQFP with 2-Layer Board ...... .. ......... .. ............ 57

Figure 19. Typical Ambient Temperatures for PQFP with 4-Layer to 6-Layer Board ......... .... 58

Figure 20. Typical Ambient Temperatures for TQFP with 4-Layer to 6-Layer Board .............. 59

LIST OF TABLES

Table 1. Data Byte Encoding ............................................................................................... 26

Table 2. Numeric PIO Pin Assignments .............................................................................. 30

Table 3. Alphabetic PIO Pin Assignments ........................................................................... 30

Table 4. Bus Cycle Encoding ............................................................................................... 31

Table 5. Segment Register Selection Rules ........................................................................ 34

Table 6. Am186EM Microcontroller Maximum DMA Transfer Rates .................. .. ............ .. . 46

Table 7. Typical Power Consumption Calculation for the

Am186EMLV and Am188EMLV ............... .. .. ............ .. .. .. .. .............. .. .. .. .. ............ .. . 53

Table 8. Thermal Characteristics (°C/Watt) ......................................................................... 54

Table 9. Typical Power Consumption Calculation ............................................................... 55

Table 10. Junction Temperature Calculation ......................................................................... 55

Table 11. Typical Ambient Temperature s for PQFP with 2- Layer Board .............. ................. 56

Table 12. Typical Ambient Temperature s for TQFP wit h 2-Layer Board ............................... 57

Table 13. Typical Ambient Temperature s for PQFP with 4- Layer to 6-Layer Board .......... ... 58

Table 14. Typical Ambient Temperatures for TQFP with 4-Layer to 6-Layer Board .............. 59

8 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

RELATED AMD PRODUCTS

E86™ Family Devices

Device Description

80C186 16-bit microcontroller

80C188 16-bit microcontroller with 8-bit external data bus

80L186 Low-voltage, 16-bit microcontroller

80L188 Low-voltage, 16-bit microcontroller with 8-bit external data bus

Am186EM High-performance, 80C186-compatible, 16-bit embedded microcontroller

Am188EM High-performance, 80C188-compatible, 16-bit embedded microcontroller with 8-bit external data bus

Am186EMLV High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller

Am188EMLV High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit

external data bus

Am186ES High-performance, 80C186-compatible, 16-bit embedded microcontroller

Am188ES High-performance, 80C188-compatible, 16-bit embedded microcontroller with 8-bit external data bus

Am186ESLV High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller

Am188ESLV High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit

external data bus

Am186ER High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller with 32 Kbyte

of internal RAM

Am188ER High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit ex-

ternal data bus and 32 Kbyte of internal RAM

Élan™SC300 High-performance, highly integrated, low-voltage, 32-bit embedded microcontroller

ÉlanSC310 High-performance, single-chip, 32-bit embedded PC/AT microcontroller

ÉlanSC400 Single-chip, low-power, PC/AT-compatible microcontroller

Am386®DX High-performance, 32-bit embedded microprocessor with 32-bit external data bus

Am386SX High-performance, 32-bit embedded microprocessor with 16-bit external data bus

Am486®DX High-performance, 32-bit embedded microprocessor with 32-bit external data bus

AT Peripheral

Microcontrollers

186 Periphera l

Microcontrollers ÉlanS C 400

Microcontroller

80C186 and 80C1 88

Microcontrollers

Microprocessors

ÉlanSC300

Microcontroller

Am386SX/DX

Microprocessors

Am486DX

Microprocessor

AMD-K5™

Microprocessor

Time

The E86 Family of Embedded Microprocessors and Microcontrollers

Am186 ES and

Am188ES

Microcontrollers

Am186EM and

Am188EM

Microcontrollers

Am186 and

Am188 Fu tur e

ÉlanSC310

Microcontroller

80L186 and 80L188

Microcontrollers

Am186EMLV &

Am188EMLV

Microcontrollers

Am186ESLV &

Am188ESLV

Microcontrollers

32-bit Future

Am186ER and

Am188ER

Microcontrollers

Future

K86™

Am486

Future

Am186/188EM and Am186/188EMLV Microcontrollers 9

PRELIMINARY

Related Documents

The following documents provide additional informa-

tion regarding the Am186EM and Am188EM microcon-

trollers.

nThe Am186EM and Am188EM Microcontrollers

User’s Manual, order# 19713

nThe Am186 and Am188 Family Instruction Set

Manual, order# 21267

nThe FusionE86SM Catalog, order# 19255

Third-Party Development

Support Products

The FusionE86 Program of Partnerships for Applica-

tion Solutions provides the customer with an array of

products designed to meet critical time-to-market

needs. Products and solutions available from the AMD

FusionE86 partners include emulators, hardware and

software debuggers, board-level products, and soft-

ware development tools, among others.

In addition, mature development tools and applications

for the x86 platform are widely available in the general

marketplace.

Customer Service

The AMD customer service network includes U.S. of-

fices, international offices, and a customer training cen-

ter. Expert technical assistance is available from the

AMD worldwide staff of field application engineers and

factory support staff who can answer E86 family hard-

ware and software development questions.

Hotline and World Wide Web Support

For answers to technical questions, AMD provides a

toll-free n umber for di rect access to our corpor ate ap-

plications hotline. Also available is the AMD World

Wide Web home page and FTP site, which provides

the latest E86 family product information, including

technical information and data on upcoming product re-

le ases.

Corporate Applications Hotline

800-222-9323 Toll-free for U.S. and

Canada

44-(0) 1276-803-299 U.K. and Europe hotline

World Wide Web Home Page and FTP Site

To access the AMD home page go to http://

www.amd.com.

To download documents and software, ftp to

ftp.amd.com and log on as anonymous using your

E-mail address as a password. Or via your web

browser, go to ftp://ftp.amd.com.

Questions, requests, and input concerning AMD’s

WWW pages can be sent via E-mail to

webmaster@amd.com.

Documentation and Literature

Free E86 family information such as data books, user’s

manuals, data sheets, application notes, the

FusionE86 Partner Solutions Catalog, and other litera-

ture is available with a simple phone call. Internation-

ally, contact your local AMD sales office for complete

E86 family literature.

Literature Ordering

800-222-9323 Toll-free for U.S. and

Canada

512-602-5651 Direct dial worldwide

800-222-9323 AMD Facts-On-Demand™

fax information service,

toll-free for U.S. and Canada

10 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

KEY FEATURES AND BENEFITS

The Am186EM and Am188EM microcontrollers extend

the AMD family of microcontrollers based on the indus-

try-standard x86 architecture. The Am186EM and

Am188EM microcontrollers are higher-performance,

more integrated versions of the 80C186/188 micropro-

cessors, offering a migration path that was previo usly

unavailable. Upgrading to the Am186EM and

Am188 EM microc ontr ollers is an attracti ve sol ution for

several reasons:

nMinimized total system cost—New peripherals and

on-chip system interface logic on the Am186EM and

Am188EM microcontrollers reduce the cost of existing

80C186/188 designs.

nX86 software compatibility—80C186/188-com-

patible and upward-compatible with the other mem-

bers of the AMD E86 family.

nEnhanced performance—The Am186EM and

Am188EM microcontrollers increase the perfor-

mance of 80C186/188 systems, and the demulti-

plexed address bus offers faster, unbuffered access

to memory.

nEnhanced functionality—The new and enhanced

on-chip peripherals of the Am186EM and Am188EM

microcontrollers include an asynchronous serial

port, 32 PIOs, a watchdog timer, an additional inter-

rupt pin, a synchronous serial interface, a PSRAM

controller, a 16-bit reset configuration register, and

enhanced chip-select functionality.

Application Considerations

The integration enhancements of the Am186EM and

Am188EM microcontrollers provide a high-perfor-

mance, low-system-cost solution for 16-bit embe dded

microcontroller designs. The nonmultiplexed address

bus eliminates the need for system-support logic to in-

terface memory devices, while the multiplexed ad-

dress/data bus maintains the value of previously

engine ered, cu sto mer-sp ecific perip herals and ci rcuits

within the upgraded design.

Figure 1 illustrates an example system design that

uses the integrate d pe riphe ra l s et to achi ev e hi gh per-

formance with reduced system co st.

Clock Generati on

The integrated clock generation circuitry of the

Am186EM and Am188EM microcontrollers allows the

use of a times-one crystal frequency. The design in

Figure 1 a chieves 40-MHz CPU operation while using

a 40-MHz crystal.

Memory Interface

The integrated memory controller logic of the

Am186EM an d Am188EM micr ocontrollers provides a

direct address bus interface to memory devices. The

use of an externa l address latch controlled by the ad-

dress latch enable (ALE) signal is no longer needed.

Individual byte-write-enable signals are provided to

elimina te the need for external h igh/low by te-write-en-

able circuitry. The maximum bank size that is program-

mable for the memory chip-select signals has been

increa sed to f acilitate t he use of high-densi ty memory

devices.

The improved memory timing specifications for the

Am186EM and Am188EM microcontrollers allow no

wait-state operation with 70-ns memory access times

at a 40-MHz CPU clock speed. This reduces overall

system cost significantly by allowing the use of a more

commonly available memory speed and technology.

Direct Memory Interface Example

Figure 1 illustrates the Am186EM microcontroller direct

memory interface. The processor A19–A0 bus con-

nects to t he memory addr ess inputs, the AD bus con-

nects to the data inputs and outputs, and the chip

selects connect to the memory chip-select inputs.

The RD output connects to the SRAM Output Enable

(OE) pin for read operations. Write operations use the byte

write enables connected to the SRAM Write Enable (WE)

pins.

The example design uses 2-Mbit memory technology

(256 Kbytes) to fully populate the available address

space. Two flash PROM devices provide 512 Kbytes of

nonvolatile program storage and two static RAM de-

vices provide 512 Kbytes of data storage area.

Figure 1 also shows an implementation of an RS-23 2

console or modem communications port. The RS-232-

to-CMOS voltage-level converter is required for the

electrical interface with the external device.

Figure 1. Example System Design

RS-232

Level

Converter

TXD

RXD

LCS

UCS

WHB

WLB

AD15–AD0

A19–A0

Flash PROM

Static RAM

Serial Port

Am186EM

Microcontroller

40-MHz

Crystal Address

Data

Address

Am186/188EM and Am186/188EMLV Microcontrollers 11

PRELIMINARY

TQFP CONNECTION DIAGRAMS AND PINOUTS

Am186EM Microcontroller

Top Side View—100-Pin Thin Quad Flat Pack (TQFP)

Note

Pin 1 is ma rked for orien tation.

GND

6/A2

5/A1

AD0 1

AD8 2

AD1 3

AD9 4

AD2 5

AD10 6

AD3 7

AD11 8

AD4 9

AD12 10

AD5 11

AD13 13

AD6 14

AD14 16

AD7 17

AD15 18

TXD 21

RXD 22

SDATA 23

SDEN1 24

SDEN0 25

VCC

75 INT4

70 NMI

69 SRDY

68 HOLD

67 HLDA

63 A0

62 A1

60 A2

59 A3

58 A4

57 A5

56 A6

55 A7

54 A8

53 A9

52 A10

51 A11

VCC

100 DRQ0

99 DRQ1

98 TMRIN0

97 TMROUT0

96 TMROUT1

95 TMRIN1

79 INT0

78 INT1/

77 INT2/

76 INT3/

VCC

1/IRQ

SCLK 26

ALE 30

ARDY 31

X1 36

CLKOUTA 39

A19 42

A18 43

A17 45

A16 46

A15 47

A14 48

A13 49

A12 50

VCC

CLKOUTB

VCC /0

GND

GND GND

GND

WHB

WLB

DT/R

DEN

MCS0

MCS1

BHE/ADEN

INTA

SELECT

UCS ONCE

ONCE

PCS

MCS

MCS RFSH

RES

LCS

S6/CLKDIV2

UZI

Am186EM Microcontroller

12 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

TQFP PIN ASSIGNMENTS—Am186EM Microcontroller

(Sorted by Pin Number)

Pin No. Name Pin No. Name Pin No. Name Pin No. Name

1AD0 26 SCLK/PIO20 51 A11 76 INT3/INTA1/IRQ

2AD8 27 BHE/ADEN 52 A10 77 INT2/INTA0

3AD1 28 WR 53 A9 78 INT1/SELECT

4AD9 29 RD 54 A8 79 INT0

5AD2 30 ALE 55 A7 80 UCS/ONCE1

6AD10 31 ARDY 56 A6 81 LCS/ONCE0

7AD3 32 S2 57 A5 82 PCS6/A2/PIO2

8AD11 33 S1 58 A4 83 PCS5/A1/PIO3

9AD4 34 S0 59 A3 84 VCC

10 AD12 35 GND 60 A2 85 PCS3/PIO19

11 AD5 36 X1 61 VCC 86 PCS2/PIO18

12 GND 37 X2 62 A1 87 GND

13 AD13 38 VCC 63 A0 88 PCS1/PIO17

14 AD6 39 CLKOUTA 64 GND 89 PCS0/PIO16

15 VCC 40 CLKOUTB 65 WHB 90 VCC

16 AD14 41 GND 66 WLB 91 MCS2

17 AD7 42 A19/PIO9 67 HLDA 92 MCS3/RFSH

18 AD15 43 A18/PIO8 68 HOLD 93 GND

19 S6/CKLDIV2/PIO29 44 VCC 69 SRDY/PIO6 94 RES

20 UZI/PIO26 45 A17/PIO7 70 NMI 95 TMRIN1/PIO0

21 TXD 46 A16 71 DT/R/PIO4 96 TMROUT1/PIO1

22 RXD 47 A15 72 DEN/PIO5 97 TMROUT0/PIO10

23 SDATA/PIO21 48 A14 73 MCS0/PIO14 98 TMRIN0/PIO11

24 SDEN1/PIO23 49 A13 74 MCS1/PIO15 99 DRQ1/PIO13

25 SDEN0/PIO22 50 A12 75 INT4 100 DRQ0/PIO12

Am186/188EM and Am186/188EMLV Microcontrollers 13

PRELIMINARY

TQFP PIN ASSIGNMENTS—Am186EM Microcontroller

(Sorted by Pin Name)

Pin Name No. Pin Name No. Pin Name No. Pin Name No.

A0 63 AD5 11 GND 93 S2 32

A1 62 AD6 14 HLDA 67 S6/CLKDIV2/PIO29 19

A2 60 AD7 17 HOLD 68 SCLK/PIO20 26

A3 59 AD8 2 INT0 79 SDATA/PIO21 23

A4 58 AD9 4 INT1/SELECT 78 SDEN0/PIO22 25

A5 57 AD10 6 INT2/INTA0 77 SDEN1/PIO23 24

A6 56 AD11 8 INT3/INTA1/IRQ 76 SRDY/PIO6 69

A7 55 AD12 10 INT4 75 TMRIN0/PIO11 98

A8 54 AD13 13 LCS/ONCE0 81 TMRIN1/PIO0 95

A9 53 AD14 16 MCS0/PIO14 73 TMROUT0/PIO10 97

A10 52 AD15 18 MCS1/PIO15 74 TMROUT1/PIO1 96

A11 51 ALE 30 MCS2 91 TXD 21

A12 50 ARDY 31 MCS3/RFSH 92 UCS/ONCE1 80

A13 49 BHE/ADEN 27 NMI 70 UZI/PIO26 20

A14 48 CLKOUTA 39 PCS0/PIO16 89 VCC 15

A15 47 CLKOUTB 40 PCS1/PIO17 88 VCC 38

A16 46 DEN/PIO5 72 PCS2/PIO18 86 VCC 44

A17/PIO7 45 DRQ0/PIO12 100 PCS3/PIO19 85 VCC 61

A18/PIO8 43 DRQ1/PIO13 99 PCS5/A1/PIO3 83 VCC 84

A19/PIO9 42 DT/R/PIO4 71 PCS6/A2/PIO2 82 VCC 90

AD0 1 GND 12 RD 29 WHB 65

AD1 3 GND 35 RES 94 WLB 66

AD2 5 GND 41 RXD 22 WR 28

AD3 7 GND 64 S0 34 X1 36

AD4 9 GND 87 S1 33 X2 37

14 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

CONNECTION DIAGRAM

Am188EM Microcontroller

Top Side View—100-Pin Thin Quad Flat Pack (TQFP)

Note

Pin 1 is ma rked for orien tation.

GND

6/A2

5/A1

AD0 1

AO8 2

AD1 3

AO9 4

AD2 5

AO10 6

AD3 7

AO11 8

AD4 9

AO12 10

AD5 11

AO13 13

AD6 14

AO14 16

AD7 17

AO15 18

TXD 21

RXD 22

SDATA 23

SDEN1 24

SDEN0 25

VCC

75 INT4

70 NMI

69 SRDY

68 HOLD

67 HLDA

63 A0

62 A1

60 A2

59 A3

58 A4

57 A5

56 A6

55 A7

54 A8

53 A9

52 A10

51 A11

VCC

100 DRQ0

99 DRQ1

98 TMRIN0

97 TMROUT0

96 TMROUT1

95 TMRIN1

79 INT0

78 INT1/

77 INT2/

76 INT3/

VCC

1/IRQ

SCLK 26

ALE 30

ARDY 31

X1 36

CLKOUTA 39

A19 42

A18 43

A17 45

A16 46

A15 47

A14 48

A13 49

A12 50

VCC

CLKOUTB

VCC /0

GND

GND GND

GND

DT/R

DEN

MCS0

MCS1

RFSH2/ADEN

INTA

SELECT

UCS ONCE

ONCE

PCS

MCS

MCS RFSH

RES

LCS

S6/CLKDIV2

UZI

Am188EM Microcontroller

Am186/188EM and Am186/188EMLV Microcontrollers 15

PRELIMINARY

TQFP PIN ASSIGNMENTS—Am188EM Microcontroller

(Sorted by Pin Number)

Pin No. Name Pin No . Name Pin No. Name Pin No. Name

1AD0 26 SCLK/PIO20 51 A11 76 INT3/INTA1/IRQ

2AO8 27 RFSH2/ADEN 52 A10 77 INT2/INTA0/PIO31

3AD1 28 WR 53 A9 78 INT1/SELECT

4AO9 29 RD 54 A8 79 INT0

5AD2 30 ALE 55 A7 80 UCS/ONCE1

6AO10 31 ARDY 56 A6 81 LCS/ONCE0

7AD3 32 S2 57 A5 82 PCS6/A2/PIO2

8AO11 33 S1 58 A4 83 PCS5/A1/PIO3

9AD4 34 S0 59 A3 84 VCC

10 AO12 35 GND 60 A2 85 PCS3/PIO19

11 AD5 36 X1 61 VCC 86 PCS2/PIO18

12 GND 37 X2 62 A1 87 GND

13 AO13 38 VCC 63 A0 88 PCS1/PIO17

14 AD6 39 CLKOUTA 64 GND 89 PCS0/PIO16

15 VCC 40 CLKOUTB 65 GND 90 VCC

16 AO14 41 GND 66 WB 91 MCS2/PIO24

17 AD7 42 A19/PIO9 67 HLDA 92 MCS3/RFSH/PIO25

18 AO15 43 A18/PIO8 68 HOLD 93 GND

19 S6/CLKDIV2/PIO29 44 VCC 69 SRDY/PIO6 94 RES

20 UZI/PIO26 45 A17/PIO7 70 NMI 95 TMRIN1/PIO0

21 TXD/PIO27 46 A16 71 DT/R/PIO4 96 TMROUT1/PIO1

22 RXD/PIO28 47 A15 72 DEN/PIO5 97 TMROUT0/PIO10

23 SDATA/PIO21 48 A14 73 MCS0/PIO14 98 TMRIN0/PIO11

24 SDEN1/PIO23 49 A13 74 MCS1/PIO15 99 DRQ1/PIO13

25 SDEN0/PIO22 50 A12 75 INT4/PIO30 100 DRQ0/PIO12

16 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

TQFP PIN ASSIGNMENTS—Am188EM Microcontroller

(Sorted by Pin Name)

Pin Name No. Pin Name No. Pin Name No. Pin Name No.

A0 63 AD5 11 GND 93 S1 33

A1 62 AD6 14 HLDA 67 S2 32

A2 60 AD7 17 HOLD 68 S6/CLKDIV2/PIO29 19

A3 59 ALE 30 INT0 79 SCLK/PIO20 26

A4 58 AO8 2 INT1/SELECT 78 SDATA/PIO21 23

A5 57 AO9 4 INT2/INTA0/PIO31 77 SDEN0/PIO22 25

A6 56 AO10 6 INT3/INTA1/IRQ 76 SDEN1/PIO23 24

A7 55 AO11 8 INT4/PIO30 75 SRDY/PIO6 69

A8 54 AO12 10 LCS/ONCE0 81 TMRIN0/PIO11 98

A9 53 AO13 13 MCS0/PIO14 73 TMRIN1/PIO0 95

A10 52 AO14 16 MCS1/PIO15 74 TMROUT0/PIO10 97

A11 51 AO15 18 MCS2/PIO24 91 TMROUT1/PIO1 96

A12 50 ARDY 31 MCS3/RFSH/PIO25 92 TXD/PIO27 21

A13 49 CLKOUTA 39 NMI 70 UCS/ONCE1 80

A14 48 CLKOUTB 40 PCS0/PIO16 89 UZI/PIO26 20

A15 47 DEN/PIO5 72 PCS1/PIO17 88 VCC 15

A16 46 DRQ0/PIO12 100 PCS2/PIO18 86 VCC 38

A17/PIO7 45 DRQ1/PIO13 99 PCS3/PIO19 85 VCC 44

A18/PIO8 43 DT/R/PIO4 71 PCS5/A1/PIO3 83 VCC 61

A19/PIO9 42 GND 12 PCS6/A2/PIO2 82 VCC 84

AD0 1 GND 35 RD 29 VCC 90

AD1 3 GND 41 RES 94 WB 66

AD2 5 GND 64 RFSH2/ADEN 27 WR 28

AD3 7 GND 65 RXD/PIO28 22 X1 36

AD4 9 GND 87 S0 34 X2 37

Am186/188EM and Am186/188EMLV Microcontrollers 17

PRELIMINARY

PQFP CONNECTION DIAGRAMS AND PINOUTS

Am186EM Microcontroller

Top Side View—100-Pin Plastic Quad Flat Pack (PQFP)

Note:

Pin 1 is marked for orienta tion.

AD0

AD8

AD1

AD9

AD2

AD10

AD3

AD11

AD4

AD12

AD5

AD13

AD6

AD14

AD7

AD15

TXD

RXD

SDATA

SDEN1

SDEN0

GND

SCLK

ALE

ARDY

CLKOUTA

A19

A18

A17

A16

A15

A14

A12

A13

VCC

CLKOUTB

VCC

GND

INT4

DT/R

NMI

SRDY

HOLD

HLDA

A10

A11

VCC

GND

TMRIN0

TMROUT0

TMROUT1

TMRIN1

INT0

GND

VCC

S6/CLKDIV

DRQ1

DRQ0

VCC

Am186EM Microcontroller

100

BHE/ADEN

UZI

WHB

WLB

DEN

MCS0

MCS1

INT3/INTA1/IRQ

INT2/INTA0

INT1/SELECT

UCS/ONCE1

LCS/ONCE0

PCS6/A2

PCS5/A1

PCS3

PCS2

PCS1

PCS0

MCS2

MCS3/RFSH

RES

18 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

PQFP PIN ASSIGNMENTS—Am186EM Microcontroller

(Sorted by Pin Number)

Pin No. Name Pin No . Name Pin No. Name Pin No. Name

1SDEN1/PIO23 26 A13 51 MCS1/PIO15 76 DRQ1/PIO13

2SDEN0/PIO22 27 A12 52 INT4/PIO30 77 DRQ0/PIO12

3SCLK/PIO20 28 A11 53 INT3/INTA1/IRQ 78 AD0

4BHE/ADEN 29 A10 54 INT2/INTA0/PIO31 79 AD8

5WR 30 A9 55 INT1/SELECT 80 AD1

6RD 31 A8 56 INT0 81 AD9

7ALE 32 A7 57 UCS/ONCE1 82 AD2

8 ARDY 33 A6 58 LCS/ONCE0 83 AD10

9 S2 34 A5 59 PCS6/A2/PIO2 84 AD3

10 S1 35 A4 60 PCS5/A1/PIO3 85 AD11

11 S0 36 A3 61 VCC 86 AD4

12 GND 37 A2 62 PCS3/PIO19 87 AD12

13 X1 38 VCC 63 PCS2/PIO18 88 AD5

14 X2 39 A1 64 GND 89 GND

15 VCC 40 A0 65 PCS1/PIO17 90 AD13

16 CLKOUTA 41 GND 66 PCS0/PIO16 91 AD6

17 CLKOUTB 42 WHB 67 VCC 92 VCC

18 GND 43 WLB 68 MCS2/PIO24 93 AD14

19 A19/PIO9 44 HLDA 69 MCS3/RFSH/PIO25 94 AD7

20 A18/PIO8 45 HOLD 70 GND 95 AD15

21 VCC 46 SRDY/PIO6 71 RES 96 S6/CLKDIV2/PIO29

22 A17/PIO7 47 NMI 72 TMRIN1/PIO0 97 UZI/PIO26

23 A16 48 DT/R/PIO4 73 TMROUT1/PIO1 98 TXD/PIO27

24 A15 49 DEN/PIO5 74 TMROUT0/PIO10 99 RXD/PIO28

25 A14 50 MCS0/PIO14 75 TMRIN0/PIO11 100 SDATA/PIO21

Am186/188EM and Am186/188EMLV Microcontrollers 19

PRELIMINARY

PQFP PIN ASSIGNMENTS—Am186EM Microcontroller

(Sorted by Pin Name)

Pin Name No. Pin Name No. Pin Name No. Pin Name No.

A0 40 AD5 88 GND 89 S2 9

A1 39 AD6 91 HLDA 44 S6/CLKDIV2/PIO29 96

A2 37 AD7 94 HOLD 45 SCLK/PIO20 3

A3 36 AD8 79 INT0 56 SDATA/PIO21 100

A4 35 AD9 81 INT1/SELECT 55 SDEN0/PIO22 2

A5 34 AD10 83 INT2/INTA0/PIO31 54 SDEN1/PIO23 1

A6 33 AD11 85 INT3/INTA1/IRQ 53 SRDY/PIO6 46

A7 32 AD12 87 INT4/PIO30 52 TMRIN0/PIO11 75

A8 31 AD13 90 LCS/ONCE0 58 TMRIN1/PIO0 72

A9 30 AD14 93 MCS0/PIO14 50 TMROUT0/PIO10 74

A10 29 AD15 95 MCS1/PIO15 51 TMROUT1/PIO1 73

A11 28 ALE 7 MCS2/PIO24 68 TXD/PIO27 98

A12 27 ARDY 8 MCS3/RFSH/PIO25 69 UCS/ONCE1 57

A13 26 BHE/ADEN 4 NMI 47 UZI/PIO26 97

A14 25 CLKOUTA 16 PCS0/PIO16 66 VCC 15

A15 24 CLKOUTB 17 PCS1/PIO17 65 VCC 21

A16 23 DEN/PIO5 49 PCS2/PIO18 63 VCC 38

A17/PIO7 22 DRQ0/PIO12 77 PCS3/PIO19 62 VCC 61

A18/PIO8 20 DRQ1/PIO13 76 PCS5/A1/PIO3 60 VCC 67

A19/PIO9 19 DT/R/PIO4 48 PCS6/A2/PIO2 59 VCC 92

AD0 78 GND 12 RD 6 WHB 42

AD1 80 GND 18 RES 71 WLB 43

AD2 82 GND 41 RXD/PIO28 99 WR 5

AD3 84 GND 64 S0 11 X1 13

AD4 86 GND 70 S1 10 X2 14

20 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

CONNECTION DIAGRAM

Am188EM Microcontroller

Top Side View—100-Pin Plastic Quad Flat Pack (PQFP)

Note:

Pin 1 is marked for orienta tion.

AD0

AD8

AD1

AD9

AD2

AD10

AD3

AD11

AD4

AD12

AD5

AD13

AD6

AD14

AD7

AD15

TXD

RXD

SDATA

SDEN1

SDEN0

GND

SCLK

ALE

ARDY

CLKOUTA

A19

A18

A17

A16

A15

A14

A12

A13

VCC

CLKOUTB

VCC

GND

INT4

DT/R

NMI

SRDY

HOLD

HLDA

A10

A11

VCC

GND

TMRIN0

TMROUT0

TMROUT1

TMRIN1

INT0

GND

VCC

S6/CLKDIV

DRQ1

DRQ0

VCC

Am188EM Microcontroller

100

RFSH2/ADEN

UZI

GND

DEN

MCS0

MCS1

INT3/INTA1/IRQ

INT2/INTA0

INT1/SELECT

UCS/ONCE1

LCS/ONCE0

PCS6/A2

PCS5/A1

PCS3

PCS2

PCS1

PCS0

MCS2

MCS3/RFSH

RES

Am186/188EM and Am186/188EMLV Microcontrollers 21

PRELIMINARY

PQFP PIN ASSIGNMENTS—Am188EM Microcontroller

(Sorted by Pin Number)

Pin No. Name Pin No . Name Pin No. Name Pin No. Name

1SDEN1/PIO23 26 A13 51 MCS1/PIO15 76 DRQ1/PIO13

2SDEN0/PIO22 27 A12 52 INT4/PIO30 77 DRQ0/PIO12

3SCLK/PIO20 28 A11 53 INT3/INTA1/IRQ 78 AD0

4RFSH2/ADEN 29 A10 54 INT2/INTA0/PIO31 79 AO8

5WR 30 A9 55 INT1/SELECT 80 AD1

6RD 31 A8 56 INT0 81 AO9

7ALE 32 A7 57 UCS/ONCE1 82 AD2

8 ARDY 33 A6 58 LCS/ONCE0 83 AO10

9 S2 34 A5 59 PCS6/A2/PIO2 84 AD3

10 S1 35 A4 60 PCS5/A1/PIO3 85 AO11

11 S0 36 A3 61 VCC 86 AD4

12 GND 37 A2 62 PCS3/PIO19 87 AO12

13 X1 38 VCC 63 PCS2/PIO18 88 AD5

14 X2 39 A1 64 GND 89 GND

15 VCC 40 A0 65 PCS1/PIO17 90 AO13

16 CLKOUTA 41 GND 66 PCS0/PIO16 91 AD6

17 CLKOUTB 42 GND 67 VCC 92 VCC

18 GND 43 WB 68 MCS2/PIO24 93 AO14

19 A19/PIO9 44 HLDA 69 MCS3/RFSH/PIO25 94 AD7

20 A18/PIO8 45 HOLD 70 GND 95 AO15

21 VCC 46 SRDY/PIO6 71 RES 96 S6/CLKDIV2/PIO29

22 A17/PIO7 47 NMI 72 TMRIN1/PIO0 97 UZI/PIO26

23 A16 48 DT/R/PIO4 73 TMROUT1/PIO1 98 TXD/PIO27

24 A15 49 DEN/PIO5 74 TMROUT0/PIO10 99 RXD/PIO28

25 A14 50 MCS0/PIO14 75 TMRIN0/PIO11 100 SDATA/PIO21

22 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

PQFP PIN ASSIGNMENTS—Am188EM Microcontroller

(Sorted by Pin Name)

Pin Name No. Pin Name No. Pin Name No. Pin Name No.

A0 40 AD5 88 GND 89 S1 10

A1 39 AD6 91 HLDA 44 S2 9

A2 37 AD7 94 HOLD 45 S6/CLKDIV2/PIO29 96

A3 36 ALE 7 INT0 56 SCLK/PIO20 3

A4 35 AO8 79 INT1/SELECT 55 SDATA/PIO21 100

A5 34 AO9 81 INT2/INTA0/PIO31 54 SDEN0/PIO22 2

A6 33 AO10 83 INT3/INTA1/IRQ 53 SDEN1/PIO23 1

A7 32 AO11 85 INT4/PIO30 52 SRDY/PIO6 46

A8 31 AO12 87 LCS/ONCE0 58 TMRIN0/PIO11 75

A9 30 AO13 90 MCS0/PIO14 50 TMRIN1/PIO0 72

A10 29 AO14 93 MCS1/PIO15 51 TMROUT0/PIO10 74

A11 28 AO15 95 MCS2/PIO24 68 TMROUT1/PIO1 73

A12 27 ARDY 8 MCS3/RFSH/PIO25 69 TXD/PIO27 98

A13 26 CLKOUTA 16 NMI 47 UCS/ONCE1 57

A14 25 CLKOUTB 17 PCS0/PIO16 66 UZI/PIO26 97

A15 24 DEN/PIO5 49 PCS1/PIO17 65 VCC 15

A16 23 DRQ0/PIO12 77 PCS2/PIO18 63 VCC 21

A17/PIO7 22 DRQ1/PIO13 76 PCS3/PIO19 62 VCC 38

A18/PIO8 20 DT/R/PIO4 48 PCS5/A1/PIO3 60 VCC 61

A19/PIO9 19 GND 12 PCS6/A2/PIO2 59 VCC 67

AD0 78 GND 18 RD 6 VCC 92

AD1 80 GND 41 RES 71 WB 43

AD2 82 GND 42 RFSH2/ADEN 4 WR 5

AD3 84 GND 64 RXD/PIO28 99 X1 13

AD4 86 GND 70 S0 11 X2 14

Am186/188EM and Am186/188EMLV Microcontrollers 23

PRELIMINARY

LOGIC SYMBOL—Am186EM MICROCONTROLLER

Notes:

* These signals are the normal function of a pin that can be used as a PIO. See the pin descriptions beginning on page 25 and

Table 2 on page 30 for information on shared function.

** All PIO signals are shared with other physical pins.

CLKOUTA

CLKOUTB

A19–A0

AD15–AD0

ALE

WHB

WLB

S2–S0

HOLD

HLDA

DT/R

DEN

ARDY

SRDY

TMRIN0

TMROUT0

SDEN1–SDEN0

SCLK

SDATA

Clocks

Address and

Address/Data Buses

Bus Control

Timer Control

Synchronous

Serial Port Control

RES

INT4

INT3/INTA1/IRQ

INT2/INTA0

INT1/SELECT

INT0

NMI

PCS6/A2

PCS5/A1

PCS3–PCS0

LCS/ONCE0

MCS2–MCS0

UCS/ONCE1

DRQ1–DRQ0

TXD

RXD

PIO32–PIO0

Reset Control and

Interrupt Service

Memory and

Peripheral Control

DMA Control

Asynchronous

Serial Port Control

Programmable

I/O Control

TMRIN1

TMROUT1

MCS3/RFSH

S6/CLKDIV2

BHE/ADEN

UZI

shared

24 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

LOGIC SYMBOL—Am188EM MICROCONTROLLER

Notes:

* These signals are the normal function of a pin that can be used as a PIO. See the pin descriptions beginning on page 25 and

Table 2 on page 30 for information on shared function.

** All PIO signals are shared with other physical pins.

CLKOUTA

CLKOUTB

AO15–AO8

AD7–AD0

S6/CLKDIV2

ALE

RFSH2/ADEN

S2–S0

HOLD

HLDA

DT/R

DEN

ARDY

SRDY

TMRIN0

TMROUT0

SDEN1–SDEN0

SCLK

SDATA

Clocks

Address and

Address/Data Buses

Bus Control

Timer Control

Synchronous

Serial Port Control

RES

INT4

INT3/INTA1/IRQ

INT2/INTA0

INT1/SELECT

INT0

NMI

PCS6/A2

PCS5/A1

PCS3–PCS0

LCS/ONCE0

MCS2–MCS0

UCS/ONCE1

DRQ1–DRQ0

TXD

RXD

PIO31–PIO0

shared

Reset Control and

Interrupt Service

Memory and

Peripheral Control

DMA Control

Asynchronous

Serial Port Control

Programmable

I/O Control

UZI

TMRIN1

TMROUT1

MCS3/RFSH

A19–A020

Am186/188EM and Am186/188EMLV Microcontrollers 25

PRELIMINARY

PIN DESCRIPTIONS

Pins That Are Used by Emulators

The following pins are used by emulators: A19–A0,

AO15–AO8, AD7–AD0, ALE, BHE/ADEN (on the

Am186EM), CLKOUTA, RFSH2/ADEN (on the

Am188EM), RD, S2–S0, S6/CLKDIV2, and UZI.

Emulator s requir e that S6 /CLKDIV 2 and UZI be config-

ured in their normal functionality, that is as S6 and UZI.

If BHE/ADEN (on the 186) or RFSH2/ADEN (on the 188)

is held Low during the rising edge of RES, S6 and UZI are

configured in their normal functionality.

Pin Terminology

The following terms are used to describe the pins:

Input—An input-only pin.

Output—An output-only pin.

Input/Output—A pin that can be either input or output.

Synchronous—Synch ronous i nputs mu st meet s etup

and hold times in relation to CLKOUTA. Synchronous

outputs are synchronous to CLKOUTA.

Asynchronous—Inputs or outputs that are

asynchronous to CLKOUTA.

A19–A0

(A19/PIO9, A18/PIO8, A17/PIO7)

Address Bus (output, three-state, synchronous)

These pins supply nonmultiplexed memory or I/O ad-

dresse s to the system o ne-half of a CLKO UTA period

earlier than the multiplexed address and data bus

(AD15–AD0 on the 186 or AO15–AO8 and AD7–AD0

on the 18 8). During a bu s hold or reset cond ition, the

address bus is in a high-impedance state.

AD7–AD0

Address and Data Bus (input/output, three-state,

synchronous, level-sensitive)

These time-multiplexed pins supply partial memory or

I/O addresses, as well as data, to the system. This bus

supplie s the low-orde r 8 bits of an addres s to the sys-

tem during the first period of a bus cycle (t1), and it sup-

plies data to the system during the remaining periods of

tha t cycl e (t2, t3, and t4).

The address phase of these pins can be disabled. See

the ADEN description with the BHE/ADEN pin. When

WLB is negated, t hes e pi ns are th re e- st ated d uring t2,

t3, and t4.

During a bus hold or reset condition, the address and

data bus is in a high-impedance state.

During a power-on reset, the address and data bus

pins (AD15–AD0 for the 186, AO15–AO8 and AD7–

AD0 for the 188) can also be used to load system con-

figuration information i nto the inte rnal reset con figura-

tion registe r.

AD15–AD8 (Am186EM Microcontroller)

AO15–AO8 (Am188EM Microc ontrol ler)

Address and Data Bus (input/output, three-state,

synchronous, level-sensitive)

Address-Only Bus (output, three-state,

synchronous, level-sensitive)

AD15–AD8—On the Am186 EM mi crocon troll er, thes e

ti me- m ul t ip l ex ed pi ns supply m e mo ry o r I /O a d dr es s e s

and data to the system. This bus can supply an ad-

dress to the system during the first period of a bus cycle

(t1). It supplies data to the system during the remaining

periods of that cycle (t2, t3, and t4).

The address phase of these pins can be disabled. See

the ADEN description with the BHE /ADEN p in. Wh en

WHB i s nega ted, these pins are th ree- stated du ring t 2, t3,

and t4.

During a bus hold or reset condition, the address and

data bus is in a high-impedance state.

During a power-on reset, the address and data bus

pins (AD15–AD0 for the 186, AO15–AO8 and AD7–

AD0 for the 188) can also be used to load system con-

figuration information i nto the inte rnal reset con figura-

tion registe r.

AO15–AO8—On the Am188EM microcontroller, the

address-only bus (AO15–AO8) contains valid high-

order address bits from bus cycles t1–t4. These o utput s

are floated during a bus hold or reset.

On the Am188EM microcontroller, AO15–AO8 com-

bine with AD7–AD0 to form a complete multiplexed ad-

dress bus while AD7–AD0 is the 8-bit data bus.

ALE

Address Latch Enable (output, synchronous)

This pin indicates to the system that an address ap-

pears on the address and data bus (AD15–AD0 for the

186 or AO15–AO8 and AD7–AD0 for the 188). The ad-

dress is guarantee d valid on the trailing edge of ALE.

This pin is three-stated during ONCE mode. This pin is

not three-stated during a bus hold or reset.

ARDY

Asynchronous Ready (input, asynchronous,

level-sensitive)

This pin indicates to the microcontroller that the ad-

dressed memory space or I/O device will complete a

data transfer. The ARDY pin accepts a rising edge that

is async hrono us to CLK OUTA a nd is active High. Th e

26 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

falling edge of ARDY must be synchronized to CLK-

OUTA. To always assert the ready condition to the mi-

crocontroller, tie ARDY High. If the system does not

use ARDY, tie the pin Low to yield control to SRDY.

BHE/ADEN

(Am186EM Microcontroller Only)

Bus High Enable (three-state, output, synchronous)

Address Enable (input, internal pullup)

BHE—During a memory access, this pin and the least-

signifi cant ad dres s bit (A D0 or A 0) indic ate to th e sys -

tem which bytes of the data bus (upper, lower, or both)

participate in a bus cycle. The BHE/ADEN and AD0

pins are encoded as shown in Table 1.

BHE is asserted during t1 and remains asserted

through t3 and tW. BHE does not need to be latched.

BHE floats during bus hold and reset.

On the Am186EM and Am188EM microcontrollers,

WLB and WH B implement the functionality of B HE and

AD0 for high and low byte write enables.

Table 1. Data Byte Encoding

BHE/ADEN also signals DRAM refresh cycles when

using the multiplexed address and data (AD) bus. A re-

fresh cycle is indicated when both BHE/ADEN and AD0

are High. Du ring refres h cycl es, the A bus and the A D

bus are not guaranteed to provide the same address

during the address phase of the AD bus cycle. For this

reason, the A0 signal cannot be used in place of the

AD0 signal to determine refresh cycles. PSRAM re-

freshes also provide an additional RFSH signal (see

the MCS3/RFSH pin description on page 28).

ADEN—If BH E/ADEN is held High or left float ing dur-

ing power-on r eset, the addres s portion of the AD bus

(AD15–AD0 for the 186 or AO15–AO8 and AD7–AD0

for the 188) is enabled or disabled during LCS and

UCS bus c ycles ba sed on the DA bi t in th e LM CS and

UMCS registers. If the DA bit is set, the memory ad-

dress is accessed on the A19–A0 pins. There is a weak

internal pullup resistor on BHE/ADEN so no external

pullup is required. This mode of operation reduces

power cons ump tion .

If BHE/ADEN is held Low on power-on reset, the AD

bus drives both addresse s and data , regar dles s of the

DA bit setting. This pin is sampled on the rising edge of

RES. (S6 and UZI also assume their normal functional-

ity in this instance. See Table 2 on page 30.)

Note: On the Am188EM microcontroller, AO15

–

AO8

are driven during the entire bus cycle, regardless of the

setting of the DA bit in the UMCS and LMCS registers.

CLKOUTA

Clock Output A (output, synchronous)

This pin sup plies the inter nal clock to the syste m. De-

pending on the value of the power-save control register

(PDCON), CLKOUTA operates at either the crystal

input frequency (X1), the power-save frequency, or is

three-stated. CLKOUTA remains active during reset

and bus hold conditions.

CLKOUTB

Clock Output B (output, synchronous)

This pin supplies an additional clock to the system. De-

pending upon the value of the power-save control reg-

ister (PDCON), CLKOUTB operates at either the

crystal input frequency (X1), the power-save fre-

quency, or is three-stated. CLKOUTB remains active

during reset and bus hold conditions.

DEN/PIO5

Data Enable (output, three-state, synchronous)

This pin supplies an output enable to an external data-

bus transceiver. DEN is asserted during memo ry, I/O,

and interrupt ackno wledge cycles. D EN is deasserted

when DT/R cha nges sta te. D EN floats during a bus hold

or reset condition.

DRQ1–DRQ0

(DRQ 1/ PIO1 3, DR Q0/PIO12 )

DMA Requests (input, synchronous,

level-sensitive)

These pins indicate to the microcontroller that an exter-

nal devi ce is read y for DMA chann el 1 or chan nel 0 t o

perform a transfer. DRQ1–DRQ0 are level-triggered

and internally synchronized.

The DRQ sig nal s are no t lat ch ed an d mu st remai n ac-

tive until serviced.

DT/R/PIO4

Data Transmit or Receive (output, three-state,

synchronous)

This pin indicates which direction data should flow

through an exte rnal data-bu s tran sceiver. When DT/R

is asserted High, the microcontroller transmits data. When

this pin is deasserted L ow, the microcontrol ler receives

data. DT/R floats during a bus hold or reset condition.

BHE AD0 Type of Bus Cycle

0 0 Word Transfer

01High Byte Transfer (Bits 15–8)

10Low Byte Transfer (Bits 7–0)

11Refresh

Am186/188EM and Am186/188EMLV Microcontrollers 27

PRELIMINARY

GND

Ground

The ground pins connect the system ground to the mi-

crocontroller.

HLDA

Bus Hold Acknowledge (output, synchronous)

This pin is asserted High to indicate to an external bus

master t hat the mic r ocontroll er ha s rel eased c ont ro l o f

the local bus. When an external bus master requests

control of the local bus (by asserting HOLD), the micro-

controller completes the bus cycle in progress and then

relinquishes control of the bus to the external bus mas-

ter by asserting HLDA and floating DEN, RD, WR, S2–

S0, AD15–AD0, S6, A19–A0, BHE, WHB, WLB, and

DT/R, and then driving the chip selects UCS, LCS,

MCS3–MCS0, PCS6–PCS5, and PCS3–PCS0 High.

When the external bus master has finished using the

local bus, it indicates this to the microcontroller by

deasserting HOLD. The microcontroller responds by

deasserting HLDA.

If the microcontroller requires access to the bus (i.e. for

refresh) , it will deasser t HLDA befor e the external bus

master deasserts HOLD. The external bus master

must be able to deassert HOLD and allow the micro-

controller access to the bus. See the timing diagrams

for bus hold on page 92.

HOLD

Bus Hold Request (input, synchronous,

level-sensitive)

This pin indicates to the microcontroller that an external

bus master needs control of the local bus.

The Am186EM and Am188EM microcontrollers’ HOLD

latency time is a function of the activity occurring in the

processor when the HOLD request is received. A

DRAM request will delay a HOLD request when both

requests are made at the same time. In addition, if

locked transfers are performed, the HOLD latency time

is increased by the length of the locked transfer.

For more information, see the HLDA pin description.

INT0

Maskable Interrupt Request 0 (input,

asynchronous)

This pin indicates to the microcontroller that an inter-

rupt request has occurred. If the INT0 pin is not

masked, the microcontroller transfers program execu-

tion to the location sp ecified by the I NT0 vector in the

microcontroller interrupt vector table.

Interrupt r eques ts are s ynchro nized in terna lly and c an

be edge-triggered or level-triggered. To guarantee in-

terrupt recognition, the requesting device must con-

tinue asserting INT0 until the request is acknowledged.

INT1/SELECT

Maskable Interrupt Request 1 (input,

asynchronous)

Slave Select (input, asynchronous)

INT1—This pi n indic ates t o the microc ontrol ler that a n

interrupt r equest has o ccurred. If INT1 is n ot masked,

the microco ntroller tran sfers program ex ecution to the

location specified by the INT1 vector in the microcon-

troller interrupt vector table.

Interrupt r eques ts are s ynchr onize d interna lly and can

be edge-triggered or level-triggered. To guarantee in-

terrupt recognition, the requesting device must con-

tinue asserting INT1 until the request is acknowledged.

SELECT—When the microcontroller interrupt control

unit is operating as a slave to an external interrupt con-

troller, this pin indicates to the microcontroller that an

interrupt type appears on the address and data bus.

The INT0 pin m ust indicate to the microcontroller that

an interrupt has occ urred bef ore the SELE CT pi n indi-

cates to the microcontroller that the interrupt type ap-

pears on the bus.

INT2/INTA0/PIO31

Maskable Interrupt Request 2 (input,

asynchronous)

Interrupt Acknowledge 0 (output, synchronous)

INT2—This pi n indic ates t o the microc ontrol ler that a n

interrupt request has occurred. If the INT2 pin is not

masked, the microco ntroller trans fers program execu-

tion to the location sp ecified by the INT2 vector in th e

microcontroller interrupt vector table.

Interrupt r eques ts are s ynchr onize d interna lly and can

be edge-triggered or level-triggered. To guarantee in-

terrupt recognition, the requesting device must con-

tinue asserting INT2 until the request is acknowledged.

INT2 becomes INT A0 when INT0 is configured in cas-

cade mode.

INTA0—When the microcontroller interrupt control unit

is oper ating in c asc ade m ode, th is p in in dicat es to the

system that the microcontroller needs an interrupt type

to process the interrupt request on INT0. The periph-

eral is suing the int errupt reques t must provide t he mi-

crocontroller with the corresponding interrupt type.

INT3/INTA1/IRQ

Maskable Interrupt Request 3

(input, asynchronous)

Interrupt Acknowledge 1 (output, synchronous)

Slave Interrupt Request (output, synchronous)

INT3—This pi n indic ates t o the microc ontrol ler that a n

interrupt request has occurred. If the INT3 pin is not

masked, the microcontroller then transfers program ex-

ecution to the location specified by the INT3 vector in

the microcontroller interrupt vector table.

28 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

Interrupt requests are synchronized internally, and can

be edge-triggered or level-triggered. To guarantee in-

terrupt recognition, the requesting device must con-

tinue asserting INT3 until the request is acknowledged.

INT3 becomes INTA1 when INT1 is configured in cas-

cade mode.

INTA1—When the microcontroller interrupt control unit

is operating in cascade mode or special fully-nested

mode, this pin indicates to the system that the micro-

control ler needs an inter rupt type to pr ocess the in ter-

rupt request on INT1. In both modes, the peripheral

issuing the interrupt request must provide the micro-

controller with the corresponding interrupt type.

IRQ—When the microcontroller interrupt control unit is

operating as a slave to an external master interrupt

controller, this pin lets the microcontroller issue an in-

terrupt request to the external master interrupt control-

ler.

INT4/PIO30

Maskable Interrupt Request 4 (input,

asynchronous)

This pin indicates to the microcontroller that an inter-

rupt request has occurred. If the INT4 pin is not

masked, the microcontroller then transfers program ex-

ecution to the location specified by the INT4 vector in

the microcontroller interrupt vector table.

Interrupt requests are synchronized internally, and can

be edge-triggered or level-triggered. To guarantee in-

terrupt recognition, the requesting device must con-

tinue asserting INT4 until the request is acknowledged.

LCS/ONCE0

Lower Memory Chip Select (output, synchronous,

internal pullup)

ONCE Mode Request 0 (input)

LCS—This pi n indicates to th e system that a me mory

access is in progr ess to the low er memory block. The

base addr ess and si ze of th e lower memo ry block a re

programmable up to 512 Kbytes. LCS is held High dur-

ing a bus hold condition.

ONCE0—During r eset this pin and ONCE1 i ndic ate to

the microcontroller the mode in which it should operate.

ONCE0 and ONCE1 are sampled on the rising edge of

RES. If both pins are asserted Low, the microcontroller

enters ONCE mode; otherwise, it operates normally.

In ONCE mode, all pins assume a high-impedance

state a nd rem ain in t hat stat e until a subs equent rese t

occurs. To guarantee that the microcontroller does not

inadvertently enter ONCE mode, ONCE0 has a weak in-

ternal pul lup resistor that is a ctive only d uring re set. This

pin is not three-stated during a bus hold condition.

MCS3/RFSH/PIO25

Midrange Memory Chip Select 3

(output, synchronous, internal pullup)

Automatic Refresh (output, synchronous)

MCS3—This pin indicates to the system that a memory

access is in progress to the fourth region of the

midrange memory block. The base address and size of

the midrange memory block are programmable. MCS3

is held High during a bus hold condition. In addition,

this pin has a weak internal pullup resistor that is active

during reset.

RFSH—This pin provides a signal timed for auto re-

fresh to PSR AM dev ices. It i s onl y enab led to fu nctio n

as a refres h pul se when the P SRAM m ode bit is set i n

the LMCS Regis ter. An active Low pulse is gener ated

for 1.5 clock cycles with an adequate deassertion pe-

riod to ensure that overall auto refresh cycle time is

met. Thi s pin is no t thr ee- sta ted du ri ng a b us h old con di-

tion.

MCS2–MCS0

(MCS2/PIO24, MC S 1/PIO15, MCS0/PIO14)

Midrange Memory Chip Selects (output,

synchronous, internal pullup)

These pins indicate to the system that a memory ac-

cess is in progress to the corresponding region of th e

midrange memory block. The base address and size of

the midrange memory block are programmable.

MCS2–MCS0 are held High during a bus hold condi-

tion. In ad dition, they have weak internal pullup resis-

tors that are active during reset.

NMI

Nonmaskable Interrupt (input, synchronous, edge-

sensitive)

This pin indicates to the microcontroller that an inter-

rupt reque st has oc curre d. The NMI signa l is the hig h-

est priority hardware interrupt and, unlike the INT4–

INT0 pins, cannot be masked. The microcontroller al-

ways transfers program execution to the location spec-

ified by the nonmaskable interrupt vector in the

microcontroller interrupt vector table when NMI is as-

serted.

Although NMI is the hi ghest prio rity interr upt so urce , it

does not participate in the priority resolution process of

the maskable interr upts. T here is no bit a ssocia ted with

NMI in the interr upt in-se rvice or interr upt reques t reg-

isters. This means that a new NMI request can interrupt

an executing NM I interrupt service routine. As with all

hardware interrupts, the IF (interrupt flag) is cleared

when the processor takes the interrupt, disabling the

maskable interrupt sources. However, if maskable in-

terrupts are re-enabled by software in the NMI interrupt

service routine, via the STI instruction for example, the

fact that an NMI is currently in service will not have any

Am186/188EM and Am186/188EMLV Microcontrollers 29

PRELIMINARY

effect on the priority resolution of maskable interrupt re-

quests. For this reason, it is strongly advised that the

interrupt service routine for NMI does not enable the

maskable interrupts.

An NMI transition from Low to High is latched and syn-

chronized internally, and it initiates the interrupt at the

next inst ruction b oun dary. To gua rantee that the in ter-

rupt is recognized, the NMI pin must be asserted for at

least one CLKOUTA period.

PCS3–PCS0

(PCS3/PIO19, PCS2/PIO18,

PCS1/PIO17, PCS0/ PIO16)

Peripheral Chip Selects (output, synchronous)

These pins indicate to the system that a memory ac-

cess i s in progres s to the corresponding region of the

peripheral memory block (either I/O or memory ad-

dress space). The base address of the peripheral

memory block is programmable. PCS3–PCS0 are held

High during a bus hold condition. They are also held

High during reset.

PCS4 is not available on the Am186EM and Am188EM

microcontrollers.

Unlike the UCS and LCS chip selects, the PCS outputs

assert with the multiplexed AD address bus. Note also

that each per ipheral chip select asserts over a 256-byte

address range, which is twice the address range cov-

ered by peripheral chip selects in the 80C186 and

80C188 microcontrollers.

PCS5/A1/PIO3

Peripheral Chip Select 5 (output, synchronous)

Latched Address Bit 1 (output, synchronous)

PCS5—This pin indicates to the system that a memory

access is in progre ss to the si xth regio n of the perip h-

eral memory block (either I/O or memory address

space). The base address of the peripheral memory

block is programmable. PCS5 is held High during a bus

hold condition. It is also held High during reset.

Unlike the UCS and LCS chip sel ects, t he PCS outputs

assert with the mu lti pl exe d AD add re ss bus. Note al so

that each peripheral chip select asserts over a 256-

byte address range, which is twice the address range

covered by periphe ral chip selects in the 80C1 86 and

80C188 micr oc ontro ll er s.

A1—When the EX bit in the MCS and PCS auxiliary

registe r is 0, this pin sup plies an inte rnally latc hed ad-

dress b it 1 to the s ystem . During a bu s hold con dition ,

A1 retains its previously latched value.

PCS6/A2/PIO2

Peripheral Chip Select 6 (output, synchronous)

Latched Address Bit 2 (output, synchronous)

PCS6—This pin indicates to the system that a memory

access is in progress to the seve nth region of the pe-

ripheral memory block (either I/O or memory address

space). The base address of the peripheral memory

block is programmable. PCS6 is held High during a bus

hold condition or reset.

Unlike the UCS and LCS chip sel ects, t he PCS outputs

assert with the multiplexed AD address bus. Note also

that each peripheral chip select asserts over a 256-

byte address range, which is twice the address rang e

cove red by peripher al chip s elects in the 80C186 and

80C188 micr oc ont ro ll ers.

A2—When the EX bit in the MCS and PCS Auxiliary

dress b it 2 to the s ystem . During a bu s hold con dition ,

A2 retains its previously latched value.

PIO31–PIO0 (Shared)

Programmable I/O Pins (input/output,

asynchronous, open-drain)

The Am186EM and Am188EM microcontrollers pro-

vide 32 i ndividuall y programmab le I/O pins. Each PIO

can be programmed w ith the following attributes: PIO

function (enabled/disabled), direction (input/output),

and weak pullup or pulldown.

The pins that are multiplexed with PIO31–PIO0 are

listed in Table 2 and Table 3.

After power-on reset, the PIO pins default to various

configurations. The column titled

Power-On Reset Sta-

tus

in Table 2 and Table 3 lists the defaults for the PIOs. The

system initialization code must reconfigure any PIOs as

required.

The A19–A17 address pins default to normal operation

on power-on res et, allowing the processo r to correc tly

begin fetching instructions at the boot address

FFFF0h. The DT/R, DEN, and SRDY pins also default to

normal operation on power-on reset.

30 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

Table 2. Numeric PIO Pin Assignments

Notes:

1. Thes e pins ar e used by emulator s. (Emulat ors also u se

S2–S0

RES

NMI

CLKOUTA

BHE

ALE

AD15–AD0

and

A16

–

A0.

)

2. These pins revert t o nor mal operation if

BHE/ADEN

(186) or

RFSH2/ADEN

(188) is held Low du ring power-on reset.

3. When used as a PIO, inp ut with pull up opt ion availab le.

4. When used as a PIO, inp ut with pull down op tion avai lable.

Table 3. Alphabetic PIO Pin Assignments

Notes:

1. These p ins ar e used by em ulator s. (Emulato rs also u se

S2–S0

RES

NMI

CLKOUTA

BHE

ALE

AD15–AD0

and

A16

–

A0.

)

2. These pins revert to normal operation if

BHE/ADEN

(186) or

RFSH2/ADEN

(188) is hel d Low during power-on reset.

3. When used as a PIO, inp ut with pull up option availab le.

4. When used as a PIO, inp ut with pull down op tion avai lable.

PIO No Associated Pin Power-On Reset Status

0TMRIN1 Input with pullup

1TMROUT1 Input with pulldown

2PCS6/A2 Input with pullup

3PCS5/A1 Input with pullup

4DT/R Normal operation(3)

5DEN Normal operation(3)

6SRDY Normal operation(4)

7(1) A17 Normal operation(3)

8(1) A18 Normal operation(3)

9(1) A19 Normal operation(3)

10 TMROUT0 Input with pulldown

11 TMRIN0 Input with pullup

12 DRQ0 Input with pullup

13 DRQ1 Input with pullup

14 MCS0 Input with pullup

15 MCS1 Input with pullup

16 PCS0 Input with pullup

17 PCS1 Input with pullup

18 PCS2 Input with pullup

19 PCS3 Input with pullup

20 SCLK Input with pullup

21 SDATA Input with pullup

22 SDEN0 Input with pulldown

23 SDEN1 Input with pulldown

24 MCS2 Input with pullup

25 MCS3/RFSH Input with pullup

26(1,2) UZI Input with pullup

27 TXD Input with pullup

28 RXD Input with pullup

29(1,2) S6/CLKDIV2 Input with pullup

30 INT4 Input with pullup

31 INT2 Input with pullup

Associated Pin PIO No Power-On Reset Status

A17(1) 7Normal operation(3)

A18(1) 8Normal operation(3)

A19(1) 9Normal operation(3)

DEN 5 Normal operation(3)

DRQ0 12 Input with pullup

DRQ1 13 Input with pullup

DT/R 4 Normal operation(3)

INT2 31 Input with pullup

INT4 30 Input with pullup

MCS0 14 Input with pullup

MCS1 15 Input with pullup

MCS2 24 Input with pullup

MCS3/RFSH 25 Input with pullup

PCS0 16 Input with pullup

PCS1 17 Input with pullup

PCS2 18 Input with pullup

PCS3 19 Input with pullup

PCS5/A1 3 Input with pullup

PCS6/A2 2 Input with pullup

RXD 28 Input with pullup

S6/CLKDIV2(1,2) 29 Input with pullup

SCLK 20 Input with pullup

SDATA 21 Input with pullup

SDEN0 22 Input with pulldown

SDEN1 23 Input with pulldown

SRDY 6 Normal operation(4)

TMRIN0 11 Input with pullup

TMRIN1 0 Input with pullup

TMROUT0 10 Input w ith pulldown

TMROUT1 1 Input with pulldown

TXD 27 Input with pullup

UZI(1,2) 26 Input w ith pul lup

Am186/188EM and Am186/188EMLV Microcontrollers 31

PRELIMINARY

Read Strobe (output, synchronous, three-state)

This pin indicates to the system that the microcontroller

is perf orming a me mory or I/O read cycle. RD is guar-

anteed not to be asserted before the address and data bus

is floated dur ing the address -to-data transiti on. RD floats

during a bus hold condition.

RES

Reset (input, asynchronous, level-sensitive)

This pin requires the microcontroller to perform a reset.

When RES is asserted, the microcontroller immediately

terminates its present activity, clears its internal logic, and

CPU control is transferred to the reset address FFFF0h.

RES must be held Low for at least 1 ms.

RES can be asserted asynchronously to CLKOUTA

because RES is synchronized internally. For proper ini-

tial izat ion, V CC must be wi thin spec ificati ons, and CLK-

OUTA must be stable for more than four CLKOUTA

periods during which RES is asserted.

The microcontroller begins fetching instructions ap-

proximately 6.5 CLKOUTA periods after RES is deas-

serted. This input is provided with a Schmitt trigger to

facilitate power-on RES generation via an RC network.

RFSH2/ADEN

(Am188EM Microcontroller Only)

Refresh 2 (three-state, output, synchronous)

Address Enable (input, internal pullup)

RFSH2—Asser ted Lo w to si gni fy a DRAM r efres h b us

cycle. The use of RFSH2/ADEN to signal a refresh is

not vali d when P SR AM mo de is sele cted. I nst ead, the

MCS3/RFSH signal is provided to the PSRAM.

ADEN—If RFSH2/ADEN is held High or left floating on

power-on reset, the AD bus (AO15–AO8 and AD7–

AD0) is enabled or disabled during the address portion

of LCS and UCS bus cycles based on the DA bit in the

LMCS and UMCS registers. If the DA bit is set, the

memory address is accessed on the A19–A0 pins. This

mode of operation reduces power consumption. For

more information, see the “Bus Operation” section on

page 37. There is a weak internal pullup resistor on

RFSH2/ADEN so no external pullup is required.

If RFSH2/ADEN is held Low on power-on r eset, the A D

bus drives both addresses and data regardless of the DA

bit setting. The pin is sampled one crystal clock cycle after

the rising edge of RE S. R FS H 2/ADEN is three-stated

during bus holds and ONCE mode.

RXD/PIO28

Receive Data (input, asynchronous)

This pin supplies asynchronous serial receive data

from the syste m to t he i nter nal UA RT of t he m icr oco n-

troller.

S2–S0

Bus Cycle Status (output, three-state,

synchronous)

These pins indicate to the system the type of bus cycle

in progress. S2 ca n be u sed as a lo gical memory or I/O

indicator, and S1 can be used as a data transmit or receive

indicator . S 2–S0 float during bus hold and hold ac knowl-

edge conditions. The S2–S0 pins are encoded as show n

in Tabl e 4.

Table 4. Bus Cycle Encoding

S6/CLKDIV2/PIO29

Bus Cycle Status Bit 6 (output, synchronous)

Clock Divide by 2 (input, internal pullup)

S6—During the second and remaining periods of a

cycle (t2, t3, and t4), this pin is asserted High to indicate

a DMA-initiated bus cycle. During a bus hold or reset

condition, S6 floats.

CLKDIV2—If S6/CLKDIV2/PIO29 is held Low during

power-on reset, the chip enters clock divided by 2

mode where the processor clock is derived by dividing

the external clock input by 2. If this mode is selected ,

the PLL is disabled. The pin is sampled on the rising

edge of RES.

If S6 is t o be us ed as PIO 29 in in put mod e, the devi c e

driving PIO29 must not drive the pin Low during power-

on reset. S6/CLKDIV2/PIO29 defaults to a PIO input with

pullup, so the pi n does not need to be d riven Hi gh exte r-

nally.

S2 S1 S0 Bus Cycle

000Interrupt acknowledge

001Read data from I/O

0 1 0 Write data to I/O

011Halt

100Instruction fetch

101Read data from memory

110Write data to memory

111None (passive)

32 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

SCLK/PIO20

Serial Clock (output, synchronous)

This pin supplies the synchronous serial interface (SSI)

clock to a slave device, allowing transmit and receive

operatio ns to be synchroniz ed between the mic rocon-

troller and the slave. SCLK is derived from the micro-

control ler interna l clock a nd then divi ded by 2, 4, 8, or

16 depending on register settings.

An access to any of the SSR or SSD registers activates

SCLK for eight SCLK cycles (see Figure 11 and Figure

12 on page 49). When SCLK is inactive, it is held High

by the microcontroller.

SDATA/PIO21

Serial Data (input/output, synchronous)

This pin transmits synchronous serial interface (SSI)

data to and from a slave device. When SDATA is inac-

tive, a weak k eeper holds the last v alue of SDATA on

the pin.

SDEN1/PIO23, SDEN0/PIO22

Serial Data Enables (output, synchronous)

These pins enabl e data transfers on port 1 and port 0

of the synchronous serial interface (SSI). The micro-

controller asserts either SDEN1 or SDEN0 at the be-

ginning o f a transfe r and d easse rts it aft er the t ransfer

is complete. When SDEN1–SDEN0 are inactive, they

are held Low by the microcontroller.

SRDY/PIO6

Synchronous Ready (input, synchronous,

level-sensitive)

This pin indicates to the microcontroller that the ad-

dressed memory space or I/O device will complete a

data transfer. The SRDY pin accepts an active High

input synchronized to CLKOUTA .

Using SRDY instead of ARDY allows a relaxed system

timing be ca use of the el imina tion of the one-hal f cloc k

period req ui re d to in ternal ly s ync hr onize A RDY. To al-

ways assert the ready conditi on to the microc ontroll er,

tie SRDY High. If the system does not use SRDY, tie

the pin Low to yield control to ARDY.

TMRIN0/PIO11

Timer Input 0 (input, synchronous, edge-sensitive)

This pin supplies a clock or control signal to the internal

microcontroller timer 0. After internally synchronizing a

Low-to-High tr a nsi ti on on TM RIN0, th e mi croc on tro ller

increm ents t he timer . TMRIN0 must be ti ed Hi gh if no t

being used.

TMRIN1/PIO0

Timer Input 1 (input, synchronous, edge-sensitive)

This pin supplies a clock or control signal to the internal

microcontroller timer 1. After internally synchronizing a

Low-to-H igh t ra nsiti on on TM RIN1, th e mi cr oc on troll er

increm ents the ti mer. TMRIN1 m ust be ti ed Hi gh if no t

being used.

TMROUT0/PIO10

Timer Output 0 (output, synchronous)

This pin sup plies the sy stem w ith eith er a sin gle puls e

or a continuous waveform with a programmable duty

cycle. TMROUT0 is floated during a bus hold or reset.

TMROUT1/PIO1

Timer Output 1 (output, synchronous)

This pin sup plies the sy stem w ith eith er a sin gle puls e

or a continuous waveform with a programmable duty

cycle. TMROUT1 can also be programmed as a watch-

dog timer. TMROUT1 is floated during a bus hold or re-

set.

TXD/PIO27

Transmit Data (output, asynchronous)

This pin sup plies a synchr onous seri al trans mit data t o

the system from the internal UART of the microcontrol-

ler.

UCS/ONCE1

Upper Memory Chip Select (output, synchronous)

ONCE Mode Request 1 (input, internal pullup)

UCS—This pin i ndicates to the system th at a memory

access is i n pr ogress to th e uppe r memor y bloc k. Th e

base addre ss and size of the upp er memo ry block are

programmable up to 512 Kbytes. UCS is held High dur-

ing a bus hold condition.

After pow er-o n res et, UCS is asserted because the pro-

cessor begins executing at FFFF0h and the default config-

uration for the UCS chip select is 64 Kbytes from F0000h

to FFFFFh.

ONCE1—During reset, this pin and ONCE0 indicate to

the microcontroller the mode in which it should operate.

ONCE0 and ONCE1 are sampled on the rising edge of

RES. If both pins are asserted Low, the microcontroller

enters ONCE mode. Otherwise, it operates normally. In

ONCE mo de, al l pi ns ass ume a high -impedan ce s tate

and remain in that state until a subsequent reset oc-

curs. To guarantee that the microcontroller does not in-

advertently enter ONCE mode, ONCE1 has a weak

internal pullup resistor that is active only during a reset.

This pin is not three-stated during a bus hold condition.

Am186/188EM and Am186/188EMLV Microcontrollers 33

PRELIMINARY

UZI/PIO26

Upper Zero Indicate (output, synchronous)

UZI—This pin lets the designer determine if an access

to the interrupt vector table is in progress by ORing it

with bits 15–10 of the address and data bus (AD15–

AD10 on the 18 6 and AO15 –AO 1 0 on th e 188 ). UZI is

the logica l OR of th e inver ted A1 9–A 16 bits, and it as-

serts in the first period of a bus cycle and is held

throughout the cycle.

This signal s ho uld be pu ll ed Hi gh or a llowed to fl oat a t

reset. If this pin is Low at the negation of reset, the

Am186EM and Am188EM microcontrollers will enter a re-

served clock test mode.

VCC

Power Supply (input)

These pins supply power (+5 V) to the microcontroller.

WHB (Am186EM Microcontroller Only)

Write High Byte (output, three-state, synchronous)

This pin and WLB indicate to the sys tem which by tes of

the data bu s (uppe r, lower, o r both) par ticipate i n a writ e

cycle. In 80 C186 designs , this informa tion is provid ed by

BHE, AD0, and WR. However, by using WHB and WLB,

the standard system inte rface logic and exte rnal addre ss

latch that were required are eliminated.

WHB is asserted with AD15–AD8. WHB is the logical

OR of BHE and WR. This pin floats during reset.

WLB (Am186EM Microcontroller Only)

WB (Am188EM Microcontroller Only)

Write Low Byte (output, three-state, synchronous)

Write Byte (output, three-state, synchronous)

WLB—This pin and WHB indica te to th e sys tem whic h

bytes of the data bus (upper, lower, or both) participate

in a write cycle. In 80C186 desi gns, this infor mation is

provided by BHE, AD0, and WR. However, by using

WHB and WLB, the standard system interface logic

and external address latch that were required are elim-

inated.

WLB is asserted with AD7–AD0. WLB is the logical OR

of AD0 and WR. This pin floats during reset.

WB—On the Am188EM microcontroller, this pin indi-

cates a write to the bus. WB uses the same early timing

as the nonmu ltiplexed ad dress bus . WB is asso ciated

with AD7–AD0. This pin floats during reset.

Write Strobe (output, synchronous)

This pin indicates to the system that the data on the bus

is to be written to a memory or I/O device. WR floats

during a bus hold or reset condition.

Crystal Input (input)

This pi n and the X2 p in p rovide conn ections for a fu n-

damental mode or third-overtone parallel-resonant

crystal used by the internal oscillator circuit. To provide

the microcontroller with an external clock source, con-

nect the s ourc e to the X1 pi n an d l eav e th e X 2 p in u n-

connected.

Crystal Output (output)

This pi n and the X1 p in p rovide conn ections for a fu n-

damental mode or third-overtone parallel-resonant

crystal used by the internal oscillator circuit. To provide

the microcontroller with an external clock source, leave

the X2 pin unconnected and connect the source to the

X1 pin.

34 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

FUNCTIONAL DESCRIPTION

AMD’s Am186 and Am188 family of microcontrollers

and microprocessors is based on the architecture of

the original 8086 and 8088 microcontrollers and cur-

rently includes the 80C186, 80C188, 80L186, 80L188,

Am186EM, Am188EM, Am186EMLV, Am188EMLV,

Am186ES, Am188ES, Am186ESLV, Am188ESLV,

Am186ER, and Am 188E R mic roc ontr olle rs.

All family members contain the same basic set of

registe rs, instruct ions, and a ddressing mod es and are

compatible with the industry-standard 80C186/188

microcontrollers.

A full description of all the Am186EM and Am188EM

microcontroller registers is included in the

Am186EM

and Am188 EM Micro control lers User ’s M anual

, order#

19713. The instruction set for the Am186EM and

Am188EM m icrocont roller s is d ocu mented i n the

Am186

and Am188 Family Instruction Set Manual

, order# 21267.

Memory Organization

Memory is organized in sets of segments. Each seg-

ment is a linear contiguous sequence of 64K (216) 8-bit

bytes. Memory is addressed using a two-component

address that consists of a 16-bit segment value and a

16-bit offset. The 16-bit segment values are contained

in one of four internal segment registers (CS, DS, SS,

or ES). The physical address is calculated by shifting

the segment value left by 4 bits and adding the 16-bit

offset value to yield a 20-bit physical address (see Figure 3).

This all ows f or a 1 -Mbyt e ph ysical ad dress size .

All instructions that address operands in memory must

specify the segment v alue and the 16- bit offset val ue.

For speed a nd compac t instruc tion en codin g, the se g-

ment register used for physical address generation is

implied by the addre ss in g mode us ed (see Ta bl e 5).

Figure 2. Two-Component Address

I/O Space

The I/O space consists of 64K 8-bit or 32K 16-bit ports.

Separate instructions (IN, INS and OUT, OUTS) ad-

dress the I/O space with either an 8-bit port address

specified in the instruction, or a 16-bit port address in

the DX register. Eight-bit port addresses are zero-ex-

tended so that A15–A8 are Low. I/O port addresses

00F8h through 00FFh are reserved. The Am186EM

and Am188EM microcontrollers provide specific in-

structions for addressing I/O space.

Table 5. Segment Register Selection Rules

1 2 A 4 0

0 0 0 2 2

1 2 A 6 2

1 2 A 4

0 0 2 2

Segment

Base Logical

Address

Shift

Left

4 Bits

Physical Address

To Me mory

15 0

19 0

15 0

Offset

Memory Reference

Needed Segment Register

Used Implicit Segment Selection Rule

Instructions Code (CS) Instructions (including immediate data)

Local Data Data (DS) All data references

Stack Stack (SS) All stack pushes and pops;

any memory references that use BP Register

External Data (Global) Extra (ES) All string instruction references that use the DI Register as an index

Am186/188EM and Am186/188EMLV Microcontrollers 35

PRELIMINARY

BUS OPERATION

The indus tr y-s tan dar d 80 C186 a nd 80C 188 mic roco n-

trollers use a multiplexed address and data (AD) bus.

The addres s is prese nt on the A D bus only during the

t1 clock phase. The Am186EM and Am188EM microcon-

trollers continue to provide the multiplexed AD bus and, in

addition, provide a nonmultiplexed address (A) bus. The A

bus provides an address to the system for the complete

bus cycle (t1–t4).

For systems where power consumption is a concern, it

is possible to disable the address from being driven on

the AD bus on the Am186EM microcontroller and on

the AD and AO buses on the Am188EM microcontroller

during the normal address portion of the b us cycle for

accesses to UCS and/or LCS address spaces. In this

mode, the affec ted bus is placed in a hig h impedan ce

state duri ng the address porti on of the bus cycle . This

feature is enabled through the DA bits in the UMCS and

LMCS registers. When address disable is in effect, the

number of signals that assert on the bus during all nor-

mal bus c ycles to th e assoc iated addr ess space is re-

duced, decreasing power consumption and reducing

processor switching noise. On the Am188EM micro-

controller, the address is driven on A015–A08 during

the data portion of the bus cycle, regardless of the set-

ting of the DA bits.

If the ADEN pin is pulled Low during processor reset, the

value of the DA bits in the UMCS and LMCS registers is

ignored and the address is driven on the AD bus for all ac-

cesses, thus preserving the industry-standard 80C186

and 80C188 microcontrollers’ multiplexed address bus

and providing support for existing emulation tools.

The following diagrams show the Am186EM and

Am188EM microcontroller bus cycles when the ad-

dress bus disable feature is in effect.

Figure 3 shows the affected signals during a normal

read or wri te operati on for a n Am186 EM micr ocont rol-

ler. The ad dress and d ata will be multiplexe d onto the

AD bus.

Figure 4 shows an Am186EM microcontroller bus cycle

when address bus disable is in effect. This results in

having the AD bus operate in a nonmultiplexed ad-

dress/data mode. The A bus will have the address dur-

ing a read or write operation.

Figure 5 shows the affected signals during a normal

read or wri te operati on for a n Am188 EM micr ocont rol-

ler. The multiplexed address/data mode is compatible

with the 80C186 and 80C188 microcontrollers and

might be used to take advantage of existing logic or pe-

ripherals.

Figure 6 shows an Am188EM microcontroller bus cycle

when address bus disable is in effect. The address and

data is not multiplexed. The AD7–AD0 signals will have

only data on the bus, while the AO bus will have the ad-

dress during a read or write operation.

Figure 3. Am186EM Microcontroller Address Bus—Normal Read and Write Operation

CLKOUTA

t1t2t3t4

AD15–AD0

(Read) Data

AD15–AD0

(Write)

LCS or UCS

Address

DataAddress

Address

Phase Data

Phase

A19–A0 Address

MCSx, PCSx

36 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

Figure 4. Am186EM Microcontroller—Read and Write with Address Bus Disable In Effect

Figure 5. Am188EM Microcontroller Address Bus—Normal Read and Write Operation

CLKOUTA

t1t2t3t4

AD15–AD0

(Write) Data

LCS, UCS

AD15–AD8

(Read)

AD7–AD0

(Read)

Address

Phase

Data

Phase

Data

A19–A0 Address

CLKOUTA

t1t2t3t4

AD7–AD0

(Read) Data

AO15–AO8

(Rea d or Write)

AD7–AD0

(Write)

Address

DataAddress

Address

Phase Data

Phase

A19–A0 Address

LCS or UCS

MCSx, PCSx

Am186/188EM and Am186/188EMLV Microcontrollers 37

PRELIMINARY

Figure 6. Am188EM Microcontroller—Read and Write with Address Bus Disable In Effect

BUS INTERFACE UNIT

The bus interface unit controls all accesses to external

peripherals and memory devices. External accesses

include those to memory devices, as well as those to

memory- mappe d and I/O- mappe d peri pherals and the

peripheral control block. The Am186EM and

Am188EM microcontrollers provide an enhanced bus

interface unit with the following features:

nA nonmultiplexed address bus

nSeparate b yte w rite enabl es f or h igh and l ow by tes

in the Am186EM mic roc ontr o ll er only

nPseudo Static RAM (PSRAM) support

The standard 80C186/188 multiplexed address and

data bu s requi res syst em int erfac e logic and an exter -

nal address latch. On the Am186EM and Am188EM

microcontrollers, new byte write enables, PSRAM con-

trol logic, and a new nonmultiplexed address bus can

reduce design costs by eliminating this external logic.

Nonmultiplexed Address Bus

The nonmultiplexed address bus (A19–A0) is valid

one-half CLKOUTA cycle in advance of the address on

the AD bus. When used in conjunction with the modi-

fied UCS and LCS outputs and the byte write enable sig-

nals, the A19– A0 bus provides a seamless interface to

SRAM, PSRAM, and Flash/EPROM memory systems.

Byte Write Enables

The Am186EM microcontroller provides the WHB

(Write High Byte) and WLB (Write Low Byte) signals, which

act as byte write enables.

WHB is the logical OR of BHE and WR. WHB is Low

when BHE and WR are both Low. WLB is the logical

OR of AD0 a nd WR. WLB is Low when AD0 and WR

are both Low. WB is Low whenever a byte is written on

the Am188EM microcontroller.

The byte write enables are driven in conjunction with

the nonmultiplexed address bus as required for the

write timing requirements of common SRAMs.

CLKOUTA

t1t2t3t4

AD7–AD0

(Read) Data

Address

AO15–AO8

LCS, UCS

AD7–AD0

(Write) Data

Address

Phase Data

Phase

A19–A0 Address

38 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

Pseudo Static RAM (PSRAM) Support

The Am186EM and Am188EM microcontrollers sup-

port the use of PSRAM devices in low memory chip-se-

lect (LCS) space only. When PSRAM mode is enabled,

the timing for the LCS signal is modified by the chip-select

control unit to provide a C S precharge period during

PSRAM accesses. The 40-MHz timing of the Am186EM

and Am188EM microcontrollers is appropriate to allow

70-ns PSRAM to run with one wait state. PSRAM mode is

enabled through a bit in the Low Memory Chip-Select

(LM CS) Re giste r. The PSRA M fea ture is disa bled on CPU

reset.

In addition to the LCS ti ming changes for PSRAM pr e-

charge, the PSRAM devices also require periodic refresh of

all in ter na l row add r es ses to r eta in th ei r da ta. Alth ou gh r e-

fresh of PSRAM c an be accompl ished several way s, the

Am186EM and Am188EM microcontrollers implement auto

refresh only.

The Am186EM and Am188EM microcontrollers gener-

ate RFSH, a re fresh s igna l, to the P SRAM dev ices w hen

PSRAM mode is enabled. No refresh address is required

by the PSRAM when us ing the auto refresh m echanism.

The RFSH signal is multiplexed with the MCS3 si gn al pi n.

When PSRAM mode is enabled, MCS3 is not available for

use as a chip-select signal.

The refresh control unit must be programmed before

access ing PSRAM in LCS spac e. The refres h coun ter

in the Clock Prescaler (CDRAM) Register must be con-

figured with the required refresh interval value. The

ending addr ess of LCS spa ce and the ready and wait-

state generation in the LMCS Register must also be

programmed. The refresh counter reload value in the

CDRAM Register should not be set to less than 18

(12h) in order to provide time for processor cycles

within refresh. The refresh address counter must be set

to 000000h to prevent another chip select from assert-

ing.

LCS is held High du ring a refresh cycle. The A bus is

not used during refresh cycles. The LMCS Register

must be configured to external ready ignored (R2=1)

with one wait state (R1–R0=01b), and the PSRAM

mode enable bit (SE) must be set.

PERIPHERAL CONTROL BLOCK (PCB)

The integrated peripherals of the Am186EM and

Am188EM microcontrollers are controlled by 16-bit

read/write registers. The peripheral registers are con-

tained within an internal 256-byte control block. The

registers are physically located in the peripheral de-

vices they control, b ut they are ad dressed as a single

256-byt e block. Figure 7 s hows a map of thes e regis-

ters.

Reading and Writing the PCB

Code that is intended to execute on the Am188EM mi-

crocon troller s hould perfo rm all writes t o the P CB reg-

isters as byte writes. The se writes will tr ansfer 16 bits

of data to the PCB register even if an 8-bit register is

named in the instruction. For example, out dx, al re-

sult s in t he val ue of ax being written to the port address in

dx. Reads to the PCB should be done as word reads.

Code written in this manner will run correctly on the

Am188EM microcontroller and on the Am186EM micro-

controller.

Unaligned reads and writes to the PCB result in unpre-

dictable behavior on both the Am186EM and

Am188EM microcontrollers.

For a complete description of all the registers in the

PCB, see t he

Am186E M and Am 188EM Mic rocontro l-

lers User’s Manual

, order# 19713.

Am186/188EM and Am186/188EMLV Microcontrollers 39

PRELIMINARY

Figure 7. Peripheral Control Block Re gister Ma p

PCS and M CS Auxiliary Register

Memory Partition Register

PDCON Register

Reset Configuration Register

Peripheral Control Block Relocation RegisterFE Registe r Name

Offset

(Hexadecimal)

Clock Prescaler Register

Enable RCU Register

DMA 1 Control Register

DMA 1 Transfer Count Register

DMA 1 Des tination Address Low R egister

DMA 1 Source Address High Register

DMA 1 Source Address Low Register

DMA 0 Control Register

DMA 0 Transfer Count Register

DMA 0 Destination Address High Register

DMA 0 Des tination Address Low R egister

DMA 0 Source Address Low Register

DMA 0 Source Address High Register

Midrange Memory Chip Select Register

Peripheral Chip Select Register

Low Memory Chip Select Register

Upper Memory Ch ip Select Regi ste r

80 Serial Port Status Register

84 Serial Port Receive Register

Processor Release Level Register

DMA 1 Destination Address High Register

Serial Port Baud Rate Divisor Register

Serial Port Transmit Register

Serial Port Control Register

Changed from 80C186

microcontroller.

Note: Gaps in offset addresses indicate

reserved registers.

40 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

Figure 7. Peripheral Control Block Register Map (continued)

Offset

(Hexadecimal)

INT2 Control Register

INT1 Control Register

INT0 Control Register

DMA 1 Interrupt Control Register

DMA 0 Interrupt Control Register

Timer Interrupt Cont rol Register

Interrupt Status Register

Interrupt Request Register

In-service Register

Pri orit y Mask Register

Interrupt Mask Register

Poll Status Regi ster

Poll Register

End-of-Interrupt Register

Interrupt Vector Register

12 Synchronous Serial Transmit 1 Register

PIO Mode 0 Regis ter

Registe r Name

Changed from 80C186

microcontroller.

Note: Gaps in offset addresses indicate

reserved registers.

Timer 2 Mode/Control Register

Timer 2 Maxcount Compare A Register

Timer 2 Count Register

Timer 1 Mode/Control Register

Timer 1 Maxcount Compare B Register

Timer 1 Maxcount Compare A Register

Timer 1 Count Register

Timer 0 Mode/Control Register

Timer 0 Maxcount Compare B Register

Timer 0 Maxcount Compare A Register

Timer 0 Count Register

INT3 Control Register

PIO Data 1 Register

PIO Direction 1 Register

PIO Mode 1 Regis ter

PIO Data 0 Regis t er

PIO Direction 0 Register

Serial Port Interrupt Control Register

Watchdog Timer Control Register

INT4 Control Register

Synchronous Serial Receive Register

Synchronous Serial Transmit 0 Register

Synchronous Serial Enable Register

Synchronous Serial Status Register

Am186/188EM and Am186/188EMLV Microcontrollers 41

PRELIMINARY

CLOCK AND POWER MANAGEMENT

The clock and power management unit of the

Am186EM and Am188EM microcontrollers includes a

phase -locke d loop (PLL ) and a s econd prog ramma ble

system clock output (CLKOUTB).

Phase-Locked Loop (PLL)

In a traditional 80C186/188 design, the crystal frequency is

twice that of the desired internal clock. Because of the

internal PLL on the Am186EM and Am188EM

microcontrollers, the internal clock generated by the

Am186EM and Am188EM microcontrollers (CLKOUTA) is

the same frequency as the crystal. The PL L takes th e

crystal inputs (X1 and X2) and generates a 45/55% (worst

case) duty cycle intermediate system clock of the same

frequency. This removes the need for an external 2x

oscillator, reducing system cost. The PLL is reset by an

on-chip power-on reset (POR) circuit.

Crystal-Drive n Clock Source

The internal oscillator circuit of the Am186EM and

Am188EM microcontrollers is designed to function with

a parallel-resonant fundamental or third-overtone crys-

tal. Because of the PLL, the crystal frequency should

be equal to the pro cessor freq uency . Do not replac e a

crystal with an LC or RC equivalent.

The signals X1 and X2 are connected to an internal in-

verting am pl ifi er ( os cil lato r) whi ch pr ov ides , a lo ng with

the external feedback loading, the necessary phase

shift (F igur e 8) . I n su ch a positiv e f eedback c irc ui t, the

inverting amplifier has an output signal (X2) 180 de-

grees out of phase of the input signal (X1).

The external feedb ack network provides an additional

180-degree phase shift. In an ideal system, the input to

X1 will have 360 or zero degrees of phase shift. The ex-

ternal feedback network is designed to be as close to

ideal as possible. If the feedback network is not provid-

ing necessary phase shift, negative feedback will

dampen the output of the amplifier and negatively af-

fect the operation of the clock generator. Values for the

loading on X1 and X2 must be chosen to provide the

necessary phase shift and crystal operation.

Selecting a Crystal

When se le cting a c rystal , the load c apac itanc e sho uld

always be specified (CL). This value can cause variance

in the oscillati on frequency fro m the desired sp ecified

value (resonance). The load capacitance and the loading

of the feedback network have the following relationship:

where CS is the stra y capacitan ce of the cir cuit. Plac ing

the crystal and C L in ser ies across the i nverti ng amp lifier

and tuning these values (C1, C2) allows th e crys tal to os-

cillate at re sonanc e. This rel ationsh ip is true for both fun-

damental an d thir d-overto ne operati on. Final ly, th ere is a

relationship between C1 an d C2. To en hance t he oscil la-

tion of the inverting amplifier, these values need to be off-

set with the larger load on the output (X2). Equal values of

these load s will ten d to balanc e th e po les of the inv er tin g

amplifier.

The characteristics of the inverting amplifier set limits

on the following parameters for crystals:

ESR (Equivalent Series Resistance)........... 80 ohm max

Drive Level.....................................................................................1 mW max

The recommended range of values for C1 and C2 are as

follows:

C1..............................................................................................................15 pF ± 20%

C2..............................................................................................................22 pF ± 20%

The specific values for C1 and C2 must be determined by

the designer and are depe ndent on the charac teristics of

the chosen crystal and board design.

Figure 8. Am186EM and Am188EM Microcontrollers Oscillator Configurations

(C1 ⋅ C2)

CL = (C1 + C2)+ CS

Crystal

Am186EM

200 pF

Note 1

Note 1: Use for Third Overtone Mode

XTAL Frequency L1 Value (Max)

20 MHz 12

20%

25 MHz 8.2

20%

33 MHz 4.7

20%

40 MHz 3.0

20%

b. Crystal Configuration

a. Inverting Amplifier Configuration

C1C2

Crystal

C2Microcontroller

42 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

External Source Clock

Alternately, the internal oscillator can be driven from an

external clock source. This source should be con-

nected to the inp ut of the inverting ampl ifier (X1), with

the output (X2) not connected.

Syst em Clocks

The base system clock of the 80C186 and 80C188

microcontrollers is renamed CLKOUTA and the

additional output is called CLKOUTB. CLKOUTA and

CLKOUTB operate at either the processor frequency or

the crystal input frequency. The output drivers for both

clocks are individually programmable for disable.

Figure 9 shows the organization of the clocks.

The s eco nd cl oc k ou tp ut (C L KOUTB ) al low s o ne cl oc k

to run at the crystal input frequency and the other clock

to run at the power-save frequency. Individual drive en-

able bits allow s el ec tive enablin g of j us t one or both o f

these cloc k outp uts .

Figure 9. Clock Organization

Power-Save Operation

The power-save mode of the Am186EM and

Am188EM microcontrollers reduces power consump-

tion and heat dissipation, thereby extending battery life

in portable systems. In power-save mode, operation of

the CPU and internal peripherals continues at a slower

clock freq uency. When an interrupt occur s, the micro-

control ler autom atically r eturns to its norm al operating

frequency on the internal clock’s next rising edge of t3.

In order for an interrupt to be recognized, it must be

valid before the internal clock’s rising edge of t3.

Note: Power-save operation requires that clock-de-

pendent devices be reprogrammed for clock frequency

changes . S oft war e driv er s must b e awar e o f c l ock fr e-

quency.

Initialization and Processor Reset

Processor initialization or startup is accomplished by

driving the RES input pin Low. RES must be held Low for

1 ms during power-up to ensure proper device initializa-

tion. RES forces the Am186EM and Am188EM microcon-

trollers to terminate all execution and local bus activity. No

instruction or bus activity occurs as long as RES is active.

After RES becomes inactive and an internal processing in-

terval elapses, the microcontroller begins execution with

the instruction at physical location FFFF0h. RES also se ts

some registers to predefined values.

The Reset Configuration Register

When the RES input is asserted Low, the contents of the

address/ data bus (AD15–AD0) are written int o the Reset

Configuration register. The system can place configura-

tion informat ion on t he addre ss/data bus us ing weak ex-

ternal pullup or pulldown resistors, or u sing an external

driver that is enabled during reset. The processor does not

drive the address/data bus during reset.

For example, the Reset Configuration register could be

used to provide the software with the position of a con-

figuration switch in the system. Using weak external

pullup and pulldown resistors on the address and data

bus, the system would provide the microcontroller with

a value corresponding to the position of the jumper dur-

ing a reset.

PLL Power-Save

Divisor

(/2 to /128)

Mux

CLKOUTA

CLKOUTB

Drive

Enable

Drive

Enable

X1, X2

Processor Internal Clock

Time

Delay

6 ± 2.5ns

Mux

Am186/188EM and Am186/188EMLV Microcontrollers 43

PRELIMINARY

CHIP-SELECT UNIT

The Am186EM and Am188EM microcontrollers con-

tain logic that provides programmable chip-select gen-

eration for both memories and peripherals. The logic

can be programmed to provide ready and wait-state

generation and latched address bits A1 and A2. The

chip-s elect lines are active for all memory a nd I/O cy-

cles in their programmed areas, whether they are gen-

erated by the CPU or by the integrated DMA unit.

The Am186EM and Am188EM microcontrollers pro-

vide six chip-select outputs for use with memory de-

vices and six more for use with peripherals in either

memory space or I/O space. The six chip selects for

memory devices can be used to address three memory

ranges. Each of the six peripheral chip selects ad-

dresses a 256-byte block that is offset from a program-

mable base address. A read or write access to the

corresponding chip select register activates the chip

selects.

Chip-Select Timing

The timing for the UCS and LCS outputs is modified from

the original 80C186 microcontroller. These outputs now

assert in conjunction with the nonmultiplexed address bus

for normal memory timing. To allow these outputs to be

available earlier in the bus cycle, the number of program-

mable memory size selections has been reduced.

Ready and Wait-State Programming

The Am186EM and Am188EM microcontrollers can be

programmed to sense a ready signal for each of the pe-

ripheral or memory chip-sel ect lines. The ready s ignal

can be either the ARDY or SRDY signal. Each chip-se-

lect control register (UMCS, LMCS, MMCS, PACS, and

MPCS) contains a single-bit field that determines

whether the external ready signal is required or ig-

nored.

The number of wait stat es to be inserted for each ac-

cess to a perip heral or me mory regio n is pro gramma-

ble. The chip-select control registers for UCS, L CS ,

MCS3–MCS0, PC S 6, and PC S5 contain a two-bit field

that dete rmines the nu mber of wait states from zero to

three to be inserted. P CS 3–PCS0 use three bits to pro-

vide additional values of 5, 7, 9, and 15 wait states.

When external ready is required, internally pro-

grammed wait states will always complete before ex-

ternal ready can terminate or extend a bus cycle. For

example, if the internal wait states are set to insert two

wait stat es, the proc essor sampl es the exter nal ready

pin during the first wait cycle. If external ready is as-

serted a t that time, the a ccess completes after six cy-

cles (four cycles plus two wait states). If external ready

is not asserted during the first wait stat e, the access is

extended until ready is asserted, which is followed by

one more wait state followed by t4.

Chip-Select Ove rlap

Although progr ammin g the var ious chip select s on the

Am186EM and Am188EM microcontrollers so that mul-

tiple chip select signals are asserted for the same

physical address is not recommended, it may be un-

avoidabl e in so me sy stems. In suc h syste ms, th e chip

sele cts whos e as se rt ion s ov erlap must hav e the sam e

configur ation for ready (e xternal ready r equired or not

required) and the n umber of wa it st ates t o be inserte d

into the cycle by the processor.

The peripheral control block (PCB) is accessed using

internal signals. These internal signals function as chip

selects configured with zero wait states and no external

ready. The refore, the PCB can be progr ammed to ad-

dresses that overlap external chip select signals if

those external chip selects are programmed to zero

wait states with no external ready required.

When over lapping an addi tional chip sel ect with either

the LCS or UCS chip sel ects, it must be note d that set-

ting the Disable Address (DA) bit in the LMCS or UMCS

the AD bus for all accesses for which the associated

chip select is asserted, including any accesses for

which multiple chip selects assert.

The MCS a nd PCS chi p sele ct pins can be configur ed

as either chip selects (normal function) or as PIO inputs

or outputs. It should be noted; however, that the ready

and wait state generation logic for these chip selects is

in effect regardless of their configurations as chip se-

lects or PIOs. This means that if these chip selects are

enabled (by a read or write to the MMCS and MPCS for

the MCS chip selects, or by a read or write to the PACS

and MPCS registers for the PCS chip selects), the

ready and wait state programming for these signals

must agree with the programming for any other chip se-

lects with which their assertion would overlap if they

were configure d as chip selects.

Although the PCS4 si gn al i s n ot av ai la ble on a n ex ter -

nal pin, the ready and wait state logic for this signal still

exists internal to the part. For this reason, the PCS4 ad-

dress spac e must follo w the r ules for o verlapp ing c hip

selects. The ready and wait-state logic for PCS6–

PCS5 is disabled when these signals are configured as

address bits A2–A1.

Failure to configure overlapping chip selects with the

same ready and wait state requirements may cause

the processor to hang with the appearance of waiting

for a ready signal . This behavior may occu r even in a

system in which ready is always asserted (ARDY or

SRDY tied High).

44 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

Configuring PCS in I/O space with LCS or any other

chip select configured for memory address 0 is not con-

sidered overlapping of the chip selects. Overlapping

chip selects refers to configurations where more than

one chip select asserts for the same physical address.

Upper Memory Chip Select

The Am186EM and Am188EM microcontrollers pro-

vide a UCS chip select for the top of memory. On reset,

the Am186EM and Am188EM microcontrollers begin

fetching and executing instructions starting at memory lo-

cation FFFF0h. Therefore, upper memory is usually used

as inst ructio n memo ry. To fa cilitate this usage , U CS de-

faults to active on reset, with a default memory range of 64

Kbytes from F0000h to FFFFFh, with external ready re-

quired and three wait states automatically inserted. The

UCS memory range always ends at FFFFFh. The lower

boundary is programmable.

Low Memory Chip Select

The Am186EM and Am188EM microcontrollers pro-

vide an LCS chip select for the bottom of memory. Since

the interrupt vector table is located at the bottom of mem-

ory starting at 00000h, the LCS pin is usually used to con-

trol data memory. The LCS pin is not active on reset.

Midrange Memory Chip Selects

The Am186EM and Am188EM microcontrollers pro-

vide four chip selects, M CS3–MCS0, for use in a user-

locatable memory block. The base address of the memory

block can be located anyw here within the 1- Mbyte mem-

ory address space, exclusive of the areas associated with

the UCS and LC S chip se lects, as wel l as the address

range of the Peri pheral Chip Sele cts, P C S 6, P CS 5, and

PCS3–PCS0 , if they are map ped to memory. The M CS

address rang e can overl ap th e PCS address range if th e

PCS chip selects are mapped to I/O space.

Unlike the UCS and LCS chip selects, the MCS outputs

assert with the multiplexed AD address bus.

Peripheral Chi p Selec ts

The Am186EM and Am188EM microcontrollers pro-

vide six chip selects, PCS6–PCS5 and PCS3–PCS0,

for use within a user-locatable memory or I/O block.

PCS4 is not available on the Am186EM and Am188EM

microcontrollers. The base address of the memory

block can be located anywhere within the 1-Mbyte

memory address space, exclusive of the areas associ-

ated with the UCS, LCS, and MCS chip s elects, or the y

can be configured to access the 64 Kbyte I/O space.

The PCS pins are not active on reset. PC S 6–PCS5 can

have from zero to three wait states. PCS3–PCS0 can have

four additional wait-state values—5, 7, 9, and 15.

Unlike the UCS and L C S chip selects, the P CS outputs

assert with the multiplexed AD address bus. Note also that

each peripheral chip select asserts over a 256-byte address

range, which is twice the address range covered by periph-

eral chi p s elec ts in t he 80C 18 6 and 80C18 8 micr oco ntrol-

lers.

Am186/188EM and Am186/188EMLV Microcontrollers 45

PRELIMINARY

REFRESH CONTROL UNIT

The Refresh Control Unit (RCU) automatically gener-

ates refresh bus cycles. After a programmable period

of time, the RCU generate s a memory read reques t to

the bus interface unit. The RCU is fixed to three wait

states for the PSRAM auto refresh mode.

If the HLDA pin is active when a refresh request is gen-

erated (indicating a bus hold condition), then the

Am186EM and Am188EM microcontrollers deactivate

the HLDA pi n in order to perfor m a refresh cycl e. The

external bu s m as ter mu st re mov e t he H OL D sign al for

at least one c lock in orde r to allow the r efresh c ycle to

execute. The sequence of HLDA going inactive while

HOLD is being held active can be used to signal a

pending refresh request.

INT ERRU P T CONTROL UN IT

The Am186EM and Am188EM microcontrollers can re-

ceive interrupt requests from a variety of sources, both

internal and external. The internal interrupt controller

arranges the se req uests by prio ri ty and pr es ents them

one at a time to the CPU.

There are six external interrupt sources on the

Am186EM and Am188EM microcontrollers—five

maskable interrupt pins and one nonmaskable interrupt

pin. In addition, there are six total internal interrupt

sources—three timers, two DMA channels, and the

asynchronous serial port—that are not connected to

external pins.

The Am186EM and Am188EM microcontrollers pro-

vide thr ee interrupt s our ces not pr esent on the A m18 6

and Am188 microcontrollers. The first is an additional

external interrupt pin (INT4). This pin operates much

like the already existing interrupt pins (INT3–INT0).

The second is an internal watchdog timer interrupt. The

third is an internal interrupt from the asynchronous se-

rial port.

The five maskable interrupt request pins can be used

as direct interrupt requests, or they can be cascaded

with an 82C59A-compatible external interrupt control-

ler if more inputs are needed. An external interrupt con-

troller can be used as the system master by

programming the internal interrupt controller to operate

in slave mode. In all cases, nesting can be enabled so

that interrupt service routines for lower priority inter-

rupts are interrupted by a higher priority interrupt.

46 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

TIMER CONTROL UNIT

There are three 16-bit programmable timers in the

Am186EM and Am188EM microcontrollers. Timer 0

and timer 1 are connected to four external pins (each

one has an input and an output). These two timers can

be used to count or time external events, or to generate

nonrepeti tive or vari able-duty-cyc le waveforms . In ad-

dition, timer 1 ca n be configured as a watchdog timer

interrupt.

The watchdog timer interrupt provides a mechanism for

detecting software crashes or hangs. The TMROUT1

output is internally connected to the watchdog timer in-

terrupt. The TIMER1 count register must then be re-

loaded at intervals less than the TIMER1 max count to

assure the watc hdog in terrupt is n ot take n. If the c ode

crashes or hangs, the TIMER1 countdown will cause a

watchdog interrupt.

Timer 2 is not connected to any external pins. It can be

used for real-time coding and time-delay applica tions.

It can als o be used a s a presc ale to tim ers 0 and 1 or

as a DMA request source.

The timers are controlled by eleven 16-bit registers in

the periphe ral control blo ck. A timer’s tim er-count re g-

ister contains the current value of that timer. The timer-

count register can be read or written with a value at any

time, regardless of whether the timer is running. The

microcontroller increments the value of the timer-count

Each timer also has a maximum-count register that de-

fines the maximum value the timer will reach. When the

timer reaches the maximum value, it resets to 0 during

the same clock cycle—the value in the maximum-count

Also, timers 0 and 1 have a secondary maximum-count

mum-count registers lets the timer alternate between

two maximum values.

If the timer is programmed to use only the primary max-

imum-count register, the timer output pin switches Low

for one clock cycle after the maximum value is

reached. If the timer is programmed to use both of its

maximum-count registers, the output pin indicates

which maximum-count register is currently in control,

thereby creating a waveform. The duty cycle of the

waveform depends on the values in the maximum-

count regis te rs .

Each timer is serviced every fourth clock cycle, so a

timer c an operate at a speed of up to one -quarter the

internal clock frequency. A timer can be clocked exter-

nally a t this sa me frequenc y; however, because of in-

ternal synchronization and pipelining of the timer

circuitry, the timer output may take up to six clock cy-

cles to respond to the clock or gate input.

DIRECT MEMORY ACCESS (DMA)

Direct memory access (DMA) permits transfer of data

between memory and peripherals without CPU involve-

ment. The DMA unit in the Am186EM and Am188EM

microcontrollers, shown in Figure 10, provides two

high-speed DMA channels. Da ta tr an sfe rs ca n o cc ur b e-

tween memory and I/O spaces (e.g., memory to I/O ) or

within the same space (e.g., memory-to-memory or I/O-to-

I/O). In addition, ei ther byte s or words can be tr ansferre d

to or from even or odd addresses on the Am186EM micro-

controller. The Am188EM microcontroller does not sup-

port word transfers. Only two bus cycles (a minimum of

eight clocks) are necessary for each data transfer.

Each channel accepts a DMA request from one of

three sources—the channel request pin (DRQ1–

DRQ0), timer 2 , or the system software . The cha nne ls

can be programmed with different priorities in the event

of a simul tane ous DMA re que st o r if ther e i s a n eed to

interrupt transfers on the other channel.

DMA Operation

Each channel has six registers in the peripheral control

block that define specific channel operations. The DMA

registers consist of a 20-bit source address (2 regis-

ters), a 20-bit destination address (2 registers), a 16-bit

transfer count register, and a 16-bit control register.

The DMA transfer count register (DTC) specifies the

number of DMA transfers to be performed. Up to 64K

byte or word transfers can be performed with automatic

termination. The DMA control registers define the

chann el op eration. Al l re gi st e rs c an be mo d i fi ed dur -

ing any DMA activity. Any changes made to the DMA

registers are reflected immediately in DMA operation.

Table 6. Am186EM Microcontroller Maximum

DMA Transfer Rates

Type of Synchronization

Selected

Maxim um DMA

Transfer Rate (Mbyte/s)

MHz 33

MHz 25

MHz 20

MHz

Unsynchronized 10 8.25 6.25 5

Source Synch 10 8.25 6.25 5

Destin ati on Syn ch

(CPU needs bus) 6.6 5.5 4.16 3.3

Destin ati on Syn ch

(CPU does not need bus) 86.6 5 4

Am186/188EM and Am186/188EMLV Microcontrollers 47

PRELIMINARY

Figure 10. DMA Unit Block Diagram

DMA Channel Control Registers

Each DMA control register determines the mode of op-

eration for the particular DMA channel. This register

specifie s the following:

nThe mode of synchronization

nWhether bytes or words are transferred

nIf an interrupt is generated after the last transfer

nIf DMA activity ceases after a programmed number

of DMA cycles

nThe relative priority of the DMA channel with re-

spect to the other DMA channel

nWhether the source address is incremented, decre-

mented, or maintained constant after each transfer

nWhether the source address addresses memory or

I/O space

nWhether the destination address is incremented,

decremented, or maintained constant after trans-

fers

nWhether the destination address addresses mem-

ory or I/O space

DMA Priority

The DMA channels can be programmed so that one

chann el is alw ays given prior ity over the other, or t hey

can be programmed to alternate cycles when both

have DMA requests pending. DMA cycles always have

priority over internal CPU cycles, except between

locked memory accesses or word accesses to odd

memory locations. However, an external bus hold

takes priority over an internal DMA cycle.

Because an interrupt request cannot suspend a DMA

operatio n and the CP U ca nnot a ccess memory dur ing

a DMA cycle, interrupt latency time suffers during se-

quences of continuous DMA cycles. An NMI request,

howeve r, causes all in ternal DMA acti vity to halt. This

allows the CPU to respond quickly to the NMI request.

Source Address Ch. 1

Source Address Ch. 0

20-bit Adder/Subtractor

DMA

Control

Logic

Request

Selection

Logic

Adder Control

Logic

Channel Control Register 1

Channel Control Register 0

DRQ1

DRQ0

Internal Address/Data Bus

Timer Request

Interrupt

Request

Transfer Counter Ch. 1

Destinat ion Address Ch. 1

Destination Add ress C h. 0

Transfer Counter Ch. 0

48 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

ASYNCHRONOUS SERIAL PORT

The Am186EM and Am188EM microcontrollers pro-

vide an asynchronous serial port. The asynchronous

serial port is a two-pin interface that permits full-duplex

bidirectional data transfer. The asynchronous serial

port supports the following features:

nFull-duplex operation

n7-bit or 8-bit data transfers

nOdd, ev en, or no parity

n1 or 2 stop bits

If additi onal RS-232 s ignals a re requ ired, they can be

created with available PIO pins. The asynchronous se-

rial por t tra nsmi t a nd r ec ei ve s ec tio ns a re d oub le buff-

ered. Break character, framing, parity, and overrun

error detection are provided. Exception interrupt gener-

ation is programmable by the user.

The transmit/receive clock is based on the internal pro-

cessor clock, which is divided down internally to the se-

rial port operating frequency. The serial port permits 7-

bit and 8- bi t dat a tr ansfe rs . DM A t rans fer s t hrough the

serial port are not supported.

The serial port generates one interrupt for any of three

serial port events—transmit complete, data received,

and error.

The serial port can be used in power-save mode, but

the software must adjust the transfer rate to correctly

reflect the new inte rnal operating frequency and must

ensure that the serial port does not receive any infor-

mation while the frequency is being changed.

SYNCHRONOUS SERIAL INTERFACE

The synchronous serial interface (SSI) lets the

Am186EM and Am188EM microcontrollers communi-

cate with application-specific integrated circuits

(ASICs) that require reprogrammability but are short on

pins. This four-pin interface permits half-duplex, bidi-

rectional data transfer at speeds of up to 20 Mbits/sec.

Unlike the asynchronous serial port, the SSI operates

in a master/slave configuration. The Am186EM and

Am188EM microcontrollers are the master port.

The SSI interface provides four pins for communicating

with system components: two enables (SDEN0 and

SDEN1), a clock (SCLK), and a data pin (SDATA). Five

registers are used to control and monitor the interface.

Four-Pin Interface

The two enable pins SDEN1–SDEN0 can be used di-

rectly as enables for up to two peripheral devices.

Transmit an d r ec ei ve o per ati on s are s y nchr oni ze d b e-

tween the master (Am186EM and Am188EM micro-

controllers) and slave (peripheral) by means of the

SCLK output. SCLK is derived from the internal proces-

sor clo ck and is the p ro ce ss or cl oc k d iv id ed by 2, 4, 8,

or 16.

Am186/188EM and Am186/188EMLV Microcontrollers 49

PRELIMINARY

Figure 11. Synchronous Serial Interface Multiple Write

Figure 12. Synchronous Serial Interface Multiple Read

SCLK

SDEN

SDATA

Write to SSC,

bit DE=1

Write to SSD

Poll SSS for

PB=0

Write to SSD

Poll SSS for

PB=0

Write to SSD Write to SSC,

bit DE=0

Poll SSS for

PB=0

DR/DT=0 PB=1

DR/DT=0 PB=0

DR/DT=1 PB=1

DR/DT=0 PB=0

DR/DT=1 PB=1

DR/DT=0 PB=0

DR/DT=1 PB=0

DR/DT=0

SCLK

SDEN

SDATA

Write to SSC,

bit DE=1

Write to SSD

Poll SSS for

PB=0

Read from SSR

(dummy)

Poll SSS for

PB=0

Read from

SSR Write to SSC,

bit DE=0

Poll SSS for

PB=0

DR/DT=0 PB=1

DR/DT=0 PB=0

DR/DT=1 PB=1

DR/DT=0 PB=0

DR/DT=1 PB=1

DR/DT=0 PB=0

DR/DT=1 PB=0

DR/DT=0

Read from SSR

50 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

PROGRAMMABLE I/O (PIO) PINS

There are 32 pins on the Am186EM and Am188EM mi-

crocontrollers that are available as user multipurpose

signals. Table 2 and Table 3 on page 30 list the PIO

pins. Each of these pins can be used as a user-pro-

grammabl e input or output s ignal if the normal shared

function is not needed.

If a pin is enable d to function as a PIO signal , the pre-

assigned signal function is disabled and does not affect

the level on the pi n. A P IO s ign al ca n b e c onf igu red to

operate as an input or output with or without a weak

pullup or pulldown, or as an open-drain output.

After power-on reset, the PIO pins default to various

configurations. The column titled

Power-On Reset Sta-

tus

in Table 2 and Table 3 on page 30 lists the defaults for

the PIOs. The system initialization code must reconfigure

the PIOs as required.

The A19–A17 address pins default to normal operation

on power-on reset, a llowing the processor t o correct ly

begin fetching instructions at the boot address

FFFF0h. The DT/R, DEN, and SRDY pins also default to

normal operation on power-on reset.

Note that emulators use A19, A18, A17, S6, and UZI.

If the AD15–AD0 bus ov erri de is ena ble d on power-on

reset, th en S6/CLKDIV2 and UZI revert to normal opera-

tion instead of PIO i nput with pullu p. If B HE /ADEN (1 86)

or RFSH2/ADEN (188) is held Low during power-on reset

the AD15–AD0 bus override is enabled.

Am186/188EM and Am186/188EMLV Microcontrollers 51

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Storage temperature

Am186EM/Am188EM .....................–65°C to +125°C

Am186EMLV/Am188EMLV.............–65°C to +125°C

Voltage on any pin with respect to ground

Am186/188EM ...........................–0.5 V to Vcc +0.5 V

Am186/188EMLV.......................–0.5 V to Vcc +0.5 V

Note: Stresses above those listed under Absolute

Maximum Ratings may cause permanent device failure.

Functionality at or above these limits is not implied. Ex-

posure t o ab so lut e ma xi mum r atings fo r e xte nde d pe ri-

ods may affect device reliability.

OPERATING RANGES

Operating Ranges define those limits between which

the functionality of the device is guaranteed.

Am186EM/Am188EM Microcontrollers

Commercial (TC) .................................0°C to +100°C

Industrial* (TA)...................................–40°C to +85°C

VCC up to 33 MHz..................................... 5 V ± 10%

VCC greater than 33 MHz............................ 5 V ± 5%

Am186EMLV/Am188EMLV Microcontrollers

Commercial (TA) ...................................0°C to +70°C

VCC up to 25 MHz.................................3.3 V ± 0.3 V

Where: TC = case temperature

TA = ambient temperature

*Industrial ve rsions of Am186EM and Am188EM microcontrol-

lers are available in 20 and 25 MHz operating frequencies

only.

DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGE

Notes:

a The

LCS/ONCE0

MCS3–MCS0

UCS/ONCE1

, and

pins have weak i nternal pul lup resistors. L oading the

LCS/ONCE0

and

UCS/ONCE1

pins in ex cess of I

= –200

A during reset ca n cause t he devic e to go into ONCE mode.

b Current is measured with the device in RESET with

and

driven, and all other non-power pins open but held High or Low.

c Power supply current for the Am186EMLV and Am188EMLV microcontrollers, which are available in 20 and 25 MHz

operating frequencies only.

d Testing is performed with the pins floating, either during HOLD or by invoking the ONCE mode.

Preliminary

Symbol Parameter Description Test Conditions Min Max Unit

VIL Input Low Voltage (Except X1) –0.5 0.8 V

VIL1 Clock Input Low Voltage (X1) –0.5 0.8 V

VIH Input High Voltage (Except RES and X1) 2.0 VCC + 0.5 V

VIH1 Input High Voltage (RES) 2.4 VCC + 0.5 V

VIH2 Clock Input High Voltage (X1) VCC – 0.8 VCC + 0.5 V

VOL

Output Low Voltage

Am186EM and Am188 EM IOL= 2.5 mA (S2–S0)

IOL= 2.0 mA (others) 0.45 V

Am186EMLV and Am188EMLV IOL= 1.5 mA (S2–S0)

IOL= 1.0 mA (others) 0.45 V

VOH

Output High Voltage(a)

Am186EM and Am188 EM IOH= –2.4 mA @ 2.4 V 2.4 VCC +0.5 V

IOH= –2 00 µA @

–0.5 VCC –0.5 VCC V

Am186EMLV and Am188EMLV IOH= –2 00 µA @

–0.5 VCC –0.5 VCC V

ICC

Power Supply Current @ 0°C

Am186EM and Am188 EM VCC = 5.5 V (b) 5.9 mA/

MHz

Am186EMLV and Am188EMLV VCC = 3.6 V (b) 2.75 mA/

MHz

VOL Output Lo w Voltage IOL = 2.5 mA (S2–S0)

IOL = 2.0 mA (others) 0.45 V

ILI Input Leakage Current @ 0.5 MHz 0.45 V ≤ VIN ≤ VCC ±10 µA

ILO Output Leakage Current @ 0.5 MHz 0.45 V ≤ VOUT ≤ VCC(d) ±10 µA

VCLO Clock Output Low ICLO = 4.0 mA 0.45 V

VCHO Clock Output High ICHO = –500 µA VCC – 0.5 V

52 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGE (continued)

a Measured with a device running. Not tested and not guaranteed.

b Power supply current for the Am186EMLV and Am188EMLV microcontrollers, which are available in 20 and 25 MHz

operating frequencies only.

c Power is measured while device is operating. Not tested and not guaranteed.

Capacitance

Note:

Capacitance limits are guaranteed by characterization.

Preliminary

Symbol Parameter Description Test Conditions Typical Unit

Nominal

ICC Typical Power Supply Current @ 25°C VCC = 5.5 V (a) 4.5 mA/

MHz

Nominal

ICC Am186EMLV and Am188EMLV Typical Power Supply Current @ 25°C VCC = 3.6 V (a) (b) 3.0 mA/

MHz

Peak ICC Measured Peak ICC VCC = 5.5 V (c ) 5.9 mA/

MHz

Peak ICC Am186EMLV and Am188EMLV Measured Peak ICC VCC = 3.6 V(b) (c) 4.0 mA/

MHz

Preliminary

Symbol Parameter Description Test Conditions Min Max Unit

CIN Input Capacitance @ 1 MHz 10 pF

CIO Output or I/O Capacitance @ 1 MHz 20 pF

Am186/188EM and Am186/188EMLV Microcontrollers 53

PRELIMINARY

Power Supply Current

For the typical system specification shown in Figure 13,

ICC has been measured at 3.0 mA per MHz of system

c loc k. For the typical system specification shown in Fig-

ure 14, ICC has been measured at 4.5 mA per MHz of sys-

tem clock. The typical system is measured while the

system is executing code in a typical application with max-

imum voltage and at room temperature. Actual power sup-

ply current is dependent on system design and may be

greater or less than the typical ICC figure presented here.

Typical current in Figure 13 is given by:

................. ICC=3.0 mA ⋅ freq(MHz).

Typical current in Figure 14 is given by:

................. ICC=4.5 mA ⋅ freq(MHz).

Please note that dynamic ICC measurements are de-

pendent upon chip activity, operating frequency, output

buffer logic, and capacitive/resistive loading of the out-

puts. For these ICC measurements, the devices were

set to the following modes:

nNo DC loads on the output buffers

nOutput capacitive load set to 35 pF

nAD bus set to data only

nPIOs are disabled

nTimer, serial port, refresh, and DMA are enabled

Table 7 shows the variables that are used to calculate

the typical power consumption value for each version

of the Am186EMLV and Am188EMLV microcontrol-

lers.

Table 7. Typical Power Consumption Calculation

for the Am186EMLV and Am188EMLV

Figure 13. Typical ICC Versus Frequency for the

Am186EMLV and Am188EMLV

Figure 14. Typical ICC Versus Frequency for the Am186EM and Am188EM

MHz ⋅ ICC ⋅ Volts / 1 000 = P Typical Power

in Watts

MHz Typical ICC Volts

16 3.0 3.6 0.173

20 3.0 3.6 0.216

25 3.0 3.6 0.270

Clock Frequency (MHz)

ICC (mA) 25 MHz

20 MHz

100

120

140

10 20 30

16 MHz

Clock Frequency (MHz)

ICC (mA)

120

160

200

240

280

10 20 30 40

20 MHz 25 MHz

33 MHz

40 MHz

54 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

THERMAL CHARACTERISTICS

TQFP Package

The Am186EM and Am188EM microcontrollers are

specified for operation with case temperature ranges

from 0°C to +10 0°C for a comm ercial tempera ture d e-

vice. Case temperature is measured at the top center

of the package as shown in Figure 15. The various tem-

peratur es and ther mal resist ances can be determi ned

using the equations in Figure 16 with information given

in Table 8.

θJA is the sum of θJC and θCA. θJC is the in ternal ther-

mal resistance of the assembly. θCA is the ca se to am -

bient thermal resistance.

The variable P is power in watts. Typical power

supply current (ICC) for the Am186EM and Am188EM

microcontrollers is 5.9 mA per MH z of clock frequency.

Figure 15. Thermal Resistance(°C/Watt)

Figure 16. Thermal Characteristics Equations

Table 8. Thermal Chara cteri stics ( °C/Watt)

θJA θCA

θJC

θJA = θJC + θCA

Package/Board

Airflow

(Linear Feet

per Minute) θJC θCA θJA

PQFP/2-Layer

0 fpm 7 38 45

200 fpm 7 32 39

400 fpm 7 28 35

600 fpm 7 26 33

TQFP/2-Layer

0 fpm 10 46 56

200 fpm 10 36 46

400 fpm 10 30 40

600 fpm 10 28 38

PQFP/4-Layer

to 6-Layer

0 fpm 5 18 23

200 fpm 5 16 21

400 fpm 5 14 19

600 fpm 5 12 17

TQFP/4-Layer

to 6-Layer

0 fpm 6 24 30

200 fpm 6 22 28

400 fpm 6 20 26

600 fpm 6 18 24

θJA = θJC + θCA

P=5.9 mA ⋅ freq (MHz) ⋅VCC

TJ=TC+( P ⋅θJC )

TJ=TA+ (P⋅θJA )

TC=TJ–( P⋅θJC )

TC=TA+( P ⋅θCA )

TA=TJ–( P⋅θJA )

TA=TC–( P⋅θCA )

Am186/188EM and Am186/188EMLV Microcontrollers 55
       PRELIMINARY
Typical Ambient Temperatures
The typical ambient temperature specifications are
based on the following assumptions and calculations:
The commercial operating range of the Am186EM and
Am188EM microcontrollers is a case temperature TC of
0 to 100 degrees C entigrade. TC is measured at the top
center of the package. An increase in the ambient tem-
perature causes a proportional increase in TC.
The 40-MHz  micr o con troll er  is s pe cified as 5 .0 V , pl us
or minus 5%. Th erefore,  5.25  V is use d for cal culating
typical power consumption on the 40-MHz microcon-
troller.
Microcontrollers up to 33 MHz are spe cified as 5.0 V,
plus or  m inu s  10%.  Ther ef or e,  5.5  V  is  us ed  for   ca lc u-
lating typical power consumption up to 33 MHz.
Typical power supply current (ICC) in normal usage is es-
timated at 5.9 mA per MHz of microcontroller clock rate.
Typical power consumption (watts) = (5.9 mA/MHz)
times microcontroller clock rate times voltage divided
by 1000.
Table 9 shows the variables that are used to calculate
the typical power consumption value for each version
of the Am186EM and Am188EM microcontrollers.
Table 9. Typical Power Consumption 
Calculation
Thermal resistance is a measure of the ability of a
package to remove heat from a semiconductor device.
A safe operating range for the device can be calculated
using the following formulas from Figure 16 and the
variables in Table 8.
By using the maximum case rating TC, the typical
power consumptio n value from Table 9 , and θJC from
Table 8, the junction temperature TJ can be calculated
by using the following formula from Figure 16.
TJ = TC + (  P  ⋅ θJC )
Table 10 sh ows  T J values for the various versions of the
Am186EM and Am188EM microcontrollers. The column
titled 
Speed/Pkg/Board
 in Table 10 i ndicates the cl ock
speed in MHz, the type of package (P for PQFP and T for
TQFP), and the type of board (2 for 2-layer and 4–6 for 4-
layer to 6 -layer).
Table 10. Junction Temperature Calculation
By using TJ from Table 10, the typical power consumption
value from Table 9, and a θJA value from Table 8, the typ-
ical am bient tempe rature TA c an be c alculated  using th e
following formula from Figure 16.
TA = TJ – (  P ⋅ θJA )
For example, TA for a 4 0-MHz PQFP  design with a  2-
layer board and 0 fpm airflow is calculated as follows:
TA = 108.673 – ( 1.239 ⋅ 45 )
TA = 52.918
In this calculation, TJ comes from Table 10, P comes
from Table 9, and  θJA comes from Table 8. See Table 11.
TA for a 33-MHz TQFP design with a 4-layer to 6-layer
board and 200 fpm airflow is calculated as follows:
TA = 106.4251 – ( 1.07085 ⋅ 28 )
TA = 76.4413
See Table 14 for the result of this calculation.
Table 11  thr oug h  Tabl e 1 4 a nd  Fig ure 1 7 t hroug h Fi g-
ure 20 show TA based on the preceding assumptions and
calculations for a range of θJA val ues with airflow  from 0
linear feet per minute to 600 linear feet per minute.
P = MHz ⋅ ICC ⋅ Volts / 1000 Typical
Power (P) in 
WattsMHz Typical ICC Volts
40 5.9 5.25 1.239
33 5.9 5.5 1.07085
25 5.9 5.5 0.81125
20 5.9 5.5 0.649
Speed/
Pkg/
Board
TJ = TC + ( P ⋅ θJC )
TJ
TCPθJC
40/P2 100 1.239 7 108.7
40/T2 100 1.239 10 112.4
40/P4–6 100 1.239 5 106.2
40/T4–6 100 1.239 6 107.4
33/P2 100 1.07085 7 107.5
33/T2 100 1.07085 10 110.7
33/P4–6 100 1.07085 5 105.3
33/T4–6 100 1.07085 6 106.4
25/P2 100 0.81125 7 105.7
25/T2 100 0.81125 10 108.1
25/P4–6 100 0.81125 5 104.1
25/T4–6 100 0.81125 6 104.9
20/P2 100 0.649 7 104.5
20/T2 100 0.649 10 106.5
20/P4–6 100 0.649 5 103.2
20/T4–6 100 0.649 6 103.9

56 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

Table 11 shows typical maximum ambient temperatures in degrees Ce ntigrade for a PQFP package used with a

2-layer b oard. The typ ical am bient t emp eratures a re ba sed on a 100- degree Centigr ade m aximum c ase tempera-

ture. Figure 17 illustrates the typical temperatures in Table 11.

Table 11. Typical Ambient Temperatures for PQFP with 2-Layer Board

Figure 17. Typical Ambient Temperatures for PQFP with 2-Layer Board

Microcontroll er

Speed Typical Power

(Watts) Linear Feet per Minute Airflow

0 fpm 200 fpm 400 fpm 600 fpm

40 MHz 1.239 52.918 60.352 65.308 67.786

33 MHz 1.07085 59.3077 65.7328 70.0162 72.1579

25 MHz 0.81125 69.1725 74.04 77.285 78.9075

20 MHz 0.649 75.338 79.232 81.828 83.126

Airflow (Linear Feet Per Minute)

0 fpm 200 fpm 400 fpm 600 fpm

Typical Ambient Temperature (Degrees C)

●40 MHz

■20 MHz

◆25 Mhz

✵33 MHz

Legend:

●

●●

✶

✶✶

◆

◆◆

■

■■■

Am186/188EM and Am186/188EMLV Microcontrollers 57

PRELIMINARY

Table 12 shows typical maximum ambient temperatures in degrees Centigrade for a TQFP package used with a

2-layer b oard. The typ ical am bient t emp eratures a re ba sed on a 100- degree Centigr ade m aximum c ase tempera-

ture. Figure 18 illustrates the typical temperatures in Table 12.

Table 12. Typical Ambient Temperatures for TQFP with 2-Layer Board

Figure 18. Typical Ambient Temperatures for TQFP with 2-Layer Board

Microcontroll er

Speed Typical Power

(Watts) Linear Feet per Minute Airflow

0 fpm 200 fpm 400 fpm 600 fpm

40 MHz 1.239 43.006 55.396 62.83 65.308

33 MHz 1.07085 50.7409 61.4494 67.8745 70.0162

25 MHz 0.81125 62.6825 70.795 75.6625 77.285

20 MHz 0.649 70.146 76.636 80.53 81.828

Airflow (Linear Feet Per Minute)

●

✶

✶✶

◆

◆◆

■

■■

0 fpm 200 fpm 400 fpm 600 fpm

●40 MHz

■20 MH z

◆25 Mhz

✵33 MHz

Legend:

Typical Ambient Temperature (Degrees C)

58 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

Table 13 shows typical maximum ambient temperatures in degrees Ce ntigrade for a PQFP package used with a

4-layer to 6-l ayer boa rd. The typic al am bient temp er atur es a re bas ed on a 10 0-degree Ce nti grade ma xi mum c as e

temperature. Figure 19 illustrates the typical temperatures in Table 13.

Table 13. Typical Ambient Temperatures for PQFP with 4-Layer to 6-Layer Board

Figure 19. Typical Ambient Temperatures for PQFP with 4-Layer to 6-Layer Board

Microcontroll er

Speed Typical Power

(Watts) Linear Feet per Minute Airflow

0 fpm 200 fpm 400 fpm 600 fpm

40 MHz 1.239 77.698 80.176 82.654 85.132

33 MHz 1.07085 80.7247 82.8664 85.0081 87.1498

25 MHz 0.81125 85.3975 87.02 88.6425 90.265

20 MHz 0.649 88.318 89.616 90.914 92.212

0 fpm 200 fpm 400 fpm 600 fpm

Typical Ambient Temperat ure ( Degrees C)

●40 MHz

■20 MHz

◆25 Mhz

✵33 MHz

Legend:

Airflow (Linear Feet Per Minute)

●

✶

◆

■■

Am186/188EM and Am186/188EMLV Microcontrollers 59

PRELIMINARY

Table 14 shows typical maximum ambient temperatures in degrees Centigrade for a TQFP package used with a

4-layer to 6-l ayer boa rd. The typic al am bient temp er atur es a re bas ed on a 10 0-degree Ce nti grade ma xi mum c as e

temperature. Figure 20 illustrates the typical temperatures in Table 14.

Table 14. Typical Ambient Temperatures for TQFP with 4-Layer to 6-Layer Board

Figure 20. Typical Ambient Temperatures for TQFP with 4-Layer to 6-Layer Board

Microcontroll er

Speed Typical Power

(Watts) Linear Feet per Minute Airflow

0 fpm 200 fpm 400 fpm 600 fpm

40 MHz 1.239 70.264 72.742 75.22 77.698

33 MHz 1.07085 74.2996 76.4413 78.583 80.7247

25 MHz 0.81125 80.53 82.1525 83.775 85.3975

20 MHz 0.649 84.424 85.722 87.02 88.318

0 fpm 200 fpm 400 fpm 600 fpm

Typical Ambient T emperature ( Degrees C)

●40 MHz

■20 MHz

◆25 Mhz

✵33 MHz

Legend:

Airflow (Linear Feet Per Minute)

●

✶

◆

■■■

■

60 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

COMMERCIAL SWITCHING CHARACTERISTICS AND WAVEFORMS

In the swi tching wa veforms that foll ow, several ab bre-

viations are used to indicate the specific periods of a

bus cycle. These periods are referred to as time states.

A typical bus cycle is composed of four consecutive

time states: t1, t2, t3, and t4. Wait states, which represent

multiple t3 states, are referred to as tw states. When no bus

cycle is pending, an idle (ti) state occurs.

In the switching parameter descriptions, the

multi-

plexed

address is referred to as the AD address bus; the

demultiplexed

address is referred to as the A address

bus.

Key to Switching Waveforms

Must be

Steady

May

Change

from H to L

May

Change

from L to H

Does Not

Apply

Don’t Care,

Any Change

Permitted

Will be

Steady

Will be

Changing

from H to L

Will be

Changing

from L to H

Changing,

State

Unknown

Center

Line is High-

Impedance

Off

State

WAVEFORM INPUT OUTPUT

Invalid Invalid

Am186/188EM and Am186/188EMLV Microcontrollers 61

PRELIMINARY

Alphabetical Key to Switching Parameter Symbols

Note:

The following parameters are not defined or used as this time: 41, 56, 60, 73, 74, 76.

Parameter

Symbol No. Description Parameter

Symbol No. Description

tARYCH 49 ARDY Resolution Transition Setup Time tCLDX 2Data in Hold

tARYCHL 51 ARDY Inactive Holding Time tCLEV 71 CLKOUTA Low to SDEN Valid

tARYLCL 52 ARDY Setup Time tCLHAV 62 HLDA Valid Delay

tAVBL 87 A Address Valid to WHB, WLB Low tCLRF 82 CLKOUTA High to RFSH Invalid

tAVCH 14 AD Address Valid to Clock High tCLRH 27 RD Inactive Delay

tAVLL 12 AD Address Valid to ALE Low tCLRL 25 RD Active Delay

tAVRL 66 A Address Valid to RD Low tCLSH 4Status Inactive Delay

tAVWL 65 A Address Valid to WR Low t CLSL 72 CLKOUTA Low to SCLK Low

tAZRL 24 AD Address Float to RD Active tCLSRY 48 SRDY Transition Hold Time

tCH1CH2 45 CLKOUTA Rise Time tCLTMV 55 Timer Output Delay

tCHAV 68 CLKOUTA High to A Address Valid tCOAOB 83 CLKOUTA to CLKOUTB Skew

tCHCK 38 X1 High Time tCVCTV 20 Co ntro l Active D elay 1

tCHCL 44 CLKOUTA High Time tCVCTX 31 Control In active Delay

tCHCSV 67 CLKOUTA High to LCS/UCS Valid tCVDEX 21 DEN Inactive Delay

tCHCSX 18 MCS/PCS Inactive Delay tCXCSX 17 MCS/PCS Hold from Command Inactive

tCHCTV 22 C ontrol Active Delay 2 tDVCL 1Data in Setup

tCHCV 64 Command Lines Valid Delay (after Float) tDVSH 75 Data Valid to SCLK H igh

tCHCZ 63 Command Lines Float Delay tDXDL 19 DEN Inactive to DT/R Low

tCHDX 8Status Hold Tim e tHVCL 58 HOLD Setup

tCHLH 9ALE Active Delay tINVCH 53 Peripheral Setup Time

tCHLL 11 ALE Inactive Delay tINVCL 54 DRQ Setup Time

tCHRFD 79 CLKOUTA High to RFSH valid tLCRF 86 LCS Inactive to RFSH Active Delay

tCHSV 3Status Active Delay tLHAV 23 ALE High to Address Valid

tCICOA 69 X1 to CLKOUTA Skew tLHLL 10 ALE Width

tCICOB 70 X1 to CLKOUTB Skew tLLAX 13 AD Address Hold from ALE Inactive

tCKHL 39 X1 Fall Time tLOCK 61 M ax im um PLL Loc k Tim e

tCKIN 36 X1 Period tLRLL 84 LCS Precharge Pulse Width

tCKLH 40 X1 Rise Time tRESIN 57 RES Setup Time

tCL2CL1 46 CLKOUTA Fall Time tRFCY 85 RFSH Cycle Time

tCLARX 50 ARDY Active Hold Time tRHAV 29 RD Inactive to AD Address Active

tCLAV 5AD Address Valid Delay tRHDX 59 RD High to Data Hold on AD Bus

tCLAX 6Ad dres s Hold tRHLH 28 RD Inactive to ALE High

tCLAZ 15 AD Address Float Delay tRLRH 26 RD Pulse Width

tCLCH 43 CLKOUTA Low Time tSHDX 77 SCLK High to SPI Data Hold

tCLCK 37 X1 Low Time tSLDV 78 SCLK Low to SPI Data Valid

tCLCL 42 CLKOUTA Period tSRYCL 47 SRDY Transition Setup Time

tCLCLX 80 LCS Inactive Delay tWHDEX 35 WR Inactive to DEN Inactive

tCLCSL 81 LCS Active Delay tWHDX 34 Data Hold after WR

tCLCSV 16 MCS/PCS Active Delay tWHLH 33 WR Inactive to ALE High

tCLDOX 30 Data Hold Time tWLWH 32 WR Pulse Width

tCLDV 7Data Valid Delay

62 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

Numerical Key to Switching Parameter Symbols

Note:

The following parameters are not defined or used at this time: 41, 56, 60, 73, 74, and 76.

Number Parameter

Symbol Description Number Parameter

Symbol Description

1 tDVCL Data in Setup 43 tCLCH CL KOUTA Low Time

2 tCLDX Data in Hold 44 tCHCL CLKOUTA High Time

3 tCHSV Status Active Delay 45 tCH1CH2 CLKOUTA Rise Time

4 tCLSH Status Inactive Delay 46 tCL2CL1 CLKOUTA Fall Time

5 tCLAV AD Address Valid Delay 47 tSRYCL SRDY Transition Setup Time

6 tCLAX Ad dres s H old 48 tCLSRY SRDY Transition Hold Time

7 tCLDV Data Valid Delay 49 tARYCH ARDY Resolution Transition Setup Time

8 tCHDX Status Hold Time 50 tCLARX ARDY Active Hold Time

9 tCHLH ALE Active Delay 51 tARYCHL ARDY Inactive Holding Time

10 tLHLL ALE Width 52 tARYLCL ARDY Setup Time

11 tCHLL ALE Inactive Delay 53 tINVCH Peripheral Setup Time

12 tAVLL AD Address Valid to ALE Low 54 tINVCL DRQ Setup Time

13 tLLAX AD Address Hold from ALE

Inactive 55 tCLTMV Timer Output Delay

14 tAVCH AD Address Valid to Clock High 57 tRESIN RES Setup Time

15 tCLAZ AD Address Float Delay 58 tHVCL HOLD Setup

16 tCLCSV MCS/PCS Active Delay 59 tRHDX RD High to Data Hold on AD Bus

17 tCXCSX MCS/PCS Hold from Command

Inactive 61 tLOCK Maximum P LL Loc k Tim e

18 tCHCSX MCS/PCS Inactive Delay 62 tCLHAV HLDA Valid Delay

19 tDXDL DEN Inactive to DT/R Low 63 tCHCZ Command Lines Float Delay

20 tCVCTV Control Active Delay 1 64 tCHCV Command Lines Valid Delay (after Float)

21 tCVDEX DEN Inactive Delay 65 tAVWL A Address Valid to WR Low

22 tCHCTV Control Active Delay 2 66 tAVRL A Address Valid to RD Low

23 tLHAV ALE High to Address Valid 67 tCHCSV CLKOUTA High to LCS/UCS Valid

24 tAZRL AD Address Float to RD Active 68 tCHAV CLKOUTA High to Address Valid

25 tCLRL RD Active Delay 69 tCICOA X1 to CLKOUTA Skew

26 tRLRH RD Pulse Width 70 tCICOB X1 to CLKOUTB Skew

27 tCLRH RD Inactive Delay 71 tCLEV CLKOUTA Low to SDEN Valid

28 tRHLH RD Inactive to ALE High 72 tCLSL CLKOUTA Low to SCLK Low

29 tRHAV RD Inactive to AD address Active 75 tDVSH Data Valid to SCLK High

30 tCLDOX Data Hold Time 77 tSHDX SCLK High to SPI Data Hold

31 tCVCTX Control Inactive Delay 78 tSLDV SCLK Low to SPI Data Valid

32 tWLWH WR Pulse Width 79 tCHRFD CLKOUTA High to RFSH Vali d

33 tWHLH WR Inactive to ALE High 80 tCLCLX LCS Inactive Delay

34 tWHDX Data Hold after WR 81 tCLCSL LCS Active Delay

35 tWHDEX WR Inactive to DEN Inactive 82 tCLRF CLKOUTA High to RFSH Invalid

36 tCKIN X1 Period 83 tCOAOB CLKOUTA to CLKOUTB Skew

37 tCLCK X1 Low Time 84 tLRLL LCS Precharge Pulse Width

38 tCHCK X1 High Time 85 tRFCY RFSH Cycle Time

39 tCKHL X1 Fall Time 86 tLCRF LCS Inactive to RFSH Active Delay

40 tCKLH X1 Rise Time 87 tAVBL A Address Valid to WHB, WLB Low

42 tCLCL CLKOUTA Period

Am186/188EM and Am186/188EMLV Microcontrollers 63

PRELIMINARY

SWITCHING CHARACTERISTICS o v er C O M MERC I A L o p e r a ti n g r an g e

Read Cycle (20 MHz and 25 MHz)

Note:

All timin g param eters are measu red at 1.5 V w ith 50 pF loadin g on CLKOU TA unle ss othe rwis e noted. All outpu t test co ndition s

are with C

= 50 pF. For switching tests, V

= 0.45 V and V

= 2.4 V, except at X1 where V

= V

– 0. 5 V.

a Equal loading on referenced pins.

b This parameter applies to the

DEN

INTA1–INTA0

WR, WHB,

and

WLB

signals.

c If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.

Preliminary

Parameter 20 MHz 25 MHz

No. Symbol Description Min Max Min Max Unit

General Timing Requirements

1 tDVCL Data in Setup 10 10 ns

2 tCLDX Data in Hold(c) 3 3 ns

General Timing Responses

3 tCHSV Status Active Delay 0 25 0 20 ns

4 tCLSH Statu s Inactive Delay 0 25 0 20 ns

5 tCLAV AD Address Valid Delay and BHE 0 25 0 20 ns

6 tCLAX Address Ho ld 0 25 0 20 ns

8 tCHDX Status Hold Tim e 0 0 ns

9 tCHLH ALE Active Delay 25 20 ns

10 tLHLL ALE Width tCLCL–10=40 tCLCL–10=

30 ns

11 tCHLL ALE Inactive Delay 25 20 ns

12 tAVLL AD Address Valid to ALE Low(a) tCLCH–2 tCLCH–2 ns

13 tLLAX AD Address Hold from ALE

Inactive(a) tCHCL–2 tCHCL –2 ns

14 tAVCH AD Address Valid to Clock High 0 0 ns

15 tCLAZ AD Address Float Delay tCLAX=0 25 tCLAX=0 20 ns

16 tCLCSV MCS/PCS Active Delay 0 25 0 20 ns

17 tCXCSX MCS/PCS Hold from Command

Inactive(a) tCLCH–2 tCLCH–2 ns

18 tCHCSX MCS/PCS Inactive Delay 0 25 0 20 ns

19 tDXDL DEN Inactive to DT/R Low(a) 0 0 ns

20 tCVCTV Contro l Active D elay 1(b) 025 0 20 ns

21 tCVDEX DEN Inactive Delay 0 25 0 20 ns

22 tCHCTV Contro l Active D elay 2(b) 025 0 20 ns

23 tLHAV ALE High to Address Valid 20 15 ns

Read Cycle Timing Responses

24 tAZRL AD Address Float to RD Active 0 0 ns

25 tCLRL RD Active Delay 0 25 0 20 ns

26 tRLRH RD Pulse Width 2tCLCL–15=85 2tCLCL–15=

65 ns

27 tCLRH RD Inactive Delay 0 25 0 20 ns

28 tRHLH RD Inactive to ALE High(a) tCLCH–3 tCLCH–3 ns

29 tRHAV RD Inactive to AD Address

Active(a) tCLCL–10=40 tCLCL–10=

30 ns

59 tRHDX RD High to Data Hold on AD Bus(c) 0 0 ns

66 tAVRL A Address Valid to RD Low(a) 2tCLCL–15=85 2tCLCL–15=

65 ns

67 tCHCSV CLKOUTA High to LCS/UCS Valid 0 25 0 20 ns

68 tCHAV CLKOUTA High to A Addr ess Val id 0 25 0 20 ns

64 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

SWITCHING CHARACTERISTICS o v er C O M MERC I A L o p e r a ti n g r an g e

Read Cycle (33 MHz and 40 MHz)

Notes:

All timin g param eters are measu red at 1.5 V w ith 50 pF loadin g on CLKOU TA unle ss othe rwis e noted. All outpu t test co ndition s

are with C

= 50 pF. For switching tests, V

= 0.45 V and V

= 2.4 V, except at X1 where V

= V

– 0. 5 V.

a Equal loading on referenced pins.

b This parameter applies to the

DEN

INTA1–INTA0

WR, WHB,

and

WLB

signals.

c If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.

Preliminary

Parameter 33 MHz 40 MHz

No. Symbol Description Min Max Min Max Unit

General Timing Requirements

1 tDVCL Data in Setup 8 5 ns

2 tCLDX Data in Hold(c) 3 2 ns

General Timing Responses

3 tCHSV Status Active Delay 0 15 0 12 ns

4 tCLSH Statu s Inactive Delay 0 15 0 12 ns

5 tCLAV AD Address Valid Delay and BHE 0 15 0 12 ns

6 tCLAX Address Ho ld 0 25 0 20 ns

7 tCLDV Data Valid Delay 0 15 0 12 ns

8 tCHDX Status Hold Tim e 0 0 ns

9 tCHLH ALE Active Delay 15 12 ns

10 tLHLL ALE Width tCLCL–10=20 tCLCL–5

=20 ns

11 tCHLL ALE Inactive Delay 15 12 ns

12 tAVLL AD Address Valid to ALE Low(a) tCLCH–2 tCLCH–2 ns

13 tLLAX AD Address Hold from ALE

Inactive(a) tCHCL–2 tCHCL–2 ns

14 tAVCH AD Address Valid to Clock High 0 0 ns

15 tCLAZ AD Address Float Delay tCLAX=0 15 tCLAX=0 12 ns

16 tCLCSV MCS/PCS Active Delay 0 15 0 12 ns

17 tCXCSX MCS/PCS Hold from Command

Inactive(a) tCLCH–2 tCLCH–2 ns

18 tCHCSX MCS/PCS Inactive Delay 0 15 0 12 ns

19 tDXDL DEN Inactive to DT/R Low(a) 0 0 ns

20 tCVCTV Contro l Active D elay 1(b) 015 0 12 ns

21 tCVDEX DEN Inactive Delay 0 15 0 12 ns

22 tCHCTV Contro l Active D elay 2(b) 015 0 12 ns

23 tLHAV ALE High to Address Valid 10 7.5 ns

Read Cycle Timing Responses

24 tAZRL AD Address Float to RD Active 0 0 ns

25 tCLRL RD Active Delay 0 15 0 10 ns

26 tRLRH RD Pulse Width 2tCLCL–15=45 2tCLCL–10=40 ns

27 tCLRH RD Inactive Delay 0 15 0 12 ns

28 tRHLH RD Inactive to ALE High(a) tCLCH–3 tCLCH–2 ns

29 tRHAV RD Inactive to AD Address

Active(a) tCLCL–10=20 tCLCL–5

=20 ns

59 tRHDX RD High to Data Hold on AD Bus(c) 0 0 ns

66 tAVRL A Address Valid to RD Low(a) 2tCLCL–15=45 2tCLCL–10=40 ns

67 tCHCSV CLKOUTA High to LCS/UCS Valid 0 15 0 10 ns

68 tCHAV CLKOUTA High to A Addr ess Val id 0 15 0 10 ns

Am186/188EM and Am186/188EMLV Microcontrollers 65

PRELIMINARY

Read Cycle W av eforms

CLKOUTA

t1t2t3t4

S2–S0

LCS, UCS

AD15–AD0*,

AD7–AD0**

MCS1–MCS0,

PCS6–PCS5,

PCS3–PCS0

AddressA19–A0

DEN

DT/R

BHE*

ALE

16 17

20 21

2222

26 27

UZI

AO15–AO8**

Notes:

Am186EM microcontroller only

Am188EM microcontroller only

*** Changes in t

phase of the clock preceding next bus cycle if followed by read, INTA, or halt

23 11

Data

Status

Address

BHE

******

66 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

SWITCHING CHARACTERISTICS o v er C O M MERC I A L o p e r a ti n g r an g e

Write Cycle (20 MHz and 25 MHz)

Notes:

All timin g param eters are measu red at 1.5 V w ith 50 pF loadin g on CLKOU TA unle ss othe rwis e noted. All outpu t test co ndition s

are with C

= 50 pF. For switching tests, V

= 0.45 V and V

= 2.4 V, except at X1 where V

= V

– 0. 5 V.

a Equal loading on referenced pins.

b This parameter applies to the

DEN

INTA1–INTA0

WR, WHB,

and

WLB

signals.

Preliminary

Parameter 20 MHz 25 MHz

No. Symbol Description Min Max Min Max Unit

General Timing Responses

3 tCHSV Status Active Delay 0 25 0 20 ns

4 tCLSH Statu s Inactive Delay 0 25 0 20 ns

5 tCLAV AD Address Valid Delay and BHE 0 25 0 20 ns

6 tCLAX Address Ho ld 0 25 0 20 ns

7 tCLDV Data Valid Delay 0 25 0 20 ns

8 tCHDX Status Hold Tim e 0 0 ns

9 tCHLH ALE Active Delay 25 20 ns

10 tLHLL ALE Width tCLCL–10=

40 tCLCL–10=

30 ns

11 tCHLL ALE Inactive Delay 25 20 ns

12 tAVLL AD Address Valid to ALE Low(a) tCLCH tCLCH ns

13 tLLAX AD Address Hold from ALE

Inactive(a) tCHCL tCHCL ns

14 tAVCH AD Address Valid to Clock High 0 0 ns

16 tCLCSV MCS/PCS Active Delay 0 25 0 20 ns

17 tCXCSX MCS/PCS Hold from Command

Inactive(a) tCLCH tCLCH ns

18 tCHCSX MCS/PCS Inactive Delay 0 25 0 20 ns

19 tDXDL DEN Inactive to DT/R Low(a) 0 0 ns

20 tCVCTV Contro l Active D elay 1(b) 025 0 20 ns

22 tCHCTV Contro l Active D elay 2 0 25 0 20 ns

23 tLHAV ALE High to Address Valid 20 15 ns

Write Cycle Timing Responses

30 tCLDOX Data Hold Time 0 0 ns

31 tCVCTX Contro l Inactive De lay(b) 025 0 20 ns

32 tWLWH WR Puls e Widt h 2tCLCL–10

=90 2tCLCL–10

=70 ns

33 tWHLH WR Inactive to ALE High(a) tCLCH–2 tCLCH–2 ns

34 tWHDX Data Hold after WR(a) tCLCL–10=

40 tCLCL–10=

30 ns

35 tWHDEX WR Inactive to DEN Inactive(a) tCLCH–3 tCLCH–3 ns

65 tAVWL A Address Valid to WR Low tCLCL+tCHCL

–3 tCLCL+tCHCL

–3 ns

67 tCHCSV CLKOUTA High to LCS/UCS Valid 0 25 0 20 ns

68 tCHAV CLKOUTA High to A Address

Valid 025 0 20 ns

87 tAVBL A Addre ss Valid to WH B, WLB Lo w tCHCL–3 25 tCHCL–3 20 ns

Am186/188EM and Am186/188EMLV Microcontrollers 67

PRELIMINARY

SWITCHING CHARACTERISTICS o v er C O M MERC I A L o p e r a ti n g r an g e

Write Cycle (33 MHz and 40 MHz)

Notes:

All timin g param eters are measu red at 1.5 V w ith 50 pF loadin g on CLKOU TA unle ss othe rwis e noted. All outpu t test co ndition s

are with C

= 50 pF. For switching tests, V

= 0.45 V and V

= 2.4 V, except at X1 where V

= V

– 0. 5 V.

a Equal loading on referenced pins.

b This parameter applies to the

DEN

INTA1–INTA0

WR, WHB,

and

WLB

signals.

Preliminary

Parameter 33 MHz 40 MHz

No. Symbol Description Min Max Min Max Unit

General Timing Responses

3 tCHSV Status Active Delay 0 15 0 12 ns

4 tCLSH Statu s Inactive Delay 0 15 0 12 ns

5 tCLAV AD Address Valid Delay and BHE 0 15 0 12 ns

6 tCLAX Address Ho ld 0 25 0 20 ns

7 tCLDV Data Valid Delay 0 15 0 12 ns

8 tCHDX Status Hold Tim e 0 0 ns

9 tCHLH ALE Active Delay 15 12 ns

10 tLHLL ALE Width tCLCL–10=

20 tCLCL–5

=20 ns

11 tCHLL ALE Inactive Delay 15 12 ns

12 tAVLL AD Address Valid to ALE Low(a) tCLCH tCLCH ns

13 tLLAX AD Address Hold from ALE

Inactive(a) tCHCL tCHCL ns

14 tAVCH AD Address Valid to Clock High 0 0 ns

16 tCLCSV MCS/PCS Active Delay 0 15 0 12 ns

17 tCXCSX MCS/PCS Hold from Command

Inactive(a) tCLCH tCLCH ns

18 tCHCSX MCS/PCS Inactive Delay 0 15 0 12 ns

19 tDXDL DEN Inactive to DT/R Low(a) 0 0 ns

20 tCVCTV Contro l Active D elay 1(b) 015 0 12 ns

22 tCHCTV Contro l Active D elay 2 0 15 0 12 ns

23 tLHAV ALE High to Address Valid 10 7.5 ns

Write Cycle Timing Responses

30 tCLDOX Data Hold Time 0 0 ns

31 tCVCTX Contro l Inactive De lay(b) 015 0 12 ns

32 tWLWH WR Puls e Widt h 2tCLCL–10

=50 2tCLCL–10

=40 ns

33 tWHLH WR Inactive to ALE High(a) tCLCH–2 tCLCH–2 ns

34 tWHDX Data Hold after WR(a) tCLCL–10=

20 tCLCL–10=

15 ns

35 tWHDEX WR Inactive to DEN Inactive(a) tCLCH–5 tCLCH ns

65 tAVWL A Address Valid to WR Low tCLCL+tCHCL

–3 tCLCL+tCHCL

–1.25 ns

67 tCHCSV CLKOUTA High to LCS/UCS Valid 0 15 0 10 ns

68 tCHAV CLKOUTA High to A Address

Valid 015 0 10 ns

87 tAVBL A Addre ss Valid to WH B, WLB Low tCHCL–3 15 tCHCL–1.25 12 ns

68 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

Write Cycle Waveforms

CLKOUTA

t1t2t3t4

S2–S0 Status

LCS, UCS

Address Data

AD15–AD0*,

AD7–AD0**

MCS3–MCS0,

PCS6–PCS5,

PCS3–PCS0

AddressA19–A0

DEN

DT/R

S6 S6

ALE

WHB*, WLB*

WB**

BHE*

UZI

20 31

AO15–AO8**

Note:

Am186EM microcontroller only

Am188EM microcontroller only

*** Changes in t

phase of the clock preceding next bus cycle if followed by read, INTA, or halt.

Address

BHE

22***

***

Am186/188EM and Am186/188EMLV Microcontrollers 69

PRELIMINARY

SWITCHING CHARACTERISTICS o v er C O M MERC I A L o p e r a ti n g r an g e

PSRAM Read Cycl e (20 MHz and 25 MHz)

Notes:

All timin g param eters are measu red at 1.5 V w ith 50 pF loadin g on CLKOU TA unle ss othe rwis e noted. All outpu t test co ndition s

are with C

= 50 pF. For switching tests, V

= 0.45 V and V

= 2.4 V, except at X1 where V

= V

– 0. 5 V.

a Equal loading on referenced pins.

b If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.

Preliminary

Parameter 20 MHz 25 MHz

No. Symbol Description Min Max Min Max Unit

General Timing Requirements

1 tDVCL Data in Setup 10 10 ns

2 tCLDX Data in Hold(b) 3 3 ns

General Timing Responses

5 tCLAV AD Address Valid Delay and BHE 0 25 0 20 ns

7 tCLDV Data Valid Delay 0 25 0 20 ns

8 tCHDX Status Hold Tim e 0 0 ns

9 tCHLH ALE Active Delay 25 20 ns

10 tLHLL ALE Width tCLCL–10=

40 tCLCL–10=

30 ns

11 tCHLL ALE Inactive Delay 25 20 ns

23 tLHAV ALE High to Address Valid 20 15 ns

80 tCLCLX LCS Inactive Delay 0 25 0 20 ns

81 tCLCSL LCS Active Delay 0 25 0 20 ns

84 tLRLL LCS Precharge Pulse Width tCLCL + tCLCH

–3 tCLCL + tCLCH

–3 ns

Read Cycle Timing Responses

24 tAZRL AD Address Float to RD Active 0 0 ns

25 tCLRL RD Active Delay 0 25 0 20 ns

26 tRLRH RD Pulse Width 2tCLCL–15

=85 2tCLCL–15

=65 ns

27 tCLRH RD Inactive Delay 0 25 0 20 ns

28 tRHLH RD Inactive to ALE High(a) tCLCH–3 tCLCH–3 ns

59 tRHDX RD High to Data Hold on AD Bus (b) 0 0 ns

66 tAVRL A Address Valid to RD Low 2tCLCL–15

=85 2tCLCL–15

=65 ns

68 tCHAV CLKOUTA High to A Addr ess Val id 0 25 0 20 ns

70 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

SWITCHING CHARACTERISTICS o v e r C o mm e r c i a l o p e r at i n g r a n g e

PSRAM Read Cycl e (33 MHz and 40 MHz)

Notes:

All timin g param eters are measu red at 1.5 V w ith 50 pF loadin g on CLKOU TA unle ss othe rwis e noted. All outpu t test co ndition s

are with C

= 50 pF. For switching tests, V

= 0.45 V and V

= 2.4 V, except at X1 where V

= V

– 0. 5 V.

a Equal loading on referenced pins.

b If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.

Preliminary

Parameter 33 MHz 40 MHz

No. Symbol Description Min Max Min Max Unit

General Timing Requirements

1 tDVCL Data in Setup 8 5 ns

2 tCLDX Data in Hold(b) 3 2 ns

General Timing Responses

5 tCLAV AD Address Valid Delay and BHE 0 15 0 12 ns

7 tCLDV Data Valid Delay 0 15 0 12 ns

8 tCHDX Status Hold Tim e 0 0 ns

9 tCHLH ALE Active Delay 15 12 ns

10 tLHLL ALE Width tCLCL–10=

20 tCLCL–5=

20 ns

11 tCHLL ALE Inactive Delay 15 12 ns

23 tLHAV ALE High to Address Valid 10 7.5 ns

80 tCLCLX LCS Inactive Delay 0 15 0 12 ns

81 tCLCSL LCS Active Delay 0 15 0 12 ns

84 tLRLL LCS Precharge Pulse Width tCLCL + tCLCH

–3 tCLCL + tCLCH

–1.25 ns

Read Cycle Timing Responses

24 tAZRL AD Address Float to RD Active 0 0 ns

25 tCLRL RD Active Delay 0 15 0 10 ns

26 tRLRH RD Pulse Width 2tCLCL–15

=45 2tCLCL–10

=40 ns

27 tCLRH RD Inactive Delay 0 15 0 12 ns

28 tRHLH RD Inactive to ALE High(a) tCLCH–3 tCLCH–1.25 ns

59 tRHDX RD High to Data Hold on AD Bus (b) 0 0 ns

66 tAVRL A Address Valid to RD Low 2tCLCL–15

=45 2tCLCL–10

=40 ns

68 tCHAV CLKOUTA High to A Addr ess Val id 0 15 0 10 ns

Am186/188EM and Am186/188EMLV Microcontrollers 71

PRELIMINARY

PSRAM Read Cycle Wave forms

Data

CLKOUTA

t1t2t3

LCS

Address

AD15–AD0*,

AD7–AD0**

Address

A19–A0

S6 S6

ALE

911

Address

AO15–AO8** Address

Notes:

Am186EM microcontroller only

Am188EM microcontroller only

72 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

SWITCHING CHARACTERISTICS o v er C O M MERC I A L o p e r a ti n g r an g e

PSRAM Wri te Cycle (20 MHz and 25 MHz)

Notes:

All timin g param eters are measu red at 1.5 V w ith 50 pF loadin g on CLKOU TA unle ss othe rwis e noted. All outpu t test co ndition s

are with C

= 50 pF. For switching tests, V

= 0.45 V and V

= 2.4 V, except at X1 where V

= V

– 0. 5 V.

a Equal loading on referenced pins.

b This parameter applies to the

DEN

WR, WHB,

and

WLB

signals.

Preliminary

Parameter 20 MHz 25 MHz

No. Symbol Description Min Max Min Max Unit

General Timing Responses

5 tCLAV AD Address Valid Delay and

BHE 025 0 20 ns

7 tCLDV Data Valid Delay 0 25 0 20 ns

8 tCHDX Status Hold Tim e 0 0 ns

9 tCHLH ALE Active Delay 25 20 ns

10 tLHLL ALE Width tCLCL–10=40 tCLCL–10=30 ns

11 tCHLL ALE Inactive Delay 25 20 ns

23 tLHAV ALE High to Address Valid 20 15 ns

20 tCVCTV Contro l Active D elay 1(b) 025 0 20 ns

80 tCLCLX LCS Inactive Delay 0 25 0 20 ns

81 tCLCSL LCS Active Delay 0 25 0 20 ns

84 tLRLL LCS Precharge Pulse Width tCLCL + tCLCH

–3 tCLCL + tCLCH –

Write Cycle Timing Responses

30 tCLDOX Data Hold Time 0 0 ns

31 tCVCTX Contro l Inactive De lay(b) 025 0 20 ns

32 tWLWH WR Puls e Widt h 2tCLCL–10

=90 2tCLCL–10

=70 ns

33 tWHLH WR Inactive to ALE High(a) tCLCH–2 tCLCH–2 ns

34 tWHDX Data Hold after WR(a) tCLCL–10=40 tCLCL–10=30 ns

65 tAVWL A Address Valid to WR Low tCLCL+tCHCL

–3 tCLCL+tCHCL

–3 ns

68 tCHAV CLKOUTA High to A

Address Vali d 025 0 20 ns

87 tAVBL A Address Valid to WHB,

WLB Low tCHCL–3 25 tCHCL–3 20 ns

Am186/188EM and Am186/188EMLV Microcontrollers 73

PRELIMINARY

SWITCHING CHARACTERISTICS o v er C O M MERC I A L o p e r a ti n g r an g e

PSRAM Wri te Cycle (33 MHz and 40 MHz)

Notes:

All timin g param eters are measu red at 1.5 V w ith 50 pF loadin g on CLKOU TA unle ss othe rwis e noted. All outpu t test co ndition s

are with C

= 50 pF. For switching tests, V

= 0.45 V and V

= 2.4 V, except at X1 where V

= V

– 0. 5 V.

a Equal loading on referenced pins.

b This parameter applies to the

DEN

WR, WHB,

and

WLB

signals.

Preliminary

Parameter 33 MHz 40 MHz

No. Symbol Description Min Max Min Max Unit

General Timing Responses

5 tCLAV AD Address Valid Delay and

BHE 015 0 12 ns

7 tCLDV Data Valid Delay 0 15 0 12 ns

8 tCHDX Status Hold Tim e 0 0 ns

9 tCHLH ALE Active Delay 15 12 ns

10 tLHLL ALE Width tCLCL–10=20 tCLCL–5=20 ns

11 tCHLL ALE Inactive Delay 15 12 ns

20 tCVCTV Contro l Active D elay 1(b) 015 0 12 ns

23 tLHAV ALE High to Address Valid 10 7.5 ns

80 tCLCLX LCS Inactive Delay 0 15 0 12 ns

81 tCLCSL LCS Active Delay 0 15 0 12 ns

84 tLRLL LCS Precharge Pulse Width tCLCL + tCLCH

–3 tCLCL + tCLCH

–1.25

Write Cycle Timing Responses

30 tCLDOX Data Hold Time 0 0 ns

31 tCVCTX Contro l Inactive De lay(b) 015 0 12 ns

32 tWLWH WR Puls e Widt h 2tCLCL–10

=50 2tCLCL–10

=40 ns

33 tWHLH WR Inactive to ALE High(a) tCLCH–2 tCLCH–2 ns

34 tWHDX Data Hold after WR(a) tCLCL–10=20 tCLCL–10=15 ns

65 tAVWL A Address Valid to WR Low tCLCL+tCHCL

–3 tCLCL+tCHCL

–1.25 ns

68 tCHAV CLKOUTA High to A

Address Vali d 015 0 10 ns

87 tAVBL A Address Valid to WHB,

WLB Low tCHCL–3 15 tCHCL–1.25 12 ns

74 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

PSRAM Write Cycle Waveforms

CLKOUTA

t1t2t3t4

LCS

Address Data

AD15–AD0*,

AD7–AD0**

Address

A19–A0

S6 S6

ALE

WHB*, WLB*

WB**

32 33

84 81

AO15–AO8** Address

Notes:

Am186EM microcontroller only

Am188EM microcontroller only

Am186/188EM and Am186/188EMLV Microcontrollers 75

PRELIMINARY

SWITCHING CHARACTERISTICS o v er C O M MERC I A L o p e r a ti n g r an g e

PSRAM Refresh Cycle (20 MHz and 25 MHz)

Note:

All timin g param eters are measu red at 1.5 V w ith 50 pF loadin g on CLKOU TA unle ss othe rwis e noted. All outpu t test co ndition s

are with C

= 50 pF. For switching tests, V

= 0.45 V and V

= 2.4 V, except at X1 where V

= V

– 0.5 V.

a Equal loading on referenced pins.

Preliminary

Parameter 20 MHz 25 MHz

No. Symbol Description Min Max Min Max Unit

General Timing Responses

9 tCHLH ALE Active Delay 25 20 ns

10 tLHLL ALE Width tCLCL–10=

40 tCLCL–10=

30 ns

11 tCHLL ALE Inactive Delay 25 20 ns

Read/Write Cycle Timing Responses

25 tCLRL RD Active Delay 0 25 0 20 ns

26 tRLRH RD Pulse Width 2tCLCL–15

=85 2tCLCL–15

=65 ns

27 tCLRH RD Inactive Delay 0 25 0 20 ns

28 tRHLH RD Inactive to ALE High(a) tCLCH–3 tCLCH–3 ns

80 tCLCLX LCS Inactive Delay 0 25 0 20 ns

81 tCLCSL LCS Active Delay 0 25 0 20 ns

Refresh Timing Cycle Parameters

79 tCLRFD CLKOUTA Low to RFSH Valid 0 25 0 20 ns

82 tCLRF CLKOUTA High to RFSH Invalid 0 25 0 20 ns

85 tRFCY RFSH Cycle Time 6 • tCLCL 6 • tCLCL ns

86 tLCRF LCS In activ e to RFSH Active Del ay 2tCLCL–3 2tCLCL–3

76 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

SWITCHING CHARACTERISTICS o v er C O M MERC I A L o p e r a ti n g r an g e

PSRAM Refresh Cycle (33 MHz and 40 MHz)

Note:

All timin g param eters are measu red at 1.5 V w ith 50 pF loadin g on CLKOU TA unle ss othe rwis e noted. All outpu t test co ndition s

are with C

= 50 pF. For switching tests, V

= 0.45 V and V

= 2.4 V, except at X1 where V

= V

– 0.5 V.

a Equal loading on referenced pins.

Preliminary

Parameter 33 MHz 40 MHz

No. Symbol Description Min Max Min Max Unit

General Timing Responses

9 tCHLH ALE Active Delay 15 12 ns

10 tLHLL ALE Width tCLCL–10=20 tCLCL–5

=20 ns

11 tCHLL ALE Inactive Delay 15 12 ns

Read/Write Cycle Timing Responses

25 tCLRL RD Active Delay 0 15 0 10 ns

26 tRLRH RD Pulse Width 2tCLCL–15

=45 2tCLCL–10

=40 ns

27 tCLRH RD Inactive Delay 0 15 0 12 ns

28 tRHLH RD Inactive to ALE High(a) tCLCH–3 tCLCH–2 ns

80 tCLCLX LCS Inactive Delay 0 15 0 12 ns

81 tCLCSL LCS Active Delay 0 15 0 12 ns

Refresh Timing Cycle Parameters

79 tCLRFD CLKOUTA Low to RFSH Valid 0 15 0 12 ns

82 tCLRF CLKOUTA High to RFSH Invalid 0 15 0 12 ns

85 tRFCY RFSH Cycle Time 6 • tCLCL 6 • tCLCL ns

86 tLCRF LCS In activ e to RFSH Active Del ay 2tCLC L –3 2tCL C L –1.25

Am186/188EM and Am186/188EMLV Microcontrollers 77

PRELIMINARY

PSRAM Re f res h Cycl e Wav efo rms

CLKOUTA

t1t2t3t4

tW *

LCS

Address

A19–A0

ALE

RFSH

80 81

The period tw is fixed at 3 wait states for PSRAM auto refresh only.

Note:

78 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

SWITCHING CHARACTERISTICS o v er C O M MERC I A L o p e r a ti n g r an g e

Interrupt Acknowledge Cycle (20 MHz and 25 MHz)

Notes:

All timin g param eters are measu red at 1.5 V w ith 50 pF loadin g on CLKOU TA unle ss othe rwis e noted. All outpu t test co ndition s

are with C

= 50 pF. For switching tests, V

= 0.45 V and V

= 2.4 V, except at X1 where V

= V

– 0.5 V.

a Equal loading on referenced pins.

b This parameter applies to the

INTA1–INTA0

signals.

c This parameter applies to the

DEN and DT/R

signals.

Preliminary

Parameter 20 MHz 25 MHz

No. Symbol Description Min Max Min Max Unit

General Timing Requirements

1 tDVCL Data in Setup 10 10 ns

2 tCLDX Data in Hold 3 3 ns

General Timing Responses

3 tCHSV Status Active Delay 0 25 0 20 ns

4 tCLSH Statu s Inactive Delay 0 25 0 20 ns

7 tCLDV Data Valid Delay 0 25 0 20 ns

8 tCHDX Status Hold Tim e 0 0 ns

9 tCHLH ALE Active Delay 25 20 ns

10 tLHLL ALE Width tCLCL–10=40 tCLCL–10=30 ns

11 tCHLL ALE Inactive Delay 25 20 ns

12 tAVLL AD Address Invalid to ALE

Low(a) tCLCH tCLCH ns

15 tCLAZ AD Address Float Delay tCLAX=0 25 tCLAX=0 20 ns

19 tDXDL DEN Inactive to DT/R Low(a) 0 0 ns

20 tCVCTV Contro l Active D elay 1(b) 025 0 20 ns

21 tCVDEX DEN Inactive Delay 0 25 0 20 ns

22 tCHCTV Contro l Active D elay 2(c) 025 0 20 ns

23 tLHAV ALE High to Address Valid 20 15 ns

31 tCVCTX Contro l Inactive De lay(b) 025 0 20 ns

68 tCHAV CLKOUTA High to A Address

Valid 025 0 20 ns

Am186/188EM and Am186/188EMLV Microcontrollers 79

PRELIMINARY

SWITCHING CHARACTERISTICS o v er C O M MERC I A L o p e r a ti n g r an g e

Interrupt Acknowledge Cycle (33 MHz and 40 MHz)

Notes:

All timin g param eters are measu red at 1.5 V w ith 50 pF loadin g on CLKOU TA unle ss othe rwis e noted. All outpu t test co ndition s

are with C

= 50 pF. For switching tests, V

= 0.45 V and V

= 2.4 V, except at X1 where V

= V

– 0.5 V.

a Equal loading on referenced pins.

b This parameter applies to the

INTA1–INTA0

signals.

c This parameter applies to the

DEN and DT/R

signals.

Preliminary

Parameter 33 MHz 40 MHz

No. Symbol Description Min Max Min Max Unit

General Timing Requirements

1 tDVCL Data in Setup 8 5 ns

2 tCLDX Data in Hold 3 2 ns

General Timing Responses

3 tCHSV Status Active Delay 0 15 0 12 ns

4 tCLSH Statu s Inactive Delay 0 15 0 12 ns

7 tCLDV Data Valid Delay 0 15 0 12 ns

8 tCHDX Status Hold Tim e 0 0 ns

9 tCHLH ALE Active Delay 15 12 ns

10 tLHLL ALE Width tCLCL–10=20 tCLCL–5=20 ns

11 tCHLL ALE Inactive Delay 15 12 ns

12 tAVLL AD Address Invalid to ALE

Low(a) tCLCH tCLCH ns

15 tCLAZ AD Address Float Delay tCLAX=0 15 tCLAX=0 12 ns

19 tDXDL DEN Inactive to DT/R Low(a) 0 0 ns

20 tCVCTV Contro l Active D elay 1(b) 015 0 12 ns

21 tCVDEX DEN Inactive Delay 0 15 0 12 ns

22 tCHCTV Contro l Active D elay 2(c) 015 0 12 ns

23 tLHAV ALE High to Address Valid 10 7.5 ns

31 tCVCTX Contro l Inactive De lay(b) 015 0 12 ns

68 tCHAV CLKOUTA High to A Address

Valid 015 0 10 ns

80 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

Interrupt Acknowledge Cycle Waveforms

CLKOUTA

t1t2t3t4

S2–S0 Status

ALE

AD15–AD0*,

AD7–AD0**

INTA1–INTA0

DEN

DT/R

Ptr

AddressA19–A0

S6 S6

BHE*

3 4

10 11

(a)

(b)

(c)

(d)

Notes:

Am186EM microcontroller only

Am188EM microcontroller only

a The status bits become inactive in the state preceding t

b The data hol d time lasts o nly unti l the in terrupt ac knowledge signal deasse rts, even if the interrup t ackno wledge

transition occurs prior to t

CLDX

(min).

c This parameter applies for an interrupt acknowledge cycle that follows a write cycle.

d If followed by a write cycle, this change occurs in the state preceding that write cycle.

AO15–AO8** Address

BHE

Am186/188EM and Am186/188EMLV Microcontrollers 81

PRELIMINARY

SWITCHING CHARACTERISTICS o v er C O M MERC I A L o p e r a ti n g r an g e

Software Halt Cycle (20 MHz and 25 MHz)

Notes:

All timin g param eters are measu red at 1.5 V w ith 50 pF loadin g on CLKOU TA unle ss othe rwis e noted. All outpu t test co ndition s

are with C

= 50 pF. For switching tests, V

= 0.45 V and V

= 2.4 V, except at X1 where V

= V

– 0.5 V.

a Equal loading on referenced pins.

b This parameter applies to the

DEN

signal.

Preliminary

Parameter 20 MHz 25 MHz

No. Symbol Description Min Max Min Max Unit

General Timing Responses

3 tCHSV Status Active Delay 0 25 0 20 ns

4 tCLSH Statu s Inactive Delay 0 25 0 20 ns

5 tCLAV AD Address Invalid Delay and

BHE 025 0 20 ns

9 tCHLH ALE Active Delay 25 20 ns

10 tLHLL ALE Width tCLCL–10=40 tCLCL–10=30 ns

11 tCHLL ALE Inactive Delay 25 20 ns

19 tDXDL DEN Inactive to DT/R Low(a) 0 0 ns

22 tCHCTV Contro l Active D elay 2(b) 025 0 20 ns

68 tCHAV CLKOUTA High to A Address

Invalid 025 0 20 ns

82 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

SWITCHING CHARACTERISTICS o v er C O M MERC I A L o p e r a ti n g r an g e

Software Halt Cycle (33 MHz and 40 MHz)

Notes:

All timin g param eters are measu red at 1.5 V w ith 50 pF loadin g on CLKOU TA unle ss othe rwis e noted. All outpu t test co ndition s

are with C

= 50 pF. For switching tests, V

= 0.45 V and V

= 2.4 V, except at X1 where V

= V

– 0.5 V.

a Equal loading on referenced pins.

b This parameter applies to the

DEN

signal.

Preliminary

Parameter 33 MHz 40 MHz

No. Symbol Description Min Max Min Max Unit

General Timing Responses

3 tCHSV Status Active Delay 0 15 0 12 ns

4 tCLSH Statu s Inactive Delay 0 15 0 12 ns

5 tCLAV AD Address Invalid Delay and

BHE 015 0 12 ns

9 tCHLH ALE Active Delay 15 12 ns

10 tLHLL ALE Width tCLCL–10=20 tCLCL–5=20 ns

11 tCHLL ALE Inactive Delay 15 12 ns

19 tDXDL DEN Inactive to DT/R Low(a) 0 0 ns

22 tCHCTV Contro l Active D elay 2(b) 015 0 12 ns

68 tCHAV CLKOUTA High to A Address

Invalid 015 0 10 ns

Am186/188EM and Am186/188EMLV Microcontrollers 83

PRELIMINARY

Software Halt Cycle Waveforms

CLKOUTA

t1t2titi

S2–S0 Status

ALE

Invalid Addre ss

S6, AD15–AD0*,

AD7–AD0**,

AO15-AO8**

DEN

DT/R

Invalid Address

A19–A0

Notes:

Am186EM microcontroller only

Am188EM microcontroller only

84 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

SWITCHING CHARACTERISTICS o v er C O M MERC I A L o p e r a ti n g r an g e

Clock (20 MHZ and 25 MHz)

Notes:

All timin g param eters are measu red at 1.5 V w ith 50 pF loadin g on CLKOU TA unle ss othe rwis e noted. All outpu t test co ndition s

are with C

= 50 pF. For switching tests, V

= 0.45 V and V

= 2.4 V, except at X1 where V

= V

– 0.5 V.

a The specifications for CLKIN are applicable to the normal PLL and CLKDIV2 modes.

The PLL s hould be us ed for op eratio ns from 16 .667 M Hz to 40 MHz . For op eration s below 16.667 M Hz, t he CLKDIV2 m ode

should be used.

Because the CLKDIV2 input frequency is two times the system frequency, the specifications for twice the frequency should

be used for CLKDIV2 mode. For example, use the 20 MHz CLKIN specifications for 10 MHz operation.

Preliminary

Parameter 20 MHz 25 MHz

No. Symbol Description Min Max Min Max Unit

CLKIN Requirements

36 tCKIN X1 Period(a) 50 60 40 60 ns

37 tCLCK X1 Low Time (1.5 V)(a) 15 15 ns

38 tCHCK X1 High Time (1.5 V)(a) 15 15 ns

39 tCKHL X1 Fall Time (3.5 to 1.0 V)(a) 5 5 ns

40 tCKLH X1 Rise Time (1.0 to 3.5 V)(a) 5 5 ns

CLKOUT Timing

42 tCLCL CLKOUTA Period 50 40 ns

43 tCLCH CLKOUTA Low Time

(CL=50 pF) 0.5tCLCL–2

=23 0.5tCLCL–2

=18 ns

44 tCHCL CLKOUTA High Time

(CL=50 pF) 0.5tCLCL–2

=23 0.5tCLCL–2

=18 ns

45 tCH1CH2 CLKOUTA Rise Time

(1.0 to 3.5 V) 3 3 ns

46 tCL2CL1 CLKOUTA Fall Time

(3.5 to 1.0 V) 3 3 ns

61 tLOCK Maximum PLL Lo ck Time 1 1 ms

69 tCICOA X1 to CLKOUTA Skew 15 15 ns

70 tCICOB X1 to CLKOUTB Skew 21 21 ns

Am186/188EM and Am186/188EMLV Microcontrollers 85

PRELIMINARY

SWITCHING CHARACTERISTICS o v er C O M MERC I A L o p e r a ti n g r an g e

Clock (33 MHZ and 40 MHz)

Notes:

All timin g param eters are measu red at 1.5 V w ith 50 pF loadin g on CLKOU TA unle ss othe rwis e noted. All outpu t test co ndition s

are with C

= 50 pF. For switching tests, V

= 0.45 V and V

= 2.4 V, except at X1 where V

= V

– 0.5 V.

a The specifications for CLKIN are applicable to the normal PLL and CLKDIV2 modes.

The PLL should be used for operations from 16.667 MHz to 40 MHz. For operations below 16.667 MHz, the CLKDIV2

mode should be used.

Because the CLKDIV2 input frequency is two times the system frequency, the specifications for twice the frequency should

be used for CLKDIV2 mode. For example, use the 20 MHz CLKIN specifications for 10 MHz operation.

Preliminary

Parameter 33 MHz 40 MHz

No. Symbol Description Min Max Min Max Unit

CLKIN Requirements

36 tCKIN X1 Period(a) 30 60 25 60 ns

37 tCLCK X1 Low Time (1.5 V)(a) 10 7.5 ns

38 tCHCK X1 High Time (1.5 V)(a) 10 7.5 ns

39 tCKHL X1 Fall Time (3.5 to 1.0 V)(a) 5 5 ns

40 tCKLH X1 Rise Time (1.0 to 3.5 V)(a) 5 5 ns

CLKOUT Timing

42 tCLCL CLKOUTA Period 30 25 ns

43 tCLCH CLKOUTA Low Time

(CL=50 pF) 0.5tCLCL–1.5

=13.5 0.5tCLCL–1.25

=11.25 ns

44 tCHCL CLKOUTA High Time

(CL=50 pF) 0.5tCLCL–1.5

=13.5 0.5tCLCL–1.25

=11.25 ns

45 tCH1CH2 CLKOUTA Rise Time

(1.0 to 3.5 V) 3 3 ns

46 tCL2CL1 CLKOUTA Fall Time

(3.5 to 1.0 V) 3 3 ns

61 tLOCK Maximum PLL Lo ck Time 1 1 ms

69 tCICOA X1 to CLKOUTA Skew 15 15 ns

70 tCICOB X1 to CLKOUTB Skew 21 21 ns

86 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

Clock Waveforms—Active Mode

Clock Waveforms—Power-Save Mode

CLKOUTB

CLKOUTA

(Active, F=000)

36 37

39 40

42 43

CLKOUTA(a)

CLKOUTB(c)

CLKOUTB(b)

Notes:

aThe Clock Divisor Select (F2–F0) bits in the Power Save Control Register (PDCON) are set to 010 (divide by 4).

b The CLKOUTB Output Frequency (CBF) bit in the Power Save Control Register (PDCON) is set to 1.

c The CLKOUTB Output Frequency (CBF) bit in the Power Save Control Register (PDCON) is set to 0.

Am186/188EM and Am186/188EMLV Microcontrollers 87

PRELIMINARY

SWITCHING CHARACTERISTICS o v er C O M MERC I A L o p e r a ti n g r an g e

Ready and Peripheral Timing (20 MHz and 25 MHz)

Notes:

All timin g param eters are measu red at 1.5 V w ith 50 pF loadin g on CLKOU TA unle ss othe rwis e noted. All outpu t test co ndition s

are with C

= 50 pF. For switching tests, V

= 0.45 V and V

= 2.4 V, except at X1 where V

= V

– 0.5 V.

a This timing must be met to guarantee proper operation.

b This timing must be met to guarantee recognition at the clock edge.

Preliminary Preliminary

Parameter 20 MHz 25 MHz

No. Symbol Description Min Max Min Max Unit

Ready and Peripheral Timin g Requirem ents

47 tSRYCL SRDY Transition Setup Time(a) 10 10 ns

48 tCLSRY SRDY Transition Hold Time(a) 3 3 ns

49 tARYCH ARDY Resolution Transition

Setup Time(b) 10 10 ns

50 tCLARX ARDY Active Hold Time(a) 4 4 ns

51 tARYCHL ARDY Inactive Holding Time 6 6 ns

52 tARYLCL ARDY Setup Time(a) 15 15 ns

53 tINVCH Peripheral Setup Time(b) 10 10 ns

54 tINVCL DRQ Setup Time(b) 10 10 ns

Peripheral Timing Responses

55 tCLTMV Timer Output Delay 25 20 ns

88 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

SWITCHING CHARACTERISTICS o v er C O M MERC I A L o p e r a ti n g r an g e

Ready and Peripheral Timing (33 MHz and 40 MHz)

Notes:

All timin g param eters are measu red at 1.5 V w ith 50 pF loadin g on CLKOU TA unle ss othe rwis e noted. All outpu t test co ndition s

are with C

= 50 pF. For switching tests, V

= 0.45 V and V

= 2.4 V, except at X1 where V

= V

– 0.5 V.

a This timing must be met to guarantee proper operation.

b This timing must be met to guarantee recognition at the clock edge.

Synchronous Ready Waveforms

Preliminary

Parameter 33 MHz 40 MHz

No. Symbol Description Min Max Min Max Unit

Ready and Peripheral Timin g Requirem ents

47 tSRYCL SRDY Transition Setup Time(a) 8 5 ns

48 tCLSRY SRDY Transition Hold Time(a) 3 2 ns

49 tARYCH ARDY Resolution Transition

Setup Time(b) 8 5 ns

50 tCLARX ARDY Active Hold Time(a) 4 3 ns

51 tARYCHL ARDY Inactive Holding Time 6 5 ns

52 tARYLCL ARDY Setup Time(a) 10 5 ns

53 tINVCH Peripheral Setup Time(b) 8 5 ns

54 tINVCL DRQ Setup Time(b) 8 5 ns

Peripheral Timing Responses

55 tCLTMV Timer Output Delay 15 12 ns

CLKOUTA

tWtWtWt4

SRDY

t3tWtWt4

t2t3tWt4

t1t2t3t4

Case 2

Case 3

Case 4

Case 1

Am186/188EM and Am186/188EMLV Microcontrollers 89

PRELIMINARY

Asynchronous Ready Waveforms

Peripheral Wa ve form s

CLKOUTA

tWtWtWt4

ARDY (Normally Not-

Ready System)

t3tWtWt4

t2t3tWt4

t1t2t3t4

Case 2

Case 3

Case 4

ARDY (Normally

Ready System)

49 50

51 50

Case 1

CLKOUTA

TMROUT1–

TMROUT0

DRQ1–DRQ0

INT4–INT0, NMI,

TMRIN1–TMRIN0

90 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

SWITCHING CHARACTERISTICS o v er C O M MERC I A L o p e r a ti n g r an g e

Reset and Bus Hold (20 MHz and 25 MHz)

Note:

All timin g param eters are measu red at 1.5 V w ith 50 pF loadin g on CLKOU TA unle ss othe rwis e noted. All outpu t test co ndition s

are with C

= 50 pF. For switching tests, V

= 0.45 V and V

= 2.4 V, except at X1 where V

= V

– 0.5 V.

a This timing must be met to guarantee recognition at the next clock.

Reset and Bus Hold (33 MHz and 40 MHz)

Note:

All timin g param eters are measu red at 1.5 V w ith 50 pF loadin g on CLKOU TA unle ss othe rwis e noted. All outpu t test co ndition s

are with C

= 50 pF. For switching tests, V

= 0.45 V and V

= 2.4 V, except at X1 where V

= V

– 0.5 V.

a This timing must be met to guarantee recognition at the next clock.

Preliminary

Parameter 20 MHz 25 MHz

No. Symbol Description Min Max Min Max Unit

Reset and Bus Hold Timing Requirements

5 tCLAV AD Address Valid Delay and BHE 0 25 0 20 ns

15 tCLAZ AD Address Float Delay 0 25 0 20 ns

57 tRESIN RES Setup Time 10 10 ns

58 tHVCL HOLD Setup(a) 10 10 ns

Reset and Bus Hold Timing Responses

62 tCLHAV HLDA Valid Delay 0 25 0 20 ns

63 tCHCZ Command Lines Float Delay 25 20 ns

64 tCHCV Command Lines Valid Delay

(after Float) 25 20 ns

Preliminary

Parameter 33 MHz 40 MHz

No. Symbol Description Min Max Min Max Unit

Reset and Bus Hold Timing Requirements

5 tCLAV AD Address Valid Delay and BHE 0 15 0 12 ns

15 tCLAZ AD Address Float Delay 0 15 0 12 ns

57 tRESIN RES Setup Time 8 5 ns

58 tHVCL HOLD Setup(a) 8 5 ns

Reset and Bus Hold Timing Responses

62 tCLHAV HLDA Valid Delay 0 15 0 12 ns

63 tCHCZ Command Lines Float Delay 15 12 ns

64 tCHCV Command Lines Valid Delay

(after Float) 15 12 ns

Am186/188EM and Am186/188EMLV Microcontrollers 91

PRELIMINARY

Reset Waveforms

Signals Related to Reset Waveforms

RES

CLKOUTA

57 57

RES

CLKOUTA

BHE/ADEN,

RFSH2/ADEN,

S6/CLKDIV2, and

UZI

AD15–AD0 (186)

AO15–AO8,

AD7–AD0 (188)

three-state

92 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

Bus Hold Waveforms—Entering

Bus Hold Waveforms—Leaving

CLKOUTA

tititi

AD15–AD0, DEN

HLDA

A19–A0, S6, RD,

WR, BHE,

DT/R, S2–S0

WHB, WLB

HOLD

t4titi

Case 2

Case 1

CLKOUTA

titit1

AD15–AD0, DEN

HLDA

A19–A0, S6, RD,

WR, BHE,

DT/R, S2–S0

WHB, WLB

HOLD

tit4t1

Case 2

Case 1

Am186/188EM and Am186/188EMLV Microcontrollers 93

PRELIMINARY

SWITCHING CHARACTERISTICS o v er C O M MERC I A L o p e r a ti n g r an g e

Synchronous Serial Interface (SSI) (20 MHz and 25 MHz)

Note:

All timin g param eters are measu red at 1.5 V w ith 50 pF loadin g on CLKOU TA unle ss othe rwis e noted. All outpu t test co ndition s

are with C

= 50 pF. For switching tests, V

= 0.45 V and V

= 2.4 V, except at X1 where V

= V

– 0. 5 V.

Synchronous Serial Interface (SSI) (33 MHz and 40 MHz)

Note:

All timin g param eters are measu red at 1.5 V w ith 50 pF loadin g on CLKOU TA unle ss othe rwis e noted. All outpu t test co ndition s

are with C

= 50 pF. For switching tests, V

= 0.45 V and V

= 2.4 V, except at X1 where V

= V

– 0. 5 V.

Preliminary

Parameter 20 MHz 25 MHz

No. Symbol Description Min Max Min Max Unit

Synchronous Serial Port Timing Requirements

75 tDVSH Data Valid to SCLK High 10 10 ns

77 tSHDX SCLK High to SPI Data Hold 3 3 ns

Synchronous Serial Port Timing Responses

71 tCLEV CLKOUTA Low to SDEN Valid 25 20 ns

72 tCLSL CLKOUTA Low to SCLK Low 25 20 ns

78 tSLDV SCLK Low to Data Valid 25 20 ns

Preliminary

Parameter 33 MHz 40 MHz

No. Symbol Description Min Max Min Max Unit

Synchronous Serial Port Timing Requirements

75 tDVSH Data Valid to SCLK High 8 5 ns

77 tSHDX SCLK High to SPI Data Hold 2 2 ns

Synchronous Serial Port Timing Responses

71 tCLEV CLKOUTA Low to SDEN Valid 0 15 0 12 ns

72 tCLSL CLKOUTA Low to SCLK Low 0 15 0 12 ns

78 tSLDV SCLK Low to Data Valid 0 15 0 12 ns

94 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

Synchronous Serial Interface (SSI) Waveforms

Note:

SDATA is bidirectional and used for either transmit (TX) or receive (RX). Timing is shown separately for each case.

CLKOUTA

SDATA (RX)

SCLK

SDEN

DATA

75 77

SDATA (TX) DATA

Am186/188EM and Am186/188EMLV Microcontrollers 95

PRELIMINARY

TQFP PHYSICAL DIMENSIONS

PQL 100, Trimmed and Formed

Thin Quad Flat Pack

Pin 100

Pin 25

Pin 1 ID

12.00

Ref

Notes:

1. All measurements are in millimeters unless otherwise noted.

2. Not to scale; for reference only.

pql100

4-15-94

–B–

–A–

–D–

Pin 75

12.00

Ref

13.80

14.20

15.80

16.20

Pin 50

13.80

14.20 15.80

16.20

–A–

–C–

S1.60

Max

0.50 Basic

1.00 Ref

1.35

1.45

See Detail X

Seating Plan e

Top View

Side View

96 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

PQL 100 (continued)

0.17

0.27

0.05

0.15

Seating Plane

Detail X

0.17

0.27

0°–7°

Gage

Plane

0.20

0.45

0.75

0.13

0.20

0° Min

0.25

0.14

0.18

Section S-S

1.60

Max

Notes:

1. All measurements are in millimeters unless otherwise noted.

2. Not to scale; for reference only.

Max 0.08 Lead Coplanarity

pql100

4-15-94

Am186/188EM and Am186/188EMLV Microcontrollers 97

PRELIMINARY

PQFP PHYSICAL DIMENSIONS

PQR 100, Trimmed and Formed

Plastic Quad Flat Pack

Notes:

1. All measurements are in millimeters unless otherwise noted.

2. Not to scale; for reference only.

17.00

17.40

13.90

14.10

12.35

REF Pin 80

Pin 100

Pin 30

Pin 50

Pin 1 I.D.

19.90

20.10

See Detail X

Seating

0.65

BASIC

0.25

Min

2.70

2.90 3.35

Max

-–A–

- –D–

–B–

–A–

–C–

Top View

Side View

18.85

REF

23.00

23.40

pqr100

4-15-94

98 Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINARY

PQFP PQR 100 (continued)

0.20 Min. Flat Shoulder

7° Typ.

0° Min.

0.30±0.05 R

Gage

Plane 0.25

0.73

1.03

0°–7°

7° Typ.

Detail X 0.22

0.38

0.15

0.23

3.35

Max

Secti on S- S

0.15

0.23

0.22

0.38

Note:

Not to scale; for reference only.

pqr100

4-15-94

Trademarks

AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.

Am386 and Am486 are registered trademarks of Advanced Micro Devices, Inc.

Am186, Am188, E86, K86, Élan, and AMD Facts-On-Demand are trademarks of Advanced Micro Devices, Inc.

FusionE86 is a service mark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.