NCP1361BABAYSNT1G - APTINA IMAGING

February, 2018 − Rev. 3

1Publication Order Number:

NCP1361/D

NCP1361, NCP1366

Low Power Offline Constant

Current PWM Current-Mode

Controller with/without

High Voltage Startup

Current Source

The NCP1361/66 offers a new solution targeting output power

levels from a few watts up to 20 W in a universal−mains flyback

application. Due to a novel method this new controller offers a

primary−side constant current control, saving secondary−side

components to perform current regulation.

The NCP1361/66 operates in valley−lockout quasi−resonant peak

current mode control mode at nominal load to provide high efficiency.

When the secondary−side power starts diminishing, the switching

frequency naturally increases until a voltage−controlled oscillator

(VCO) takes the lead, synchronizing the MOSFET turn−on in a

drain−source voltage valley. The frequency is thus reduced by

stepping into successive valleys until the number 4 is reached. Beyond

this point, the frequency is linearly decreased in valley−switching

mode until a minimum is hit. Valley lockout during the first four

drain−source valleys prevents erratic discrete jumps and provides

good efficiency in lighter load situations.

Features

•±10% Current Regulation

•560 V Startup Current Source

•No Frequency Clamp, 80 or 110 kHz Maximum Switching

Frequency Options

•Quasi−Resonant Operation with Valley Switching

Operation

•Fixed Peak Current & Deep Frequency Foldback @

Light Load Operation.

•External Constant Voltage Feedback Adjustment

•Cycle by Cycle Peak Current Limit

•Built−In Soft−Start

•Over & Under Output Voltage Protection

•Wide Operation VCC Range (up to 28 V)

•Low Start−up Current (2.5 mA typ.) with NCP1361

•Clamped Gate−drive Output for MOSFET

•CS & Vs/ZCD pin Short and Open Protection

•Internal Temperature Shutdown

•Less than 30 mW No−Load Performance at High Line

with NCP1366 Version

•These are Pb−Free Devices

Typical Applications

•Low power ac−dc Adapters for Chargers

•Ac−dc USB chargers for Cell Phones, Tablets and

Cameras

TSOP−6

CASE 318G

MARKING

DIAGRAMS

www.onsemi.com

(Note: Microdot may be in either location)

xxxAYWG

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb−Free Package

See detailed ordering and shipping information on page 25 of

this data sheet.

ORDERING INFORMATION

SOIC−7

CASE 751U

XXXXX

ALYWX

NCP1361, NCP1366

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3CS

VCC

DRV 4

VS/ZCD

5FB

GND

Figure 1. Pin Connections

(Top View)

GND

VCC

VS/ZCD

DRV

(Top View)

NCP1361 NCP1366

Figure 2. NCP1366 Typical Application Circuit

Figure 3. NCP1361 Typical Application Circuit

NCP1366

Vs/ZCD 1

DRV 4

FB 2

CS 3

GND

VCC

Ac Vout

Sec

Prim

Aux

Ac Vout

Sec

Prim

Aux

NCP1361

Vs/ZCD

DRV 3

GND 2

VCC 1

NCP1361, NCP1366

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Figure 4. Functional Block Diagram: A Version

VCC and Logic

Management of

double hiccup

UVLO

GND

DRV

UVLO

POReset

Vdd

VCC(OVP)

FB Reset

Max_Ipk reset

Soft Start

POReset

Vs /

ZCD

OCP

Timer

Count

Reset Timer

VCC(Reset)

Reset

Double_Hiccup_ends

Vcc

Clamp

LEB1

Blanking

VILIM

QR multi−mode

Valley lockout &

Valley Switching &

VCO management

POReset

126% Vref_CV2

Latch

ICS

VDD

POReset

DbleHiccup

VUVP

OVP_Cmp

UVP_Cmp

LEB2

VCS(Stop)

4 clk

Counter

Reset

Counter

Note:

OVP: Over Voltage Protection

UVP: Under Voltage Protection

OCP: Over Current Protection

SCP: Short Circuit Protection

CBC: CaBle Compensation

tLEB1 > tLEB2

OCP

Peak current

Freeze

1/Kcomp

DbleHiccup

VCC(OVP)

CS pin Open (VCS > 2 V)

& Short (VCS < 50 mV)

detection is activated at

each startup

ICS_EN

SCP

CS pin Fault

IHV

QUVP

DbleHiccup

Vcc

Vcc(clamp)

Rlim

Latch

EN_UVP

SCP

Zero Crossing &

Signal Sampling

Control

Sampled Vout

FBint

FB_CC

FB_CV

NCP1366 Only

4 clk

Counter

VCC(Reset)

Vref_CC

Control Law

Primary Peak

Current Control

OVP

RFB

VDD

NCP1361, NCP1366

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PIN FUNCTION DESCRIPTION

Pin out

NCP1366

Pin out

NCP1361 Name Function

1 6 Vs/ZCD Connected to the auxiliary winding; this pin senses the voltage output for the primary

regulation and detects the core reset event for the Quasi−Resonant mode of operation.

2 5 FB This pin connects to an optocoupler collector and adjusts the peak current setpoint.

3 4 CS This pin monitors the primary peak current.

4 3 DRV Controller switch driver.

5 2 GND Ground reference.

6 1 VCC This pin is connected to an external auxiliary voltage and supplies the controller.

7−NC Not Connected for creepage distance between high and low Voltage pins

8−HV Connected the high−voltage rail, this pin injects a constant current into the VCC capaci-

tor for starting−up the power supply.

MAXIMUM RATINGS

Symbol Rating Value Unit

VCC(MAX) Maximum Power Supply voltage, VCC pin, continuous voltage −0.3 to 28 V

ΔVCC/ΔtMaximum slew rate on VCC pin during startup phase +0.4 V/ms

VDRV(MAX)

IDRV(MAX)

Maximum driver pin voltage, DRV pin, continuous voltage

Maximum current for DRV pin

−0.3, VDRV (Note 1)

−300, +500

VMAX

IMAX

Maximum voltage on low power pins (except pins DRV and VCC)

Current range for low power pins (except pins DRV and VCC)

−0.3, 5.5

−2, +5

VHV High Voltage pin voltage −0.3 to 560 V

RθJ−AThermal Resistance Junction−to−Air 200 °C/W

TJ(MAX) Maximum Junction Temperature 150 °C

Operating Temperature Range −40 to +125 °C

Storage Temperature Range −60 to +150 °C

Human Body Model ESD Capability per JEDEC JESD22−A114F 2 kV

Machine Model ESD Capability (All pins except DRV) per JEDEC JESD22−A115C 200 V

Charged−Device Model ESD Capability per JEDEC JESD22−C101E 500 V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. VDRV is the DRV clamp voltage VDRV(high) when VCC is higher than VDRV(high). VDRV is VCC otherwise

2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.

NCP1361, NCP1366

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ELECTRICAL CHARACTERISTICS: (VCC = 12 V, CDRV = 1 nF, For typical values TJ = 25°C, for min/max values TJ = −40°C to

+125°C, Max TJ = 150°C, unless otherwise noted)

Characteristics Conditions Symbol Min Typ Max Unit

HIGH VOLTAGE STARTUP SECTION (NCP1366 only)

Startup current sourced by VCC

VHV = 100 V IHV 70 100 150 mA

Leakage current at HV VHV = 400 V, all options except

NCP1366AABAY and NCP1366BABAY

All other options

IHV_LKG −

−

0.1

1.0

1.3

Minimum Start−up HV voltage IHV = 95% of IHV@VHV = 100 V, VCC =

VCC(on) − 0.2 V

VHV(min) −22 25 V

SUPPLY SECTION AND VCC MANAGEMENT

VCC level at which driving

pulses are authorized

VCC increasing VCC(on) 16 18 20 V

VCC level at which driving

pulses are stopped

VCC decreasing VCC(off) 6.0 6.5 7.0 V

Internal Latch / Logic Reset

Level

VCC clamp level

VCC(reset) −5.6 −V

VCC clamp level (A & C

version)

Activated after Latch protection @ ICC =

100 mA

VCC(Clamp) −4.2 −V

Minimal current into VCC pin

that keeps the controller

Latched (NCP1366, A & C fault

mode version)

ICC(Clamp) − − 20 mA

Minimal current into VCC pin

that keeps the controller

Latched (NCP1361, A & C fault

mode version)

ICC(Clamp) − − 6mA

Current−limit resistor in series

with the latch SCR Rlim −7−kW

Over Voltage Protection Over Voltage threshold VCC(OVP) 24 26 28 V

Start−up supply current,

controller disabled or latched

(Only valid with NCP1361 )

VCC < VCC(on) & VCC increasing from

0 V

ICC1 −2.5 5.0 mA

Internal IC consumption,

steady state

Fsw = 65 kHz, CDRV = 1 nF ICC2 −1.7 2.5 mA

Internal IC consumption,

frequency foldback mode

VCO mode, Fsw = 1 kHz, CDRV = 1 nF ICC3 −0.8 1.2 mA

Internal IC consumption when

STBY mode is activated

VCO mode, Fsw = fVCO(min),

VComp = GND, CDRV = 1 nF

fVCO(min) = 200 Hz, (options

NCP1366AABAY, NCP1366BABAY,

NCP1361AABAY, NCP1361BABAY and

NCP1361EABAY)

fVCO(min) = 200 Hz, all other options

fVCO(min) = 600 Hz

fVCO(min) = 1.2 kHz

ICC4

−

200

470

500

530

250

520

TBD*

CURRENT COMPARATOR

Current Sense Voltage

Threshold

VComp = VComp(max), VCS increasing VILIM 0.76 0.80 0.84 V

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

3. The timer can be reset if there are 4 DRV cycles without overload or short circuit conditions

4. Guaranteed by Design.

* Characterization upon request

NCP1361, NCP1366

www.onsemi.com

ELECTRICAL CHARACTERISTICS: (VCC = 12 V, CDRV = 1 nF, For typical values TJ = 25°C, for min/max values TJ = −40°C to

+125°C, Max TJ = 150°C, unless otherwise noted)

Characteristics UnitMaxTypMinSymbolConditions

CURRENT COMPARATOR

Cycle by Cycle Leading Edge

Blanking Duration

options NCP1366AABAY,

NCP1366BABAY, NCP1361AABAY,

NCP1361BABAY and NCP1361EABAY

All other options

tLEB1 250

240

300

360

Cycle by Cycle Current Sense

Propagation Delay

VCS > (VILIM+ 100 mV) to DRV turn−off tILIM −50 100 ns

Timer Delay Before Latching in

Overload Condition

When CS pin w VILIM

(Note 3)

TOCP 50 70 90 ms

Threshold for Immediate Fault

Protection Activation VCS(stop) 1.08 1.2 1.32 V

Leading Edge Blanking

Duration for VCS(stop) tLEB2 −120 −ns

Maximum peak current level at

which VCO takes over or

frozen peak current

VComp < 1.9 V, VCS increasing

option X (~15%VILIM)

option Y (~20%VILIM)

option Z (~25%VILIM)

VCS(VCO) −

−

120

160

200

−

REGULATION BLOCK

Internal Voltage reference for

Constant Current regulation

TJ = 25°C

−40°C < TJ < 125°CVref_CC 0.98

0.97

1.00

1.02

1.03

Pullup Resistor RFB −20 −kW

Valley Thresholds

Transition from 1st to 2nd valley

Transition from 2nd to 3rd valley

Transition from 3rd to 4th valley

Transition from 4th valley to VCO

Transition from VCO to 4th valley

Transition from 4th to 3rd valley

Transition from 3rd to 2nd valley

Transition from 2nd to 1st valley

VComp decreasing

VComp increasing

VH2D

VH3D

VH4D

VHVCOD

VHVCOI

VH4I

VH3I

VH2I

−

2.50

2.30

2.10

1.90

2.50

2.70

2.90

3.10

−

Minimal difference between any

two valleys

VComp increasing or VComp decreasing DVH176 − − mV

Internal Dead Time generation

for VCO mode

Entering in VCO when VComp is

decreasing and crosses VHVCOD

TDT(start) −2−ms

Internal Dead Time generation

for VCO mode

Leaving VCO mode when VComp is

increasing and crosses VHVCOI

TDT(ends) −1−ms

Internal Dead Time generation

for VCO mode

When in VCO mode

VComp = 1.8 V

VComp = 1.3 V

VComp = 0.8 V

VComp < 0.4 V − 200 Hz option (Note 4)

VComp < 0.4 V − 600 Hz option (Note 4)

VComp < 0.4 V − 1.2 kHz option (Note 4)

TDT −

−

220

5000

1667

833

−

Minimum Operating Frequency

in VCO Mode

VComp = GND fVCO(MIN) 150

450

0.9

200

600

1.2

250

750

1.5

kHz

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

3. The timer can be reset if there are 4 DRV cycles without overload or short circuit conditions

4. Guaranteed by Design.

* Characterization upon request

NCP1361, NCP1366

www.onsemi.com

ELECTRICAL CHARACTERISTICS: (VCC = 12 V, CDRV = 1 nF, For typical values TJ = 25°C, for min/max values TJ = −40°C to

+125°C, Max TJ = 150°C, unless otherwise noted)

Characteristics UnitMaxTypMinSymbolConditions

REGULATION BLOCK

Maximum Operating Frequency

Option

fMAX −

103

Clamp

110

−

117

N/A

kHz

DEMAGNETIZATION INPUT − ZERO VOLTAGE DETECTION CIRCUIT and VOLTAGE SENSE

VZCD threshold voltage VZCD decreasing VZCD(TH) 25 45 65 mV

VZCD Hysteresis VZCD increasing VZCD(HYS) 15 30 45 mV

Threshold voltage for output

short circuit or aux. winding

short circuit detection

After tBLANK_ZCD if VZCD < VZCD(short)

Ù Latched VZCD(short) 30 50 70 mV

Propagation Delay from valley

detection to DRV high

VZCD decreasing from 4 V to 0 V tDEM − − 170 ns

Delay after on−time that the

Vs/ZCD is still pulled to ground

(Note 4) tshort_ZCD −0.7 −ms

Blanking delay after on−time

(Vs/ZCD pin is disconnected

from the internal circuitry)

tblank_ZCD 1.2 1.5 1.8 ms

Timeout after last

demagnetization transition Timeout while in Soft−start

Timeout after soft−start complete

toutSS

tout

4.5

5.5

6.5

Input leakage current VCC > VCC(on) VZCD = 4 V, DRV is low IZCD − − 0.1 mA

DRIVE OUTPUT − GATE DRIVE

Drive resistance

DRV Sink

DRV Source

RSNK

RSRC

−

Rise time CDRV = 1 nF, from 10% to 90% tr−45 80 ns

Fall time CDRV = 1 nF, from 90% to 10% tf−30 60 ns

DRV Low voltage VCC = VCC(off) + 0.2 V,

CDRV = 220 pF, RDRV = 33 kW

VDRV(low) 6.0 − − V

DRV High voltage VCC = VCC(OVP)−0.2 V, CDRV = 220 pF,

RDRV = 33 kW

VDRV(high) − − 13.0 V

SOFT START

Internal Fixed Soft Start

Duration

Current Sense peak current rising from

0.2 V to 0.8 V

tSS 3 4 5 ms

FAULT PROTECTION

Thermal Shutdown Device switching (Fsw ∼ 65 kHz)

(Note 4)

TSHTDN −150 −°C

Thermal Shutdown Hysteresis Device switching (Fsw ∼ 65 kHz)

(Note 4)

TSHTDN(HYS) −40 −°C

Number of Drive cycle before

latch confirmation

VComp = VComp(max),

VCS > VCS(stop)

Or Internal sampled Vout > VOVP

Tlatch_count −4− −

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

3. The timer can be reset if there are 4 DRV cycles without overload or short circuit conditions

4. Guaranteed by Design.

* Characterization upon request

NCP1361, NCP1366

www.onsemi.com

ELECTRICAL CHARACTERISTICS: (VCC = 12 V, CDRV = 1 nF, For typical values TJ = 25°C, for min/max values TJ = −40°C to

+125°C, Max TJ = 150°C, unless otherwise noted)

Characteristics UnitMaxTypMinSymbolConditions

FAULT PROTECTION

Fault level detection for OVP Ù

Latched or Double Hiccup

autorecovery (depends on fault

version)

Internal sampled Vout increasing

VOVP = Vref_CV2+26%

Version E

VOVP 2.95

3.4

3.15

3.6

3.35

3.8

Fault level detection for UVP Ù

Double Hiccup autorecovery

(UVP detection is disabled

during TEN_UVP)

Internal sampled Vout decreasing

Fault Mode Option A & B

Fault Mode Option Version E

VUVP 1.4

0.70

1.5

0.75

1.6

0.80

Blanking time for UVP

detection

Starting at the beginning of the Soft

start

TEN_UVP −37 −ms

Pull−up Current Source on CS

pin for Open or Short circuit

detection

When VCS > VCS_min ICS −55 −mA

CS pin Open detection CS pin open VCS(open) 0.8 − − V

CS pin Short detection VCS_min −50 70 mV

CS pin Short detection timer (Note 4) TCS_short −3−ms

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

3. The timer can be reset if there are 4 DRV cycles without overload or short circuit conditions

4. Guaranteed by Design.

* Characterization upon request

NCP1361, NCP1366

www.onsemi.com

FAULT MODE STATES TABLE (WHATEVER THE VERSION)

Event

Timer

Protection Next Device Status Release to Normal Operation Mode

Overcurrent

VCS > VILIM

OCP timer Double Hiccup •Resume to normal operation: if 4 pulses from FB

Reset & then Reset timer

•Resume operation after Double Hiccup

Winding short

VCS > VCS(stop)

Immediate 4 consecutive pulses with

VCS > VCS(stop) before

Latching

VCC is decreasing to VCC(clamp) and waiting for unplug

from line VCC < VCC(reset)

CS pin Fault:

Short & Open

Immediate Double Hiccup Resume operation after Double Hiccup

Low supply

VCC < VCC(off)

10 ms timer Double Hiccup Resume operation after Double Hiccup

Internal TSD 10 ms timer Double Hiccup Resume operation after Double Hiccup & T < (TSHTDN

− TSHTDN(Hyst))

ZCD short

VZCD < VZCD(short) after

tBLANK_ZCD time

Immediate Double Hiccup Resume operation after Double Hiccup (VCC(on) < VCC

< VCC(reset))

FAULT MODE STATES TABLE (ACCORDING TO THE CONTROLLER VERSIONS)

Event A Version B Version C Version

High supply

VCC > VCC(ovp)

Latched_Timer Autorecovery Latched_Timer

Internal Vout

OVP: Vout > 126% Vref_CV2

Latched_4clk Autorecovery Latched_4clk

Internal Vout

UVP: Vout < 60%

Vref_CV2, when Vout is decreasing only

Autorecovery Autorecovery Latched_Timer

FAULT TYPE MODE DEFINITION

Fault Mode Timer Protection Next Device Status Release to Normal Operation Mode

Latched_Timer 10 ms timer Latched VCC is decreasing to VCC(clamp) and waiting for un-

plug from line VCC < VCC(reset)

Latched_4clk Immediate 4 consecutive pulses with

VCS > 126% Vref_CV2 before

Latching

VCC is decreasing to VCC(clamp) and waiting for un-

plug from line VCC < VCC(reset)

Autorecovery Immediate Resume operation after

Double Hiccup

Resume operation after Double Hiccup (VCC(on) <

VCC < VCC(reset))

NCP1361, NCP1366

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CHARACTERIZATION CURVES

19.5

18.5

17.5

16.5

−50 −25 0 25 50 75 100 125 150

Figure 5. VCC Startup Threshold versus

Temperature

TJ, TEMPERATURE (°C)

VCC(on) (V)

7.0

−50 −25 0 25 50 75 100 125 150

Figure 6. VCC Minimum Operating versus

Temperature

TJ, TEMPERATURE (°C)

VCC(off) (V)

6.9

6.8

6.7

6.6

6.5

6.4

6.3

6.2

6.1

6.0

6.6

−50 −25 0 25 50 75 100 125 150

Figure 7. VCC(reset) versus Temperature

TJ, TEMPERATURE (°C)

VCC(reset) (V)

6.4

6.2

6.0

5.8

5.6

5.4

5.2

5.0

4.8

4.6

28.0

−50 −25 0 25 50 75 100 125 150

Figure 8. VCC(OVP) versus Temperature

TJ, TEMPERATURE (°C)

VCC(OVP) (V)

27.5

27.0

26.5

26.0

25.5

25.0

24.5

24.0

160

−50 −25 0 25 50 75 100 125 150

Figure 9. Startup Current Source versus

Temperature

TJ, TEMPERATURE (°C)

IHV (mA)

150

140

130

120

110

100

1.0

−50 −25 0 25 50 75 100 125 150

Figure 10. HV Pin Leakage versus Temperature

TJ, TEMPERATURE (°C)

IHV_LKG (mA)

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

NCP1361, NCP1366

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CHARACTERIZATION CURVES

−50 −25 0 25 50 75 100 125 150

Figure 11. Minimum Voltage for HV Startup

Current Source versus Temperature

TJ, TEMPERATURE (°C)

VHV(min) (V)

2.4

−50 −25 0 25 50 75 100 125 150

Figure 12. ICC2 versus Temperature

TJ, TEMPERATURE (°C)

ICC2 (mA)

1.00

−50 −25 0 25 50 75 100 125 150

Figure 13. ICC3 versus Temperature

TJ, TEMPERATURE (°C)

ICC3 (mA)

−50 −25 0 25 50 75 100 125 150

Figure 14. Standby Current Consumption

(200 Hz option) versus Temperature

TJ, TEMPERATURE (°C)

ICC4 (mA)

0.84

−50 −25 0 25 50 75 100 125 150

Figure 15. Max Peak Current Limit versus

Temperature

TJ, TEMPERATURE (°C)

VILIM (V)

1.32

−50 −25 0 25 50 75 100 125 150

Figure 16. Second Peak Current Limit for Fault

Protection versus Temperature

TJ, TEMPERATURE (°C)

VCS(stop) (V)

2.0

1.8

1.6

1.4

1.2

1.0

0.95

0.90

0.85

0.80

0.75

0.70

0.65

0.60

0.55

0.50

520

500

480

460

440

420

400

0.83

0.82

0.81

0.80

0.79

0.78

0.77

0.76

1.30

1.28

1.26

1.24

1.22

1.20

1.18

1.16

1.14

1.10

1.08

NCP1361, NCP1366

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CHARACTERIZATION CURVES

1.02

−50 −25 0 25 50 75 100 125 150

Figure 17. Internal Voltage Reference for

Constant Current Regulation versus

Temperature

TJ, TEMPERATURE (°C)

Vref_CC (V)

3.40

−50 −25 0 25 50 75 100 125 150

Figure 18. Output Over Voltage Level versus

Temperature (Fault Mode Options A, B & C)

TJ, TEMPERATURE (°C)

VOVP (V)

1.60

−50 −25 0 25 50 75 100 125 150

Figure 19. Output Under Voltage Level versus

Temperature (Fault Mode Options A & B)

TJ, TEMPERATURE (°C)

VUVP (V)

360

−50 −25 0 25 50 75 100 125 150

Figure 20. Cycle−by−Cycle Leading Edge

Blanking Duration versus Temperature

TJ, TEMPERATURE (°C)

tLEB1 (ns)

180

−50 −25 0 25 50 75 100 125 150

Figure 21. Leading Edge Blanking Duration for

VCS(stop) Level versus Temperature

TJ, TEMPERATURE (°C)

tLEB2 (ns)

1.01

1.00

0.99

0.98

3.35

3.30

3.25

3.20

3.15

3.10

3.05

3.00

2.95

2.90

1.58

1.56

1.54

1.52

1.50

1.48

1.46

1.44

1.42

1.40

340

320

300

280

260

240

160

140

120

100

NCP1361, NCP1366

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CHARACTERIZATION CURVES

100

−50 −25 0 25 50 75 100 125 150

Figure 22. Cycle−by−Cycle Current Sense

Propagation Delay versus Temperature

TJ, TEMPERATURE (°C)

tILIM (ns)

−50 −25 0 25 50 75 100 125 150

Figure 23. Timeout After Last Demagnetization

Transition in Soft−Start versus Temperature

TJ, TEMPERATURE (°C)

toutSS (ms)

6.5

−50 −25 0 25 50 75 100 125 150

Figure 24. Timeout After Last Demagnetization

Transition versus Temperature

TJ, TEMPERATURE (°C)

tout (ms)

−50 −25 0 25 50 75 100 125 150

Figure 25. Timer Delay Before Latching in

Overload Condition versus Temperature

TJ, TEMPERATURE (°C)

TOCP (ms)

−50 −25 0 25 50 75 100 125 150

Figure 26. Zero Voltage Detection Threshold

Voltage versus Temperature

TJ, TEMPERATURE (°C)

VZCD(TH) (mV)

−50 −25 0 25 50 75 100 125 150

Figure 27. Zero Voltage Detection Hysteresis

versus Temperature

TJ, TEMPERATURE (°C)

VZCD(HYS) (mV)

6.3

6.1

5.9

5.7

5.5

5.3

5.1

4.9

4.7

4.5

NCP1361, NCP1366

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CHARACTERIZATION CURVES

1.8

−50 −25 0 25 50 75 100 125 150

Figure 28. Blanking Delay for ZCD Detection

versus Temperature

TJ, TEMPERATURE (°C)

Tblank_ZCD (ms)

8.0

−50 −25 0 25 50 75 100 125 150

Figure 29. VDRV(low) versus Temperature

TJ, TEMPERATURE (°C)

VDRV(low) (V)

13.0

−50 −25 0 25 50 75 100 125 150

Figure 30. VDRV(high) versus Temperature

TJ, TEMPERATURE (°C)

VDRV(high) (V)

−50 −25 0 25 50 75 100 125 150

Figure 31. Gate Drive Rise Time versus

Temperature

TJ, TEMPERATURE (°C)

tr (ns)

−50 −25 0 25 50 75 100 125 150

Figure 32. Gate Drive Fall Time versus

Temperature

TJ, TEMPERATURE (°C)

tf (ns)

1.7

1.6

1.5

1.4

1.3

1.2

7.8

7.6

7.4

7.2

7.0

6.8

6.6

6.4

6.2

6.0

12.5

12.0

11.5

11.0

10.5

10.0

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CHARACTERIZATION CURVES

Figure 33. Minimum or Frozen Peak Current on

CS Pin versus Temperature (Frozen Peak

Current optionY)

VCS(VCO) (mV)

−50 −25 0 25 50 75 100 125 150

Figure 34. Threshold Level for Detecting

Output or Aux. Winding Short versus

Temperature

TJ, TEMPERATURE (°C)

VZCD(short) (mV)

−50 −25 0 25 50 75 100 125 150

Figure 35. Startup Blanking Time for UVP

Detection versus Temperature

TJ, TEMPERATURE (°C)

TEN_UVP (ms)

−50 −25 0 25 50 75 100 125 150

Figure 36. Pull−up Current Source for

Detecting Open or Short on CS Pin versus

Temperature

TJ, TEMPERATURE (°C)

ICS (mA)

−50 −25 0 25 50 75 100 125 150

TJ, TEMPERATURE (°C)

200

180

160

140

120

100

−50 −25 0 25 50 75 100 125 150

Figure 37. CS Pin Short Detection Threshold

versus Temperature

TJ, TEMPERATURE (°C)

VCS_min (mV)

1.20

−50 −25 0 25 50 75 100 125 150

Figure 38. CS Pin Open Detection Threshold

versus Temperature

TJ, TEMPERATURE (°C)

VCS(open) (V)

1.10

1.00

0.90

0.80

0.70

0.60

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APPLICATION INFORMATION

The NCP1366/61 is a flyback power supply controller

providing a means to implement primary side

constant−current regulation. This technique does not need a

secondary side feedback circuitry, associated bias current

and an opto−coupler. NCP1366/61 implements a

current−mode architecture operating in quasi−resonant

mode. The controller prevents valley−jumping instability

and steadily locks out in a selected valley as the power

demand goes down. As long as the controller is able to detect

a valley, the new cycle or the following drive remains in a

valley. Due to a dedicated valley detection circuitry

operating at any line and load conditions, the power supply

efficiency will always be optimized. In order to prevent any

high switching frequency two frequency clamp options are

available.

•Quasi−Resonance Current−mode operation:

implementing quasi−resonance operation in peak

current−mode control optimizes the efficiency by

switching in the valley of the MOSFET drain−source

voltage. Due to a proprietary circuitry, the controller

locks−out in a selected valley and remains locked until

the input voltage significantly changes. Only the four

first valleys could be locked out. When the load current

diminishes, valley switching mode of operation is kept

but without valley lock−out. Valley−switching

operation across the entire input/output conditions

brings efficiency improvement and lets the designer

build higher−density converters.

•Frequency Clamp: As the frequency is not fixed and

dependent on the line, load and transformer

specifications, it is important to prevent switching

frequency runaway for applications requiring maximum

switching frequencies up to 90 kHz or 130 kHz. Two

frequency clamp options at 80 kHz or 110 kHz are

available for this purpose. In case frequency clamp is

not needed, a specific version of the 1361/66 exists in

which the clamp is deactivated.

•Primary Side Constant Current Regulation: Battery

charging applications request constant current

regulation. NCP1361/66 controls and regulates the

output current at a constant level regardless of the input

and output voltage conditions. This function offers tight

over power protection by estimating and limiting the

maximum output current from the primary side, without

any particular sensor.

•Optocoupler−based feedback: the voltage feedback

loop is classically implemented with an optocoupler

and a NCP431 voltage reference in the secondary side.

By pulling the feedback pin low, the controller adjusts

the peak current setpoint and regulates Vout.

Vout

Iout

Optocoupler−based feedback

CC mode

Vnom

Inom

Figure 39. Constant−Voltage & Constant−Current

Mode

Primary−side

•Soft−Start: 4 ms internal fixed soft start guarantees a

peak current starting from zero to its nominal value

with smooth transition in order to prevent any

overstress on the power components at each startup.

•Cycle−by−Cycle peak current limit: If the max peak

current reaches the VILIM level, the over current

protection timer is enabled and starts counting. If the

overload lasts TOCP delay, then the fault is latched and

the controller stops immediately driving the power

MOSFET. The controller enters in a double hiccup

mode before autorecovering with a new startup cycle.

•VCC Over Voltage Protection: If the VCC voltage

reaches the VCC(OVP) threshold the controller enters in

latch mode. Thus it stops driving pulse on DRV pin:

♦A & C version − (Latched VCC(OVP)): VCC

capacitor is internally discharged to the VCC(Clamp)

level with a very low power consumption: the

controller is completely disabled. Resuming

operation is possible by unplugging the line in order

to releasing the internal VCC thyristor with a VCC

current lower than the ICC(Clamp).

♦B version − (Autorecovery): it enters in double

hiccup mode before resuming operation.

•Winding Short−Circuit Protection: An additional

comparator senses the CS signal and stops the

controller if VCS reaches VILIM+50% (after a reduced

LEB: tLEB2). Short circuit protection is enabled only if

4 consecutive pulses reach SCP level. This small

counter prevents any false triggering of short circuit

protection during surge test for instance. This fault is

latched and operations will be resumed like in a case of

VCC Over Voltage Protection.

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•Vout Over Voltage Protection: if the internally−built

output voltage becomes higher than VOVP level

ref_CV1 + 26%) a fault is detected.

♦A & C version: This fault is latched and operations

are resumed like in the VCC Over Voltage Protection

case.

♦B version: the part enters in double hiccup mode

before resuming operations.

•Vout Under Voltage Protection: After each circuit

power on sequence, V

out UVP detection is enabled only

after the startup timer TEN_UVP. This timer ensures that

the power supply is able to fuel the output capacitor

before checking the output voltage in on target. After

this startup blanking time, UVP detection is enabled

and monitors the Output voltage level. When the power

supply is running in constant−current mode and when

the output voltage falls below VUVP level, the controller

stops sending drive pulses and enters a double hiccup

mode before resuming operations (A & B version), or

latches off (C version).

•Vs/ZCD Pin Short Protection: at the beginning of

each off−time period, the Vs/ZCD pin is tested to check

whether it is shorted or left open. In case a fault is

detected, the controller enters in a double hiccup mode

before resuming operations.

•Temperature Shutdown: if the junction temperature

reaches the TSHTDN level, the controller stop driving the

power mosfet until the junction temperature decreases

by TSHTDN(HYS), then the operation is resumed after a

double hiccup mode.

Startup Operation

The high−voltage startup current source is connected to

the bulk capacitor via the HV pin, it charges the VCC

capacitor. During startup phase, it delivers 100 mA to fuel the

VCC capacitor. When VCC pin reaches VCC(on) level, the

NCP1361/66 is enabled. Before sending the first drive pulse

to the power MOSFET, the CS pin has been tested for an

open or shorted situation. If CS pin is properly wired, then

the controller sends the first drive pulse to the power

MOSFET. After sending these first pulses, the controller

checks the correct Vs/ZCD pin wiring. Considering the

Vs/ZCD pin properly wired, the controller engages a

softstart sequence. The softstart sequence controls the max

peak current from the minimal frozen primary peak current

(VCS(VCO)= 120 mV: 15% of VILIM) to the nominal pulse

width by smoothly increasing the level.

Figure 40 illustrates a standard connection of the HV pin

to the bulk capacitor. If the controller is in a latched fault

mode (ex VCC_OVP has been detected), the power supply will

resume the operation after unplugging the converter from

the ac line outlet. Due the extremely low controller

consumption in latched mode, the release of the latch could

be very long. The unplug duration for releasing the latch will

be dependent on the bulk capacitor size.

5DRV GND

Vs/ZCD HV

6VccCS

Vbulk RHV

CVcc Vaux

Figure 40. HV Startup Connection to the Bulk Capacitor (NCP1366)

The following calculation illustrates the time needed for

releasing the latch state:

tunplug u

CbulkVin_ac 2

IHV

(eq. 1)

For the following typical application with a 10 mF bulk

capacitor and a wide mains input range, in the worst case the

power supply needs to be unplug at least for 38 seconds @

265 V ac and 12 seconds @ 85 Vac. It is important to note

that the previous recommendation is no longer valid with the

B version, as all the faults are set to autorecovery mode only.

Protecting the Controller Against Negative Spikes

As with any controller built upon a CMOS technology, it

is the designer’s duty to avoid the presence of negative

spikes on sensitive pins. Negative injection has the bad habit

to forward−bias the controller substrate and can induce

erratic behaviors. Sometimes, the injection can be so strong

that internal parasitic SCRs are triggered and latch the

controller. The HV pin can be the problem in certain

circumstances. During the turn−off sequence, e.g. when the

user unplugs the power supply, the controller is still fed by

its VCC capacitor and keeps activating the MOSFET ON and

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OFF with a peak current limited by Rsense. Unfortunately, if

the quality factor Q of the resonating network formed by Lp

and Cbulk is high (e.g. the MOSFET RDS(on) + Rsense are

small), conditions are met to make the circuit resonate and

a negative ringing can potentially appear at the HV pin.

Simple and inexpensive cures exist to prevent the internal

parasitic SCR activation. One of them consist of inserting a

resistor in series with the HV pin to keep the negative current

at the lowest when the bulk swings negative (Figure 40).

Another option (Figure 41) consists of connecting the

HV pin directly to the line or neutral input via a high−voltage

diode. This configuration offers the benefits to release a

latch state immediately after unplugging the power supply

from the mains outlet. There is no delay for resetting the

controller as there no capacitor keeps the HV bias.

RHV resistor value must be sized as follow in order to

guarantee a correct behavior of the HV startup in the worst

case conditions:

RHV t

Vin,ac_min 2

Ǹ*VHV(min)_max

IHV_max

(eq. 2)

Where:

•V

in,ac_min is minimal input voltage, for example 85 V ac

for universal input mains.

•VHV(min)_max is the worst case of the minimal input

voltage needed for the HV startup current source

(25 V−max).

•IHV_max is the maximum current delivered by the HV

startup current source (150 mA−max)

With this typical example

RHV t85 2

Ǹ*25

150 m+633 kW,

then any value below this one will be ok.

5DRV GND

Vs/ZCD HV

6VCC2CS

Vbulk

Vaux

CVcc

Figure 41. Recommended HV Startup Connection for Fast Release after a Latched Fault (NCP1366)

Primary Side Regulation: Constant Current Operation

Figure 42 portrays idealized primary and secondary

transformer currents of a flyback converter operating in

Discontinuous Conduction Mode (DCM).

Figure 42. Primary and Secondary Transformer Current Waveforms

Ip(t)

Is(t), IOUT

IOUT = <Is(t)>

ppk

spk

Ipk

tdemag

tsw

time

ton

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When the primary power MOSFET is turned on, the

primary current is illustrated by the green curve of

Figure 42. When the power MOSFET is turned off the

primary side current drops to zero and the current into the

secondary winding immediately rises to its peak value equal

to the primary peak current divided by the primary to

secondary turns ratio. This is an ideal situation in which the

leakage inductance action is neglected.

The output current delivered to the load is equal to the

average value of the secondary winding current, thus we can

write:

Iout +t isec(t)u+

Ip,pk

2Nps

tdemag

tsw

(eq. 3)

Where:

•tsw is the switching period

•tdemag is the demagnetizing time of the transformer

•Nps is the secondary to primary turns ratio, where Np

and Ns are respectively the transformer primary and

secondary turns:

Nps +Ns

(eq. 4)

•Ip,pk is the magnetizing peak current sensed across the

sense resistor on CS pin:

Ip,pk +

VCS

Rsense

(eq. 5)

Internal constant current regulation block is building the

constant current feedback information as follow:

VFB_CC +Vref_CC

tsw

tdemag

(eq. 6)

As the controller monitors the primary peak current via the

sense resistor and due to the internal current setpoint divider

(Kcomp ) between the CS pin and the internal feedback

information, the output current could be written as follow:

Iout +

Vref_CC

8NpsRsense

(eq. 7)

The output current value is set by choosing the sense

resistor value:

Rsense +

Vref_CC

8NpsIout

(eq. 8)

When the power MOSFET is released at the end of the on

time, because of the transformer leakage inductance and the

drain lumped capacitance some voltage ringing appears on

the drain node. These voltage ringings are also visible on the

auxiliary winding and could cheat the controller detection

circuits. To avoid false detection operations, two protecting

circuits have been implemented on the Vs/ZCD pin (see

Figure 43):

1. An internal switch grounds the Vs/ZCD pin during

ton+tshort_ZCD in order to protect the pin from

negative voltage.

2. In order to prevent any misdetection from the zero

crossing block an internal switch disconnects

Vs/ZCD pin until tblank_ZCD time (1.5 ms typ.)

ends.

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Figure 43. Vs/ZCD Pin Waveforms

Constant−Current and Constant−Voltage Overall

Regulation:

As already presented in the two previous paragraphs, the

controller integrates two different feedback loops: the first

one deals with the constant−current regulation scheme while

the second one builds the constant−voltage regulation with

an opto−based voltage loop. One of the two feedback paths

sets the primary peak current into the transformer. During

startup phase, however, the peak current is controlled by the

soft−start.

Zero Current Detection

The NCP1361/66 integrates a quasi−resonant (QR)

flyback controller. The power switch turn−off of a QR

converter is determined by the peak current whose value

depends on the feedback loop. The switch restart event is

determined by the transformer demagnetization end. The

demagnetization end is detected by monitoring the

transformer auxiliary winding voltage. Turning on the

power switch once the transformer is demagnetized (or

reset) reduces turn−on switching losses. Once the

transformer is demagnetized, the drain voltage starts ringing

at a frequency determined by the transformer magnetizing

inductance and the drain lumped capacitance, eventually

settling at the input voltage value. A QR controller takes

advantage of the drain voltage ringing and turns on the

power switch at the drain voltage minimum or “valley” to

reduce turn−on switching losses and electromagnetic

interference (EMI).

As sketched by Figure 44, a valley is detected once the

ZCD pin voltage falls below the QR flyback

demagnetization threshold, VZCD(TH), typically 45 mV. The

controller will switch once the valley is detected or

increment the valley counter depending on FB voltage.

Rs1

Rs2

ZCD

Timeout

(toutSS or tout)

QR multi−mode

Valley lockout &

Valley Switching &

VCO management

Blanking

Tblank_ZCD

DRV

(Internal)

VZCD(TH)

Figure 44. Valley Lockout Detection Circuitry internal Schematic

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Timeout

The ZCD block actually detects falling edges of the

auxiliary winding voltage applied to the ZCD pin. At

start−up or during other transient phases, the ZCD

comparator may be unable to detect such an event. Also, in

the case of extremely damped oscillations, the system may

not succeed in detecting all the valleys required by valley

lockout operation (VLO, see next section). In this condition,

the NCP1361/66 ensures continued operation by

incorporating a maximum timeout period that resets itself

when a demagnetization phase is properly detected. In case

the ringing signal is too weak or heavily damped, the timeout

signal supersedes the ZCD signal for the valley counter.

Figure 44 shows the timeout period generator circuit

schematic. The timeout duration, tout, is set to 5.5 ms (typ.).

During startup, the output voltage is still low, leading to

long demagnetization phase, difficult to detect since the

auxiliary winding voltage is small as well. In this condition,

the tout timeout is generally shorter than the inductor

demagnetization period and if used to restart a switching

cycle, it can cause continuous current mode (CCM)

operation for a few cycles until the voltage on the ZCD pin

is high enough for proper valleys detection. A longer

timeout period, toutSS, (typically 44 ms) is therefore set

during soft−start to prevent CCM operation.

In VLO operation, the timeout occurrences are counted

instead of valleys when the drain−source voltage

oscillations are too damped to be detected. For instance,

assume the circuit must turn on at the third valley and the

ZCD ringing only enables the detection of:

•Valleys #1 to #2: the circuit generates a DRV pulse tout

(steady−state timeout delay) after valley #2 detection.

•Valley #1: the timeout delay must run twice so that the

circuit generates a DRV pulse 10 ms (2*tout typ.) after

valley #1 detection.

Valley LockOut (VLO) and Frequency Foldback (FF)

The operating frequency of a traditional Quasi−Resonant

(QR) flyback controller is inversely proportional to the

system load. In other words, a load reduction increases the

operating frequency. A maximum frequency clamp can be

useful to limit the operating frequency range. However,

when associated with a valley−switching circuit,

instabilities can arise because of the discrete frequency

jumps. The controller tends to hesitate between two valleys

and audible noise can be generated

To avoid this issue, the NCP1361/66 incorporates a

proprietary valley lockout circuitry which prevents

so−called valley jumping. Once a valley is selected, the

controller stays locked in this valley until the input level or

output power changes significantly. This technique extends

QR operation over a wider output power range while

maintaining good efficiency and naturally limiting the

maximum operating frequency.

The operating valley (from 1st to 4th valley) is determined

by the internal feedback level (FB node on Figure 4). As FB

voltage level decreases or increases, the valley comparators

toggle one after another to select the proper valley.

The decimal counter increases each time a valley is

detected. The activation of an “n” valley comparator blanks

the “n−1” or “n+1” valley comparator output depending if

VFB decreases or increases, respectively. Figure 45 shows a

typical frequency characteristic obtained at low line in a

10 W charger.

Figure 45. Typical Switching Frequency versus Output Power Relationship in a 10 W Adapter

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When an “n” valley is asserted by the valley selection

circuitry, the controller locks in this valley until the FB

voltage decreases to the lower threshold (“n+1” valley

activates) or increases to the “n valley threshold” + 600 mV

(“n−1” valley activates). The regulation loop adjusts the

peak current to deliver the necessary output power at the

valley operating point. Each valley selection comparator

features a 600 mV hysteresis that helps stabilize operation

despite the FB voltage swing produced by the regulation

loop.

Table 1. VALLEY FB THRESHOLD ON CONSTANT VOLTAGE REGULATION

FB Falling FB Rising

1st to 2nd valley 2.5 V FF mode to 4th 2.5 V

2nd to 3rd valley 2.3 V 4th to 3rd valley 2.7 V

3rd to 4th valley 2.1 V 3rd to 2nd valley 2.9 V

4th to FF mode 1.9 V 2nd to 1st valley 3.1 V

Frequency Foldback (FF)

As the output current decreases (FB voltage decreases),

the valleys are incremented from 1 to 4. In case the fourth

valley is reached, the FB voltage further decreases below

1.9 V and the controller enters the frequency foldback mode

(FF). The current setpoint being internally forced to remain

above 0.12 V (setpoint corresponding to VComp = 1.9 V), the

controller regulates the power delivery by modulating the

switching frequency. When an output current increase

causes FB to exceed the 2.5 V FF upper threshold (600−mV

hysteresis), the circuit recovers VLO operation.

In frequency foldback mode, the system reduces the

switching frequency by adding some dead−time after the 4th

valley is detected. However, in order to keep the high

efficiency benefit inherent to the QR operation, the

controller turns on again with the next valley after the dead

time has ended. As a result, the controller will still run in

valley switching mode even when the FF is enabled. This

dead−time increases when the FB voltage decays. There is

no discontinuity when the system transitions from VLO to

FF and the frequency smoothly reduces as FB goes below

1.9 V.

The dead−time is selected to generate a 2 ms dead−time

when VComp is decreasing and crossing VHVCOD (1.9 V

typ.). At this moment, it can linearly go down to the minimal

frequency limit (fVCO(min)= 200, 600 or 1200 Hz version are

available). The generated dead−time is 1ms when VComp is

increasing and crossing VHVCOI (2.5 V typ.).

Figure 46. Valley Lockout Threshold

Current Setpoint

As explained in this operating description, the current

setpoint is affected by several functions. Figure 47

summarizes these interactions. As shown by this figure, the

current setpoint is the output of the control law divided by

Kcomp (4 typ.). This current setpoint is clamped by the

soft−start slope as long as the peak current requested by the

FB_CV or FB_CC level are higher. The softstart clamp is

starting from the frozen peak current (VCS(VCO) = 120 mV

typ.) to VILIM (0.8 V typ.) within 4 ms (tss).

However, this internal FB value is also limited by the

following functions:

♦A minimum setpoint is forced that equals VCS(VCO)

(0.12 V, typ.)

♦In addition, a second OCP comparator ensures that

in any case the current setpoint is limited to VILIM.

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This ensures the MOSFET current setpoint remains

limited to VILIM in a fault condition.

FB Reset

Max_Ipk reset

OCP

Timer

Count

Reset Timer

LEB1

VILIM

POReset

DbleHiccup

LEB2

VCS(Stop)

4 clk

Counter

Reset

Counter

OCP

1/Kcomp

SCP

Peak current

Freeze

Control Law

For

Primary Peak

Current Control

SoftStart

FB_CV

FB_CC

PWM

Latch

Reset

PWM Comp

OCP

Comp

Short Circuit

Comp

Rsense

RCS

CCS

Figure 47. Current Setpoint

A 2nd Over−Current Comparator for Abnormal

Overcurrent Fault Detection

A severe fault like a winding short−circuit can cause the

switch current to increase very rapidly during the on−time.

The current sense signal significantly exceeds VILIM. But,

because the current sense signal is blanked by the LEB

circuit during the switch turn on, the power switch current

can abnormally increase, possibly causing system damages.

The NCP1361/66 protects against this dangerous mode by

adding an additional comparator for abnormal overcurrent

fault detection or short−circuit condition. The current sense

signal is blanked with a shorter LEB duration, tLEB2,

typically 120 ns, before applying it to the short−circuit

comparator. The voltage threshold of this extra comparator,

VCS(stop), is typically 1.2 V, set 50% higher than VILIM. This

is to avoid interference with normal operation. Four

consecutive abnormal overcurrent faults cause the

controller to enter in auto−recovery mode. The count to 4

provides noise immunity during surge testing. The counter

is reset each time a DRV pulse occurs without activating the

fault overcurrent comparator or after double hiccup

sequence or if the power supply is unplugged with a new

startup sequence after the initial power on reset.

Standby Power Optimization

Assuming the no−load standby power is a critical

parameter, the NCP1361/66 is optimized to reach an ultra

low standby power. When the controller enters standby

mode, a part of the internal circuitry has been disabled in

order to minimize its supply current. When the STBY mode

is enabled, the consumption is only 200 mA (ICC4) with the

200 Hz minimal frequency option.

Fault mode and Protection

♦CS pin: at each startup, a 55 mA (ICS ) current source

pulls up the CS pin to disable the controller if the pin

is left open or grounded. Then the controller enters

in a double hiccup mode.

♦Vs/ZCD pin: after sending the first drive pulse the

controller checks the correct wiring of Vs/ZCD pin:

after the ZCD blanking time, if there is an open or

short conditions, the controller enters in double

hiccup mode.

Thermal Shutdown: An internal thermal shutdown circuit

monitors the junction temperature of the IC. The controller

is disabled if the junction temperature exceeds the thermal

shutdown threshold (TSHDN), typically 150°C. A continuous

VCC hiccup is initiated after a thermal shutdown fault is

detected. The controller restarts at the next VCC(on) once the

IC temperature drops below TSHDN reduced by the thermal

shutdown hysteresis (TSHDN(HYS)), typically 40°C. The

thermal shutdown is also cleared if VCC drops below

VCC(reset ). A new power up sequences commences at the

next VCC(on) once all the faults are removed.

Driver

The NCP1361/66 maximum supply voltage, VCC(max), is

28 V. Typical high−voltage MOSFETs have a maximum

gate voltage rating of 20 V. The DRV pin incorporates an

active voltage clamp which limits the gate voltage on the

external mosfet. The DRV voltage clamp, VDRV(high) is set to

13 V maximum.

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TABLE OF AVAILABLE OPTIONS

Function Options

Fault Mode VCC_OVP Latched / Full Autorecovery /

Vout_UVP latched

Minimum operating frequency in VCO 200 Hz / 600 Hz / 1.2 kHz / 23 kHz

Frequency Clamp or Maximum operating

frequency

No Clamp / 80 kHz / 110 kHz

ORDERING TABLE OPTION

OPN #

NCP136_ _ _ _ _

Start-

up Fault Mode Min Operating Fsw (STBY) Frequency Clamp

Frozen Peak Current

VCS(VCO)

6 1 A B C E A B C D E A B C X Y Z

Yes No Vcc_OVP

Latched

Full

Autorecovery

Vout_UVP

Latched

VOVP=3.6V

VUVP=0.75V

200Hz 600Hz 1.2kHz 23kHz No

min

No 80kHz 110kHz 120mV 160mV 200mV

NCP1366AABAY X X X X X

NCP1366BABAY X X X X X

NCP1366CABAY X X X X X

NCP1366EABAY X X X X X

NCP1361AABAY X X X X X

NCP1361BABAY X X X X X

NCP1361CABAY X X X X X

NCP1361EABAY X X X X X

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ORDERING INFORMATION

Device Marking Package Shipping†

NCP1366AABAYDR2G 1366A1 SOIC−7

(Pb−Free)

2500 / Tape & Reel

NCP1366BABAYDR2G 1366B1 SOIC−7

(Pb−Free)

2500 / Tape & Reel

NCP1361AABAYSNT1G ADE TSOP−6

(Pb−Free)

3000 / Tape & Reel

NCP1361BABAYSNT1G ADF TSOP−6

(Pb−Free)

3000 / Tape & Reel

NCP1361EABAYSNT1G ACU TSOP−6

(Pb−Free)

3000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

ÉÉ

TSOP−6

CASE 318G−02

ISSUE V

DATE 12 JUN 2012

SCALE 2:1

STYLE 1:

PIN 1. DRAIN

2. DRAIN

3. GATE

4. SOURCE

5. DRAIN

6. DRAIN

456

0.05

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM

LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.

4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,

PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR

GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D

AND E1 ARE DETERMINED AT DATUM H.

5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.

STYLE 2:

PIN 1. EMITTER 2

2. BASE 1

3. COLLECTOR 1

4. EMITTER 1

5. BASE 2

6. COLLECTOR 2

STYLE 3:

PIN 1. ENABLE

2. N/C

3. R BOOST

4. Vz

5. V in

6. V out

STYLE 4:

PIN 1. N/C

2. V in

3. NOT USED

4. GROUND

5. ENABLE

6. LOAD

XXX MG

XXX = Specific Device Code

A =Assembly Location

Y = Year

W = Work Week

G= Pb−Free Package

STYLE 5:

PIN 1. EMITTER 2

2. BASE 2

3. COLLECTOR 1

4. EMITTER 1

5. BASE 1

6. COLLECTOR 2

STYLE 6:

PIN 1. COLLECTOR

2. COLLECTOR

3. BASE

4. EMITTER

5. COLLECTOR

6. COLLECTOR

STYLE 7:

PIN 1. COLLECTOR

2. COLLECTOR

3. BASE

4. N/C

5. COLLECTOR

6. EMITTER

STYLE 8:

PIN 1. Vbus

2. D(in)

3. D(in)+

4. D(out)+

5. D(out)

6. GND

GENERIC

MARKING DIAGRAM*

STYLE 9:

PIN 1. LOW VOLTAGE GATE

2. DRAIN

3. SOURCE

4. DRAIN

5. DRAIN

6. HIGH VOLTAGE GATE

STYLE 10:

PIN 1. D(OUT)+

2. GND

3. D(OUT)−

4. D(IN)−

5. VBUS

6. D(IN)+

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

STYLE 11:

PIN 1. SOURCE 1

2. DRAIN 2

3. DRAIN 2

4. SOURCE 2

5. GATE 1

6. DRAIN 1/GATE 2

STYLE 12:

PIN 1. I/O

2. GROUND

3. I/O

4. I/O

5. VCC

6. I/O

*This information is generic. Please refer to device data sheet

for actual part marking. Pb−Free indicator, “G” or microdot “

G”, may or may not be present.

XXXAYWG

STANDARDIC

XXX = Specific Device Code

M = Date Code

G= Pb−Free Package

DIM

MIN NOM MAX

MILLIMETERS

0.90 1.00 1.10

A1 0.01 0.06 0.10

b0.25 0.38 0.50

c0.10 0.18 0.26

D2.90 3.00 3.10

E2.50 2.75 3.00

e0.85 0.95 1.05

L0.20 0.40 0.60

0.25 BSC

−

0°10°

STYLE 13:

PIN 1. GATE 1

2. SOURCE 2

3. GATE 2

4. DRAIN 2

5. SOURCE 1

6. DRAIN 1

STYLE 14:

PIN 1. ANODE

2. SOURCE

3. GATE

4. CATHODE/DRAIN

5. CATHODE/DRAIN

6. CATHODE/DRAIN

STYLE 15:

PIN 1. ANODE

2. SOURCE

3. GATE

4. DRAIN

5. N/C

6. CATHODE

1.30 1.50 1.70

RECOMMENDED

NOTE 5

SEATING

PLANE

GAUGE

PLANE

DETAIL Z

0.60

3.20 0.95

0.95

PITCH

DIMENSIONS: MILLIMETERS

STYLE 16:

PIN 1. ANODE/CATHODE

2. BASE

3. EMITTER

4. COLLECTOR

5. ANODE

6. CATHODE

STYLE 17:

PIN 1. EMITTER

2. BASE

3. ANODE/CATHODE

4. ANODE

5. CATHODE

6. COLLECTOR

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

98ASB14888C

DOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1

TSOP−6

SOIC−7

CASE 751U−01

ISSUE E

DATE 20 OCT 2009

SEATING

PLANE

X 45 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B ARE DATUMS AND T

IS A DATUM SURFACE.

4. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

SCALE 1:1

DIM

MIN MAX MIN MAX

INCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B3.80 4.00 0.150 0.157

C1.35 1.75 0.053 0.069

D0.33 0.51 0.013 0.020

G1.27 BSC 0.050 BSC

H0.10 0.25 0.004 0.010

J0.19 0.25 0.007 0.010

K0.40 1.27 0.016 0.050

M0 8 0 8

N0.25 0.50 0.010 0.020

S5.80 6.20 0.228 0.244

−A−

−B−

0.25 (0.010)

−T−

0.25 (0.010) TSAS

XXX = Specific Device Code

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb−Free Package

GENERIC

MARKING DIAGRAM

7 PL

____

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “ G”,

may or may not be present.

XXXXX

ALYWX

STYLES ON PAGE 2

1.52

0.060

7.0

0.275

0.6

0.024

1.270

0.050

4.0

0.155

ǒmm

inchesǓ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

98AON12199D

DOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 2

7−LEAD SOIC

SOIC−7

CASE 751U−01

ISSUE E

DATE 20 OCT 2009

STYLE 4:

PIN 1. ANODE

2. ANODE

3. ANODE

4. ANODE

5. ANODE

6. ANODE

7. NOT USED

8. COMMON CATHODE

STYLE 1:

PIN 1. EMITTER

2. COLLECTOR

3. COLLECTOR

4. EMITTER

5. EMITTER

7. NOT USED

8. EMITTER

STYLE 2:

PIN 1. COLLECTOR, DIE, #1

2. COLLECTOR, #1

3. COLLECTOR, #2

4. COLLECTOR, #2

5. BASE, #2

6. EMITTER, #2

7. NOT USED

8. EMITTER, #1

STYLE 3:

PIN 1. DRAIN, DIE #1

2. DRAIN, #1

3. DRAIN, #2

4. DRAIN, #2

5. GATE, #2

6. SOURCE, #2

7. NOT USED

8. SOURCE, #1

STYLE 6:

PIN 1. SOURCE

2. DRAIN

3. DRAIN

4. SOURCE

5. SOURCE

7. NOT USED

8. SOURCE

STYLE 5:

PIN 1. DRAIN

2. DRAIN

3. DRAIN

4. DRAIN

7. NOT USED

8. SOURCE

STYLE 7:

PIN 1. INPUT

2. EXTERNAL BYPASS

3. THIRD STAGE SOURCE

4. GROUND

5. DRAIN

6. GATE 3

7. NOT USED

8. FIRST STAGE Vd

STYLE 8:

PIN 1. COLLECTOR (DIE 1)

2. BASE (DIE 1)

3. BASE (DIE 2)

4. COLLECTOR (DIE 2)

5. COLLECTOR (DIE 2)

6. EMITTER (DIE 2)

7. NOT USED

8. COLLECTOR (DIE 1)

STYLE 9:

PIN 1. EMITTER (COMMON)

2. COLLECTOR (DIE 1)

3. COLLECTOR (DIE 2)

4. EMITTER (COMMON)

5. EMITTER (COMMON)

6. BASE (DIE 2)

7. NOT USED

8. EMITTER (COMMON)

STYLE 10:

PIN 1. GROUND

2. BIAS 1

3. OUTPUT

4. GROUND

5. GROUND

6. BIAS 2

7. NOT USED

8. GROUND

STYLE 11:

PIN 1. SOURCE (DIE 1)

2. GATE (DIE 1)

3. SOURCE (DIE 2)

4. GATE (DIE 2)

5. DRAIN (DIE 2)

6. DRAIN (DIE 2)

7. NOT USED

8. DRAIN (DIE 1)

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

98AON12199D

DOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 2 OF 2

7−LEAD SOIC

www.onsemi.com

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such

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