100344
100344 Low Power 8-Bit Latch with Cut-Off Drivers
Literature Number: SNOS132
100344
Low Power 8-Bit Latch with Cut-Off Drivers
General Description
The 100344 contains eight D-type latches, individual inputs
(D
n
), outputs (Q
n
), a common enable pin (E), latch enable
(LE), and output enable pin (OEN). A Q output follows its D
input when both E and LE are LOW. When either E or LE (or
both) are HIGH, a latch stores the last valid data present on
its D input prior to E or LE going HIGH.
A HIGH on OEN holds the outputs in a cut-off state. The
cut-off state is designed to be more negative than a normal
ECL LOW level. This allows the output emitter-followers to
turn off when the termination supply is −2.0V, presenting a
high impedance to the data bus. This high impedance re-
duces termination power and prevents loss of low state
noise margin when several loads share the bus.
The 100344 outputs are designed to drive a doubly termi-
nated 50Ωtransmission line (25Ωload impedance). All in-
puts have 50 kΩpull-down resistors.
Features
nCut-off drivers
nDrives 25Ωload
nLow power operation
n2000V ESD protection
nVoltage compensated operating range =−4.2V to −5.7V
nAvailable to MIL-STD-883
Logic Symbol Pin Names Description
D
0
–D
7
Data Inputs
EEnable Input
LE Latch Enable Input
OEN Output Enable Input
Q
0
–Q
7
Data Outputs
Connection Diagrams
DS100317-4
24-Pin DIP
DS100317-1
24-Pin Quad Cerpak
DS100317-2
August 1998
100344 Low Power 8-Bit Latch with Cut-Off Drivers
© 1998 National Semiconductor Corporation DS100317 www.national.com
Logic Diagram
Truth Table
Inputs Outputs
D
n
E LE OEN Q
n
LLL L L
HLL L H
X H X L Latched (Note 1)
X X H L Latched (Note 1)
X X X H Cutoff
H=HIGH Voltage level
L=LOW Voltage level
Cutoff =lower-than-LOW state
X=Don’t Care
Note 1: Retains data present before either LE or E go HIGH.
DS100317-5
www.national.com 2
Absolute Maximum Ratings (Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Above which the useful life may be impaired
Storage Temperature (T
STG
) −65˚C to +150˚C
Maximum Junction Temperature (T
J
)
Ceramic +175˚C
V
EE
Pin Potential to Ground Pin −7.0V to +0.5V
Input Voltage (DC) V
EE
to +0.5V
Output Current (DC Output HIGH) −100 mA
ESD (Note 3) ≥2000V
Recommended Operating
Conditions
Case Temperature (T
C
)
Military −55˚C to +125˚C
Supply Voltage (V
EE
) −5.7V to −4.2V
Note 2: Absolute maximum ratings are those values beyond which the de-
vice may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 3: ESD testing conforms to MIL-STD-883, Method 3015.
Military Version
DC Electrical Characteristics
V
EE
=−4.2V to −5.7V, V
CC
=V
CCA
=GND, T
C
=−55˚C to +125˚C
Symbol Parameter Min Max Units T
C
Conditions Notes
V
OH
Output HIGH Voltage −1025 −870 mV 0˚C to
(Notes 4, 5,
6)
+125˚C
−1085 −870 mV −55˚C V
IN
=V
IH
(Max) Loading with
V
OL
Output LOW Voltage −1830 −1620 mV 0˚C to or V
IL
(Min) 25Ωto −2.0V
+125˚C
−1830 −1555 mV −55˚C
V
OHC
Output HIGH Voltage −1035 mV 0˚C to
(Notes 4, 5,
6)
+125˚C
−1085 mV −55˚C V
IN
=V
IH
(Min) Loading with
V
OLC
Output LOW Voltage −1610 mV 0˚C to or V
IL
(Max) 25Ωto −2.0V
+125˚C
−1555 mV −55˚C
V
OLZ
Cutoff LOW Voltage −1950 0˚C to V
IN
=V
IH
(Min) (Notes 4, 5,
6)
mV +125˚C or V
IL
(Max) OEN =HIGH
−1850 −55˚C
V
IH
Input HIGH Voltage −1165 −870 mV −55˚C to Guaranteed HIGH Signal (Notes 4, 5,
6, 7)
+125˚C for All Inputs
V
IL
Input LOW Voltage −1830 −1475 mV −55˚C to Guaranteed LOW Signal (Notes 4, 5,
6, 7)
+125˚C for All Inputs
I
IL
Input LOW Current 0.50 µA −55˚C to V
EE
=−4.2V (Notes 4, 5,
6, 7)
+125˚C V
IN
=V
IL
(Min)
I
IH
Input HIGH Current 240 µA 0˚C to V
EE
=−5.7V (Notes 4, 5,
6)
+125˚C V
IN
=V
IH
(Max)
340 µA −55˚C
I
EE
Power Supply Current −55˚C to Inputs Open (Notes 4, 5,
6)
−195 −73 mA +125˚C V
EE
=−4.2V to −4.8V
−205 −73 V
EE
=−4.2V to −5.7V
Note 4: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case
condition at cold temperatures.
Note 5: Screen tested 100%on each device at −55˚C, +25˚C, and +125˚C, Subgroups 1, 2, 3, 7, and 8.
Note 6: Sample tested (Method 5005, Table I) on each manufactured lot at −55˚C, +25˚C, and +125˚C, Subgroups A1, 2, 3, 7, and 8.
Note 7: Guaranteed by applying specified input condition and testing VOH/VOL.
www.national.com3
AC Electrical Characteristics
V
EE
=−4.2V to −5.7V, V
CC
=V
CCA
=GND
Symbol Parameter T
C
=−55˚C T
C
=+25˚C T
C
=+125˚C Units Conditions Notes
Min Max Min Max Min Max
t
PLH
Propagation Delay 0.50 2.60 0.70 2.60 0.70 3.10 ns
Figures 1, 2
(Notes 8, 9,
10, 12)
t
PHL
D
n
to Output
t
PLH
Propagation Delay 0.80 3.30 1.00 3.30 1.10 3.80 ns
Figures 1, 4
(Notes 8, 9,
10, 12)
t
PHL
LE, E to Output
t
PZH
Propagation Delay 1.00 4.60 1.10 4.20 1.20 4.40 ns
Figures 1, 2
(Notes 8, 9,
10, 12)
t
PHZ
OEN to Output 0.70 3.00 0.70 2.80 0.70 3.20
t
TLH
Transition Time 0.40 2.50 0.40 2.40 0.40 2.70 ns
Figures 1, 3
(Note 11)
t
THL
20%to 80%,80
%to
20%
t
s
Setup Time (Note 11)
D
0
–D
7
1.50 1.50 1.70 ns
Figures 1, 3
t
h
Hold Time (Note 11)
D
0
–D
7
0.60 0.60 0.60 ns
Figures 1, 3
t
pw
(H) Pulse Width HIGH (Note 11)
LE, E 2.40 2.40 2.40 ns
Figures 1, 3
Note 8: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures.
Note 9: Screen tested 100%on each device at +25˚C temperature only, Subgroup A9.
Note 10: Sample tested (Method 5005, Table I) on each manufactured lot at +25˚C, Subgroup A9, and at +125˚C and −55˚C temperatures, SubgroupsA10 andA11.
Note 11: Not tested at +25˚C, +125˚C, and −55˚C temperature (design characterization data).
Note 12: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching.
Test Circuitry
DS100317-6
Notes:
VCC,V
CCA =+2V, VEE =−2.5V
L1 and L2 =equal length 50Ωimpedance lines
RT=50Ωterminator internal to scope
Decoupling 0.1 µF from GND to VCC and VEE
All unused outputs are loaded with 25Ωto GND
CL=Fixture and stray capacitance ≤3pF
FIGURE 1. AC Test Circuit
www.national.com 4
Switching Waveforms
DS100317-7
FIGURE 2. Propagation Delay and Cutoff Times
DS100317-8
FIGURE 3. Setup, Hold and Pulse Width Times
DS100317-9
FIGURE 4. Propagation Delay LE, E to Q
www.national.com5
6
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Ceramic Dual-In-Line Package (0.400" Wide) (D)
NS Package Number J24E
24-Lead Quad Cerpak (F)
NS Package Number W24B
www.national.com7
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100344 Low Power 8-Bit Latch with Cut-Off Drivers
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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