MOS INTEGRATED CIRCUIT
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
V850E/MS1TM
32-/16-BIT SINGLE-CHIP MICROCONTROLLERS
Document No. U13995EJ2V0DS00 (2nd edition)
Date Published November 2000 N CP(K) The mark shows major revised points.
Printed in Japan
DATA SHEET
1999©
The
µ
PD703101-33 and
µ
PD703102-33 are members of the V850 FamilyTM of 32-bit single-chip microcontrollers
designed for real-time control operations. These microcontrollers provide on-chip features, including a 32-bit CPU
core, ROM, RAM, interrupt controller, real-time pulse unit, serial interface, A/D converter, and DMA controller.
The
µ
PD703100-33 and
µ
PD703100-40 are ROMless versions of the
µ
PD703101-33 and
µ
PD703102-33
products.
The
µ
PD703100A-33,
µ
PD703100A-40,
µ
PD703101A-33, and
µ
PD703102A-33 are also available as products
having a 3.3 V power supply for external pins.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing. V850E/MS1 User’s Manual Hardware: U12688E
V850E/MS1 User’s Manual Architecture: U12197E
FEATURES
• Number of instructions: 81
• Minimum instruction execution time 25 ns (@ 40 MHz operation) ·····
µ
PD703100-40
30 ns (@ 33 MHz operation) ·····
µ
PD703100-33, 703101-33, 703102-33
• General-purpose registers 32 bits × 32
• Instruction set optimized for control applications
• Internal memory ROM: None (
µ
PD703100-33, 703100-40),
96 KB (
µ
PD703101-33),
128 KB (
µ
PD703102-33)
RAM : 4 KB
• Advanced on-chip interrupt controller
• Real-time pulse unit suitable for control operations
• Powerful serial interface (on-chip dedicated baud rate generator)
• On-chip clock generator
• 10-bit resolution A/D converter: 8 channels
• DMA controller: 4 channels
• Power saving functions
APPLICATIONS
• Office automation equipment: printers, facsimile machines, PPCs, etc.
• Multimedia equipment: digital still cameras, video printers, etc.
• Consumer equipment: single-lens reflex cameras, etc.
• Industrial equipment: motor controllers, NC machine tools, etc.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Data Sheet U13995EJ2V0DS00
2
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
ORDERING INFORMATION
Part Number Package Maximum Operating
Frequency Internal ROM
µ
PD703100GJ-33-UEN 144-pin plast i c LQFP (fine pi tch) (20 × 20) 33 MHz None
µ
PD703100GJ-40-UEN 144-pin plast i c LQFP (fine pi tch) (20 × 20) 40 MHz None
µ
PD703101GJ-33-xxx-UEN 144-pin plasti c LQFP (fine pi tch) (20 × 20) 33 MHz 96 KB
µ
PD703102GJ-33-xxx-UEN 144-pin plasti c LQFP (fine pi tch) (20 × 20) 33 MHz 128 KB
Remark xxx indicates ROM code suffix.
PIN CONFIGURATION (TOP VIEW)
144-pin plastic LQFP (fine pitch) (20 ×
××
× 20)
•
µ
PD703100GJ-33-UEN •
µ
PD703101GJ-33-xxx-UEN
•
µ
PD703100GJ-40-UEN •
µ
PD703102GJ-33-xxx-UEN
INTP103/DMARQ3/ P07 1
INTP102/DMARQ2/ P06 2
INTP101/DMARQ1/ P05 3
INTP100/DMARQ0/ P04 4
TI10/P03 5
TCLR10/P02 6
TO101/P01 7
TO100/P00 8
V
SS
9
INTP113/DMAAK3/ P17 10
INTP112/DMAAK2/ P16 11
INTP111/DMAAK1/ P15 12
INTP110/DMAAK0/ P14 13
TI11/P13 14
TCLR11/P12 15
TO111/P11 16
TO110/P10 17
INTP123/TC3/P107 18
INTP122/TC2/P106 19
INTP121/TC1/P105 20
INTP120/TC0/P104 21
TI12/P103 22
TCLR12/P102 23
TO121/P101 24
TO120/P100 25
ANI7/ P77 26
ANI6/ P76 27
ANI5/ P75 28
ANI4/ P74 29
ANI3/ P73 30
ANI2/ P72 31
ANI1/ P71 32
ANI0/ P70 33
AV
DD
34
AV
SS
35
AV
REF
36
A16/P60108 A17/P61107 A18/P62106 A19/P63105 A20/P64104 A21/P65103 A22/P66102 A23/P67101 HV
DD
100 CS0/RAS0/ P8099 CS1/RAS1/ P8198 CS2/RAS2/ P8297 CS3/RAS3/ P8396 CS4/ RAS4/ IOWR/ P8495 CS5/ RAS5/ IORD/ P8594 CS6/RAS6/ P8693 CS7/RAS7/ P8792 LCAS/ LWR/ P9091 UCAS/ UWR/ P9190 RD/ P9289 WE/ P9388 BCYST/ P9487 OE/ P9586 HLDAK/ P9685 HLDRQ/ P9784 V
SS
83 REFRQ/ PX582 WAIT/ PX681 CLKOUT/ PX780 TO150/P12079 TO151/P12178 TCLR15/P12277 TI15/P12376 INTP150/P12475 INTP151/P12574 INTP152/P12673
V
DD
144 D0/ P40143 D1/ P41142 D2/ P42141 D3/ P43140 D4/ P44139 D5/ P45138 D6/ P46137 D7/ P47136 V
SS
135 D8/ P50134 D9/ P51133 D10/ P52132 D11/P53131 D12/P54130 D13/ P55129 D14/P56128 D15/P57127 HV
DD
126 A0/ PA0125 A1/ PA1124 A2/ PA2123 A3/ PA3122 A4/ PA4121 A5/ PA5120 A6/ PA6119 A7/ PA7118 V
SS
117 A8/ PB0116 A9/ PB1115 A10/PB2114 A11/ PB3113 A12/PB4112 A13/PB5111 A14/PB6110 A15/PB7109
NMI/P20 37
P21 38
TXD0/SO0/P22 39
RXD0/SI0/P23 40
SCK0/ P24 41
TXD1/SO1/P25 42
RXD1/SI1/P26 43
SCK1/ P27 44
V
DD
45
INTP133/SCK2/P37 46
INTP132/SI2/P36 47
INTP131/SO2/P35 48
INTP130/P34 49
TI13/P33 50
TCLR13/P32 51
TO131/P31 52
TO130/P30 53
INTP143/SCK3/P117 54
INTP142/SI3/P116 55
INTP141/SO3/P115 56
INTP140/P114 57
TI14/P113 58
TCLR14/P112 59
TO141/P111 60
TO140/P110 61
CV
DD
62
X2 63
X1 64
CV
SS
65
CKSEL 66
MODE0 67
MODE1 68
MODE2 69
MODE3 70
RESET 71
INTP153/ADTRG/P127 72
Data Sheet U13995EJ2V0DS00 3
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
PIN NAMES
A0 to A23: Address Bus P50 to P57: Port 5
ADTRG: AD Trigger Input P60 to P67: Port 6
ANI0 to ANI7: Analog Input P70 to P77: Port 7
AVDD: Analog Power Supply P80 to P87: Port 8
AVREF: Analog Reference Voltage P90 to P97: Port 9
AVSS: Analog Ground P100 to P107: Port 10
BCYST: Bus Cycle Start Timing P110 to P117: Port 11
CKSEL
: Clock Generator Operating Mode Select
P120 to P127: Port 12
CLKOUT: Clock Output PA0 to PA7: Port A
CS0 to CS7: Chip Select PB0 to PB7: Port B
CVDD: Clock Generator Power Supply PX5 to PX7: Port X
CVSS: Clock Generator Ground RAS0 to RAS7: Row Address Strobe
D0 to D15: Data Bus RD: Read
DMAAK0 to DMAAK3
: DMA Acknowledge REFRQ: Refresh Request
DMARQ0 to DMARQ3
: DMA Request RESET: Reset
HLDAK: Hold Acknowledge RXD0, RXD1: Receive Data
HLDRQ: Hold Request SCK0 to SCK3: Serial Clock
HVDD: Power Supply for External Pins SI0 to SI3: Serial Input
INTP100 to I N TP103, : Interrupt Request from Peripherals
SO0 to SO3: Serial Output
INTP110 to I N TP113,
TC0 to TC3: Terminal Count Signal
INTP120 to I N TP123,
TCLR10 to TCLR15: Timer Clear
INTP130 to I N TP133,
TI10 to TI15: Timer Input
INTP140 to I N TP143,
TO100, TO101, : Timer Output
INTP150 to I N TP153
TO110, TO111,
IORD: I/O Read Strobe TO120, TO121,
IOWR: I/O Write Strobe TO130, TO131,
LCAS: Lower Column Address Strobe TO140, TO141,
LWR: Lower Write Strobe TO150, TO151
MODE0 to MODE3: Mode TXD0, TXD1: Transmit Data
NMI: Non-Maskable Interrupt Request UCAS: Upper Column Address Strobe
OE: Output Enable UWR: Upper Write Strobe
P00 to P07: Port 0 VDD: Power Supply for Internal Unit
P10 to P17: Port 1 VSS: Ground
P20 to P27: Port 2 WAIT: Wait
P30 to P37: Port 3 WE: Write Enable
P40 to P47: Port 4 X1, X2: Crystal
Data Sheet U13995EJ2V0DS00
4
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
INTERNAL BLOCK DIAGRAM
Note
µ
PD703100-33, 703100-40: None
µ
PD703101-33: 96 KB (mask ROM)
µ
PD703102-33: 128 KB (mask ROM)
TCLR10 to TCLR15
TI10 to TI15
TO100, TO101,
TO110, TO111,
TO120, TO121,
TO130, TO131,
TO140, TO141,
TO150, TO151
INTP100 to INTP103,
INTP110 to INTP113,
INTP120 to INTP123,
INTP130 to INTP133,
INTP140 to INTP143,
INTP150 to INTP153
NMI
INTC
RPU
UART0/CSI0
SIO
SCK0
SI0/RXD0
SO0/TXD0
BRG0
UART1/CSI1
SCK1
SI1/RXD1
SO1/TXD1
BRG1
CSI2
SCK2
SI2
SO2
BRG2
CSI3
SCK3
SI3
SO3
AV
REF
ADC
AV
SS
AV
DD
ADTRG
ANI0 to ANI7
Port
PX5 to PX7
PB0 to PB7
PA0 to PA7
P120 to P127
P110 to P117
P100 to P107
P90 to P97
P80 to P87
P70 to P77
P60 to P67
P50 to P57
P40 to P47
P30 to P37
P21 to P27
P20
P10 to P17
P00 to P07
HV
DD
Note
ROM
4 KB
RAM
Instruction queue
PC
System registers
General-purpose
registers
(32 bits × 32)
Multiplier
(32 × 32 → 64)
Barrel
shifter
ALU
DRAMC
Page ROM
controller
DMAC
BCUCPU
TC0 to TC3
LWR/LCAS
DMAAK0 to DMARQ3
DMARQ0 to DMARQ3
D0 to D15
A0 to A23
WAIT
CS0 to CS7/RAS0 to RAS7
UWR/UCAS
OE
RD
WE
BCYST
REFRQ
IORD
IOWR
HLDAK
HLDRQ
CG
CKSEL
CLKOUT
X1
X2
CV
DD
CV
SS
System
controller RESET
V
DD
V
SS
MODE0 to MODE3
Data Sheet U13995EJ2V0DS00 5
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
CONTENTS
1. DIFFERENCES AMONG PRODUCTS........................................................................................... 6
2. PIN FUNCTIONS ............................................................................................................................. 7
2.1 Port Pins ................................................................................................................................. 7
2.2 Non-Port Pins......................................................................................................................... 10
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins..................................... 14
3. ELECTRICAL SPECIFICATIONS................................................................................................... 17
4. PACKAGE DRAWING..................................................................................................................... 74
5. RECOMMENDED SOLDERING CONDITIONS............................................................................. 75
Data Sheet U13995EJ2V0DS00
6
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
1. DIFFERENCES AMONG PRODUCTS
Product Nam e
µ
PD703100
µ
PD703101
µ
PD703102
µ
PD70F3102
Item -33 -40 A-33 A-40 -33 A-33 -33 A-33 -33 A-33
Internal ROM None 96 KB
(mask ROM) 128 KB
(mask ROM) 128 KB
(flash memory)
Maximum operating
frequency
33 MHz 40 MHz 33 MHz 40 MHz 33 MHz
HVDD 4.5 to 5.5 V 3.0 to 3.6 V 4.5 to
5.5 V 3.0 to
3.6 V 4.5 t o
5.5 V 3.0 t o
3.6 V 4.5 t o
5.5 V 3.0 t o
3.6 V
Operation mode
Single-chip
mode 0, 1 None Provided
Flash memory
programming
mode
None Provided
Flash memory
programming pin None Provided (V PP)
Electrical
specifications Power consumptions di ffer (refer t o the data sheet of each product ).
Package 144LQFP 144LQFP
157FBGA
144LQFP 144LQFP
157FBGA 144LQFP 144LQFP
157FBGA 144LQFP 144LQFP
157FBGA
Others Noise tolerance and nois e radiat ion will differ due to the differences in circuit scale and mask lay out.
Remark 144LQFP: 144-pin plastic LQFP (fine pitch) (20 × 20)
157FBGA: 157-pin plastic FBGA (14 × 14)
Data Sheet U13995EJ2V0DS00 7
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
2. PIN FUNCTIONS
2.1 Port Pins (1/3)
Pin Name I/O Function Alternat e Function
P00 TO100
P01 TO101
P02 TCLR10
P03 TI10
P04 INTP100/DMARQ0
P05 INTP101/DMARQ1
P06 INTP102/DMARQ2
P07
I/O Port 0
8-bit I/ O port
Input/output can be s pecified i n 1-bi t units
INTP103/DMARQ3
P10 TO110
P11 TO111
P12 TCLR11
P13 TI11
P14 INTP110/DMAAK0
P15 INTP111/DMAAK1
P16 INTP112/DMAAK2
P17
I/O Port 1
8-bit I/ O port
Input/output can be s pecified i n 1-bi t units
INTP113/DMAAK3
P20 Input NMI
P21 –
P22 TXD0/SO0
P23 RXD0/SI0
P24 SCK0
P25 TXD1/SO1
P26 RXD1/SI1
P27
I/O
Port 2
P20 is an i nput onl y port.
When a valid edge is input, this pin operates as NM I i nput. Also, bit 0
of the P2 regi ster indicates t he NM I input status.
P21 to P27 are 7-bi t I/O port .
Input/output can be s pecified i n 1-bi t units
SCK1
P30 TO130
P31 TO131
P32 TCLR13
P33 TI13
P34 INTP130
P35 INTP131/SO2
P36 INTP132/SI2
P37
I/O Port 3
8-bit I/ O port
Input/output can be s pecified i n 1-bi t units
INTP133/SCK2
P40 to P47 I/O Port 4
8-bit I/ O port
Input/output can be s pecified i n 1-bi t units
D0 to D7
Data Sheet U13995EJ2V0DS00
8
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(2/3)
Pin Name I/O Function Alternat e Function
P50 to P57 I/O Port 5
8-bit I/ O port
Input/output can be s pecified i n 1-bi t units
D8 to D15
P60 to P67 I/O Port 6
8-bit I/ O port
Input/output can be s pecified i n 1-bi t units
A16 to A23
P70 to P77 Input Port 7
8-bit input onl y port ANI0 to ANI7
P80 CS0/RAS0
P81 CS1/RAS1
P82 CS2/RAS2
P83 CS3/RAS3
P84 CS4/RAS4/IOWR
P85 CS5/RAS5/IORD
P86 CS6/RAS6
P87
I/O Port 8
8-bit I/ O port
Input/output can be s pecified i n 1-bi t units
CS7/RAS7
P90 LCAS/LWR
P91 UCAS/UWR
P92 RD
P93 WE
P94 BCYST
P95 OE
P96 HLDAK
P97
I/O Port 9
8-bit I/ O port
Input/output can be s pecified i n 1-bi t units
HLDRQ
P100 TO120
P101 TO121
P102 TCLR12
P103 TI12
P104 INTP120/TC0
P105 INTP121/TC1
P106 INTP122/TC2
P107
I/O Port 10
8-bit I/ O port
Input/output can be s pecified i n 1-bi t units
INTP123/TC3
P110 TO140
P111 TO141
P112 TCLR14
P113 TI14
P114 INTP140
P115 INTP141/SO3
P116 INTP142/SI3
P117
I/O Port 11
8-bit I/ O port
Input/output can be s pecified i n 1-bi t units
INTP143/SCK3
Data Sheet U13995EJ2V0DS00 9
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(3/3)
Pin Name I/O Function Alternat e Function
P120 TO150
P121 TO151
P122 TCLR15
P123 TI15
P124 INTP150
P125 INTP151
P126 INTP152
P127
I/O Port 12
8-bit I/ O port
Input/output can be s pecified i n 1-bi t units
INTP153/ADTRG
PA0 A0
PA1 A1
PA2 A2
PA3 A3
PA4 A4
PA5 A5
PA6 A6
PA7
I/O Port A
8-bit I/ O port
Input/output can be s pecified i n 1-bi t units
A7
PB0 A8
PB1 A9
PB2 A10
PB3 A11
PB4 A12
PB5 A13
PB6 A14
PB7
I/O Port B
8-bit I/ O port
Input/output can be s pecified i n 1-bi t units
A15
PX5 REFRQ
PX6 WAIT
PX7
I/O Port X
3-bit I/ O port
Input/output can be s pecified i n 1-bi t units CLKOUT
Data Sheet U13995EJ2V0DS00
10
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
2.2 Non-Port Pins (1/4)
Pin Name I/O Function Alternat e Function
TO100 P00
TO101 P01
TO110 P10
TO111 P11
TO120 P100
TO121 P101
TO130 P30
TO131 P31
TO140 P110
TO141 P111
TO150 P120
TO151
Output Pulse s i gnal output for t i m ers 10 to 15
P121
TCLR10 P02
TCLR11 P12
TCLR12 P102
TCLR13 P32
TCLR14 P112
TCLR15
Input External clear signal i nput for tim ers 10 to 15
P122
TI10 P03
TI11 P13
TI12 P103
TI13 P33
TI14 P113
TI15
Input External count cl ock input for timers 10 to 15
P123
INTP100 P04/DMARQ0
INTP101 P05/DMARQ1
INTP102 P06/DMARQ2
INTP103
Input External m askable interrupt request i nput, shared as external c apt ure
trigger input for timer 10
P07/DMARQ3
INTP110 P14/DMAAK0
INTP111 P15/DMAAK1
INTP112 P16/DMAAK2
INTP113
Input External m askable interrupt request i nput, shared as external c apt ure
trigger input for timer 11
P17/DMAAK3
INTP120 P104/TC0
INTP121 P105/TC1
INTP122 P106/TC2
INTP123
Input External m askable interrupt request i nput, shared as external c apt ure
trigger input for timer 12
P107/TC3
Data Sheet U13995EJ2V0DS00 11
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(2/4)
Pin Name I/O Function Alternat e Function
INTP130 P34
INTP131 P35/SO2
INTP132 P36/SI2
INTP133
Input External m askable interrupt request i nput, shared as external c apt ure
trigger input for timer 13
P37/SCK2
INTP140 P114
INTP141 P115/SO3
INTP142 P116/SI3
INTP143
Input External m askable interrupt request i nput, shared as external c apt ure
trigger input for timer 14
P117/SCK3
INTP150 P124
INTP151 P125
INTP152 P126
INTP153
Input External m askable interrupt request i nput, shared as external c apt ure
trigger input for timer 15
P127/ADTRG
SO0 P22/TXD0
SO1 P25/TXD1
SO2 P35/INTP131
SO3
Output Serial transmit data output (3-wire) for CSI0 t o CS I3
P115/INTP141
SI0 P23/RXD0
SI1 P26/RXD1
SI2 P36/INTP132
SI3
Input Serial receive dat a i nput (3-wire) for CS I0 to CSI3
P116/INTP142
SCK0 P24
SCK1 P27
SCK2 P37/INTP133
SCK3
I/O Serial clock I/O (3-wire) for CSI0 to CSI3
P117/INTP143
TXD0 P22/SO0
TXD1
Output Serial transmit data output f or UA RT0 and UART1
P25/SO1
RXD0 P23/SI0
RXD1
Input Serial rec ei v e data input f or UA RT0 and UART1
P26/SI1
D0 to D7 P40 to P47
D8 to D15
I/O 16-bi t data bus f or external mem ory
P50 to P57
A0 to A7 PA0 to PA7
A8 to A15 PB0 to PB7
A16 to A23
Output 24-bit address bus for ex ternal memory
P60 to P67
LWR Output Lower byte writ e-enabl e signal output for ext ernal data bus P90/LCAS
UWR Output Higher byte wri te-enable signal out put for ext ernal data bus P91/UCA S
RD Output Read strobe s i gnal out put for ext ernal data bus P92
WE Output Write enabl e s i gnal output for DRA M P93
OE Output Output enable s i gnal out put for DRAM P95
Data Sheet U13995EJ2V0DS00
12
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(3/4)
Pin Name I/O Function Alternat e Function
LCAS Output Column address strobe si gnal out put for DRAM’ s lower data P90/LWR
UCAS Output Column address strobe si gnal output for DRAM’s higher dat a P91/UWR
RAS0 to RAS3 P80/CS0 to P83/CS3
RAS4 P84/CS4/IOWR
RAS5 P85/CS5/IORD
RAS6 P86/CS6
RAS7
Output Low address s t robe signal output for DRAM
P87/CS7
BCYST Output Strobe si gnal output indicating start of bus cycle P94
CS0 to CS 3 P80/RAS0 to
P83/RAS3
CS4 P84/RAS4/IOWR
CS5 P85/RAS5/IORD
CS6 P86/RAS6
CS7
Output Chip selec t signal out put
P87/RAS7
WAIT Input Control si gnal i nput for insert i ng wai t s in bus cycle PX6
REFRQ Output Refresh reques t signal output for DRAM PX5
IOWR Output DMA write strobe signal out put P84/RAS 4/CS4
IORD Output DMA read st robe signal output P85/RAS 5/CS5
DMARQ0 to
DMARQ3 Input DMA request si gnal i nput P04/INTP 100 to
P07/INTP103
DMAAK0 to
DMAAK3 Output DMA acknowledge signal output P14/INTP 110 to
P17/INTP113
TC0 to TC3 Output DMA end (term i nal count) si gnal out put P104/INTP 120 to
P107/INTP123
HLDAK Output Bus hold acknowledge out put P96
HLDRQ Input Bus hold reques t input P97
ANI0 to A NI7 Input Analog input to A/D c onverter P70 to P77
NMI Input Non-mask abl e i nt errupt request i nput P20
CLKOUT Output System clock output PX7
CKSEL Input Input for specif ying clock generator’s operation mode –
MODE0 to
MODE3 Input Specif y operation modes –
RESET Input System reset input –
X1 Input –
X2 –
Oscillator connection f or system clock. Input is via X1 when us i ng an
external clock. –
ADTRG Input A/D converter external t ri gger i nput P127/INTP 153
AVREF Input Reference v ol tage input for A/D conv erter –
AVDD – Posit i ve power supply for A/D c onv erter –
AVSS – Ground potential for A/D c onverter –
Data Sheet U13995EJ2V0DS00 13
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(4/4)
Pin Name I/O Function Alternat e Function
CVDD – Pos i t i ve power supply for dedicated clock generat or –
CVSS – Ground potent i al for dedicated clock generat or –
VDD – Posit i ve power supply (power supply for i nternal units) –
HVDD – Pos i t i ve power supply (power supply for external pins) –
VSS – Ground potential –
Data Sheet U13995EJ2V0DS00
14
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-1 shows the I/O circuit type of each pin and recommended connection of unused pins. Figure 2-1 shows
the various circuit types using partially abridged diagrams.
When connecting to VDD or VSS via a resistor, a resistance value in the range of 1 to 10 kΩ is recommended.
Table 2-1. I/O Circuit Type of Each Pin and Recommended Connection of Unused Pins (1/2)
Pin I/O Circuit Ty pe Recommended Connect i on of Unused Pins
P00/TO100, P 01/ TO101 5
P02/TCLR10, P 03/ TI10
P04/INTP100/DMARQ0 to
P07/INTP103/DMARQ3
5-K
P10/TO110, P 11/ TO111 5
P12/TCLR11, P 13/ TI11
P14/INTP110/DMAAK0 to
P17/INTP113/DMAAK3
5-K
Input: Independently connect to HVDD or VSS via a resistor
Output: Leave open
P20/NMI 2 Connect directly to VSS
P21
P22/TXD0/SO0
5
P23/RXD0/SI0
P24/SCK0
5-K
P25/TXD1/SO1 5
P26/RXD1/SI1
P27/SCK1
5-K
P30/TO130, P 31/ TO131 5
P32/TCLR13, P 33/ TI13
P34/INTP130
P35/INTP131/SO2
P36/INTP132/SI2
P37/INTP133/SCK2
5-K
P40/D0 t o P 47/D7
P50/D8 to P57/D15
P60/A16 to P67/A23
5
Input: Independently connect to HVDD or VSS via a resistor
Output: Leave open
P70/ANI 0 to P77/A NI 7 9 Connect direc tly t o V SS
P80/CS0/RAS0 to P83/CS3/RAS3
P84/CS4/RAS4/IOWR,
P85/CS5/RAS5/IORD
P86/CS6/RAS6, P87/CS 7/RAS7
P90/LCAS/LWR
P91/UCAS/UWR
5 Input: Independently connect to HVDD or VSS via a resistor
Output: Leave open
Data Sheet U13995EJ2V0DS00 15
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
Table 2-1. I/O Circuit Type of Each Pin and Recommended Connection of Unused Pins (2/2)
Pin I/O Circuit Ty pe Recommended Connect i on of Unused Pins
P92/RD
P93/WE
P94/BCYST
P95/OE
P96/HLDAK
P97/HLDRQ
P100/TO120, P 101/ TO121
5
P102/TCLR12, P 103/ TI12
P104/INTP120/TC0 to
P107/INTP123/TC3
5-K
P110/TO140, P 111/ TO141 5
P112/TCLR14, P 113/ TI14
P114/INTP140
P115/INTP141/SO3
P116/INTP142/SI3
P117/INTP143/SCK3
5-K
P120/TO150, P 121/ TO151 5
P122/TCLR15, P 123/ TI15
P124/INTP150 to P126/INTP 152
P127/INTP153/ADTRG
5-K
PA0/A0 to PA7/A7
PB0/A8 to PB7/A15
PX5/REFRQ
PX6/WAIT
PX7/CLKOUT
5
Input: Independently connect to HVDD or VSS via a resistor
Output: Leave open
CKSEL 1 Connect directly to HVDD
RESET
MODE0 to MODE2
–
MODE3
2
Connect to VSS via a resistor (RVPP)
AVREF, AVSS – Connect di rectly t o VSS
AVDD – Connect direc tly to HVDD
Data Sheet U13995EJ2V0DS00
16
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
Figure 2-1. Pin I/O Circuits
Caution Replace VDD by HVDD when referencing the circuit diagrams shown above.
IN P-ch
V
DD
N-ch
IN
data P-ch
V
DD
N-ch
IN/OUT
output
disable
input
enable
data P-ch
V
DD
N-ch
IN/OUT
output
disable
input
enable
IN +
–
input enable
P-ch
N-ch
V
REF
(threshold voltage)
Type 1
Type 2
Type 5
Type 5-K
Type 9
Comparator
Schmitt-triggered input with hysteresis characteristics
Data Sheet U13995EJ2V0DS00 17
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
3. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°
°°
°C)
Parameter Symbol Condition Rating Unit
VDD VDD pin −0.5 to +4.6 V
HVDD HVDD pin, HVDD ≥ VDD −0.5 to +7.0 V
CVDD CVDD pin −0.5 to +4.6 V
CVSS CVSS pin −0.5 to +0.5 V
AVDD AVDD pin −0.5 to HVDD + 0.5 V
Power supply voltage
AVSS AVSS pin −0.5 to +0.5 V
X1 pin, ex cept MODE 3 pi n −0.5 to HV DD + 0. 5 VInput vol tage VI
MODE3 pin −0.5 to VDD + 0. 5 V
Clock i nput voltage VKX1, VDD = 3.0 to 3.6 V −0.5 to VDD + 1. 0 V
1 pin 4.0 mAOutput current, low I OL
Total of al l pi ns 100 mA
1 pin −4.0 mAOutput current, hi gh IOH
Total of all pins −100 mA
Output vol tage VOHVDD = 5. 0 V ±10 % −0.5 to HV DD + 0. 5 V
AVDD > HVDD −0.5 to HVDD + 0.5 VAnalog input vol t age VIAN P70/ANI0 to
P77/ANI 7 pi ns HVDD ≥ AVDD −0.5 to A V DD + 0.5 V
AVDD > HVDD −0.5 to HVDD + 0.5 VA/D convert er reference input
voltage AVREF
HVDD ≥ AVDD −0.5 to AVDD + 0.5 V
Operating ambient temperature TA
µ
PD703100-40 −40 to +70 °C
µ
PD703100-33, 703101-33, 703102-33 −40 to +85 °C
Storage tem perature Tstg −60 t o +150 °C
Cautions 1. Do not make direct connections of the output (or input/output) pins of the IC product with
each other, and also avoid direct connections to VDD, VCC, or GND. However, the open drain
pins or the open collector pins can be directly connected with each other. A direct
connection can also be made for an external circuit designed with timing specifications that
prevent conflicting output from pins subject to high-impedance state.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily
for any parameter. That is, the absolute maximum ratings are rated values at which the
product is on the verge of suffering physical damage, and therefore the product must be
used under conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions shown below for DC characteristics and AC characteristics are
within the range for normal operation and quality assurance.
Data Sheet U13995EJ2V0DS00
18
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
Capacitance (TA = 25°
°°
°C, VDD = HVDD = CVDD = VSS = 0 V)
Parameter Symbol Condition MIN. TYP. MAX. Unit
Input capacitanc e CI15 pF
I/O c apacitance CIO 15 pF
Output capacitanc e CO
fc = 1 MHz
Unmeasured pins returned to 0 V.
15 pF
Operating Conditions
Operation
Mode Internal Operat i ng Cl ock Frequency (
φ
)Operating Am bi ent
Temperature (TA)Power Supply Vol tage
(VDD, HVDD)
µ
PD703100-40 2 to 40 MHz −40 to +70°CDirect
mode
µ
PD703100-33, 703101-33, 703102-33 2 to 33 MHz −40 to +85°C
µ
PD703100-40 Note 2 20 to 40 MHz −40 to +70°CPLL
modeNote 1
µ
PD703100-33, 703101-33, 703102-33 Note 3 20 to 33 MHz −40 to +85°C
VDD = 3.0 to 3.6 V,
HVDD = 5.0 V ±10%
Notes 1. The internal operating clock frequency in PLL mode is the value for 5× operation. When used for 1× or
1/2× operation as set by the CKDIVn (n = 0, 1) bit of the CKC register, operation at a frequency of 20
MHz or less is possible.
2. Set the input clock frequency used in PLL mode to 4.0 to 8.0 MHz.
3. Set the input clock frequency used in PLL mode to 4.0 to 6.6 MHz.
Data Sheet U13995EJ2V0DS00 19
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
Recommended Oscillator
(a) Ceramic resonator (TA = −
−−
−40 to +70°
°°
°C …
µ
µµ
µ
PD703100-40,
T
A = −
−−
−40 to +85°
°°
°C …
µ
µµ
µ
PD703100-33, 703101-33, 703102-33)
(i) Murata Mfg. Co., Ltd. (TA = −
−−
−40 to +85°
°°
°C)
Recommended Circuit Cons tant Oscillation Voltage
Range
Type Part Number Oscillation
Frequency
fXX (MHz) C1 (pF) C2 (pF) Rd (kΩ) MIN. (V) MAX. (V)
Oscillation
Stabilization
Time (MAX.)
TOST (ms)
CSAC4.00MGC040 4.0 100 100 0 3.0 3.6 0.5
CSTCC4.00MG0H6 4.0 On-chip On-chip 0 3.0 3.6 0.3
CSAC5.00MGC040 5.0 100 100 0 3.0 3.6 0.4
CSTCC5.00MG0H6 5.0 On-chip On-chip 0 3.0 3.6 0.2
CSAC6.60MT 6.6 30 30 0 3.0 3.6 0.2
CSTCC6.60MG0H6 6.6 On-chip On-chip 0 3.0 3.6 0.1
CSAC8.00MT 8.0 30 30 0 3.0 3.6 0.2
Surface
mounting
CSTCC8.00MG0H6 8.0 On-chip On-chip 0 3.0 3.6 0.3
CSA4.00MG040 4.0 100 100 0 3.0 3.6 0.5
CST4.00MGW040 4.0 On-chip On-chip 0 3.0 3.6 0.5
CSA5.00MG040 5.0 100 100 0 3.0 3.6 0.5
CST5.00MGW040 5.0 On-chip On-chip 0 3.0 3.6 0.5
CSA6.60MTZ 6.6 30 30 0 3.0 3.6 0.1
CST6.60MTW 6.6 On-chip On-chip 0 3.0 3.6 0.1
CSA8.00MTZ 8.0 30 30 0 3.0 3.6 0.1
Lead
CST8.00MTW 8.0 On-chip On-chip 0 3.0 3.6 0.1
Cautions 1. Connect the oscillator as closely to the X1 and X2 pins as possible.
2. Do not wire any other signal lines in the area enclosed by broken lines.
3. Sufficiently evaluate the matching between the
µ
µµ
µ
PD703100-33, 703100-40, 703101-33,
703102-33 and the resonator.
X1
C1
X2
C2
R
d
Data Sheet U13995EJ2V0DS00
20
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(ii) TDK (TA = −
−−
−40 to +85°
°°
°C)
Recommended Circuit Cons tant Oscillation
Voltage Range
Manufac-
turer Part Number Oscillation
Frequency
fXX (MHz) C1 (pF) C2 (pF) Rd (kΩ) MIN. (V) MAX. (V)
Oscillation
Stabilization Time
(MAX.) TOST (ms)
CCR4.0MC3 4.0 On-chip On-chip 0 3.0 3.6 0.17
CCR5.0MC3 5.0 On-chip On-chip 0 3.0 3.6 0.15
TDK
CCR8.0MC5 8.0 On-chip On-chip 0 3.0 3.6 0.11
Cautions 1. Connect the oscillator as closely to the X1 and X2 pins as possible.
2. Do not wire any other signal lines in the area enclosed by broken lines.
3. Sufficiently evaluate the matching between the
µ
µµ
µ
PD703100-33, 703100-40, 703101-33,
703102-33 and the resonator.
(iii) Kyocera Corporation (TA = −
−−
−20 to +80°
°°
°C)
Recommended Circuit Cons tant Oscillati on
Voltage Range
Manufac-
turer Part Number Oscillation
Frequency
fXX (MHz) C1 (pF) C2 (pF) Rd (kΩ) MIN. (V) MAX. (V)
Oscillation
Stabilization Time
(MAX.) TOST (ms)
PBRC5.00BR-A 5.0 On-chip On-chip 0 3.0 3.6 0.06
PBRC6.00BR-A 6.0 On-chip On-chip 0 3.0 3.6 0.06
Kyocera
PBRC6.60BR-A 6.6 On-chip On-chip 0 3.0 3.6 0.06
Cautions 1. Connect the oscillator as closely to the X1 and X2 pins as possible.
2. Do not wire any other signal lines in the area enclosed by broken lines.
3. Sufficiently evaluate the matching between the
µ
µµ
µ
PD703100-33, 703100-40, 703101-33,
703102-33 and the resonator.
X1
C1
X2
C2
R
d
X1
C1
X2
C2
R
d
Data Sheet U13995EJ2V0DS00 21
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(b) External clock input (TA = –40 to +70°
°°
°C ...
µ
µµ
µ
PD703100-40,
TA = –40 to +85°
°°
°C ...
µ
µµ
µ
PD703100-33,
µ
µµ
µ
PD703101-33,
µ
µµ
µ
PD703102-33)
X1 X2
Open
External clock
Caution Input CMOS-level voltage to the X1 pin.
Data Sheet U13995EJ2V0DS00
22
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
DC Character istics (TA = –40 to +70°
°°
°C ...
µ
µµ
µ
PD703100-40, TA = –40 to +85°
°°
°C ...
µ
µµ
µ
PD703100-33,
µ
µµ
µ
PD703101-33,
µ
µµ
µ
PD703102-33, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 ±
±±
±10%, VSS = 0 V)
Parameter Symbol Condition MIN. TYP. MAX. Unit
Except Note 1 2.2 HVDD + 0.3 VInput vol tage, high VIH
Note 1 0.8HVDD HVDD + 0.3 V
Except Note 1 and Note 2 −0.5 +0.8 V
Input vol tage, low VIL
Note 1 −0.5 0.2HVDD V
X1 pin Direct mode 0.8VDD VDD + 0.3 VClock input voltage, hi gh VXH
PLL mode 0.8VDD VDD + 0.3 V
X1 pin Direct mode −0.3 0.15V DD VCl ock input voltage, l ow VXL
PLL mode −0.3 0. 15VDD V
HVT+Note 1, ri sing edge 3.0 V
Schmi t t-triggered input
threshold voltage HVT−Note 1, falling edge 2.0 V
Schmi t t-triggered input
hyst eresis wi dt h HVT+
–HVT−Note 1 0.5 V
IOH = −2.5 mA 0.7HVDD VOutput voltage, hi gh VOH
IOH = −100
µ
AHV
DD − 0.4 V
Output vol tage, low VOL IOL = 2.5 mA 0.45 V
Input leak age current, hi gh ILIH Except VI = HVDD or No te 2 10
µ
A
Input leak age current, l ow ILIL Except V I = 0 V or Note 2 −10
µ
A
Output leak age current, hi gh ILOH VO = HVDD 10
µ
A
Output leak age current, l ow ILOL VO = 0 V −10
µ
A
Notes 1. P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3,
P34/INTP130, P35/INTP131/SO2, P36/INTP132/SI2, P37/INTP133/SCK2, P104/INTP120/TC0 to
P107/INTP123/TC3, P114/INTP140, P115/INTP141/SO3, P116/INTP142/SI3, P117/INTP143/SCK3,
P124/INTP150 to P126/INTP152, P127/INTP153/ADTRG, P02/TCLR10, P12/TCLR11, P32/TCLR13,
P102/TCLR12, P112/TCLR14, P122/TCLR15, P03/TI10, P13/TI11, P33/TI13, P103/TI12, P113/TI14,
P123/TI15, P20/NMI, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, MODE0 to MODE2,
RESET
2. When the P70/ANI0 to P77/ANI7 pins are used as analog input.
Remark TYP. values are reference values for when TA = 25°C, VDD = CVDD = 3.3 V, and HVDD = 5.0 V.
Data Sheet U13995EJ2V0DS00 23
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
DC Characteristics (TA = –40 to +70 °
°°
°C ...
µ
µµ
µ
PD703100-40, TA = –40 to +85°
°°
°C ...
µ
µµ
µ
PD703100-33,
µ
µµ
µ
PD703101-33,
µ
µµ
µ
PD703102-33, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 ±
±±
±10%, VSS = 0 V)
Parameter Symbol Condition MIN. TYP. MAX. Unit
VDD + CVDD 2.0 × fx 3.6 × fx mANormal
mode IDD1
HVDD 1.8 × fx 3.0 × fx mA
VDD + CVDD 1.4 × fx 2.5 × fx mAHALT mode IDD2
HVDD 0.8 × fx 1.6 × fx mA
VDD + CVDD 1.5 3.0 mAIDLE mode IDD3
HVDD 10 50
µ
A
VDD + CVDD 1.0 3.0 mA
µ
PD703100-40
HVDD 10 50
µ
A
VDD + CVDD 20 100
µ
A
Power supply
current
STOP
mode IDD4
µ
PD703100-33,
703101-33,
703102-33 HVDD 10 50
µ
A
Remarks 1. TYP. values are reference values for when TA = 25°C, VDD = CVDD = 3.3 V, and HVDD = 5.0 V.
2. Direct mode:
fX = 2 to 40 MHz (
µ
PD703100-40)
fX = 2 to 33 MHz (
µ
PD703100-33,
µ
PD703101-33,
µ
PD703102-33)
PLL mode:
fX = 20 to 40 MHz (
µ
PD703100-40)
fX = 20 to 33 MHz (
µ
PD703100-33,
µ
PD703101-33,
µ
PD703102-33)
3. The unit for fX is MHz.
Data Sheet U13995EJ2V0DS00
24
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
Data Hold Characteristics (TA = –40 to +70°
°°
°C ...
µ
µµ
µ
PD703100-40, TA = –40 to +85°
°°
°C ...
µ
µµ
µ
PD703100-33,
µ
µµ
µ
PD703101-
33,
µ
µµ
µ
PD703102-33)
Parameter Symbol Condition MIN. TYP. MAX. Unit
VDDDR STOP mode, VDD = VDDDR 1.5 3.6 VData hold vol t age
HVDDDR STOP m ode,
HVDD = HVDDDR
VDDDR 5.5 V
µ
PD703100-40 VDD = VDDDR 1.0 3.0 mAData hold current IDDDR
µ
PD703100-33,
703101-33,
703102-33
VDD = VDDDR 30 150
µ
A
Power supply voltage rise
time tRVD 200
µ
s
Power supply voltage f al l t i me tFVD 200
µ
s
Power supply voltage hold
time (t o S T OP mode setting) tHVD 0ms
STOP mode rel ease signal
input ti m e tDREL 0ns
Data hold high-level input
voltage VIHDR Note 0.8HVDDDR HVDDDR V
Data hold low-level input
voltage VILDR Note 00.2HV
DDDR V
Note P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3,
P34/INTP130, P35/INTP131/SO2, P36/INTP132/SI2, P37/INTP133/SCK2, P104/INTP120/TC0 to
P107/INTP123/TC3, P114/INTP140, P115/INTP141/SO3, Pl16/INTP142/SI3, P117/INTP143/SCK3,
P124/INTP150 to P126/INTP152, P127/INTP153/ADTRG, P02/TCLR10, P12/TCLR11, P32/TCLR13,
P102/TCLR12, P112/TCLR14, P122/TCLR15, P03/TI10, P13/TI11, P33/TI13, P103/TI12, P113/TI14,
P123/TI15, P20/NMI, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, MODE0 to MODE2, RESET
Remark TYP. values are reference values for when TA = 25°C.
Data Sheet U13995EJ2V0DS00 25
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
HV
DD
RESET (input) V
IHDR
V
IHDR
V
ILDR
V
DD
t
HVD
t
FVD
V
DDDR
t
RVD
t
DREL
STOP mode setting
NMI (input)
(Released by falling edge)
NMI (input)
(Released by rising edge)
Data Sheet U13995EJ2V0DS00
26
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
AC Characteristics (TA = –40 to +70°
°°
°C ...
µ
µµ
µ
PD703100-40, TA = –40 to +85°
°°
°C ...
µ
µµ
µ
PD703100-33,
µ
µµ
µ
PD703101-33,
µ
µµ
µ
PD703102-33, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 ±
±±
±10%, VSS = 0 V, output pin load
capacitance: CL = 50 pF)
AC Test Input Waveform
(a) P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3, P34/
INTP130, P35/INTP131/SO2, P36/INTP132/SI2, P37/INTP133/SCK2, P104/INTP120/TC0 to P107/INTP123/
TC3, P114/INTP140, P115/INTP141/SO3, P116/INTP142/SI3, P117/INTP143/SCK3, P124/INTP150 to P126/
INTP152, P127/INTP153/ADTRG, P02/TCLR10, P12/TCLR11, P32/TCLR13, P102/TCLR12, P112/TCLR14,
P122/TCLR15, P03/TI10, P13/TI11, P33/TI13, P103/TI12, P113/TI14, P123/TI15, P20/NMI, P23/RXD0/SI0, P24/
SCK0, P26/RXD1/SI1, P27/SCK1, MODE0 to MODE2, RESET
HV
DD
0 V
0.8HV
DD
0.2HV
DD
0.8HV
DD
0.2HV
DD
Test
points
Input signal
(b) Pins other than those listed in (a) above
2.4 V
0.4 V
2.2 V
0.8 V
2.2 V
0.8 V
Test
points
Input signal
AC Test Output Test Points
2.4 V
0.8 V
2.4 V
0.8 V
Test
points
Output signal
Data Sheet U13995EJ2V0DS00 27
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
Load Condition
Caution In cases where the load capacitance is greater than 50 pF due to the circuit configuration,
insert a buffer or other element to reduce the device's load capacitance 50 pF.
(1) Clock timing
Parameter Symbol Condition MIN. MAX. Unit
µ
PD703100-40 12.5 250 nsDirect
mode
µ
PD703100-33,
703101-33,
703102-33
15 250 ns
µ
PD703100-40 125 250 ns
X1 input cycle <1> tCYX
PLL mode
µ
PD703100-33,
703101-33,
703102-33
150 250 ns
Direct mode 5 nsX1 input high-l evel width <2> tWXH
PLL mode 50 ns
Direct mode 5 nsX1 input l ow-level width <3> tWXL
PLL mode 50 ns
Direct mode 4 nsX1 input rise ti m e <4> tXR
PLL mode 10 ns
X1 input f al l time <5> tXF Direc t mode 4 ns
PLL mode 10 ns
µ
PD703100-40 25 500 nsCLKOUT output cycle <6> tCYK
µ
PD703100-33, 703101-33,
703102-33 30 500 ns
CLKOUT high-lev el wi dth <7> tWKH 0.5T – 7 ns
CLKOUT low-l evel widt h <8> tWKL 0.5T – 4 ns
CLKOUT rise time <9> tKR 5ns
CLKOUT fall time <10> tKF 5ns
Remark T = tCYK
C
L
= 50 pF
DUT
(Device under test)
Data Sheet U13995EJ2V0DS00
28
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(2) Output waveform (other than X1, CLKOUT)
Parameter Symbol Condition MIN. MAX. Unit
Output ris e time <12> t OR 10 ns
Output fall time <13> tOF 10 ns
<13>
Signals other than X1, CLKOUT
<12>
<4> <5>
<2> <3>
<1>
X1
(PLL mode)
<1>
<2> <3>
<4>
<5>
<9> <10>
<7> <8>
<6>
X1
(Direct mode)
CLKOUT (output)
Data Sheet U13995EJ2V0DS00 29
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(3) Reset timing
Parameter Symbol Condition MIN. MAX. Unit
RESET high-level width <14> tWRSH 500 ns
When power supply i s on, and
STOP mode has been released 500 + TOS nsRESET low-level width <15> tWRSL
Other than when power suppl y is
on, and STOP m ode has been
released
500 ns
Remark TOS: Oscillation stabilization time
<14> <15>
RESET (input)
Data Sheet U13995EJ2V0DS00
30
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(4) SRAM, external ROM, or external I/O access timing
(a) Access timing (SRAM, external ROM, or external I/O) (1/2)
Parameter Symbol Condition MIN. MAX. Unit
Address, CSn output del ay time (f rom
CLKOUT ↓)<16> tDKA 210ns
Address, CSn output hol d time (from
CLKOUT ↓)<17> tHKA 210ns
RD, IORD ↓ delay time
(from CLKO UT ↑)<18> tDKRDL 214ns
RD, IORD ↑ delay time
(from CLKO UT ↑)<19> tHKRDH 214ns
UWR, LWR, IOWR ↓ delay time (from
CLKOUT ↑)<20> tDKWRL 210ns
UWR, LWR, IOWR ↑ delay time (from
CLKOUT ↑)<21> tHKWRH 210ns
BCYST ↓ delay time (from CLKOUT
↓)<22> tDKBSL 210ns
BCYST ↑ delay time (from CLKOUT
↓)<23> tHKBSH 210ns
WAIT setup time (to CLKOUT ↓) <24> tSWK 15 ns
WAIT hold time (from CLKOUT ↓) <25> tHKW 2ns
Data input s etup time
(to CLKOUT ↑)<26> tSKID 18 ns
Data input hol d t i m e
(from CLKO UT ↑)<27> tHKID 2ns
Data output del ay time
(from CLKO UT ↓)<28> tDKOD 210ns
Data output hol d time
(from CLKO UT ↓)<29> tHKOD 210ns
Remarks 1. Maintain at least one of the data input hold times tHKID and tHRDID.
2. n = 0 to 7
Data Sheet U13995EJ2V0DS00 31
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(a) Access timing (SRAM, external ROM, or external I/O) (2/2)
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero.
2. The broken lines indicate high impedance.
3. n = 0 to 7
CLKOUT (Output)
A0 to A23 (Output)
CSn (Output)
BCYST (Output)
RD, IORD (Output)
[Read time]
UWR, LWR, IOWR (Output)
[Write time]
D0 to D15 (I/O)
[Read time]
D0 to D15 (I/O)
[Write time]
WAIT (Input)
<16> <17>
<22> <23>
<18> <19>
<20> <21>
<26>
<27>
<28> <29>
<24>
<25>
<24>
<25>
T1 TW T2
Data Sheet U13995EJ2V0DS00
32
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(b) Read timing (SRAM, external ROM, or external I/O) (1/2)
Parameter Symbol Condition MIN. MAX. Unit
Data input s etup time (to address) <30> tSAID (1.5 + wD + w)T – 28 ns
Data input s etup time (to RD) <31> tSRDID (1 + wD + w)T – 32 ns
RD, IORD l ow-l evel widt h <32> t WRDL (1 + wD + w)T – 10 ns
RD, IORD hi gh-l evel width <33> tWRDH T – 10 ns
Delay time from address, CSn to RD,
IORD ↓<34> tDARD 0.5T – 10 ns
Delay time from RD, IORD ↑ to
address <35> tDRDA (0. 5 + i)T – 10 ns
Data input hold time (from RD, IORD
↑
)
<36> tHRDID 0ns
Delay time from RD, IORD ↑ to data
output <37> tDRDOD (0.5 + i)T – 10 ns
WAIT s etup time (t o address) <38> tSAW Note T – 25 ns
WAIT setup time (to BCYST ↓) <39> tSBSW Note T – 25 ns
WAIT hold time (from BCYST ↑) <40> tHBSW Note 0ns
Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wD: the number of waits due to the DWC1 and DWC2 registers.
4. i: the number of idle states that are inserted when a write cycle follows a read cycle.
5. Maintain at least one of the data input hold times tHKID and tHRDID.
6. n = 0 to 7
Data Sheet U13995EJ2V0DS00 33
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(b) Read timing (SRAM, external ROM, or external I/O) (2/2)
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero.
2. The broken lines indicate high impedance.
3. n = 0 to 7
UWR, LWR, IOWR (Output)
RD, IORD (Output)
D0 to D15 (I/O)
T1 TW T2
CLKOUT (Output)
<33> <32> <35>
<38>
<34> <31>
<30> <36>
<37>
<39> <40>
A0 to A23 (Output)
CSn (Output)
WAIT (Input)
BCYST (Output)
Data Sheet U13995EJ2V0DS00
34
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(c) Write timing (SRAM, external ROM, or external I/O) (1/2)
Parameter Symbol Condition MIN. MAX. Unit
WAIT s etup time (t o address) <38> tSAW Note T – 25 ns
WAIT setup time (to BCYST ↓) <39> tSBSW Note T – 25 ns
WAIT hold time (from BCYST ↑) <40> tHBSW Note 0ns
Delay time from address, CSn to
UWR, LWR, IOWR ↓<41> tDAWR 0.5T – 10 ns
Address setup ti m e (t o UWR, LWR,
IOWR ↑)<42> tSAWR (1.5 + wD + w)T – 10 ns
Delay time from UWR, LWR, IOWR ↑
to address <43> tDWRA 0. 5T – 10 ns
UWR, LWR, I OWR hi gh-level width <44> tWWRH T – 10 ns
UWR, LWR, I OWR l o w-l evel width <45> t WWRL (1 + wD + w)T – 10 ns
Data output setup ti m e
(to UWR, LWR, IOWR ↑)<46> tSODWR (1.5 + wD + w)T – 10 ns
Data output hol d time
(from UWR, LWR, IOWR ↑)<47> tHWROD 0.5T – 10 ns
Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wD: the number of waits due to the DWC1 and DWC2 registers.
4. n = 0 to 7
Data Sheet U13995EJ2V0DS00 35
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(c) Write timing (SRAM, external ROM, or external I/O) (2/2)
Remarks 1. This is the tim ing when the num ber of w aits due to the DWC 1 and D WC2 registers is zero.
2. The broken lines indicate high impedance.
3. n = 0 to 7
T1 TW T2
CLKOUT (Output)
<44> <45> <43>
<38>
<46>
<47>
<39> <40>
<41> <42>
A0 to A23 (Output)
CSn (Output)
RD, IORD (Output)
UWR, LWR, IOWR (Output)
D0 to D15 (I/O)
WAIT (Input)
BCYST (Output)
Data Sheet U13995EJ2V0DS00
36
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(d) DMA flyby transfer timing (SRAM →
→→
→ external I/O transfer) (1/2)
Parameter Symbol Condition MIN. MAX. Unit
WAIT setup time (to CLKOUT ↓) <24> tSWK 15 ns
WAIT hold time (from CLKOUT ↓) <25> tHKW 2ns
RD low-level wi dth <32> tWRDL
(1 + w
D
+ w
F
+ w)
T
–
10
ns
RD high-level wi dth <33> tWRDH T – 10 ns
Delay time from address, CSn to RD ↓<34> tDARD 0.5T – 10 ns
Delay time from RD ↑ to address <35> tDRDA (0.5 + i)T – 10 ns
Delay time from RD ↑ to data output <37> tDRDOD (0. 5 + i)T – 10 ns
WAIT s etup time (t o address) <38> tSAW Note T – 25 ns
WAIT setup time (to BCYST ↓) <39> tSBSW Note T – 25 ns
WAIT hold time (from BCYST ↑) <40> tHBSW Note 0ns
Delay ti m e from address to IOWR ↓<41> tDAWR 0.5T – 10 ns
Address setup ti m e (to IOWR ↑) <42> tSAWR (1.5 + wD + w)T – 10 ns
Delay time from IOWR ↑ to address <43> tDWRA 0.5T – 10 ns
IOWR high-level widt h <44> tWWRH T – 10 ns
IOWR low-level widt h <45> t WWRL (1 + wD + w)T – 10 ns
wF = 0 0 nsDelay time from IOWR ↑ to RD ↑<48> tDWRRD
wF = 1 T – 10 ns
Delay time from DMAAKm ↓ to IOWR ↓<49> tDDAWR 0. 5T – 10 ns
Delay time from IOWR ↑ to DMAAKm ↑<50> tDWRDA (0.5 + wF)T – 10 ns
Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wD: the number of waits due to the DWC1 and DWC2 registers.
4. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer.
5. i: the number of idle states that are inserted when a write cycle follows a read cycle.
6. n = 0 to 7, m = 0 to 3
Data Sheet U13995EJ2V0DS00 37
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(d) DMA flyby transfer timing (SRAM →
→→
→ external I/O transfer) (2/2)
Remarks 1. This is the tim ing when the num ber of w aits due to the D WC1 and D WC 2 registers is zero and wF = 0.
2. The broken lines indicate high impedance.
3. n = 0 to 7, m = 0 to 3
CLKOUT (Output)
T1 TW T2
<33> <32> <35>
<34> <48>
<50><49>
<43><42>
<41>
<44> <45>
<37>
<38>
<24> <24>
<25> <25>
<40>
<39>
A0 to A23 (Output)
CSn (Output)
RD (Output)
DMAAKm (Output)
IORD (Output)
IOWR (Output)
UWR, LWR (Output)
D0 to D15 (I/O)
WAIT (Input)
BCYST (Output)
Data Sheet U13995EJ2V0DS00
38
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(e) DMA flyby transfer timing (external I/O →
→→
→ SRAM transfer) (1/2)
Parameter Symbol Condition MIN. MAX. Unit
WAIT setup time (to CLKOUT ↓) <24> tSWK 15 ns
WAIT hold time (from CLKOUT ↓) <25> tHKW 2ns
IORD low-level widt h <32> tWRDL (1 + wD + wF + w)T
– 10 ns
IORD high-level widt h <33> tWRDH T – 10 ns
Delay time from address, CSn to
IORD ↓<34> tDARD 0.5T – 10 ns
Delay time from IORD ↑ to address <35> tDRDA (0. 5 + i )T – 10 ns
Delay time from IORD ↑ to data output <37> tDRDOD (0.5 + i)T – 10 ns
WAIT s etup time (t o address) <38> tSAW Note T – 25 ns
WAIT setup time (to BCYST ↓) <39> tSBSW Note T – 25 ns
WAIT hold time (from BCYST ↑) <40> tHBSW Note 0ns
Delay time from address to UWR,
LWR ↓<41> tDAWR 0.5T – 10 ns
Address setup ti m e (t o UWR, LWR ↑) <42> tSAWR (1.5 + wD + w)T – 10 ns
Delay time from UWR, LWR to
address <43> tDWRA 0.5T – 10 ns
UWR, LWR high-level width <44> t WWRH T – 10 ns
UWR, LWR low-level width <45> tWWRL (1 + wD + w)T – 10 ns
wF = 0 0 nsDelay time from UWR, LWR↑ to IORD ↑<48> tDWRRD
wF = 1 T – 10 ns
Delay time from DMAAKm ↓ to IORD ↓<51> tDDARD 0.5T – 10 ns
Delay time from IORD ↑ to DMAAKm ↑<52> tDRDDA 0.5T – 10 ns
Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wD: the number of waits due to the DWC1 and DWC2 registers.
4. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer.
5. i: the number of idle states that are inserted when a write cycle follows a read cycle.
6. n = 0 to 7, m = 0 to 3
Data Sheet U13995EJ2V0DS00 39
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(e) DMA flyby transfer timing (external I/O →
→→
→ SRAM transfer) (2/2)
Remarks 1. This is the tim ing when the num ber of w aits due to the D WC1 and D WC 2 registers is zero and wF = 0.
2. The broken lines indicate high impedance.
3. n = 0 to 7, m = 0 to 3
CLKOUT (Output)
T1 TW T2
<44> <45>
<48>
<52>
<33>
<37>
<38>
<24> <24>
<25> <25>
<40>
<39>
<42>
<41> <43>
<51>
<32> <35>
<34>
A0 to A23 (Output)
CSn (Output)
UWR, LWR (Output)
RD (Output)
DMAAKm (Output)
IOWR (Output)
IORD (Output)
D0 to D15 (I/O)
WAIT (Input)
BCYST (Output)
Data Sheet U13995EJ2V0DS00
40
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(5) Page ROM access timing (1/2)
Parameter Symbol Condition MIN. MAX. Unit
WAIT setup time (to CLKOUT ↓) <24> tSWK 15 ns
WAIT hold time (from CLKOUT ↓) <25> tHKW 2ns
Data input s etup time
(to CLKOUT ↑)<26> tSKID 18 ns
Data input hol d t i m e
(from CLKO UT ↑)<27> tHKID 2ns
Off-page data i nput setup t i m e (to
address) <30> tSAID (1.5 + wD + w)T – 28 ns
Off-page data i nput setup t i m e (to RD) <31> tSRDID (1 + wD + w)T – 32 ns
Off-page RD low-l e vel width <32> tWRDL (1 + wD + w)T – 10 ns
RD high-level wi dth <33> tWRDH 0.5T – 10 ns
Data input hol d t i m e (from RD) <36> tHRDID 0ns
Delay time from RD ↑ to data output <37> tDRDOD (0. 5 + i)T – 10 ns
On-page RD low-level wi dth <53> tWORDL (1.5 + wPR + w)T
– 10 ns
On-page data input s etup time
(to address ) <54> tSOAID (1.5 + wPR + w)T – 28 ns
On-page data input s etup time (to RD) <55> tSORDID (1.5 + wPR + w)T – 32 ns
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wD: the number of waits due to the DWC1 and DWC2 registers.
4. wPR: the number of waits due to the PRC register.
5. i: the number of idle states that are inserted when a write cycle follows a read cycle.
6. Maintain at least one of the data input hold times tHKID and tHRDID.
Data Sheet U13995EJ2V0DS00 41
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(5) Page ROM access timing (2/2)
Note On-page and off-page addresses are as follows.
PRC Register
MA5 MA4 MA3 On-page Address es Off-page Addresses
0 0 0 A0, A1 A2 to A23
0 0 1 A0 to A2 A3 to A23
0 1 1 A0 to A3 A4 to A23
1 1 1 A0 to A4 A5 to A23
Remarks 1. This is the timing for the following case.
Number of waits due to the DWC1 and DWC2 registers (TDW): 1
Number of waits due to the PRC register (TPRW): 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
CLKOUT (Output)
On-page address
Note
T1 TDW TW T2 TO1 TPRW TW TO2
<24>
<25> <24>
<25> <24>
<25> <24>
<25>
<26>
<27>
<36>
<32>
<31> <53>
<55>
<27>
<26> <36>
<37>
<33>
<30> <54>
Off-page address
Note
CSn (Output)
UWR, LWR (Output)
RD (Output)
D0 to D15 (I/O)
WAIT (Input)
BCYST (Output)
Data Sheet U13995EJ2V0DS00
42
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(6) DRAM access timing
(a) Read timing (high-speed page DRAM access, normal access: off-page) (1/3)
Parameter Symbol Condition MIN. MAX. Unit
WAIT setup time (to CLKOUT ↓) <24> tSWK 15 ns
WAIT hold time (from CLKOUT ↓) <25> tHKW 2ns
Data input s etup time (to CLKOUT ↑) <26> tSKID 18 ns
Data input hol d t i m e (from CLKOUT ↑) <27> tHKID 2ns
Delay time from OE ↑ to data out put <37> tDRDOD (0.5 + i)T – 10 ns
Row address s et up time <56> tASR (0.5 + wRP)T – 10 ns
Row address hold time <57> tRAH (0.5 + wRH)T – 10 ns
Column address setup time <58> tASC 0.5T – 10 ns
Column address hol d time <59> tCAH (1.5 + wDA + w)T – 10 ns
Read/write cycle time <60> tRC
(3 + w
RP
+ w
RH
+ w
DA
+ w)
T
–
10
ns
RAS precharge time <61> tRP (0.5 + wRP)T – 10 ns
RAS puls e time <62> tRAS (2.5 + wRH + wDA +
w)T – 10 ns
RAS hold t i m e <63> tRSH (1.5 + wDA + w)T – 10 ns
Column address read tim e for RAS <64> tRAL (2 + wDA + w)T – 10 ns
CAS pulse width <65> tCAS (1 + wDA + w)T – 10 ns
CAS-RAS precharge time <66> tCRP (1 + wRP)T – 10 ns
CAS hold t i m e <67> tCSH (2 + wRH + wDA + w)T
– 10 ns
WE setup time <68> t RCS (2 + wRP + wRH)T – 10 ns
WE hold ti m e (f rom RAS ↑) <69> tRRH 0.5T – 10 ns
WE hold ti m e (f rom CAS ↑) <70> tRCH T – 10 ns
CAS precharge time <71> tCPN (2 + wRP + wRH)T – 10 ns
Output enable ac cess time <72> tOEA
(2 + w
RP
+ w
RH
+ w
DA
+ w)
T
–
28
ns
RAS access time <73> tRAC
(2 + w
RH
+ w
DA
+ w)
T
–
28
ns
Access ti m e from colum n address <74> tAA (1.5 + wDA + w)T – 28 ns
CAS access time <75> tCAC (1 + wDA + w)T – 28 ns
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6. i: the number of idle states that are inserted when a write cycle follows a read cycle.
Data Sheet U13995EJ2V0DS00 43
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(a) Read timing (high-speed page DRAM access, normal access: off-page) (2/3)
Parameter Symbol Condition MIN. MAX. Unit
RAS col um n address delay time <76> tRAD (0.5 + wRH)T – 10 ns
RAS-CAS del ay time <77> tRCD (1 + wRH)T – 10 ns
Output buffer turn-off delay time (from
OE ↑)<78> tOEZ 0ns
Output buffer turn-off delay time (from
CAS ↑)<79> tOFF 0ns
Remarks 1. T = tCYK
2. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
Data Sheet U13995EJ2V0DS00
44
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(a) Read timing (high-speed page DRAM access, normal access: off-page) (3/3)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
TRPW TRHW T2T1 TDAW TW T3
<56>
<61>
<57>
<58>
<59>
<62>
<76> <63>
<64>
<60>
<77> <65>
<67><66>
<71> <73>
<68> <75>
<74>
<72>
<70>
<69>
<79>
<37>
<27>
<25>
<26>
<25><24>
<78>
<24>
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
WE (Output)
OE (Output)
WAIT (Input)
D0 to D15 (I/O)
UCAS (Output)
LCAS (Output)
Row address Column address
Data Sheet U13995EJ2V0DS00 45
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
[MEMO]
Data Sheet U13995EJ2V0DS00
46
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(b) Read timing (high-speed page DRAM access: on-page) (1/2)
Parameter Symbol Condition MIN. MAX. Unit
Data input s etup time (to CLKOUT ↑) <26> tSKID 18 ns
Data input hol d t i m e (from CLKOUT ↑) <27> tHKID 2ns
Delay time from OE ↑ to data out put <37> tDRDOD (0.5 + i)T – 10 ns
Column address setup time <58> tASC (0.5 + wCP)T – 10 ns
Column address hol d time <59> tCAH (1.5 + wDA)T – 10 ns
RAS hold t i m e <63> tRSH (1.5 + wDA)T – 10 ns
Column address read tim e for RAS <64> tRAL (2 + wCP + wDA)T – 10 ns
CAS pulse width <65> tCAS (1 + wDA)T – 10 ns
WE setup time (to CA S ↓) <68> tRCS (1 + wCP)T – 10 ns
WE hold ti m e (f rom RAS ↑) <69> tRRH 0.5T – 10 ns
WE hold ti m e (f rom CAS ↑) <70> tRCH T – 10 ns
Output enable ac cess time <72> tOEA
(1 + w
CP
+ w
DA
)T – 28
ns
Access ti m e from colum n address <74> tAA
(1.5 + w
CP
+ w
DA
)
T –
28
ns
CAS access time <75> tCAC (1 + wDA)T – 28 ns
Output buffer turn-off delay time (from
OE ↑)<78> tOEZ 0ns
Output buffer turn-off delay time (from
CAS ↑)<79> tOFF 0ns
Access ti m e from CAS precharge <80> tACP
(2 + w
CP
+ w
DA
)T – 28
ns
CAS precharge time <81> tCP (1 + wCP)T – 10 ns
High-speed page mode cycle time <82> tPC (2 + wCP + wDA)T – 10 ns
RAS hold t i me for CAS precharge <83> t RHCP
(2.5 + w
CP
+ w
DA
)
T –
10
ns
Remarks 1. T = tCYK
2. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. i: the number of idle states that are inserted when a write cycle follows a read cycle.
Data Sheet U13995EJ2V0DS00 47
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(b) Read timing (high-speed page DRAM access: on-page) (2/2)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
TCPW TO1 TDAW TO2
<58> <59>
<63>
<64>
<83> <65><81> <82>
<68>
<75>
<72> <26>
<79>
<37>
<74>
<80> <27>
<78>
<70>
<69>
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
UCAS (Output)
LCAS (Output)
WE (Output)
OE (Output)
D0 to D15 (I/O)
WAIT (Input)
Column address
Data Sheet U13995EJ2V0DS00
48
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(c) Write timing (high-speed page DRAM access, normal access: off-page) (1/2)
Parameter Symbol Condition MIN. MAX. Unit
WAIT setup time (to CLKOUT ↓) <24> tSWK 15 ns
WAIT hold time (from CLKOUT ↓) <25> tHKW 2ns
Row address s et up time <56> tASR (0.5 + wRP)T – 10 ns
Row address hold time <57> tRAH (0.5 + wRH)T – 10 ns
Column address setup time <58> tASC 0.5T – 10 ns
Column address hol d time <59> tCAH (1.5 + wDA + w)T – 10 ns
Read/write cycle time <60> tRC
(3 + w
RP
+ w
RH
+ w
DA
+
w)T – 10
ns
RAS precharge time <61> tRP (0.5 + wRP)T – 10 ns
RAS puls e time <62> tRAS (2.5 + wRH + wDA +
w)T – 10 ns
RAS hold t i m e <63> tRSH (1.5 + wDA + w)T – 10 ns
Column address read time (from RAS
↑
)
<64> tRAL (2 + wDA + w)T – 10 ns
CAS pulse width <65> tCAS (1 + wDA + w)T – 10 ns
CAS-RAS precharge time <66> tCRP (1 + wRH)T – 10 ns
CAS hold t i m e <67> tCSH (2 + wRH + wDA + w)T
– 10 ns
CAS precharge time <71> tCPN (2 + wRP + wRH)T – 10 ns
RAS col um n address delay time <76> tRAD (0.5 + wRH)T – 10 ns
RAS-CAS del ay time <77> tRCD (1 + wRH)T – 10 ns
WE set up time (to CAS ↓) <84> tWCS (1 + wRP + wRH )T
– 10 ns
WE hold ti m e (f rom CAS ↓) <85> tWCH (1 + wDA + w)T – 10 ns
Data setup time (to CAS ↓) <86> tDS
(1.5 + w
RP
+ w
RH
)
T –
10
ns
Data hold time (from CAS ↓) <87> tDH (1.5 + wDA + w)T – 10 ns
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
Data Sheet U13995EJ2V0DS00 49
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(c) Write timing (high-speed page DRAM access, normal access: off-page) (2/2)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
TRPW TRHW T2T1 TDAW TW T3
<56>
<61>
<57>
<58>
<59>
<62>
<76> <63>
<64>
<60>
<77> <65>
<67><66>
<71>
<84>
<25> <25><24>
<24>
<85>
<86> <87>
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
UCAS (Output)
LCAS (Output)
WE (Output)
OE (Output)
D0 to D15 (I/O)
WAIT (Input)
Row address Column address
Data Sheet U13995EJ2V0DS00
50
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(d) Write timing (high-speed page DRAM access: on-page) (1/2)
Parameter Symbol Condition MIN. MAX. Unit
Column address setup time <58> tASC (0.5 + wCP)T – 10 ns
Column address hol d time <59> tCAH (1.5 + wDA)T – 10 ns
RAS hold t i m e <63> tRSH (1.5 + wDA)T – 10 ns
Column address read time (from RAS
↑
)
<64> tRAL (2 + wCP + wDA)T – 10 ns
CAS pulse width <65> tCAS (1 + wDA)T – 10 ns
CAS precharge time <81> tCP (1 + wCP)T – 10 ns
RAS hold t i me for CAS precharge <83> t RHCP
(2.5 + w
CP
+ w
DA
)T
– 10
ns
WE set up time (to CAS ↓) <84> tWCS wCP ≥ 1w
CPT – 10 ns
WE hold ti m e (f rom CAS ↓) <85> tWCH (1 + wDA)T – 10 ns
Data setup time (to CAS ↓) <86> tDS (0.5 + wCP)T – 10 ns
Data hold time (from CAS ↓) <87> tDH (1.5 + wDA)T – 10 ns
WE read tim e (from RAS ↑) <88> tRWL wCP = 0 (1.5 + wDA)T – 10 ns
WE read tim e (from CAS ↑) <89> tCWL wCP = 0 (1 + wDA)T – 10 ns
Data setup time (to WE ↓) <90> tDSWE wCP = 0 0.5T – 10 ns
Data hold ti m e (f rom WE ↓) <91> tDHWE wCP = 0 (1.5 + wDA)T – 10 ns
WE pulse wi dt h <92> tWP wCP = 0 (1 + wDA)T – 10 ns
Remarks 1. T = tCYK
2. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
Data Sheet U13995EJ2V0DS00 51
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(d) Write timing (high-speed page DRAM access: on-page) (2/2)
TCPW TO1 TDAW TO2
<58> <59>
<63>
<64>
<83>
<81> <65>
<89>
<88>
<84> <85>
<92>
<91>
<86> <87>
<90>
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
UCAS (Output)
LCAS (Output)
OE (Output)
WE (Output)
D0 to D15 (I/O)
WAIT (Input)
Column address
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the CPCxx bit of the DRCn register (TCPW ): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
Data Sheet U13995EJ2V0DS00
52
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(e) Read timing (EDO DRAM) (1/3)
Parameter Symbol Condition MIN. MAX. Unit
Data input s etup time (to CLKOUT ↑) <26> tSKID 18 ns
Data input hol d t i m e (from CLKOUT ↑) <27> tHKID 2ns
Delay time from OE ↑ to data out put <37> tDRDOD (0.5 + i)T – 10 ns
Row address s et up time <56> tASR (0.5 + wRP)T – 10 ns
Row address hold time <57> tRAH (0.5 + wRH)T – 10 ns
Column address setup time <58> tASC 0.5T – 10 ns
Column address hol d time <59> tCAH (0.5 + wDA)T – 10 ns
RAS precharge time <61> tRP (0.5 + wRP)T – 10 ns
Column address read time (from RAS
↑
)
<64> tRAL
(2 + w
CP
+ w
DA
)T – 10
ns
CAS-RAS precharge time <66> tCRP (1 + wRP)T – 10 ns
CAS hold t i m e <67> tCSH
(1.5 + w
RH
+ w
DA
)
T –
10
ns
WE setup time (to CA S ↓) <68> tRCS
(2 + w
RP
+ w
RH
)T – 10
ns
WE hold ti m e (f rom RAS ↑) <69> tRRH 0.5T – 10 ns
WE hold ti m e (f rom CAS ↑) <70> tRCH 1.5T – 10 ns
RAS access time <73> tRAC
(2 + w
RH
+ w
DA
)
T –
28
ns
Access ti m e from colum n address <74> tAA (1.5 + wDA)T – 28 ns
CAS access time <75> tCAC (1 + wDA)T – 28 ns
Delay ti m e from RAS t o column address <76> t RAD (0.5 + wRH)T – 10 ns
RAS-CAS del ay time <77> tRCD (1 + wRH)T – 10 ns
Output buffer turn-off delay time (from
OE) <78> tOEZ 0ns
Access ti m e from CAS precharge <80> tACP
(1.5 + w
CP
+ w
DA
)
T –
28
ns
CAS precharge time <81> tCP (0.5 + wCP)T – 10 ns
RAS hold t i me for CAS precharge <83> t RHCP
(2 + w
CP
+ w
DA
)T – 10
ns
Read cycle time <93> tHPC
(1 + w
DA
+ w
CP
)T – 10
ns
RAS pulse width <94> tRASP
(2.5 + w
RH
+ w
DA
)
T –
10
ns
CAS pulse width <95> tHCAS (0.5 + wDA)T – 10 ns
Off-page <96> tOCH1
(2 + w
RH
+ w
DA
)T – 10
nsCAS hold t i m e from OE
On-page <97> tOCH2 (0.5 + wDA)T – 10 ns
Data input hol d time (f rom CAS ↓) <98> tDHC 0ns
Remarks 1. T = tCYK
2. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6. i: the number of idle states that are inserted when a write cycle follows a read cycle.
Data Sheet U13995EJ2V0DS00 53
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(e) Read timing (EDO DRAM) (2/3)
Parameter Symbol Condition MIN. MAX. Unit
Off-page <99> tOEA1 (2 + wRP + wRH + wDA)T
– 28 nsOutput enable ac cess
time
On-page <100> tOEA2
(1 + w
CP
+ w
DA
)
T –
28
ns
Remarks 1. T = tCYK
2. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
Data Sheet U13995EJ2V0DS00
54
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(e) Read timing (EDO DRAM) (3/3)
Note For on-page access from another cycle during the RASn low-level signal.
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
TRPW T1 TRHW T2 TDAW TCPW TB TDAW TE
<56> <57> <59>
<58>
<76> <64>
<94><61>
<67> <83>
<77> <95> <81> <75><66>
<93> <95>
<80>
<97>
<74> <27> <78>
Data
<74>
Data
<70>
<69>
<68>
<96> <100> <26> <37>
<27><98>
<26>
<75>
<73>
<99>
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
UCAS (Output)
LCAS (Output)
WE (Output)
OE (Output)
D0 to D15 (I/O)
BCYST (Output)
WAIT (Input)
Row address
Column address
Column address
Note
Data Sheet U13995EJ2V0DS00 55
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
[MEMO]
Data Sheet U13995EJ2V0DS00
56
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(f) Write timing (EDO DRAM) (1/2)
Parameter Symbol Condition MIN. MAX. Unit
Row address s et up time <56> tASR (0.5 + wRP)T – 10 ns
Row address hold time <57> tRAH (0.5 + wRH)T – 10 ns
Column address setup time <58> tASC 0.5T – 10 ns
Column address hol d time <59> tCAH (0.5 + wDA)T – 10 ns
RAS precharge time <61> tRP (0.5 + wRP)T – 10 ns
RAS hold t i m e <63> tRSH (1.5 + wDA)T – 10 ns
Column address read time
(from RAS ↑)<64> tRAL (2 + wCP + wDA)T – 10 ns
CAS-RAS precharge time <66> tCRP (1 + wRP)T – 10 ns
CAS hold t i m e <67> tCSH
(1.5 + w
RH
+ w
DA
)
T –
10
ns
Delay time from RAS to column address
<76> tRAD (0.5 + wRH)T – 10 ns
RAS-CAS del ay time <77> tRCD (1 + wRH)T – 10 ns
CAS precharge time <81> tCP (0.5 + wCP)T – 10 ns
RAS hold t i me for CAS precharge <83> t RHCP (2 + wCP + wDA)T – 10 ns
WE hold ti m e (f rom CAS ↓) <85> tWCH (1 + wDA)T – 10 ns
Data hold time (from CAS ↓) <87> tDH (0.5 + wDA)T – 10 ns
WE read tim e
(from RAS ↑)On-page <88> tRWL wCP = 0 (1.5 + wDA)T – 10 ns
WE read tim e
(from CAS ↑)On-page <89> tCWL wCP = 0 (0.5 + wDA)T – 10 ns
WE pulse wi dt h On-page <92> tWP wCP = 0 (1 + wDA)T – 10 ns
Write cycle time <93> tHPC (1 + wDA + wCP)T – 10 ns
RAS pulse width <94> tRASP
(2.5 + w
RH
+ w
DA
)
T –
10
ns
CAS pulse width <95> tHCAS (0.5 + wDA)T – 10 ns
Off-page <101> tWCS1
(1 + w
RP
+ w
RH
)
T –
10
nsWE set up t i m e
(to CAS ↓)On-page <102> tWCS2 wCP ≥ 1w
CPT – 10 ns
Off-page <103> tDS1
(1.5 + w
RP
+ w
RH
)
T –
10
nsData setup time
(to CAS ↓)On-page <104> tDS2 (0.5 + wCP)T – 10 ns
Remarks 1. T = tCYK
2. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
Data Sheet U13995EJ2V0DS00 57
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(f) Write timing (EDO DRAM) (2/2)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
TRPW T1 TRHW T2 TDAW TCPW TB TDAW TE
<56> <57> <59>
<58>
<58> <59>
<76> <64>
<94><61>
<67> <83>
<77> <95> <81> <63><66>
<93> <95>
<89> <88>
<102>
<101> <92>
<85>
<85>
<103> <87> <104> <87>
Data Data
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
UCAS (Output)
LCAS (Output)
RD (Output)
OE (Output)
WE (Output)
D0 to D15 (I/O)
BCYST (Output)
WAIT (Input)
Row address
Column address
Column address
Data Sheet U13995EJ2V0DS00
58
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) →
→→
→ external I/O transfer) (1/3)
Parameter Symbol Condition MIN. MAX. Unit
WAIT setup time (to CLKOUT ↓) <24> tSWK 15 ns
WAIT hold time (from CLKOUT ↓) <25> tHKW 2ns
Delay time from OE ↑ to data out put <37> tDRDOD (0.5 + i)T – 10 ns
Delay ti m e from address to IOWR ↓<41> tDAWR (0.5 + wRP)T – 10 ns
Address setup ti m e (to IOWR ↑) <42> tSAWR (2 + wRP + wRH + wDA
+ w)T – 10 ns
Delay time from IOWR ↑ to address <43> tDWRA 0.5T – 10 ns
wF = 0 0 nsDelay time from IOWR ↑ to RD ↑<48> tDWRRD
wF = 1 T – 10 ns
IOWR low-level widt h <50> t WWRL (2 + wRH + wDA + w)T
– 10 ns
Row address s et up time <56> tASR (0.5 + wRP)T – 10 ns
Row address hold time <57> tRAH (0.5 + wRH)T – 10 ns
Column address setup time <58> tASC 0.5T – 10 ns
Column address hol d time <59> tCAH (1.5 + wDA + wF + w)T
– 10 ns
Read/write cycle time <60> tRC (3 + wRP + wRH + wDA +
wF + w)T – 10 ns
RAS precharge time <61> tRP (0.5 + wRP)T – 10 ns
RAS hold t i m e <63> tRSH (1.5 + wDA + wF + w)T
– 10 ns
Column address read tim e for RAS <64> tRAL
(2 + w
CP
+ w
DA
+ w
F
+
w)T – 10
ns
CAS pulse width <65> tCAS (1 + wDA + wF + w)T
– 10 ns
CAS-RAS precharge time <66> tCRP (1 + wRP)T – 10 ns
CAS hold t i m e <67> tCSH
(2 + w
RH
+ w
DA
+ w
F
+
w)
T –
10
ns
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5.w
DA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
7. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer.
8. i: the number of idle states that are inserted when a write cycle follows a read cycle.
Data Sheet U13995EJ2V0DS00 59
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) →
→→
→ external I/O transfer) (2/3)
Parameter Symbol Condition MIN. MAX. Unit
WE setup time (to CA S ↓) <68> tRCS (2 + wRP + wRH)T – 10 ns
WE hold ti m e (f rom RAS ↑) <69> tRRH 0.5T – 10 ns
WE hold ti m e (f rom CAS ↑) <70> tRCH 1.5T – 10 ns
CAS precharge time <71> tCPN (2 + wRP + wRH)T – 10 ns
Delay ti m e from RAS t o column address <76> tRAD (0.5 + wRH)T – 10 ns
RAS-CAS del ay time <77> tRCD (1 + wRH)T – 10 ns
Output buffer turn-off delay time (from
OE ↑)<78> tOEZ 0ns
Output buffer turn-off delay time (from
CAS ↑)<79> tOFF 0ns
CAS precharge time <81> tCP (0.5 + wCP)T – 10 ns
High-speed page mode cycle time <82> tPC
(2 + w
CP
+ w
DA
+ w
F
+ w)
T
–
10
ns
RAS hold t i me for CAS precharge <83> t RHCP
(2.5 + w
CP
+ w
DA
+ w
F
+ w)
T
–
10
ns
RAS pulse width <94> tRASP
(2.5 + w
RH
+ w
DA
+ w
F
+ w)T
– 10
ns
Off-page <96> tOCH1 (2.5 + wRP + wRH + wDA +
wF + w)T – 10 ns
CAS hold t i m e from OE
(from CAS ↑)
On-page <97> tOCH2
(1.5 + w
CP
+ w
DA
+ w
F
+ w)
T
–
10
ns
Delay time from DMAAKm ↓ to CAS ↓<105> tDDACS (1.5 + wRH)T – 10 ns
Delay time from IOWR ↓ to CAS ↓<106> tDRDCS (1 + wRH)T – 10 ns
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
7. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer.
8. m = 0 to 3
Data Sheet U13995EJ2V0DS00
60
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) →
→→
→ external I/O transfer) (3/3)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
Number of waits that are inserted for a source-side access during a DMA flyby transfer: 0
2. The broken lines indicate high impedance.
3. n = 0 to 7, m = 0 to 3
TRPW
T1
TRHW
T2
TDAW
TW T3
TCPW
TO1 TO2TW
TDAW
<56> <57>
<58> <59>
<76>
<61> <60>
<94> <64>
<77> <65> <83> <63><81><67><66>
<71> <82>
<96>
<105>
<68>
<69>
<70>
<79>
<48> <97>
<106>
<42>
<41> <50>
<43> <78>
<37>
<24>
<25>
<24> <25> <25>
<24>
Data Data
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
UCAS (Output)
LCAS (Output)
RD (Output)
OE (Output)
DMAAKm (Output)
WE (Output)
IORD (Output)
IOWR (Output)
D0 to D15 (I/O)
WAIT (Input)
BCYST (Output)
Row address Column address Column address
Data Sheet U13995EJ2V0DS00 61
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(h) DMA flyby transfer timing (external I/O →
→→
→ DRAM (EDO, high-speed page) transfer) (1/3)
Parameter Symbol Condition MIN. MAX. Unit
WAIT setup time (to CLKOUT ↓) <24> tSWK 15 ns
WAIT hold time (from CLKOUT ↓) <25> tHKW 2ns
IORD low-level widt h < 32> tWRDL (2 + wRH + wDA + wF + w)T – 10 ns
IORD high-level widt h <33> tWRDH T – 10 ns
Delay time from address to IORD ↑<34> tDARD 0.5T – 10 ns
Delay time from IORD ↑ to address <35> t DRDA (0. 5 + i )T – 10 ns
Row address s et up time <56> tASR (0.5 + wRP)T – 10 ns
Row address hold time <57> tRAH (0.5 + wRH)T – 10 ns
Column address setup time <58> tASC 0.5T – 10 ns
Column address hol d time <59> tCAH (1.5 + wDA + wF)T – 10 ns
Read/write cycle time <60> tRC (3 + wRP + wRH + wDA + wF + w)T
– 10 ns
RAS precharge time <61> tRP (0.5 + wRP)T – 10 ns
RAS hold t i m e <63> tRSH (1.5 + wDA + wF)T – 10 ns
Column address read tim e for RAS <64> tRAL (2 + wCP + wDA + wF + w)T – 10 ns
CAS pulse width <65> tCAS (1 + wDA + wF)T – 10 ns
CAS-RAS precharge time <66> tCRP (1 + wRP)T – 10 ns
CAS hold t i m e <67> tCSH (2 + wRH + wDA + wF + w)T – 10 ns
CAS precharge time <71> tCPN (2 + wRP + wRH + w)T – 10 ns
Delay ti m e from RAS t o column address <76> tRAD (0.5 + wRH)T – 10 ns
RAS-CAS del ay time <77> tRCD (1 + wRH + w)T – 10 ns
CAS precharge time <81> tCP (0.5 + wCP + w)T – 10 ns
High-speed page mode cycle time <82> tPC (2 + wCP + wDA + wF + w)T – 10 ns
RAS hold t i me for CAS precharge <83> t RHCP (2.5 + wCP + wDA + w)T – 10 ns
WE hold ti m e (f rom CAS ↓) <85> tWCH (1 + wDA)T – 10 ns
WE read tim e (from RAS ↑) <88> tRWL wCP = 0 (1.5 + wDA + w)T – 10 ns
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
7. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer.
8. i: the number of idle states that are inserted when a write cycle follows a read cycle.
9. n = 0 to 7
Data Sheet U13995EJ2V0DS00
62
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(h) DMA flyby transfer timing (external I/O →
→→
→ DRAM (EDO, high-speed page) transfer) (2/3)
Parameter Symbol Condition MIN. MAX. Unit
WE read tim e (from CAS ↑) <89> tCWL wCP = 0 (1 + wDA + w)T – 10 ns
WE pulse wi dt h <92> tWP wCP = 0 (1 + wDA + w)T – 10 ns
RAS pulse width <94> tRASP (2.5 + wRH + wDA + wF + w)T – 10 ns
Off-page <101> tWCS1 wCP = 0 (1 + wRH + wRP + w)T – 10 nsWE setup tim e
(to CAS ↓)On-page <102> tWCS2 wCP ≥ 1w
CPT – 10 ns
Delay time from DMAAKm ↓ to CAS ↓<105> tDDACS (1.5 + wRH + w)T – 10 ns
Delay time from IORD ↓ to CAS ↓<106> tDRDCS (1 + wRH + w)T – 10 ns
Delay time from WE ↑ to IORD ↑<107> tDWERD wF = 0 0 ns
wF = 1 T – 10 ns
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
7. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer.
8. m = 0 to 3
Data Sheet U13995EJ2V0DS00 63
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(h) DMA flyby transfer timing (external I/O →
→→
→ DRAM (EDO, high-speed page) transfer) (3/3)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
Number of waits that are inserted for a source-side access during a DMA flyby transfer: 0
2. The broken lines indicate high impedance.
3. n = 0 to 7, m = 0 to 3
TRPW T1 TRHW TW T2 TDAW T3 TCPW TW TO2TDAWTO1
<56> <57> <58>
<76>
<61> <60>
<94> <64>
<77> <65> <63><81><67><66>
<71> <82>
<101>
<105>
<83>
<85> <89>
<106>
<34> <107>
<33>
<24>
<25><24> <25>
<24>
Data Data
<59>
<88>
<102>
<92>
<35>
<32>
<25>
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
UCAS (Output)
LCAS (Output)
RD (Output)
OE (Output)
DMAAKm (Output)
WE (Output)
IOWR (Output)
IORD (Output)
D0 to D15 (I/O)
WAIT (Input)
BCYST (Output)
Row address Column address Column address
Data Sheet U13995EJ2V0DS00
64
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(i) CBR refresh timing
Parameter Symbol Condition MIN. MAX. Unit
RAS precharge time <61> tRP (1.5 + wRRW)T – 10 ns
RAS pulse width <62> tRAS (1.5 + wRCWNote)T – 10 ns
CAS hold t i m e <108> tCHR (1.5 + wRCWNote)T – 10 ns
REFRQ pulse wi dt h <109> tWRFL (3 + wRRW + wRCWNote)T – 10 ns
RAS precharge CAS hold ti m e <110> tRPC (0.5 + wRRW)T – 10 ns
REFRQ acti ve delay t i m e
(from CLKO UT ↓)<111> tDKRF 210ns
REFRQ inact i ve delay t i m e
(from CLKO UT ↓)<112> tHKRF 210ns
CAS setup time <113> tCSR T – 10 ns
Note At least one clock cycle is inserted by default for wRCW regardless of the settings of the RCW0 to RCW2 bits
of the RWC register.
Remarks 1. T = tCYK
2. wRRW: the number of waits due to the RRW0 and RRW1 bits of the RWC register.
3. wRCW: the number of waits due to the RCW0 to RCW2 bits of the RWC register.
TI
REFRQ (Output)
T3TRCWTRCW
Note
T2T1TRRW
<109>
<111> <112>
RASn (Output)
<62>
UCAS (Output)
<108>
<110>
<61>
<113><110>
LCAS (Output)
CLKOUT (Output)
Note This TRCW is always inserted regardless of the settings of the RCW0 to RCW2 bits of the RWC register.
Remarks 1. This is the timing for the following case.
Number of waits due to the RRW0 and RRW1 bits of the RWC register (TRRW): 1
Number of waits due to the RCW0 to RCW2 bits of the RWC register (TRCW): 2
2. n = 0 to 7
Data Sheet U13995EJ2V0DS00 65
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(j) CBR self-refresh timing
Parameter Symbol Condition MIN. MAX. Unit
REFRQ acti ve delay t i m e
(from CLKO UT ↓)<111> tDKRF 210ns
REFRQ inact i ve delay t i m e
(from CLKO UT ↓)<112> tHKRF 210ns
CAS hold t i m e <114> tCHS −5ns
RAS precharge time <115> t RPS (1 + 2wSRW)T – 10 ns
Remarks 1. T = tCYK
2. wSRW: the number of waits due to the SRW0 to SRW2 bits of the RWC register.
Remarks 1. This is the timing for the following case.
Number of waits due to the RRW0 and RRW1 bits of the RWC register (TRRW): 1
Number of waits due to the RCW0 to RCW2 bits of the RWC register (TRCW): 1
Number of waits due to the SRW0 to SRW2 bits of the RWC register (TSRW): 2
2. The broken lines indicate high impedance.
3. n = 0 to 7
<111>
THTHTHTRRW TSRWTITHTRCW TSRW
Output signals
other than above
<115>
<112>
<114>
CLKOUT (Output)
REFRQ (Output)
RASn (Output)
UCAS (Output)
LCAS (Output)
Data Sheet U13995EJ2V0DS00
66
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(7) DMAC timing
Parameter Symbol Condition MIN. MAX. Unit
DMARQn setup tim e (to CLKOUT ↑) <116> tSDRK 15 ns
<117> tHKDR1 2nsDMARQn hold t i me (from CLK OUT ↑)
<118> tHKDR2 Until DMAAKn ↓ns
DMAAKn output delay time
(from CLKO UT ↓)<119> tDKDA 210ns
DMAAKn output hold time
(from CLKO UT ↓)<120> tHKDA 210ns
TCn output delay time
(from CLKO UT ↓)<121> tDKTC 210ns
TCn output hold t i m e
(from CLKO UT ↓)<122> tHKTC 210ns
Remark n = 0 to 3
Remark n = 0 to 3
<121>
DMARQn (Input)
DMAAKn (Output)
TCn (Output)
<122>
<120>
<119>
<118>
<117>
<116>
<116>
CLKOUT (Output)
Data Sheet U13995EJ2V0DS00 67
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
[MEMO]
Data Sheet U13995EJ2V0DS00
68
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(8) Bus hold timing (1/2)
Parameter Symbol Condition MIN. MAX. Unit
HLDRQ setup t i me (to CLKOUT ↑) <123> tSHRK 15 ns
HLDRQ hold tim e (from CLKOUT ↑) <124> tHKHR 2ns
Delay time from CLKOUT ↓ to HLDAK <125> tDKHA 210ns
HLDRQ high-level wi dth <126> tWHQH T + 17 ns
HLDAK low-l evel widt h <127> tWHAL T – 8 ns
Delay time from CLKOUT ↓ to bus float <128> tDKCF 10 ns
Delay time from HLDAK ↑ to bus output <129> tDHAC 0ns
Delay time from HLDRQ ↓ to HLDAK ↓<130> tDHQHA1 2.5T ns
Delay time from HLDRQ ↑ to HLDAK ↑<131> tDHQHA2 0.5T 1.5T ns
Remark T = tCYK
Data Sheet U13995EJ2V0DS00 69
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(8) Bus hold timing (2/2)
Remarks 1. The broken lines indicate high impedance.
2. n = 0 to 7
T1 T2 T3 TI TH TH TH TI T1
A0 to A23 (Output)
D0 to D15 (I/O)
<123>
<124>
<124>
<123>
<123> <123> <126>
<130>
<125>
<127>
<125>
<128> <129>
<131>
Address
Undefined
Data
CLKOUT (Output)
HLDRQ (Input)
HLDAK (Output)
CSn/RASn (Output)
BCYST (Output)
RD (Output)
WE (Output)
WAIT (Input)
UCAS (Output)
LCAS (Output)
Data Sheet U13995EJ2V0DS00
70
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(9) Interrupt timing
Parameter Symbol Condition MIN. MAX. Unit
NMI high-l evel width <132> tWNIH 500 ns
NMI low-l evel widt h <133> tWNIL 500 ns
INTPn high-level width < 134> tWITH 4T + 10 ns
INTPn low-level width <135> tWITL 4T + 10 ns
Remarks 1. n = 100 to 103, 110 to 113, 120 to 123, 130 to 133, 140 to 143, or 150 to 153
2. T = tCYK
NMI (Input)
<132> <133>
INTPn (Input)
<134> <135>
Remark n = 100 to 103, 110 to 113, 120 to 123, 130 to 133, 140 to 143, or 150 to 153
(10) RPU timing
Parameter Symbol Condition MIN. MAX. Unit
TI1n high-lev el wi dt h <136> tWTIH 3T + 18 ns
TI1n low-lev el wi dt h <137> tWTIL 3T + 18 ns
TCLR1n high-level wi dth <138> tWTCH 3T + 18 ns
TCLR1n low-level wi dth <139> tWTCL 3T + 18 ns
Remarks 1. n = 0 to 5
2. T = tCYK
TI1n (Input)
<136> <137>
TCLR1n (Input)
<138> <139>
Remark n = 0 to 5
Data Sheet U13995EJ2V0DS00 71
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(11) UART0, UART1 timing (clock-synchronized or master mode only)
Parameter Symbol Condition MIN. MAX. Unit
SCKn cycle <140> tCYSK0 Output 250 ns
SCKn high-level width <141> tWSK0H Output 0.5tCYSK0 – 20 ns
SCKn low-l evel widt h <142> t WSK0L Output 0.5tCYSK0 – 20 ns
RXDn setup time (to SCKn ↑) <143> tSRXSK 30 ns
RXDn hold ti me (from S CKn ↑) <144> tHSKRX 0ns
TXDn output del ay time (from SCKn ↓) <145> tDSKTX 20 ns
TXDn output hol d time (from SCKn ↑) <146> tHSKTX 0.5tCYSK0 – 5 ns
Remark n = 0, 1
SCKn (I/O)
<142>
<140>
<141>
RXDn (Input)
<143> <144>
Input data
TXDn (Output)
<145>
Output data
<146>
Remarks 1. The broken lines indicate high impedance.
2. n = 0, 1
Data Sheet U13995EJ2V0DS00
72
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
(12) CSI0 to CSI3 timing
(a) Master mode
Parameter Symbol Condition MIN. MAX. Unit
SCKn cycle <147> tCYSK1 Output 100 ns
SCKn high-level width <148> tWSK1H Output 0.5tCYSK1 – 20 ns
SCKn low-l evel widt h <149> t WSK1L Output 0.5tCYSK1 – 20 ns
SIn setup time (to SCKn ↑) <150> tSSISK 30 ns
SIn hold t i me (from SCK n ↑) <151> tHSKSI 0ns
SOn output delay tim e (from SCKn ↓) <152> tDSKSO 20 ns
SOn output hold time (f rom SCKn ↑) <153> tHSKSO 0.5tCYSK1 – 5 ns
Remark n = 0 to 3
(b) Slave mode
Parameter Symbol Condition MIN. MAX. Unit
SCKn cycle <147> tCYSK1 Input 100 ns
SCKn high-level width <148> tWSK1H Input 30 ns
SCKn low-l evel widt h <149> t WSK1L Input 30 ns
SIn setup time (to SCKn ↑) <150> tSSISK 10 ns
SIn hold t i me (from SCK n ↑) <151> tHSKSI 10 ns
SOn output delay tim e (from SCKn ↓) <152> tDSKSO 30 ns
SOn output hold time (f rom SCKn ↑) <153> tHSKSO tWSK1H ns
Remark n = 0 to 3
SCKn (I/O)
<149>
<147>
<148>
Sln (Input)
<150> <151>
Input data
SOn (Output)
<152>
Output data
<153>
Remarks 1. The broken lines indicate high impedance.
2. n = 0 to 3
Data Sheet U13995EJ2V0DS00 73
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
A/D Converter Characteristics (TA = –40 to +70°
°°
°C ...
µ
µµ
µ
PD703100-40,
TA = –40 to +85°
°°
°C ...
µ
µµ
µ
PD703100-33, 703101-33, 703102-33,
VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 V ±
±±
±10%, VSS = 0 V,
HVDD – 0.5 V ≤
≤≤
≤ AVDD ≤
≤≤
≤ HVDD, output pin load capacitance: CL = 50 pF)
Parameter Symbol Condition MIN. TYP. MAX. Unit
Resolution – 10 bit
Total error – ±4LSB
Quantizat i on error – ±1/2 LSB
Conversion time tCONV 510
µ
s
Sampling time tSAMP Conversion
clockNote/6 ns
Zero sca l e error – ±4LSB
Scale error – ±4LSB
Linearity error – ±3LSB
Analog input voltage VIAN −0.3 AVREF + 0.3 V
Analog input resist ance RAN 2M
Ω
AVREF input voltage A V REF AVREF = AVDD 4.5 5.5 V
AVREF input current AIREF 2.0 mA
AVDD current AIDD 6mA
Note Conversion clock is the number of clocks set by the ADM1 register.
Data Sheet U13995EJ2V0DS00
74
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
4. PACKAGE DRAWING
108 73
136
109
144
72
37
144-PIN PLASTIC LQFP (FINE PITCH) (20x20)
ITEM MILLIMETERS
NOTE
A 22.0±0.2
B 20.0±0.2
C 20.0±0.2
D
F 1.25
22.0±0.2
S144GJ-50-UEN
S 1.5±0.1
K 1.0±0.2
L 0.5±0.2
R3°+4°
−3°
G 1.25
H 0.22±0.05
I 0.08
J 0.5 (T.P.)
M 0.17
N 0.08
P 1.4
Q 0.10±0.05
+0.03
−0.07
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
S
S
M
detail of lead end
IJ
F
GH
QR
PK
M
L
N
CD
S
A
B
Data Sheet U13995EJ2V0DS00 75
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
5. RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the following recom m ended conditions.
For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales
representative.
Table 5-1. Surface Mounting Type Soldering Conditions
µ
µµ
µ
PD703100GJ-40-UEN: 144-pin plastic LQFP (fine pitch) (20 ×
××
× 20)
µ
µµ
µ
PD703100GJ-33-UEN: 144-pin plastic LQFP (fine pitch) (20 ×
××
× 20)
µ
µµ
µ
PD703101GJ-33-xxx-UEN: 144-pin plastic LQFP (fine pitch) (20 ×
××
× 20)
µ
µµ
µ
PD703102GJ-33-xxx-UEN: 144-pin plastic LQFP (fine pitch) (20 ×
××
× 20)
Soldering Method Soldering Condit i ons Recommended
Condition
Symbol
Infrared refl ow P ackage peak t em perature: 235°C, Time: 30 sec. Max. (at 210°C or higher), Count:
two times or less , Expos ure l imit: 3 daysNote (after that, prebake at 125°C for 10 hours ) IR35-103-2
VPS Pac kage peak tem perat ure: 215°C, Time: 25 to 40 sec. Max. (at 200°C or higher),
Count: two times or l ess, E xposure lim i t: 3 daysNote (after that , prebake at 125°C for 10
hours)
VP15-103-2
Partial heating Pin temperat ure: 300°C Max., Time: 3 sec. M ax . (per pin row) –
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Data Sheet U13995EJ2V0DS00
76
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Related documents
µ
PD70F3102-33 Data Sheet (U13844E)
µ
PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Data Sheet (U14168E)
µ
PD70F3102A-33 Data Sheet (U13845E)
Reference materials Electrical Characteristics for Microcomputer (U15170JNote)
Note This document number is that of Japanese version.
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
V850E/MS1 and V850 Family are trademarks of NEC Corporation.
Data Sheet U13995EJ2V0DS00 77
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.l.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
NEC Electronics (France) S.A.
Madrid Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP Brasil
Tel: 55-11-6462-6810
Fax: 55-11-6462-6829
J00.7
µ
µµ
µ
PD703100-33, 703100-40, 703101-33, 703102-33
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
License not needed:
µ
PD703100-33, 703100-40
The customer must judge the need for license:
µ
PD703101-33, 703102-33
M8E 00. 4
The information in this document is current as of August, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
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