V :1.575V
400mA
out1
SW1
FB1
SW2
ADJ2
DEF_1
10 Fm
VIN2.5V – 6V
VIN
EN_1
EN_2
MODE/
DATA
TPS62401
GND
2.2 Hm
10 Fm
2.2 HmV :1.8V
600mA
out2
10 Fm
0
10
20
30
40
50
60
70
80
90
100
0.01 0.1 1 10 100 1000
IOUTmA
Efficiency
V
IN =3.6V
MODE/DATA =0
VOUT1=1.575V
VOUT2 =1.8V
TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
www.ti.com
SLVS681E –JUNE 2006–REVISED APRIL 2010
2.25MHz 400mA/600mA Dual Step-Down Converter In Small 3x3mm QFN Package
Check for Samples: TPS62400,TPS62401,TPS62402,TPS62403,TPS62404
1FEATURES DESCRIPTION
2• High Efficiency—Up to 95%
• VIN Range From 2.5 V to 6 V The TPS6240x device series are synchronous dual
step-down DC-DC converters optimized for battery
• 2.25 MHz Fixed Frequency Operation powered portable applications. They provide two
• Output Current 400 mA and 600 mA independent output voltage rails powered by 1-cell
• Adjustable Output Voltage From 0.6V to VIN Li-Ion or 3-cell NiMH/NiCD batteries. The devices are
also suitable to operate from a standard 3.3V or 5V
• Pin Selectable Output Voltage Supports voltage rail.
Simple Dynamic Voltage Scaling With an input voltage range of 2.5V to 6V the
• EasyScale™ Optional One-Pin Serial Interface TPS62400 is ideal to power portable applications like
• Power Save Mode at Light Load Currents smart phones, PDAs and other portable equipment.
• 180° Out of Phase Operation With the EasyScale™ serial interface the output
• Output Voltage Accuracy in PWM Mode ±1% voltages can be modified during operation. The fixed
• Typical 32-mA Quiescent Current for Both output voltage versions TPS62401, TPS62402,
Converters TPS62403, and TPS62404 support one pin controlled
simple Dynamic Voltage Scaling for low power
• 100% Duty Cycle for Lowest Dropout processors.
• Available in a 10-Pin QFN (3×3mm) The TPS6240x operates at 2.25MHz fixed switching
frequency and enters the power save mode operation
APPLICATIONS at light load currents to maintain high efficiency over
• Cell Phones, Smart-phones the entire load current range. For low noise
• PDAs, Pocket PCs applications the devices can be forced into fixed
• OMAP™ and Low Power DSP Supply frequency PWM mode by pulling the MODE/DATA
• Portable Media Players pin high. In the shutdown mode, the current
consumption is reduced to 1.2mA, typical. The
• Digital Radio devices allow the use of small inductors and
• Digital Cameras capacitors to achieve a small solution size.
The TPS62400 is available in a 10-pin leadless
package (3×3mm QFN)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2EasyScale, OMAP, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2006–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
SLVS681E –JUNE 2006–REVISED APRIL 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
PART DEFAULT OUTPUT OUTPUT QFN(2) PACKAGE
TAORDERING(3)
NUMBER VOLTAGE (1) CURRENT PACKAGE MARKING
OUT1 400mA
TPS62400 Adjustable DRC TPS62400DRC BQE
OUT2 600mA
DEF_1 = High 1.1V
Fixed
OUT1 400mA
default
TPS62401 DEF_1 = Low 1.575V DRC TPS62401DRC BRN
OUT2 Fixed default 1.8V 600mA
OUT1 DEF_1 = High 1.8V
Fixed 400mA
default
TPS62402 DEF_1 = Low 1.2V DRC TPS62402DRC BYH
–40°C to 85°C OUT2 Fixed default 3.3V 600mA
DEF_1 = High 1.1V
Fixed
OUT1 400mA
default
TPS62403 DEF_1 = Low 1.575V DRC TPS62403DRC BYI
OUT2 Fixed default 2.8V 600mA
DEF_1 = High 1.9V
Fixed
OUT1 400mA
default
TPS62404 DEF_1 = Low 1.2V DRC TPS62404DRC PTVI
OUT2 Fixed default 3.3V 600mA
(1) Contact TI for other fixed output voltage options.
(2) The DRC (QFN 10 PIN) package is available in tape on reel. Add R suffix to order quantities of 3000 parts per reel, T suffix for 250 parts
per reel.
(3) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE UNIT
Input voltage range on VIN (2) –0.3 to 7 V
Voltage range on EN, MODE/DATA, DEF_1 –0.3 to VIN +0.3, ≤7 V
current into MODE/DATA ≤0.5 mA
Voltage on SW1, SW2 –0.3 to 7 V
Voltage on ADJ2, FB1 –0.3 to VIN +0.3, ≤7 V
HBM Human body model 2 kV
ESD Charge device model CDM 1 kV
rating(3) Machine model 200 V
TJ(max) Maximum operating junction temperature 150 °C
TAOperating ambient temperature range –40 to 85 °C
Tstg Storage temperature range –65 to 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) The human body model is a 100pF capacitor discharged through a 1.5kΩresistor into each pin. The machine model is a 200pF
capacitor discharged directly into each pin.
DISSIPATION RATINGS
PACKAGE RqJA POWER RATING FOR TA≤25°C DERATING FACTOR ABOVE TA= 25°C
DRC 49°C/W 2050mW 21mW/°C
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Product Folder Link(s): TPS62400 TPS62401 TPS62402 TPS62403 TPS62404
TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
www.ti.com
SLVS681E –JUNE 2006–REVISED APRIL 2010
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
VIN Supply voltage 2.5 6 V
Output voltage range for adjustable voltage 0.6 VIN V
TAOperating ambient temperature -40 85 °C
TJOperating junction temperature -40 125 °C
ELECTRICAL CHARACTERISTICS
VIN = 3.6V, VOUT = 1.8V, EN = VIN, MODE = GND, L = 2.2mH, COUT = 20mF, TA= –40°C to 85°C typical values are at
TA= 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
VIN Input voltage range 2.5 6.0 V
One converter, IOUT = 0mA. PFM mode 19 29 mA
enabled (Mode = 0) device not switching,
EN1 = 1 OR EN2 = 1
Two converter, IOUT = 0mA. PFM mode 32 48 mA
enabled (Mode = 0) device not switching,
IQOperating quiescent current EN1 = 1 AND EN2 = 1
IOUT = 0mA, MODE/DATA = GND, for one 23 mA
converter, VOUT 1.575V(1)
IOUT = 0mA, MODE/DATA = VIN, for one 3.6 mA
converter, VOUT 1.575V (1)
EN1, EN2 = GND, VIN = 3.6V(2) 1.2 3
ISD Shutdown current mA
EN1, EN2 = GND, VIN ramped from 0V to 0.1 1
3.6V(3)
Falling 1.5 2.35
VUVLO Undervoltage lockout threshold V
Rising 2.4
ENABLE EN1, EN2
VIH High-level input voltage, EN1, EN2 1.2 VIN V
VIL Low-level input voltage, EN1, EN2 0 0.4 V
IIN Input bias current, EN1, EN2 EN1, EN2 = GND or VIN 0.05 1.0 mA
DEF_1 INPUT
DEF_1 pin is a digital input at TPS62401
VDEF_1H DEF_1 high level input voltage 0.9 VIN V
fixed output voltage option
DEF_1 pin is a digital input at TPS62401
VDEF_1L DEF_1 low level input voltage 0 0.4 V
fixed output voltage option
IIN Input bias current DEF_1 DEF_1 GND or VIN 0.01 1.0 mA
MODE/DATA
VIH High-level input voltage, MODE/DATA 1.2 VIN V
VIL Low-level input voltage, MODE/DATA 0 0.4 V
IIN Input bias current, MODE/DATA MODE/DATA = GND or VIN 0.01 1.0 mA
VOH Acknowledge output voltage high Open drain, via external pullup resistor VIN V
VOL Acknowledge output voltage low Open drain, sink current 500mA 0 0.4 V
INTERFACE TIMING
tStart Start time 2 ms
tH_LB High time low bit, logic 0 detection Signal level on MODE/DATA pin is > 1.2V 2 200 ms
(1) Device is switching with no load on the output, L = 3.3mH, value includes losses of the coil
(2) These values are valid after the device has been already enabled one time (EN1 or EN2 = high) and supply voltage VIN has not
powered down.
(3) These values are valid when the device is disabled (EN1 and EN2 low) and supply voltage VIN is powered up. The values remain valid
until the device has been enabled first time (EN1 or EN2 = high). After first enable, Note 3 becomes valid.
Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TPS62400 TPS62401 TPS62402 TPS62403 TPS62404
TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
SLVS681E –JUNE 2006–REVISED APRIL 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.6V, VOUT = 1.8V, EN = VIN, MODE = GND, L = 2.2mH, COUT = 20mF, TA= –40°C to 85°C typical values are at
TA= 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
2x
tL_LB Low time low bit, logic 0 detection Signal level on MODE/DATA pin < 0.4V 400 ms
tH_LB
tL_HB Low time high bit, logic 1 detection Signal level on MODE/DATA pin < 0.4V 2 200 ms
2x
tH_HB High time high bit, logic 1 detection Signal level on MODE/DATA pin is > 1.2V 400 ms
tL_HB
TEOS End of Stream TEOS 2ms
Duration of acknowledge condition
tACKN (MODE/DATE line pulled low by the VIN 2.5V to 6V 400 520 ms
device)
tvalACK Acknowledge valid time 2 ms
ttimeout Timeout for entering power save mode MODE/DATA Pin changes from high to low 520 ms
POWER SWITCH
P-Channel MOSFET on-resistance,
RDS(ON) VIN = VGS = 3.6V 280 620 mΩ
Converter 1,2
ILK_PMOS P-Channel leakage current VDS = 6.0V 1 mA
N-Channel MOSFET on-resistance
RDS(ON) VIN = VGS = 3.6V 200 450 mΩ
Converter 1,2 Includes N-Chanel leakage current,
ILK_SW1/SW2 Leakage current into SW1/SW2 pin 6 7.5 mA
VIN = open, VSW = 6.0V, EN = GND(4)
OUTPUT 1 0.68 0.8 0.92
Forward Current Limit
ILIMF 2.5V ≤VIN ≤6.0V A
PMOS and NMOS OUTPUT 2 0.85 1.0 1.15
TSD Thermal shutdown Increasing junction temperature 150 °C
Thermal shutdown hysteresis Decreasing junction temperature 20 °C
OSCILLATOR
fSW Oscillator frequency 2.5V ≤VIN ≤6V 2.0 2.25 2.5 MHz
OUTPUT
VOUT Adjustable output voltage range 0.6 VIN V
Vref Reference voltage 600 mV
Voltage positioning active,
MODE/DATA = GND, 1.01
VOUT (PFM) –1.5% 2.5%
device operating in PFM mode, VOUT
VIN = 2.5V to 5.0V (6) (7)
MODE/DATA = GND;
DC output voltage accuracy adjustable device operating in PWM Mode, –1% 0% 1%
and fixed output voltage(5) VIN = 2.5V to 6.0V(7)
VIN = 2.5V to 6.0V, Mode/Data = VIN ,
VOUT(PWM) Fixed PWM operation, –1% 0% 1%
0mA < IOUT1 < 400mA ; 0mA < IOUT2 <
600mA(8)
DC output voltage load regulation PWM operation mode 0.5 %/A
tStart up Start-up time Activation time to start switching(9) 170 ms
tRamp VOUT Ramp UP time Time to ramp from 5% to 95% of VOUT 750 ms
(4) On pins SW1 and SW2 an internal resistor of 1MΩis connected to GND.
(5) Output voltage specification does not include tolerance of external voltage programming resistors
(6) Configuration L typ 2.2mH, COUT typ 20mF, see parameter measurement information, the output voltage ripple in PFM mode depends on
the effective capacitance of the output capacitor, larger output capacitors lead to tighter output voltage tolerance.
(7) In Power Save Mode, PWM operation is typically entered at IPSM = VIN/32Ω.
(8) For VOUT > 2V, VIN min = VOUT +0.5V
(9) This time is valid if one converter turns from shutdown mode (EN2 = 0) to active mode (EN2 = 1) AND the other converter is already
enabled (e.g., EN1 = 1). In case both converters are turned from shutdown mode (EN1 and EN2 = low) to active mode (EN1 and/or
EN2=1) a value of typ 80 ms for ramp up of internal circuits needs to be added. After tStart the converter starts switching and ramps
VOUT.
4Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS62400 TPS62401 TPS62402 TPS62403 TPS62404
DEF_1
FB1
MODE/DATA
VIN
EN1
SW2
ADJ2
GND
EN2
PowerPAD
SW1
1
2
3
4
5
10
9
8
7
6
TopviewDRCpackage
TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
www.ti.com
SLVS681E –JUNE 2006–REVISED APRIL 2010
PIN ASSIGNMENTS
TERMINAL FUNCTIONS
TERMINAL I/O DESCRIPTION
NO.
NAME (QFN)
Input to adjust output voltage of converter 2. In adjustable version (TPS62400) connect a external resistor
divider between VOUT2, this pin and GND to set output voltage between 0.6V and VIN. At fixed output
ADJ2 1 I voltage version (TPS62401) this pin MUST be directly connected to the output. If EasyScale Interface is
used for converter 2, this pin must be directly connected to the output, too.
This Pin has 2 functions:
1. Operation Mode selection: With low level, Power Save Mode is enabled where the device operates
in PFM mode at light loads and enters automatically PWM mode at heavy loads. Pulling this PIN to
high forces the device to operate in PWM mode over the whole load range.
MODE/DATA 2 I/0 2. EasyScale™ Interface function: One wire serial interface to change the output voltage of both
converters. The pin has an open drain output to provide an acknowledge condition if requested. The
current into the open drain output stage may not exceed 500mA. The interface is active if either EN1
or EN2 is high.
VIN 3 Supply voltage, connect to VBAT, 2.5V to 6V
Direct feedback voltage sense input of converter 1, connect directly to Vout 1. An internal feed forward
FB1 4 I capacitor is connected between this pin and the error amplifier. In case of fixed output voltage versions or
when the Interface is used, this pin is connected to an internal resistor divider network.
This pin defines the output voltage of converter 1. The pin acts either as analog input for output voltage
setting via external resistors (TPS62400), or digital input to select between two fixed default output
voltages (TPS62401, TPS62402, TPS62403).
For the TPS62400, an external resistor network needs to be connected to this pin to adjust the default
DEF_1 5 I output voltage.
Using the fixed output voltage device options this pin selects between two fixed default output voltages,
see table ordering information
SW1 6 I/O Switch Pin of Converter1. Connect to Inductor
EN1 7 I Enable Input for Converter1, active high
GND 8 GND for both converters; connect this pin to the PowerPAD™
EN2 9 I Enable Input for Converter 2, active high
SW2 10 I/O Switch Pin of Converter 2. Connect to Inductor.
PowerPAD™ Connect to GND
Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TPS62400 TPS62401 TPS62402 TPS62403 TPS62404
Internal
compensated
Error Amp.
Sawtooth
Generator
Skip Comp.Low
PWM
Comp.
Average
CurrentDetector
Skip ModeEntry
VREF Control
Stage
GateDriver
PMOSCurrent
LimitComparator
NMOSCurrent
LimitComparator
LoadComparator
VREF-1%
FB
VOUT1
FB_VOUT
Undervoltage
Lockout
Thermal
Shutdown Softstart
VIN
GND
MODE
Error Amp.
Sawtooth
Generator
PWM
Comp.
VREF Control
Stage
GateDriver
PMOSCurrent
LimitComparator
NMOSCurrent
LimitComparator
LoadComparator
FB_VOUT2
Thermal
Shutdown
Softstart
VIN
GND
MODE
CLK180°
Easy Scale
Interface
CLK0°
CLK180°
2.25MHz
Oscillator
Converter1
Converter2
SW1
SW2
ADJ2
FB1
DEF1
Mode/
DATA
EN1
EN2
VIN
GND
Ext. res. network
Reference
Average
CurrentDetector
Skip ModeEntry
ACK
MOSFET
Opendrain
Internal
compensated
Skip Comp.
VREF+1%
FB_VOUT
Skip Comp.Low
VREF-1%
FB_VOUT
Skip Comp.
VREF+1%
FB_VOUT
Note1
RI3
RI1
RI..N
Int.Resistor
Network
Cff 25pF
Register
DEF1_High
DEF1_Low
RI1
RI..N
Int.Resistor
Network
Cff 25pF
Register
DEF2
Note2
TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
SLVS681E –JUNE 2006–REVISED APRIL 2010
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
(1) In fixed output voltage version, the PIN DEF_1 is connected to an internal digital input and disconnected from the
error amplifier
(2) To set the output voltage of Converter 2 via EasyScale™ Interface, ADJ2 pin must be directly connected to VOUT2
6Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS62400 TPS62401 TPS62402 TPS62403 TPS62404
SW1
FB1
SW2
ADJ2
DEF_1
VIN2.5V – 6V
VIN
EN_1
EN_2
MODE/
DATA
TPS62400
GND
L
C
10 F
IN
mR11
R12
1
2.2 H
LSP4018
m
VOUT1
C 2x10 F
GRM21BR61A106K
OUT1 m
VOUT2
R21
R22
L2
Cff2
33pF
2.2 H
LSP4018
m
C 2x10 F
GRM21BR61A106K
OUT2 m
TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
www.ti.com
SLVS681E –JUNE 2006–REVISED APRIL 2010
PARAMETER MEASUREMENT INFORMATION
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS AND FIGURES
FIGURE NO.
Efficiency TPS62401 VOUT1 = 1.1V 1
Efficiency TPS62401 VOUT1 = 1.575V 2
Efficiency VOUT 2 = 1.8V 3
Efficiency TPS62400 VOUT2 = 3.3V 4
Efficiency TPS62402 5
Efficiency TPS62403 6
Efficiency TPS62404 7
Efficiency vs VIN 8,9
DC Output Accuracy VOUT1 = 1.1V 10
DC Output Accuracy VOUT2 = 3.3V 11
DC Output Accuracy VOUT2 = 1.8V 12
DC Output Accuracy VOUT1 1.575V, L = 2.2mH, COUT = 22mF 13
DC Output Accuracy VOUT1 1.575V, L = 3.3mH, COUT = 10mF 14
FOSC vs VIN 15
Iqfor one converter 16
Iqfor both converters, not switching 17
RDSON PMOS vs VIN 18
RDSON NMOS vs VIN 19
Light Load Output Voltage Ripple in Power Save Mode 20
Output Voltage Ripple in Forced PWM Mode 21
Output Voltage Ripple in PWM Mode 22
Forced PWM/ PFM Mode Transition 23
Load Transient Response PFM/PWM 24
Load Transient Response PWM Operation 25
Line Transient Response 26
Startup Timing One Converter 27
Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TPS62400 TPS62401 TPS62402 TPS62403 TPS62404
0
10
20
30
40
50
60
70
80
90
100
0.01 0.1 1 10 100 1000
Efficiency%
PowerSaveMode
MODE/DATA =0
ForcedPWMMode
MODE/DATA =1
I mA
OUT
V =2.7V
IN
V =3.6V
IN
V =5V
IN
V =2.7V
IN
V =3.6V
IN
V =5V
IN
V =1.1V
OUT1
0
10
20
30
40
50
60
70
80
90
100
0.01 0.1 1 10 100 1000
Efficiency%
PowerSaveMode
MODE/DATA =0 ForcedPWMMode
MODE/DATA =1
V =1.575V
OUT1
I mA
OUT
V =2.7V
IN
V =5V
IN
V =3.6V
IN
V =2.7V
IN
V =3.6V
IN
V =5V
IN
TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
SLVS681E –JUNE 2006–REVISED APRIL 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
FIGURE NO.
TPS62401 DEF1_pin Function for Output Voltage Selection 28
Typical Operation VIN = 3.6V, VOUT1 = 1.575V, VOUT2 = 1.8V 29
Typical Operation VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 3.0V 30
Typical Operation VIN = 3.6V, VOUT1 = 1.2V, VOUT2 = 1.2V 31
VOUT1 Change With EasyScale 32
Dynamic Voltage Positioning 33
Soft Start 34
EasyScale™ Protocol Overview 35
EasyScale Protocol Without Acknowledge 36
EasyScale Protocol Including Acknowledge 37
EasyScale – Bit Coding 38
MODE/DATA PIN: Mode Selection 39
MODE/DATA Pin: Power Save Mode / Interface Communication 40
Typical Application Circuit 1.5V / 2.85V Adjustable Outputs, low PFM 41
voltage ripple optimized
Typical Application Circuit 1.5V / 2.85V Adjustable Outputs 42
TPS62401 Fixed 1.575V/1.8 V Outputs, low PFM voltage ripple optimized 43
TPS62401 Fixed 1.1V/1.8 V Outputs, low PFM voltage ripple optimized 44
TPS62401 Fixed 1.575V/1.8 V Outputs 45
Dynamic Voltage Scaling on Vout1 Controlled by DEF_1 pin 46
TPS62403 1.575V/2.8V Outputs 47
Layout Diagram 48
PCB Layout 49
EFFICIENCY TPS62401 VOUT1 = 1.1V EFFICIENCY TPS62401 VOUT1 = 1.575V
Figure 1. Figure 2.
8Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS62400 TPS62401 TPS62402 TPS62403 TPS62404
0
10
20
30
40
50
60
70
80
90
100
0.01 0.1 1 10 100 1000
Efficiency%
PowerSaveMode
MODE/DATA =0
ForcedPWMMode
MODE/DATA =1
V =1.8V
OUT2
I mA
OUT
V =2.7V
IN
V =3.6V
IN
V =5V
IN
V =2.7V
IN
V =3.6V
IN
V =5V
IN
0
10
20
30
40
50
60
70
80
90
100
0.01 0.1 1 10 100 1000
Efficiency%
PowerSaveMode
MODE/DATA =0
ForcedPWMMode
MODE/DATA =1
I mA
OUT
V =3.3V
OUT2
V =3.6V
IN
V =5V
IN
V =3.6V
IN
V =5V
IN
TPS62403
EfficiencyV /V ,
MODE/DATA =0,
DEF_1=0
OUT1 OUT2
0
10
20
30
40
50
60
70
80
90
100
0.01 0.1 1 10
I -mA
OUT
Efficiency-%
V =2.8V
V =3.3V
V =3.6V
MODE/DATA =low
OUT2
IN
IN
V =1.575V
V =3.3V
V =3.6V
MODE/DATA =high
OUT1
IN
IN
100 1000
V =2.8V
V =3.3V
V =3.6V
MODE/DATA =high
OUT2
IN
IN
V =1.575V
V =3.3V
V =3.6V
MODE/DATA =low
OUT1
IN
IN
0
10
20
30
40
50
60
70
80
90
100
0.01 0.1 1 10 100 1000
I -OutputCurrent-mA
O
Efficiency-%
V =3.7V
V =4.2V
V =3.3V
MODE/DATA =Low
I
I
O2
V =3.7V
V =4.2V
V =1.8V
MODE/DATA =Low
I
I
O1
V =3.7V
V =4.2V
V =1.2V
MODE/DATA =Low
I
I
O1
V =3.7V
V =4.2V
V =3.3V
MODE/DATA =High
I
I
O2
V =3.7V
V =4.2V
V =1.8V
MODE/DATA =High
I
I
O2
V =3.7V
V =4.2V
V =1.2V
MODE/DATA =High
I
I
O2
TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
www.ti.com
SLVS681E –JUNE 2006–REVISED APRIL 2010
EFFICIENCY VOUT 2 = 1.8V EFFICIENCY TPS62400 VOUT 2 = 3.3V
Figure 3. Figure 4.
EFFICIENCY TPS62402 VOUT1/VOUT2 EFFICIENCY TPS62403 VOUT1/VOUT2
Figure 5. Figure 6.
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0
10
20
30
40
50
60
70
80
90
100
Efficiency %
Power Save Mode
MODE/DATA = 0
Forced PWM Mode
MODE/DATA = 1
V = 1.9 V
OUT1
0.01 0.1 1 10 100 1000
I mA
OUT
V = 2.7 V
IN
V = 3.6 V
IN
V = 5 V
IN
V = 3.6 V
IN
V = 5 V
IN
V = 2.7 V
IN
50
55
60
65
70
75
80
85
90
95
100
2 3 4 5 6
Efficiency%
V -V
IN
MODE/DATA =0
V =1.575V
OUT I =10mA
OUT
I =1mA
OUT I =200mA
OUT
1.050
1.075
1.100
1.125
1.150
0.01 0.10 1 10 100 1000
I -mA
OUT
V DC-V
OUT
MODE/DATA =low,PFMMode,voltagepositioningactive
MODE/DATA =high,forcedPWMMode
PWMMode
Operation
V =1.1V
OUT1
V =3.6V
IN
V =2.7V
IN V =4.2V
IN
V =4.2V
IN
V =3.6V
IN
V =2.7V
IN
50
60
70
80
90
100
3 4 5 6
V -V
IN
Efficiency%
MODE/DATA =0
V =3.3V
OUT
I =100mA
OUT
I =10mA
OUT
I =1mA
OUT
TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
SLVS681E –JUNE 2006–REVISED APRIL 2010
www.ti.com
EFFICIENCY TPS62404 VOUT1 = 1.9V, DEF_1 = HIGH EFFICIENCY vs VIN
Figure 7. Figure 8.
EFFICIENCY vs VIN DC OUTPUT ACCURACY VOUT1 = 1.1V
Figure 9. Figure 10.
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3.200
3.250
3.300
3.350
3.400
0.01 0.10 1 10 100 1000
I -mA
OUT
V DC-V
OUT
MODE/DATA =low,PFMMode,voltagepositioningactive
MODE/DATA =high,forcedPWMMode
PWMMode
Operation
V =3.6V
IN
V =4.2V
IN
V =5V
IN
V =4.2V
IN
V =3.6V
IN
V =5V
IN
V =3.3V
OUT2
1.746
1.764
1.782
1.800
1.818
1.836
1.854
0.01 0.10 1 10 100 1000
I -mA
OUT
V DC-V
OUT
MODE/DATA =low,PFMMode,voltagepositioningactive
MODE/DATA =high,forcedPWMMode
PWMMode
Operation
V =1.8V
OUT2
V =5V
IN
V =4.2V
IN
V =3.6V
IN
V =2.7V
IN
V =3.6V
IN
V =4.2V
IN
V =5V
IN
V =2.7V
IN
1.500
1.525
1.550
1.575
1.600
1.625
1.650
0.01 0.10 1 10 1000
I -mA
OUT
V DC-V
OUT
MODE/DATA =low,PFMMode,voltagepositioningactive
MODE/DATA =high,forcedPWMMode
100
PWMMode
Operation
V =1.575V
OUT1
V =4.2V
IN
V =3.6V
IN
V =3.6V
IN
V =4.2V
IN
V =2.7V
IN
V =2.7V
IN
1.500
1.525
1.550
1.575
1.600
1.625
1.650
0.01 0.10 1 10 1000
I -mA
OUT
V DC-V
OUT
MODE/DATA =low,PFMMode,voltagepositioningactive
MODE/DATA =high,forcedPWMMode
100
PWMMode
Operation
V =1.575V
OUT1
V =3.6V
IN
V =4.2V
IN
V =2.7V
IN
V =4.2V
IN
V =3.6V
IN
V =2.7V
IN
TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
www.ti.com
SLVS681E –JUNE 2006–REVISED APRIL 2010
DC OUTPUT ACCURACY VOUT2 = 3.3V DC OUTPUT ACCURACY VOUT2 = 1.8V
Figure 11. Figure 12.
DC OUTPUT ACCURACY VOUT1 = 1.575V, DC OUTPUT ACCURACY VOUT1 = 1.575V,
L = 2.2mH, COUT = 22mF L = 3.3mH, COUT = 10mF
Figure 13. Figure 14.
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2
2.05
2.1
2.15
2.2
2.25
2.3
2.35
2.4
2.45
2.5
2.5 3 3.5 4 4.5 55.5 6
V -V
IN
Fosc-MHz
-40°C
25°C
85°C
17
18
19
20
21
22
23
24
2.5 3 3.5 4 4.5 5 5.5 6
V -V
IN
Iddq- Am
85°C
25°C
-40°C
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
2.5 3 3.5 4 4.5 5 5.5 6
V -V
IN
RDSon- W
85°C
25°C
-40°C
28
30
32
34
36
38
40
42
2.5 3 3.5 4 4.5 5 5.5 6
V -V
IN
Iddq- Am
85°C
25°C
-40°C
TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
SLVS681E –JUNE 2006–REVISED APRIL 2010
www.ti.com
FOSC vs VIN IqFOR ONE CONVERTER, NOT SWITCHING
Figure 15. Figure 16.
IqFOR BOTH CONVERTERS, NOT SWITCHING RDSON PMOS vs VIN
Figure 17. Figure 18.
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0.05
0.1
0.15
0.2
0.25
0.3
2.5 3 3.5 4 4.5 5 5.5 6
V -V
IN
RDSon- W
85°C
25°C
-40°C
IOUT =10mA
VOUT =1.8V20mV/Div
Inductorcurrent100mA/Div
PowerSaveMode
Mode/Data=low
Timebase-10 s/Divm
IOUT =10mA
VOUT =1.8V20mV/Div
Inductorcurrent100mA/Div
Mode/Data=high,
forcedPWMMODEoperation
Timebase-400ns/Div
VOUT =1.8V
IOUT =400mA
VOUT ripple20mV/Div
Inductorcurrent200mA/Div
PWMMODEOPERATION
Timebase-200ns/Div
TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
www.ti.com
SLVS681E –JUNE 2006–REVISED APRIL 2010
LIGHT LOAD OUTPUT VOLTAGE RIPPLE
RDSON NMOS vs VIN IN POWER SAVE MODE
Figure 19. Figure 20.
OUTPUT VOLTAGE RIPPLE OUTPUT VOLTAGE RIPPLE
IN FORCED PWM MODE IN PWM MODE
Figure 21. Figure 22.
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VOUT =1.8V
IOUT =20mA
VOUT 20mV/Div
EnteringPFMMode
Voltagepositioningactive
ForcedPWM
Mode
MODE/DATA 1V/Div
EnablePowerSaveMode
Timebase-200 s/Divm
IOUT=40mA
IOUT1=360mA
VOUT =1.575V
50mV/Div
VoltagepositioninginPFM
Modereducesvoltagedrop
duringloadstep
IOUT 200mA/Div
MODE/DATA =low
PWMModeoperation
Timebase-50 s/Divm
IOUT=40mA
IOUT1=360mA
VOUT =1.575V
50mV/Div
IOUT 200mA/Div
MODE/DATA =high
PWMModeoperation
Timebase-50 s/Divm
VIN1V/Div
VOUT 1.575
IOUT 200mA
VIN3.6Vto4.6V
VOUT 50mV/Div
MODE/DATA =high
Timebase-400 s/Divm
TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
SLVS681E –JUNE 2006–REVISED APRIL 2010
www.ti.com
FORCED PWM/PFM MODE TRANSITION LOAD TRANSIENT RESPONSE PFM/PWM
Figure 23. Figure 24.
LOAD TRANSIENT RESPONSE PWM OPERATION LINE TRANSIENT RESPONSE
Figure 25. Figure 26.
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VIN=3.6V,MODE/DAT =low
IOUT1=40mA
VOUT1=1.1V
DEF_1pin
2V/Div
VOUT1
500mV/Div
Icoil500mA/Div
VOUT1=1.575V
Timebase-100 s/Divm
VIN=3.8V
IOUT1max=400mA
SW11V/Div
EN1/EN25V/Div
VOUT1
500mV/Div
Icoil500mA/Div
Timebase-200 s/Divm
SW15V/Div
SW25V/Div
Icoil1 200mA/Div
Icoil2 200mA/Div
VIN 3.6V,
VOUT1:1.575V
VOUT2:1.8V
IOUT1 =IOUT2 =200mA
Timebase-100ns/Div
SW15V/Div
SW25V/Div
Icoil1 200mA/Div
Icoil2 200mA/Div
VIN 3.6V,
VOUT1:1.8V
VOUT2:3.0V
IOUT1 =IOUT2 =200mA
Timebase-100ns/Div
TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
www.ti.com
SLVS681E –JUNE 2006–REVISED APRIL 2010
TPS62401DEF1_PIN FUNCTION FOR OUTPUT VOLTAGE
STARTUP TIMING ONE CONVERTER SELECTION
Figure 27. Figure 28.
TYPICAL OPERATION VIN = 3.6V, TYPICAL OPERATION VIN = 3.6V,
VOUT1 = 1.575V, VOUT2 = 1.8V VOUT1 = 1.8V, VOUT2 = 3.0V
Figure 29. Figure 30.
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SW15V/Div
SW25V/Div
Icoil1 200mA/Div
Icoil2 200mA/Div VIN 3.6V,
VOUT1:1.2V
VOUT2:1.2V
IOUT1 =IOUT2 =200mA
Timebase-100ns/Div
MODE/DATA
2V/Div
VOUT1:1.5V
VOUT1:1.1V
VIN 3.8V
ACKN=off
IOUT1 =150mA
REG_DEF_1_Low
VOUT1:200mV/Div
Timebase-100 s/Divm
TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
SLVS681E –JUNE 2006–REVISED APRIL 2010
www.ti.com
TYPICAL OPERATION VIN = 3.6V,
VOUT1 = 1.2V, VOUT2 = 1.2V VOUT1 CHANGE WITH EASYSCALE
Figure 31. Figure 32.
DETAILED DESCRIPTION
OPERATION
The TPS62400 includes two synchronous step-down converters. The converters operate with typically 2.25MHz
fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. If Power Safe Mode is
enabled, the converters automatically enter Power Save Mode at light load currents and operate in PFM (Pulse
Frequency Modulation).
During PWM operation the converters use a unique fast response voltage mode controller scheme with input
voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is
turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch.
Each converter integrates two current limits, one in the P-channel MOSFET and another one in the N-channel
MOSFET. When the current in the P-channel MOSFET reaches its current limit, the P-channel MOSFET is
turned off and the N-channel MOSFET is turned on. If the current in the N-channel MOSFET is above the
N-MOS current limit threshold, the N-channel MOSFET remains on until the current drops below its current limit.
The two DC-DC converters operate synchronized to each other. A 180° phase shift between converter 1 and
converter 2 decreases the input RMS current.
Converter 1
In the adjustable output voltage version TPS62400 the converter 1 default output voltage can be set via an
external resistor network on PIN DEF_1, which operates as an analog input. In this case, the output voltage can
be set in the range of 0.6V to VIN V. The FB1 Pin must be directly connected to the converter 1 output voltage
VOUT1. It feeds back the output voltage directly to the regulation loop.
The output voltage of converter 1 can also be changed by the EasyScale™ serial Interface. This makes the
device very flexible for output voltage adjustment. In this case, the device uses an internal resistor network.
In the fixed default output voltage version TPS62401, the DEF_1 Pin is configured as a digital input. The
converter 1 defaults to 1.1V or 1.575V depending on the level of DEF_1 pin. If DEF_1 is low the default is
1.575V; if high, the default is 1.1V. With the EasyScale™ interface, the output voltage for each DEF_1 Pin
condition (high or low) can be changed.
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IOUT_PFM_enter +VINDCDC
32 W
IOUT_PFM_leave +VINDCDC
24 W
TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
www.ti.com
SLVS681E –JUNE 2006–REVISED APRIL 2010
Converter 2
In the adjustable output voltage version TPS62400, the converter 2 output voltage is set by an external resistor
divider connected to ADJ2 Pin and uses an external feed forward capacitor of 33pF.
In fixed output voltage version TPS62401, the default output voltage is fixed to 1.8V. In this case, the ADJ2 pin
must be connected directly to the converter 2 output voltage VOUT2.
It is also possible to change the output voltage of converter 2 via the EasyScale™ Interface. In this case, the
ADJ2 Pin must be directly connected to converter 2 output voltage VOUT2 and no external resistors may be
connected.
POWER SAVE MODE
The Power Save Mode is enabled with Mode/Data Pin set to low for both converters. If the load current of a
converter decreases, this converter will enter Power Save Mode operation automatically. The transition to Power
Save Mode of a converter is independent from the operating condition of the other converter. During Power Save
Mode the converter operates with reduced switching frequency in PFM mode and with a minimum quiescent
current to maintain high efficiency. The converter will position the output voltage in PFM mode to typically
1.01×VOUT. This voltage positioning feature minimizes voltage drops caused by a sudden load step.
In order to optimize the converter efficiency at light load the average inductor current is monitored. The device
changes from PWM Mode to Power Save Mode, if in PWM mode the inductor current falls below a certain
threshold. The typical output current threshold depends on VIN and can be calculated according to Equation 1
for each converter.
Equation 1: Average output current threshold to enter PFM Mode
(1)
Equation 2: Average output current threshold to leave PFM Mode
(2)
In order to keep the output voltage ripple in Power Save Mode low, the output voltage is monitored with a single
threshold comparator (skip comparator). As the output voltage falls below the skip comparator threshold (skip
comp) of 1.01 x VOUTnominal, the corresponding converter starts switching for a minimum time period of typ.
1ms and provides current to the load and the output capacitor. Therefore the output voltage will increase and the
device maintains switching until the output voltage trips the skip comparator threshold (skip comp) again. At this
moment all switching activity is stopped and the quiescent current is reduced to minimum. The load is supplied
by the output capacitor until the output voltage has dropped below the threshold again. Hereupon the device
starts switching again.
The Power Save Mode is left and PWM Mode entered in case the output current exceeds the current
IOUT_PFM_leave or if the output voltage falls below a second comparator threshold, called skip comparator low
(Skip Comp Low) threshold. This skip comparator low threshold is set to -2% below nominal Vout, and enables a
fast transition from Power Save Mode to PWM Mode during a load step.
In Power Save Mode the quiescent current is reduced typically to 19mA for one converter and 32mA for both
converters active. This single skip comparator threshold method in Power Save Mode results in a very low output
voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor. Increasing
output capacitor values will minimize the output ripple. The Power Save Mode can be disabled through the
MODE/DATA pin set to high. Both converters will then operate in fixed PWM mode. Power Save Mode
Enable/Disable applies to both converters.
Dynamic Voltage Positioning
This feature reduces the voltage under/overshoots at load steps from light to heavy load and vice versa. It is
activated in Power Save Mode operation. It provides more headroom for both the voltage drop at a load step,
and the voltage increase at a load throw-off. This improves load transient behavior.
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V
OUT_NOM
+1%
PWMMode
medium/heavyload
PFMMode
lightload
Smooth
increasedload
PWMMode
medium/heavyload
PFMMode
lightload
Fastloadtransient
PWMMode
medium/heavyload
COMP_LOWthreshold-2%
95%
5%
tRAMP
tStartup
EN
VOUT
Vinmin +Voutmax )Ioutmax ǒRDSonmax )RLǓ
TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
SLVS681E –JUNE 2006–REVISED APRIL 2010
www.ti.com
At light loads, in which the converter operates in PFM Mode, the output voltage is regulated typically 1% higher
than the nominal value. In case of a load transient from light load to heavy load, the output voltage drops until it
reaches the skip comparator low threshold set to –2% below the nominal value and enters PWM mode. During a
load throw off from heavy load to light load, the voltage overshoot is also minimized due to active regulation
turning on the N-channel switch.
Figure 33. Dynamic Voltage Positioning
Soft Start
The two converters have an internal soft start circuit that limits the inrush current during start-up. During soft
start, the output voltage ramp up is controlled as shown in Figure 34.
Figure 34. Soft Start
100% Duty Cycle Low Dropout Operation
The converters offer a low input-to-output voltage difference while still maintaining operation with the use of the
100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly useful in
battery-powered applications to achieve longest operation time by taking full advantage of the whole battery
voltage range. The minimum input voltage to maintain regulation depends on the load current and output voltage,
and can be calculated as:
(3)
with:
Ioutmax = maximum output current plus inductor ripple current
RDSonmax = maximum P-channel switch RDSon.
RL= DC resistance of the inductor
Voutmax = nominal output voltage plus maximum output voltage tolerance
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TPS62400, TPS62401
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www.ti.com
SLVS681E –JUNE 2006–REVISED APRIL 2010
With decreasing load current, the device automatically switches into pulse skipping operation in which the power
stage operates intermittently based on load demand. By running cycles periodically the switching losses are
minimized and the device runs with a minimum quiescent current, maintaining high efficiency.
Under-Voltage Lockout
The under-voltage lockout circuit prevents the device from malfunctioning at low input voltages, and from
excessive discharge of the battery, and disables the converters. The under-voltage lockout threshold is typically
1.5V; maximum of 2.35V. In case the default register values are overwritten by the Interface, the new values in
the registers REG_DEF_1_High, REG_DEF_1_Low and REG_DEF_2 remain valid as long the supply voltage
does not fall below the under-voltage lockout threshold, independent of whether the converters are disabled.
MODE SELECTION
The MODE/DATA pin allows mode selection between forced PWM Mode and Power Save Mode for both
converters. Furthermore, this pin is a multipurpose pin and provides (besides Mode selection) a one-pin interface
to receive serial data from a host to set the output voltage. This is described in the EasyScale™ Interface
section.
Connecting this pin to GND enables the automatic PWM and power save mode operation. The converters
operates in fixed-frequency PWM mode at moderate-to-heavy loads, and in the PFM mode during light loads,
maintaining high efficiency over a wide load current range.
Pulling the MODE/DATA pin high forces both converters to operate constantly in the PWM mode, even at light
load currents. The advantage is that the converters operate with a fixed frequency, allowing simple filtering of the
switching frequency for noise-sensitive applications. In this mode, the efficiency is lower compared to the power
save mode during light loads. For additional flexibility, it is possible to switch from power save mode to forced
PWM mode during operation. This allows efficient power management by adjusting the operation of the converter
to the specific system requirements.
In case the operation mode is changed from forced PWM mode (MODE/DATA = high) to Power Save Mode
Enable (MODE/DATA = 0), the Power Save Mode is enabled after a delay time of ttimeout , which is max. 520ms.
The forced PWM Mode operation is enabled immediately with Pin MODE/DATA set to 1.
ENABLE
The device has a separate EN pin for each converter to start up each converter independently. If EN1 and EN2
are set to high, the corresponding converter starts up with soft start as previously described.
Pulling EN1 and EN2 pin low forces the device into shutdown, with a shutdown quiescent current of typically
1.2mA. In this mode, the P and N-Channel MOSFETs are turned-off and the entire internal control circuitry is
switched-off. For proper operation the EN1 and EN2 pins must be terminated and must not be left floating.
DEF_1 PIN FUNCTION
The DEF_1 pin is dedicated to converter 1 and makes the output voltage selection very flexible to support
dynamic voltage management.
Depending on the device version, this pin works either as:
1. Analog input for adjustable output voltage setting (TPS62400):
– Connecting an external resistor network to this pin adjusts the default output voltage to any value starting
from 0.6V to VIN
2. Digital input for fixed default output voltage selection (TPS62401):
– In case this pin is tied to low level, the output voltage is set according to the value in register
REG_DEF_1_Low. The default voltage will be 1.575V. If tied to high level, the output voltage is set
according to the value in register REG_DEF_1_High. The default value in this case is 1.1V. Depending
on the level of Pin DEF_1, it selects between the two registers REG_DEF_1_Low and REG_DEF_1_High
for output voltage setting. Each register content (and therefore output voltage) can be changed
individually via the EasyScale™ interface. This makes the device very flexible in terms of output voltage
setting; see Table 4.
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TPS62400, TPS62401
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SLVS681E –JUNE 2006–REVISED APRIL 2010
www.ti.com
180° OUT-OF-PHASE OPERATION
In PWM Mode the converters operate with a 180° turn-on phase shift of the PMOS (high side) transistors. This
prevents the high-side switches of both converters from being turned on simultaneously, and therefore smooths
the input current. This feature reduces the surge current drawn from the supply.
SHORT-CIRCUIT PROTECTION
Both outputs are short-circuit protected with maximum output current = ILIMF(P-MOS and N-MOS). Once the
PMOS switch reaches its current limit, it is turned off and the NMOS switch is turned on. The PMOS only turns
on again, once the current in the NMOS decreases below the NMOS current limit.
THERMAL SHUTDOWN
As soon as the junction temperature, TJ, exceeds 150°C (typical) the device goes into thermal shutdown. In this
mode, the P and N-Channel MOSFETs are turned-off. The device continues its operation when the junction
temperature falls below the thermal shutdown hysteresis.
EasyScale™: One-Pin Serial Interface for Dynamic Output Voltage Adjustment
General
EasyScale is a simple but very flexible one pin interface to configure the output voltage of both DC/DC
converters. The interface is based on a master – slave structure, where the master is typically a microcontroller
or application processor. Figure 35 and Table 3. give an overview of the protocol. The protocol consists of a
device specific address byte and a data byte. The device specific address byte is fixed to 4E hex. The data byte
consists of five bits for information, two address bits, and the RFA bit. RFA bit set to high indicates the Request
For Acknowledge condition. The Acknowledge condition is only applied if the protocol was received correctly.
The advantage of EasyScale™ compared to other one pin interfaces is that its bit detection is in a large extent
independent from the bit transmission rate. It can automatically detect bit rates between 1.7kBit/sec and up to
160kBit/sec. Furthermore, the interface is shared with the Mode/Data Pin and requires no additional pin.
Protocol
All bits are transmitted MSB first and LSB last. Figure 36 shows the protocol without acknowledge request (bit
RFA = 0), Figure 37 with acknowledge (bit RFA = 1) request.
Prior to both bytes, device address byte and data byte, a start condition needs to be applied. For this, the
Mode/Data pin need be pulled high for at least tStart before the bit transmission starts with the falling edge. In
case the Mode/Data line was already at high level (forced PWM Mode selection), no start condition need be
applied prior the device address byte.
The transmission of each byte needs to be closed with an End Of Stream condition for at least TEOS.
Addressable Registers
Three registers with a data content of 5 bits can be addressed. With 5 bit data content, 32 different values for
each register are available. Table 1 shows the addressable registers to set the output voltage when DEF_1 pin
works as digital input. In this case, converter 1 has a related register for each DEF_1 Pin condition, and one
register for converter 2. With a high/low condition on pin DEF_1 (TPS62401) either the content of register
REG_DEF_1_high/REG_DEF1_low is selected. The output voltage of converter 1 is set according to the values
in Table 4.
Table 2 shows the addressable registers if DEF_1 pin acts as analog input with external resistors connected. In
this case one register is available for each converter. The output voltage of converter 1 is set according to the
values in Table 5. For converter 2, the available voltages are shown in Table 6. To generate these output
voltages a precise internal resistor divider network is used, making external resistors unnecessary (less board
space), and provides higher output voltage accuracy. The Interface is activated if at least one of the converters is
enabled (EN1 or EN2 is high). After the startup-time tStart (170ms) the interface is ready for data reception.
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TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
www.ti.com
SLVS681E –JUNE 2006–REVISED APRIL 2010
Table 1. Addressable Registers for default Fixed Output Voltage Options (PIN DEF_1 = digital input)
DEVICE REGISTER DESCRIPTION DEF_1 A1 A0 D4 D3 D2 D1 D0
PIN
REG_DEF_1_High Converter 1 output voltage setting for High 0 1 Output voltage setting, see
DEF_1 = High condition. The content of Table 4
the register is active with DEF1_ Pin high.
TPS62401, REG_DEF_1_Low Converter 1 output voltage setting for Low 0 0 Output voltage setting, see
TPS62402, DEF_1 = Low condition. Table 4
TPS62403,
TPS62404 REG_DEF_2 Converter 2 output voltage Not 1 0 Output voltage setting, see
applicable Table 6
Don’t use 1 1
Table 2. Addressable Registers for Adjustable Output Voltage Options (PIN DEF_1 = analog input)
DEVICE REGISTER DESCRIPTION A1 A0 D4 D3 D2 D1 D0
REG_DEF_1_High not available
REG_DEF_1_Low Converter 1 output voltage setting 0 0 see Table 5
TPS62400 REG_DEF_2 Converter 2 output voltage 1 0 see Table 6
Don’t’ use 1 1
Bit Decoding
The bit detection is based on a PWM scheme, where the criterion is the relation between tLOW and tHIGH. It can
be simplified to:
High Bit: tHigh > tLow, but with tHigh at least 2x tLow, see Figure 34
Low Bit: tLow> tHigh, but with tLow at least 2x tHigh, see Figure 34
The bit detection starts with a falling edge on the MODE/DATA pin and ends with the next falling edge.
Depending on the relation between tLow and tHigh a 0 or 1 is detected.
Acknowledge
The Acknowledge condition is only applied if:
• Acknowledge is requested by a set RFA bit
• The transmitted device address matches with the device address of the device
• 16 bits were received correctly
In this case, the device turns on the internal ACKN-MOSFET and pulls the MODE/DATA pin low for the time
tACKN, which is 520ms maximum . The Acknowledge condition is valid after an internal delay time tvalACK. This
means the internal ACKN-MOSFET is turned on after tvalACK, when the last falling edge of the protocol was
detected. The master controller keeps the line low during this time.
The master device can detect the acknowledge condition with its input by releasing the MODE/DATA pin after
tvalACK and read back a 0.
In case of an invalid device address, or not-correctly-received protocol, no-acknowledge condition is applied;
thus, the internal MOSFET is not turned on and the external pullup resistor pulls MODE/DATA pin high after
tvalACK. The MODE/DATA pin can be used again after the acknowledge condition ends.
NOTE
The acknowledge condition may only be requested in case the master device has an open
drain output.
In case of a push-pull output stage it is recommended to use a series resistor in the MODE/DATA line to limit the
current to 500 mA in case of an accidentally requested acknowledge, to protect the internal ACKN-MOSFET.
MODE Selection
Because the MODE/DATA pin is used for two functions, interface and a MODE selection, the device needs to
determine when it has to decode the bit stream or to change the operation mode.
Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): TPS62400 TPS62401 TPS62402 TPS62403 TPS62404
DATA IN
Start
DATA OUT ACK
RFA A1 A0 D4 D3 D2 D1 D0DA7
0
DA6
1
DA5
0
DA4
0
DA3
1
DA2
1
DA1
1
DA0
0
Device Address DATABYTE
EOS Start EOS
Start
DA7
0
tStart
Mode,Static
HighorLow
Mode,Static
HighorLow
DATA IN
tStart
TEOS TEOS
DA0
0
RFA
0
D0
1
AddressByte DATA Byte
TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
SLVS681E –JUNE 2006–REVISED APRIL 2010
www.ti.com
The device enters forced PWM mode operation immediately whenever the MODE/DATA pin turns to high level.
The device also stays in forced PWM mode during the entire protocol reception time.
With a falling edge on the MODE/DATA pin the device starts bit decoding. If the MODE/DATA pin stays low for at
least ttimeout, the device gets an internal timeout and Power Save Mode operation is enabled.
A protocol sent within this time is ignored because the falling edge for the Mode change is first interpreted as
start of the first bit. In this case it is recommended to send the protocol first, and then change at the end of the
protocol to Power Save Mode.
Figure 35. EasyScale™ Protocol Overview
Table 3. EasyScale™ Bit Description
BYTE BIT NAME TRANSMISSION DESCRIPTION
NUMBER DIRECTION
Device 7 DA7 IN 0 MSB device address
Address 6 DA6 IN 1
Byte 5 DA5 IN 0
4 DA4 IN 0
4Ehex 3 DA3 IN 1
2 DA2 IN 1
1 DA1 IN 1
0 DA0 IN 0 LSB device address
Databyte 7(MSB) RFA IN Request For Acknowledge, if high, Acknowledge condition will applied by the device
6 A1 Address Bit 1
5 A0 Address Bit 0
4 D4 Data Bit 4
3 D3 Data Bit 3
2 D2 Data Bit 2
1 D1 Data Bit 1
0(LSB) D0 Data Bit 0
ACK OUT Acknowledge condition active 0, this condition will only be applied in case RFA bit is
set. Open drain output, Line needs to be pulled high by the host with a pullup
resistor.
This feature can only be used if the master has an open drain output stage. In case
of a push pull output stage Acknowledge condition may not be requested!
Figure 36. EasyScale™ Protocol Without Acknowledge
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Product Folder Link(s): TPS62400 TPS62401 TPS62402 TPS62403 TPS62404
Mode,Static
HighorLow
tACKN
Acknowledge
true,DataLine
pulleddownby
device
DATA IN
DATA OUT Acknowledge
false,nopull
down
Controllerneedsto
PullupDataLineviaa
resistortodetect ACKN
ACKN
DA7
0
Mode,Static
HighorLow
TEOS tvalACK
DA0
0
RFA
1
D0
1
tStart tStart
AddressByte DATA Byte
LowBit
(Logic0)
HighBit
(Logic1)
tLow tHigh tHigh
tLow
PowerSaveMode ForcedPWMMODE PowerSaveMode
ttimeout
MODE/DATA
tStart tStart
TEOS
TEOS
AddressByte DATA Byte
ForcedPWMMODE PowerSaveMode
ttimeout
MODE/DATA
PowerSaveMode
TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
www.ti.com
SLVS681E –JUNE 2006–REVISED APRIL 2010
Figure 37. EasyScale™ Protocol Including Acknowledge
Figure 38. EasyScale™ – Bit Coding
Figure 39. MODE/DATA PIN: Mode Selection
Figure 40. MODE/DATA Pin: Power Save Mode/Interface Communication
Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 23
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TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
SLVS681E –JUNE 2006–REVISED APRIL 2010
www.ti.com
Table 4. Selectable Output Voltages for Converter 1,
With Pin DEF_1 as Digital Input (TPS62401)
TPS62401 OUTPUT TPS62401 OUTPUT D4 D3 D2 D1 D0
VOLTAGE [V] VOLTAGE [V]
REGISTER REG_DEF_1_LOW REGISTER REG_DEF_1_HIGH
0 0.8 0.9 0 0 0 0 0
1 0.825 0.925 0 0 0 0 1
2 0.85 0.95 0 0 0 1 0
3 0.875 0.975 0 0 0 1 1
4 0.9 1.0 0 0 1 0 0
5 0.925 1.025 0 0 1 0 1
6 0.95 1.050 0 0 1 1 0
7 0.975 1.075 0 0 1 1 1
81.0 1.1(default TPS62401, 0 1 0 0 0
TPS62403)
9 1.025 1.125 0 1 0 0 1
10 1.050 1.150 0 1 0 1 0
11 1.075 1.175 0 1 0 1 1
12 1.1 1.2 0 1 1 0 0
13 1.125 1.225 0 1 1 0 1
14 1.150 1.25 0 1 1 1 0
15 1.175 1.275 0 1 1 1 1
16 1.2 (default TPS62402, TPS62404) 1.3 1 0 0 0 0
17 1.225 1.325 1 0 0 0 1
18 1.25 1.350 1 0 0 1 0
19 1.275 1.375 1 0 0 1 1
20 1.3 1.4 1 0 1 0 0
21 1.325 1.425 1 0 1 0 1
22 1.350 1.450 1 0 1 1 0
23 1.375 1.475 1 0 1 1 1
24 1.4 1.5 1 1 0 0 0
25 1.425 1.525 1 1 0 0 1
26 1.450 1.55 1 1 0 1 0
27 1.475 1.575 1 1 0 1 1
28 1.5 1.6 1 1 1 0 0
29 1.525 1.7 1 1 1 0 1
30 1.55 1.8 (default TPS62402) 11110
31 1.575 (default TPS62401, 1.9 (default TPS62404) 1 1 1 1 1
TPS62403)
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TPS62400, TPS62401
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SLVS681E –JUNE 2006–REVISED APRIL 2010
Table 5. Selectable Output Voltages for Converter 1,
With DEF1 Pin as Analog Input (Adjustable, TPS62400)
TPS62400 OUTPUT VOLTAGE [V] D4 D3 D2 D1 D0
REGISTER REG_DEF_1_LOW
0 VOUT1 Adjustable with Resistor Network on DEF_1 Pin (default 0 0 0 0 0
TPS62400)
0.6V with DEF_1 connected to VOUT1 (default TPS62400)
1 0.825 0 0 0 0 1
2 0.85 0 0 0 1 0
3 0.875 0 0 0 1 1
4 0.9 0 0 1 0 0
5 0.925 0 0 1 0 1
6 0.95 0 0 1 1 0
7 0.975 0 0 1 1 1
8 1.0 0 1 0 0 0
9 1.025 0 1 0 0 1
10 1.050 0 1 0 1 0
11 1.075 0 1 0 1 1
12 1.1 0 1 1 0 0
13 1.125 0 1 1 0 1
14 1.150 0 1 1 1 0
15 1.175 0 1 1 1 1
16 1.2 1 0 0 0 0
17 1.225 1 0 0 0 1
18 1.25 1 0 0 1 0
19 1.275 1 0 0 1 1
20 1.3 1 0 1 0 0
21 1.325 1 0 1 0 1
22 1.350 1 0 1 1 0
23 1.375 1 0 1 1 1
24 1.4 1 1 0 0 0
25 1.425 1 1 0 0 1
26 1.450 1 1 0 1 0
27 1.475 1 1 0 1 1
28 1.5 1 1 1 0 0
29 1.525 1 1 1 0 1
30 1.55 1 1 1 1 0
31 1.575 1 1 1 1 1
Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): TPS62400 TPS62401 TPS62402 TPS62403 TPS62404
TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
SLVS681E –JUNE 2006–REVISED APRIL 2010
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Table 6. Selectable Output Voltages for Converter 2,
(ADJ2 Connected to VOUT)
OUTPUT VOLTAGE [V] D4 D3 D2 D1 D0
FOR REGISTER REG_DEF_2
0 VOUT2 Adjustable with resistor network and Cff on ADJ2 pin 0 0 0 0 0
(default TPS62400)
0.6V with ADJ2 pin directly connected to VOUT2 (default
TPS62400)
1 0.85 0 0 0 0 1
2 0.9 0 0 0 1 0
3 0.95 0 0 0 1 1
4 1.0 0 0 1 0 0
5 1.05 0 0 1 0 1
6 1.1 0 0 1 1 0
7 1.15 0 0 1 1 1
8 1.2 0 1 0 0 0
9 1.25 0 1 0 0 1
10 1.3 0 1 0 1 0
11 1.35 0 1 0 1 1
12 1.4 0 1 1 0 0
13 1.45 0 1 1 0 1
14 1.5 0 1 1 1 0
15 1.55 0 1 1 1 1
16 1.6 1 0 0 0 0
17 1.7 1 0 0 0 1
18 1.8 (default TPS62401) 1 0 0 1 0
19 1.85 1 0 0 1 1
20 2.0 1 0 1 0 0
21 2.1 1 0 1 0 1
22 2.2 1 0 1 1 0
23 2.3 1 0 1 1 1
24 2.4 1 1 0 0 0
25 2.5 1 1 0 0 1
26 2.6 1 1 0 1 0
27 2.7 1 1 0 1 1
28 2.8 (default TPS62403) 1 1 1 0 0
29 2.85 1 1 1 0 1
30 3.0 1 1 1 1 0
31 3.3 (default TPS62402, TPS62404) 1 1 1 1 1
26 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS62400 TPS62401 TPS62402 TPS62403 TPS62404
VOUT +VREF ǒ1)R11
R12Ǔwith an internal reference voltage VREF typical 0.6V
VOUT +VREF ǒ1)R21
R22Ǔwith an internal reference voltage VREF typical 0.6V
TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
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SLVS681E –JUNE 2006–REVISED APRIL 2010
APPLICATION INFORMATION
OUTPUT VOLTAGE SETTING
Converter1 Adjustable Default Output Voltage Setting: TPS62400
The output voltage can be calculated to:
(4)
To keep the operating current to a minimum, it is recommended to select R12 within a range of 180kΩto 360kΩ.
The sum of R12 and R11 should not exceed ~1MΩ. For higher output voltages than 3.3V, it is recommended to
choose lower values than 180kΩfor R12. Route the DEF_1 line away from noise sources, such as the inductor
or the SW1 line. The FB1 line needs to be directly connected to the output capacitor. A feed-forward capacitor is
not necessary.
Converter1 Fixed Default Output Voltage Setting (TPS62401, TPS62402, TPS62403, TPS62404).
The output voltage VOUT1 is selected with DEF_1 pin.
Pin DEF_1 = low:
TPS62401, TPS62403 = 1.575V
TPS62402, TPS62404 = 1.2V
Pin DEF_1 = high:
TS62401, TPS62403 = 1.1V
T62402: = 1.8V
T62404: = 1.9V
Converter 2 Adjustable Default Output Voltage Setting TPS62400:
The output voltage of converter 2 can be set by an external resistor network. For converter 2 the same
recommendations apply as for converter1. In addition to that, a 33pF feed-forward Capacitor Cff2 for good load
transient response should be used. The output voltage can be calculated to:
(5)
Converter 2 Fixed Default Output Voltage Setting
ADJ2 pin must be directly connected with VOUT2
TPS62401, VOUT2 default = 1.8V
TPS62403, VOUT2 default = 2.8V
TPS62402, TPS62404, VOUT2 default = 3.3V
Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): TPS62400 TPS62401 TPS62402 TPS62403 TPS62404
SW1
FB1
SW2
ADJ2
DEF_1
L2
VIN3.3V – 6V
VIN
EN_1
EN_2
MODE/
DATA
TPS62400
GND
L1
C
10 F
IN
m2.2 HmR11
270kW
R12
180kW
V =2.85V
OUT2
I upto600mA
OUT2
Cff2
33pF
3.3 HmR21
825kW
R22
220kW
C 22 F
OUT2 m
V =1.5V
OUT1
I upto400mA
OUT1
C 22 F
OUT1 m
SW1
FB1
SW2
ADJ2
DEF_1
L2
VIN3.3V – 6V
VIN
EN_1
EN_2
MODE/
DATA
TPS62400
GND
Cff2
33pF
L1
2.2 Hm
C
10 F
IN
m
3.3 Hm
R11
270kW
R12
180kW
R21
825kW
R22
220kW
V =1.5V
OUT1
I upto400mA
OUT1
C 10 F
OUT1 m
V =2.85
OUT2
I upto600mA
OUT2
C 10 F
OUT2 m
TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
SLVS681E –JUNE 2006–REVISED APRIL 2010
www.ti.com
Figure 41. Typical Application Circuit 1.5V/2.85V Adjustable Outputs, low PFM Voltage Ripple Optimized
Figure 42. Typical Application Circuit 1.5V/2.85V Adjustable Outputs
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VIN2.5V – 6V
TPS62401
10 Fm
VIN
EN_1
EN_2
MODE/
DATA
GND
DEF_1
SW2
SW1
ADJ2
FB1
2.2 Hm
2.2 Hm
22 Fm
22 Fm
V =1.575V
400mA
OUT1
V =1.8V
600mA
OUT2
22 Fm
SW1
FB1
SW2
ADJ2
DEF_1
10 Fm
VIN2.5V – 6V
VIN
EN_1
EN_2
MODE/
DATA
TPS62401
GND
2.2 HmV =1.1V
400mA
OUT1
22 Fm
V =1.8V
600mA
OUT2
2.2 Hm
TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
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SLVS681E –JUNE 2006–REVISED APRIL 2010
Figure 43. TPS62401 Fixed 1.575V/1.8V Outputs, low PFM Voltage Ripple Optimized
Figure 44. TPS62401 Fixed 1.1V/1.8V Outputs, low PFM Ripple Voltage Optimized
Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 29
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VIN2.5V – 6V
TPS62401
10 Fm
VIN
EN_1
EN_2
MODE/
DATA
GND
DEF_1
SW2
SW1
ADJ2
FB1
2.2 Hm
2.2 Hm
10 Fm
10 Fm
V =1.575V
400mA
OUT1
V =1.8V
600mA
OUT2
L1 Vout 1400 mA:
DEF _1 = 0: 1.575 V
DEF _1 = 1: 1.1 V
Vout 2600 mA :
TPS 62401 : 1.8 V
TPS 62403 : 2.8 V
SW1
FB 1
SW2
ADJ2
DEF _1
10 µF
VIN 2.5V – 6V VIN
EN_1
EN_2
MODE /
DATA
TPS62401/03
GND
Processor
VCore
VI/O
VCore_Sel
L2
10 µF
10 µF
TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
SLVS681E –JUNE 2006–REVISED APRIL 2010
www.ti.com
Figure 45. TPS62401 Fixed 1.575V/1.8V Outputs
Figure 46. Dynamic Voltage Scaling on Vout1 Controlled by DEF_1 pin
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600 mA
400 mA
3.3 µH
10 µF
Vout 1: 1.575V
Vout 2: 2.8V
SW 1
FB 1
SW 2
ADJ 2
DEF _1
10 µF
10 mF
VIN
2.5V – 6V
VIN
EN _1
EN _2
MODE/
DATA
TPS62403
GND
2.2 µH
DIL+Vout 1*Vout
Vin
L ƒ
ILmax +Ioutmax )
DIL
2
TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
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SLVS681E –JUNE 2006–REVISED APRIL 2010
Figure 47. TPS62403 1.575V/2.8V Outputs
OUTPUT FILTER DESIGN (INDUCTOR AND OUTPUT CAPACITOR)
The converters are designed to operate with a minimum inductance of 1.75mH and minimum capacitance of 6mF.
The device is optimized to operate with inductors of 2.2mH to 4.7mH and output capacitors of 10mF to 22mF.
Inductor selection
The selected inductor has to be rated for its DC resistance and saturation current. The DC resistance of the
inductor will influence directly the efficiency of the converter. Therefore an inductor with lowest DC resistance
should be selected for highest efficiency.
Equation 6 calculates the maximum inductor current under static load conditions. The saturation current of the
inductor should be rated higher than the maximum inductor current as calculated with Equation 7. This is
recommended because during heavy load transient the inductor current rises above the calculated value.
(6)
(7)
with:
f = Switching Frequency (2.25MHz typical)
L = Inductor Value
ΔIL= Peak-to-Peak inductor ripple current
ILmax = Maximum Inductor current
The highest inductor current occurs at maximum Vin.
Open core inductors have a soft saturation characteristic and they can usually handle higher inductor currents
versus a comparable shielded inductor.
A more conservative approach is to select the inductor current rating just for the maximum switch current of the
corresponding converter. Take into consideration that the core material from inductor to inductor differs and this
difference has an impact on the efficiency.
Refer to Table 7 and the typical application circuit examples for possible inductors.
Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 31
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IRMSCout +Vout 1*Vout
Vin
L ƒ 1
2 3
Ǹ
DVout +Vout 1*Vout
Vin
L ƒ ǒ1
8 Cout ƒ)ESRǓ
TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
SLVS681E –JUNE 2006–REVISED APRIL 2010
www.ti.com
Table 7. List of Inductors
DIMENSIONS [mm3] INDUCTOR TYPE SUPPLIER
3.2×2.6×1.0 MIPW3226 FDK
3×3×0.9 LPS3010 Coilcraft
2.8×2.6×1.0 VLF3010 TDK
2.8x2.6×1.4 VLF3014 TDK
3×3×1.4 LPS3015 Coilcraft
3.9×3.9×1.7 LPS4018 Coilcraft
Output Capacitor Selection
The advanced fast response voltage mode control scheme of the converters allows the use of tiny ceramic
capacitors with a typical value of 10mF to 22mF, without having large output voltage under and overshoots during
heavy load transients. Ceramic capacitors with low ESR values results in lowest output voltage ripple, and are
therefore recommended. The output capacitor requires either X7R or X5R dielectric. Y5V and Z5U dielectric
capacitors are not recommended due to their wide variation in capacitance.
If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application
requirements. The RMS ripple current is calculated as:
(8)
At nominal load current the inductive converters operate in PWM mode and the overall output voltage ripple is
the sum of the voltage spike caused by the output capacitor ESR, plus the voltage ripple caused by charging and
discharging the output capacitor:
(9)
Where the highest output voltage ripple occurs at the highest input voltage Vin.
At light load currents the converters operate in Power Save Mode and the output voltage ripple is dependent on
the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external
capacitor. Higher output capacitors like 22mF values minimize the voltage ripple in PFM Mode and tighten DC
output accuracy in PFM Mode.
Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required to prevent large voltage transients that can cause misbehavior of the device or interference with other
circuits in the system. An input capacitor of 10mF is sufficient.
LAYOUT CONSIDERATIONS
As for all switching power supplies, the layout is an important step in the design. Proper function of the device
demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If
the layout is not carefully done, the regulator could show poor line and/or load regulation, stability issues as well
as EMI problems. It is critical to provide a low-inductance, impedance ground path. Therefore, use wide and
short traces for the main current paths as indicated in bold in Figure 48.
The input capacitor should be placed as close as possible to the IC pins VIN and GND, the inductor and output
capacitor as close as possible to the pins SW1 and GND.
32 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS62400 TPS62401 TPS62402 TPS62403 TPS62404
SW1
FB1
DEF_1
VIN3V – 6V
VIN
EN_1
EN_2
MODE/
DATA
TPS62400
GND
R11
R12
L1
PowerPAD
R21
R22
SW2
ADJ2
L2
Cff2
33pF
C
10 F
IN
m
3.3 Hm
COUT2
3.3 Hm
COUT1
TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
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SLVS681E –JUNE 2006–REVISED APRIL 2010
Connect the GND Pin of the device to the PowerPAD of the PCB and use this Pad as a star point. For each
converter use a common Power GND node and a different node for the signal GND to minimize the effects of
ground noise. Connect these ground nodes together to the PowerPAD (star point) underneath the IC. Keep the
common path to the GND PIN, which returns the small signal components and the high current of the output
capacitors, as short as possible to avoid ground noise. The output voltage sense lines (FB 1, DEF_1, ADJ2)
should be connected right to the output capacitor and routed away from noisy components and traces (e.g., SW1
and SW2 lines). If the EasyScale™ interface is operated with high transmission rates, the MODE/DATA trace
must be routed away from the ADJ2 line to avoid capacitive coupling into the ADJ2 pin. A GND guard ring
between the MODE/DATA pin and ADJ2 pin avoids potential noise coupling.
Figure 48. Layout Diagram
Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 33
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CIN
COUT1
COUT2
GNDPin
connected
withPower
Pad
TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
SLVS681E –JUNE 2006–REVISED APRIL 2010
www.ti.com
Figure 49. PCB Layout
34 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS62400 TPS62401 TPS62402 TPS62403 TPS62404
TPS62400, TPS62401
TPS62402, TPS62403, TPS62404
www.ti.com
SLVS681E –JUNE 2006–REVISED APRIL 2010
REVISION HISTORY
NOTE: Page numbers of current version may differ from previous versions.
Changes from Revision D (June 2006) to Revision E Page
• Added TPS62404 device ...................................................................................................................................................... 1
• Added TPS62404 device to Ordering Information table. ...................................................................................................... 2
• Added TPS62404 device efficiency graph (Figure 7). ........................................................................................................ 10
• Added TPS62404 device to Addressable Registers table. ................................................................................................. 21
• Added TPS62404 device to 'Selectable Output Voltages for Converter 1' table. ............................................................... 24
• Added TPS62404 device to 'Selectable Output Voltages for Converter 2' table. ............................................................... 26
• Added TPS62404 device to 'Application Information' section. ........................................................................................... 27
Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 35
Product Folder Link(s): TPS62400 TPS62401 TPS62402 TPS62403 TPS62404
PACKAGE OPTION ADDENDUM
www.ti.com 6-Aug-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS62400DRCR ACTIVE SON DRC 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
TPS62400DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
TPS62400DRCT ACTIVE SON DRC 10 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
TPS62400DRCTG4 ACTIVE SON DRC 10 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
TPS62401DRCR ACTIVE SON DRC 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
TPS62401DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
TPS62401DRCT ACTIVE SON DRC 10 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
TPS62401DRCTG4 ACTIVE SON DRC 10 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
TPS62402DRCR ACTIVE SON DRC 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
TPS62402DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
TPS62402DRCT ACTIVE SON DRC 10 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
TPS62402DRCTG4 ACTIVE SON DRC 10 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
TPS62403DRCR ACTIVE SON DRC 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
TPS62403DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
TPS62403DRCT ACTIVE SON DRC 10 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
TPS62403DRCTG4 ACTIVE SON DRC 10 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
TPS62404DRCR ACTIVE SON DRC 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
PACKAGE OPTION ADDENDUM
www.ti.com 6-Aug-2010
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS62404DRCT ACTIVE SON DRC 10 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS62404 :
•Automotive: TPS62404-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS62400DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62400DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62400DRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62400DRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62401DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62401DRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62402DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62402DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62402DRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62402DRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62403DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62403DRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62404DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62404DRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS62400DRCR SON DRC 10 3000 367.0 367.0 35.0
TPS62400DRCR SON DRC 10 3000 367.0 367.0 35.0
TPS62400DRCT SON DRC 10 250 210.0 185.0 35.0
TPS62400DRCT SON DRC 10 250 210.0 185.0 35.0
TPS62401DRCR SON DRC 10 3000 367.0 367.0 35.0
TPS62401DRCT SON DRC 10 250 210.0 185.0 35.0
TPS62402DRCR SON DRC 10 3000 367.0 367.0 35.0
TPS62402DRCR SON DRC 10 3000 367.0 367.0 35.0
TPS62402DRCT SON DRC 10 250 210.0 185.0 35.0
TPS62402DRCT SON DRC 10 250 210.0 185.0 35.0
TPS62403DRCR SON DRC 10 3000 367.0 367.0 35.0
TPS62403DRCT SON DRC 10 250 210.0 185.0 35.0
TPS62404DRCR SON DRC 10 3000 367.0 367.0 35.0
TPS62404DRCT SON DRC 10 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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