LTC3736EGN-2#TRPBF - ANALOG DEVICES

LTC3736-2

37362fb

TYPICAL APPLICATION

DESCRIPTION

Dual 2-Phase, No RSENSE

Synchronous Controller

with Output Tracking

The LTC

3736-2 is a 2-phase dual synchronous step-down

switching regulator controller with tracking that drives

external complementary power MOSFETs using few ex-

ternal components. The constant-frequency current mode

architecture with MOSFET VDS sensing eliminates the need

for sense resistors and improves efﬁ ciency. Power loss and

noise due to the ESR of the input capacitance are minimized

by operating the two controllers out-of-phase.

Pulse-skipping operation provides high efﬁ ciency at light

loads. 100% duty cycle capability provides low dropout

operation, extending operating time in battery-powered

systems.

The switching frequency can be programmed up to 750kHz,

allowing the use of small surface mount inductors and

capacitors. For noise sensitive applications, the LTC3736-2

switching frequency can be externally synchronized from

250kHz to 850kHz. An internal soft-start, which can be

lengthened externally, smoothly ramps the output voltage

during start-up.

The LTC3736-2 is available in the tiny thermally enhanced

(4mm × 4mm) QFN and 24-lead narrow SSOP packages.

High Efﬁ ciency, 2-Phase, Dual Synchronous DC/DC Step-Down Converter

FEATURES

APPLICATIONS

n No Current Sense Resistors Required

n Out-of-Phase Controllers Reduce Required

Input Capacitance

n Tracking Function

n Wide VIN Range: 2.75V to 9.8V

n 0.6V ±1% Voltage Reference

n High Current Limit

n Constant-Frequency Current Mode Operation

n Low Dropout Operation: 100% Duty Cycle

n True PLL for Frequency Locking or Adjustment

n Selectable Pulse-Skipping/Forced Continuous

Operation

n Auxiliary Winding Regulation

n Internal Soft-Start Circuitry

n Power Good Output Voltage Monitor

n Output Overvoltage Protection

n Micropower Shutdown: IQ = 9μA

n Tiny Low Proﬁ le (4mm × 4mm) QFN and Narrow

SSOP Packages

n One or Two Lithium-Ion Powered Devices

n Notebook and Palmtop Computers, PDAs

n Portable Instruments

n Distributed DC Power Systems

Efﬁ ciency and Power Loss

vs Load Current (Figure 15 Circuit)

SENSE1+

VIN

LTC3736-2

SGND

SENSE2+

TG1 TG2

SW1 SW2

BG1 BG2

PGND PGND

VFB1 VFB2

220pF

VOUT1

2.5V

VOUT2

1.8V

47μF 47μF

15k

220pF

15k

59k 59k

187k 118k

2.2μH 2.2μH

ITH1

37362 TA01a

ITH2

10μF

VIN

2.75V TO 9.8V

LOAD CURRENT (mA)

EFFICIENCY (%)

POWER LOSS (W)

100

1 100 1000 10000

37362 TA01b

0.01

0.1

0.001

VOUT = 2.5V

EFFICIENCY

POWER LOSS

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners. Protected by U.S. Patents, including 5481178,

5929620, 6144194, 6580258, 6304066, 6611131, 6498466.

LTC3736-2

37362fb

ABSOLUTE MAXIMUM RATINGS

Input Supply Voltage (VIN) ........................ –0.3V to 10V

PLLLPF, RUN/SS, SYNC/FCB,

TRACK, SENSE1+

, SENSE2+,

IPRG1, IPRG2 Voltages ................. –0.3V to (VIN + 0.3V)

VFB1, VFB2, ITH1, ITH2 Voltages ................. –0.3V to 2.4V

SW1, SW2 Voltages ........... –2V to VIN + 1V or 10V Max

(Note 1)

TOP VIEW

GN PACKAGE

24-LEAD PLASTIC SSOP

SW1

IPRG1

VFB1

ITH1

IPRG2

PLLLPF

SGND

VIN

TRACK

VFB2

ITH2

PGOOD

SENSE1+

PGND

BG1

SYNC/FCB

TG1

PGND

TG2

RUN/SS

BG2

PGND

SENSE2+

SW2

TJMAX = 125°C, θJA = 130°C/W

24 23 22 21 20 19

789

TOP VIEW

UF PACKAGE

24-LEAD (4mm × 4mm) PLASTIC QFN

10 11 12

ITH1

IPRG2

PLLLPF

SGND

VIN

TRACK

SYNC/FCB

TG1

PGND

TG2

RUN/SS

BG2

VFB1

IPRG1

SW1

SENSE1+

PGND

BG1

VFB2

ITH2

PGOOD

SW2

SENSE2+

PGND

TJMAX = 125°C, θJA = 37°C/W

EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB

PIN CONFIGURATION

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3736-2EGN#PBF LTC3736-2EGN#TRPBF 24-Lead Plastic SSOP –40°C to 85°C

LTC3736-2EUF#PBF LTC3736-2EUF#TRPBF 37362 24-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges.

Consult LTC Marketing for information on non-standard lead based ﬁ nish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/

PGOOD ...................................................... –0.3V to 10V

TG1, TG2, BG1, BG2 Peak Output Current (<10μs) .... 1A

Operating Temperature Range (Note 2) .... –40°C to 85°C

Storage Temperature Range ................... –65°C to 125°C

Junction Temperature (Note 3) ............................ 125°C

Lead Temperature (Soldering, 10 sec)

(LTC3736EGN-2) ................................................... 300°C

LTC3736-2

37362fb

ELECTRICAL CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX UNITS

Main Control Loops

Input DC Supply Current

Normal Mode

Shutdown

UVLO

(Note 4)

RUN/SS = VIN

RUN/SS = 0V

VIN = UVLO Threshold –200mV

4.75

750

μA

Undervoltage Lockout Threshold VIN Falling

VIN Rising

1.95

2.15

2.25

2.45

2.55

2.75

Shutdown Threshold at RUN/SS 0.45 0.65 0.85 V

Start-Up Current Source RUN/SS = 0V 0.4 0.7 1 μA

Regulated Feedback Voltage 0°C to 85°C (Note 5)

–40°C to 85°C l

0.594

0.591

0.6

0.606

0.609

Output Voltage Line Regulation 2.75V < VIN < 9.8V (Note 5) 0.05 0.2 mV/ V

Output Voltage Load Regulation ITH = 0.9V (Note 5)

ITH = 1.7V

0.12

–0.12

0.5

–0.5

VFB1,2 Input Current (Note 5) 10 50 nA

TRACK Input Current TRACK = 0.6V 10 50 nA

Overvoltage Protect Threshold Measured at VFB 0.66 0.68 0.7 V

Overvoltage Protect Hysteresis 20 mV

Auxiliary Feedback Threshold SYNC/FCB Ramping Positive 0.525 0.6 0.675 V

Top Gate (TG) Drive 1, 2 Rise Time CL = 3000pF 40 ns

Top Gate (TG) Drive 1, 2 Fall Time CL = 3000pF 40 ns

Bottom Gate (BG) Drive 1, 2 Rise Time CL = 3000pF 50 ns

Bottom Gate (BG) Drive 1, 2 Fall Time CL = 3000pF 40 ns

Maximum Current Sense Voltage (ΔVSENSE(MAX))

(SENSE+ – SW)

IPRG = Floating

IPRG = 0V

IPRG = VIN

220

150

320

240

167

345

260

185

370

Soft-Start Time Time for VFB1 to Ramp from 0.05V to 0.55V 0.667 0.833 1 ms

Oscillator and Phase-Locked Loop

Oscillator Frequency Unsynchronized (SYNC/FCB Not Clocked)

PLLLPF = Floating

PLLLPF = 0V

PLLLPF = VIN

480

260

650

550

300

750

600

340

825

kHz

Phase-Locked Loop Lock Range SYNC/FCB Clocked

Minimum Synchronizable Frequency

Maximum Synchronizable Frequency

l850

200

1150

250 kHz

kHz

Phase Detector Output Current

Sinking

Sourcing

fOSC > fSYNC/FCB

fOSC < fSYNC/FCB

–4

μA

PGOOD Output

PGOOD Voltage Low IPGOOD Sinking 1mA 125 mV

PGOOD Trip Level VFB with Respect to Set Output Voltage

VFB < 0.6V, Ramping Positive

VFB < 0.6V, Ramping Negative

VFB < 0.6V, Ramping Positive

–13

–16

–10

–13.3

13.3

–7

–10

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VIN = 4.2V unless otherwise speciﬁ ed.

LTC3736-2

37362fb

LOAD CURRENT (mA)

EFFICIENCY (%)

POWER LOSS (W)

100

1 100 1000 10000

37362 G01

0.01

0.1

0.001

VOUT = 2.5V

EFFICIENCY

POWER LOSS

VIN = 3.3V

VIN = 5V

VOUT

COUPLED

100mV/

DIV

VIN = 3.3V

VOUT = 1.8V

ILOAD = 300mA TO 3A

SYNC/FCB = 0V

FIGURE 15 CIRCUIT

100μs/DIV 37362 G02

2A/DIV

TYPICAL PERFORMANCE CHARACTERISTICS

Efﬁ ciency and Power Loss

vs Load Current

Load Step

(Forced Continuous Mode) Load Step (Pulse-Skipping Mode)

Light Load

(Pulse-Skipping Mode)

Light Load

(Forced Continuous Mode)

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTC3736E-2 is guaranteed to meet speciﬁ ed performance

from 0°C to 85°C. Speciﬁ cations over the –40°C to 85°C operating range

are assured by design, characterization and correlation with statistical

process controls.

Note 3: TJ is calculated from the ambient temperature TA and power

dissipation PD according to the following formula:

J = TA + (PD • θJA°C/W)

ELECTRICAL CHARACTERISTICS

Note 4: Dynamic supply current is higher due to gate charge being

delivered at the switching frequency.

Note 5: The LTC3736-2 is tested in a feedback loop that servos ITH to a

speciﬁ ed voltage and measures the resultant VFB voltage.

Note 6: Peak current sense voltage is reduced dependent on duty cycle to

a percentage of value as shown in Figure 1.

VOUT

COUPLED

100mV/

DIV

VIN = 3.3V

VOUT = 1.8V

ILOAD = 300mA TO 3A

SYNC/FCB = VIN

FIGURE 15 CIRCUIT

100μs/DIV 37362 G03

2A/DIV

5V/DIV

VOUT

50mV/DIV

COUPLED

2.5μs/DIVVIN = 5V

VOUT = 2.5V

ILOAD = 300mA

SYNC/FBC = VIN

FIGURE 15 CIRCUIT

37362 G04

2A/DIV

5V/DIV

VOUT

50mV/DIV

AC COUPLED

2.5μs/DIV 37362 G05

2A/DIV

VIN = 5V

VOUT = 2.5V

ILOAD = 300mA

SYNC/FCB = 0V

FIGURE 15 CIRCUIT

VIN = 5V

RLOAD1 = RLOAD2 = 1Ω

FIGURE 15 CIRCUIT

200μs/DIV 37362 G06

500mV/

DIV

VOUT1

2.5V

VOUT2

1.8V

TA = 25°C, unless otherwise noted.

Tracking Start-Up with Internal

Soft-Start (CSS = 0μF)

LTC3736-2

37362fb

TYPICAL PERFORMANCE CHARACTERISTICS

Efﬁ ciency vs Load Current

Regulated Feedback Voltage

vs Temperature

Shutdown (RUN) Threshold

vs Temperature

RUN/SS Pull-Up Current

vs Temperature

Maximum Current Sense Threshold

vs Temperature

Oscillator Frequency

vs Temperature

Tracking Start-Up with External

Soft-Start (CSS = 0.10μF)

Oscillator Frequency

vs Input Voltage

Maximum Current Sense Voltage

vs ITH Pin Voltage

TA = 25°C, unless otherwise noted.

VIN = 5V

RLOAD1 = RLOAD2 = 1Ω

FIGURE 15 CIRCUIT

40ms/DIV 37362 G07

500mV/

DIV

VOUT1

2.5V

VOUT2

1.8V

INPUT VOLTAGE (V)

–5

NORMALIZED FREQUENCY SHIFT (%)

–4

–2

–1

467

37368 G08

–3

35 8910

ITH VOLTAGE (V)

0.5

–20

CURRENT LIMIT (%)

100

1 1.5

37362 G09

FORCED CONTINUOUS

MODE

PULSE-SKIPPING

MODE

LOAD CURRENT (mA)

EFFICIENCY (%)

100

1 100 1000 10000

37362 G10

FIGURE 15 CIRCUIT

VIN = 3.3V

VOUT = 2.5V

PULSE-SKIPPING

MODE

(SYNC/FCB = VIN)

FORCED

CONTINUOUS

(SYNC/FCB = 0V)

TEMPERATURE (°C)

–60

FEEDBACK VOLTAGE (V)

0.600

0.603

0.604

100

37362 G11

0.599

0.598

0.594 –20 20 60

–40 040 80

0.596

0.606

0.605

0.602

0.601

0.597

0.595

TEMPERATURE (°C)

–60

RUN/SS VOLTAGE (V)

0.1

0.3

0.4

0.5

1.0

0.7

–20 20 40

37362 G12

0.2

0.8

0.9

0.6

–40 0 60 80 100

TEMPERATURE (°C)

–60

0.4

RUN/SS PULL-UP CURRENT (μA)

0.5

0.6

0.7

0.8

–20 20 60 100

37362 G13

0.9

1.0

–40 0 40 80

TEMPERATURE (°C)

–60

150

MAXIMUM CURRENT SENSE THRESHOLD (mV)

155

160

165

170

–20 20 60 100

37362 G14

175

180

–40 0 40 80

IPRG = GND

TEMPERATURE (°C)

–60

–10

NROMALIZED FREQUENCY (%)

–8

–4

–2

–20 20 40

37362 G15

–6

–40 0 60 80 100

LTC3736-2

37362fb

PIN FUNCTIONS

ITH1/I

TH2 (Pins 1, 8/Pins 4, 11): Current Threshold and

Error Ampliﬁ er Compensation Point. Nominal operating

range on these pins is from 0.7V to 2V. The voltage on

these pins determines the threshold of the main current

comparator.

PLLLPF (Pin 3/Pin 6): Frequency Set/PLL Lowpass Filter.

When synchronizing to an external clock, this pin serves as

the lowpass ﬁ lter point for the phase-locked loop. Normally

a series RC is connected between this pin and ground.

When not synchronizing to an external clock, this pin serves

as the frequency select input. Tying this pin to GND selects

300kHz operation; tying this pin to VIN selects 750kHz

operation. Floating this pin selects 550kHz operation.

SGND (Pin 4/Pin 7): Small-Signal Ground. This pin serves

as the ground connection for most internal circuits.

VIN (Pin 5/Pin 8): Chip Signal Power Supply. This pin

powers the entire chip except for the gate drivers. Exter-

nally ﬁ ltering this pin with a lowpass RC network (e.g.,

R = 10Ω, C = 1μF) is suggested to minimize noise pickup,

especially in high load current applications.

TRACK (Pin 6/Pin 9): Tracking Input for Second Controller.

Allows the start-up of VOUT2 to track that of VOUT1 accord-

ing to a ratio established by a resistor divider on VOUT1

connected to the TRACK pin. For one-to-one tracking of

VOUT1 and VOUT2 during start-up, a resistor divider with

values equal to those connected to VFB2 from VOUT2 should

be used to connect to TRACK from VOUT1.

PGOOD (Pin 9/Pin 12): Power Good Output Voltage Moni-

tor Open-Drain Logic Output. This pin is pulled to ground

when the voltage on either feedback pin (VFB1, VFB2) is

not within ±13.3% of its nominal set point.

PGND (Pins 12, 16, 20, 25/Pins 15, 19, 23): Power

Ground. These pins serve as the ground connection for

the gate drivers and the negative input to the reverse cur-

rent comparators. The Exposed Pad must be soldered to

PCB ground.

RUN/SS (Pin 14/Pin 17): Run Control Input and Optional

External Soft-Start Input. Forcing this pin below 0.65V shuts

down the chip (both channels). Driving this pin to VIN or

releasing this pin enables the chip, using the chip’s internal

soft-start. An external soft-start can be programmed by

connecting a capacitor between this pin and ground.

TG1/TG2 (Pins 17, 15/Pins 18, 20): Top (PMOS) Gate

Drive Output. These pins drive the gates of the external

P-channel MOSFETs. These pins have an output swing

from PGND to SENSE+.

SYNC/FCB (Pin 18/Pin 21): This pin performs three func-

tions: 1) auxiliary winding feedback input, 2) external

clock synchronization input for phase-locked loop, and

3) pulse-skipping operation or forced continuous mode

(QFN/SSOP Package)

TYPICAL PERFORMANCE CHARACTERISTICS

Undervoltage Lockout Threshold

vs Temperature

Shutdown Quiescent Current

vs Input Voltage

RUN/SS Start-Up Current

vs Input Voltage

TA = 25°C, unless otherwise noted.

TEMPERATURE (°C)

–60

INPUT (VIN) VOLTAGE (V)

2.30

2.40

100

37362 G16

2.20

2.10 –20 20 60

–40 040 80

2.50

2.25

2.35

2.15

2.45 VIN RISING

VIN FALLING

INPUT VOLTAGE (V)

SHUTDOWN CURRENT (μA)

467

37362 G17

35 8910

RUN/SS = 0V

INPUT VOLTAGE (V)

RUN/SS PIN PULL-UP CURRENT (μA)

0.5

0.6

0.7

37362 G18

0.4

0.3

0.1

468

3579

0.2

0.9

0.8

RUN/SS = 0V

LTC3736-2

37362fb

PIN FUNCTIONS

FUNCTIONAL DIAGRAM

select. For auxiliary winding applications, connect to a

resistor divider from the auxiliary output. To synchronize

with an external clock using the PLL, apply a CMOS compat-

ible clock with a frequency between 250kHz and 850kHz.

To select pulse-skipping operation at light loads, tie this

pin to VIN. Grounding this pin selects forced continuous

operation, which allows the inductor current to reverse.

When synchronized to an external clock, pulse-skipping

operation is enabled at light loads.

BG1/BG2 (Pins 19, 13/Pins 22, 16): Bottom (NMOS) Gate

Drive Output. These pins drive the gates of the external

N-channel MOSFETs. These pins have an output swing

from PGND to SENSE+.

SENSE1+/SENSE2+ (Pins 21, 11/Pins 24, 14): Positive

Input to Differential Current Comparator. Also powers

the gate drivers. Normally connected to the source of the

external P-channel MOSFET.

SW1/SW2 (Pins 22, 10/Pins 1, 13): Switch Node Con-

nection to Inductor. Also the negative input to differential

peak current comparator and an input to the reverse cur-

rent comparator. Normally connected to the drain of the

external P-channel MOSFETs, the drain of the external

N-channel MOSFET, and the inductor.

IPRG1/IPRG2 (Pins 23, 2/Pins 2, 5): Three-State Pins to

Select Maximum Peak Sense Voltage Threshold. These

pins select the maximum allowed voltage drop between

the SENSE+ and SW pins (i.e., the maximum allowed drop

across the external P-channel MOSFET) for each channel.

Tie to VIN, GND or ﬂ oat to select 345mV, 167mV, or 240mV,

respectively.

VFB1/VFB2 (Pins 24, 7/Pins 3, 10): Feedback Pins. Re-

ceives the remotely sensed feedback voltage for its con-

troller from an external resistor divider across the output.

–

SHDN

0.6V

VREF

EXTSS

0.7μA

CLK1

CLK2

FCB

0.54V

VFB1

VFB2

FCB

0.6V

SLOPE1

SLOPE2

RUN/SS

VIN CVIN

VIN

(TO CONTROLLER 1, 2)

RVIN

SYNC/FCB

PLLLPF

VOLTAGE

REFERENCE

UNDERVOLTAGE

LOCKOUT

PHASE

DETECTOR

SYNC DETECT

SLOPE

COMP

VOLTAGE CONTROLLED

OSCILLATOR

tSEC = 1ms

INTSS

PGOOD

SHDN

OV1

UV1

UV2 OV2 37362 FD

(Common Circuitry)

(QFN/SSOP Package)

LTC3736-2

37362fb

FUNCTIONAL DIAGRAM

(Controller 1)

OV1

CLK1

SC1

FCB

SLOPE1

SW1

SENSE1+

IREV1

RS1

ANTISHOOT

THROUGH

PGND

TG1

SENSE1+

VIN

VOUT1

CIN

COUT1

MP1

MN1

BG1

R1B

PGND

VFB1

TH1

RITH1

CITH1

0.6V

0.12V

SC1

VFB1

SW1

SENSE1+

R1A

–

EXTSS

INTSS

EAMP

SHDN

–

IPRG1

–

ICMP

–

VFB1

OV1

0.68V

–

PGND

IREV1

IPROG1 FCB

SW1

37362 CONT1

–

SWITCHING

LOGIC

AND

BLANKING

CIRCUIT

SCP

RICMPOVP

LTC3736-2

37362fb

FUNCTIONAL DIAGRAM

(Controller 2)

OV2

CLK2

SC2

FCB

SLOPE2

SW2

SENSE2+

SHDN

IREV2

RS2

ANTISHOOT

THROUGH

PGND

SENSE2+

TG2

SENSE2+VIN

MP2

MN2

BG2

R2B

RTRACKB

RTRACKA

PGND

VFB2

TRACK

RITH2

ITH2

CITH2

0.6V

0.12V

SC2

TRACK

VFB2

SW2

R2A

VOUT1

–

EAMP

–

ICMP

–

VFB2

OV2

0.68V

–

PGND

IREV2

FCB

SW2

3736 CONT2

–

SWITCHING

LOGIC

AND

BLANKING

CIRCUIT

OVP

SCP

IPRG2

VOUT2

COUT2

LTC3736-2

37362fb

OPERATION

Main Control Loop

The LTC3736-2 uses a constant-frequency, current mode

architecture with the two controllers operating 180 degrees

out-of-phase. During normal operation, the top external

P-channel power MOSFET is turned on when the clock

for that channel sets the RS latch, and turned off when

the current comparator (ICMP) resets the latch. The peak

inductor current at which ICMP resets the RS latch is

determined by the voltage on the ITH pin, which is driven

by the output of the error ampliﬁ er (EAMP). The VFB pin

receives the output voltage feedback signal from an ex-

ternal resistor divider. This feedback signal is compared

to the internal 0.6V reference voltage by the EAMP. When

the load current increases, it causes a slight decrease in

VFB relative to the 0.6V reference, which in turn causes the

ITH voltage to increase until the average inductor current

matches the new load current. While the top P-channel

MOSFET is off, the bottom N-channel MOSFET is turned

on until either the inductor current starts to reverse, as

indicated by the current reversal comparator, IRCMP, or the

beginning of the next cycle.

Shutdown, Soft-Start and Tracking Start-Up (RUN/SS

and TRACK Pins)

The LTC3736-2 is shut down by pulling the RUN/SS pin

low. In shutdown, all controller functions are disabled and

the chip draws only 9μA. The TG outputs are held high

(off) and the BG outputs low (off) in shutdown. Releasing

RUN/SS allows an internal 0.7μA current source to charge

up the RUN/SS pin. When the RUN/SS pin reaches 0.65V,

the LTC3736-2’s two controllers are enabled.

The start-up of VOUT1 is controlled by the LTC3736-2’s

internal soft-start. During soft-start, the error ampliﬁ er

EAMP compares the feedback signal VFB1 to the internal

soft-start ramp (instead of the 0.6V reference), which rises

linearly from 0V to 0.6V in about 1ms. This allows the

output voltage to rise smoothly from 0V to its ﬁ nal value,

while maintaining control of the inductor current.

The 1ms soft-start time can be increased by connecting the

optional external soft-start capacitor CSS between the RUN/

SS and SGND pins. As the RUN/SS pin continues to rise

linearly from approximately 0.65V to 1.3V (being charged

by the internal 0.7μA current source), the EAMP regulates

the VFB1 proportionally linearly from 0V to 0.6V.

The start-up of VOUT2 is controlled by the voltage on the

TRACK pin. When the voltage on the TRACK pin is less

than the 0.6V internal reference, the LTC3736-2 regulates

the VFB2 voltage to the TRACK pin instead of the 0.6V ref-

erence. Typically, a resistor divider on VOUT1 is connected

to the TRACK pin to allow the start-up of VOUT2 to track

that of VOUT1. For one-to-one tracking during start-up, the

resistor divider would have the same values as the divider

on VOUT2 that is connected to VFB2.

Light Load Operation (Pulse-Skipping or Continuous

Conduction) (SYNC/FCB Pin)

The LTC3736-2 can be enabled to enter high efﬁ ciency

pulse-skipping operation or forced continuous conduc-

tion mode at low load currents. To select pulse-skipping

operation, tie the SYNC/FCB pin to a DC voltage above

0.6V (e.g., VIN). To select forced continuous operation, tie

the SYNC/FCB to a DC voltage below 0.6V (e.g., SGND).

This 0.6V threshold between pulse-skipping operation

and forced continuous mode can be used in secondary

winding regulation as described in the Auxiliary Winding

Control Using SYNC/FCB Pin discussion in the Applications

Information section.

In forced continuous operation, the inductor current is

allowed to reverse at light loads or under large transient

conditions. The peak inductor current is determined by the

voltage on the ITH pin. The P-channel MOSFET is turned

on every cycle (constant frequency) regardless of the ITH

pin voltage. In this mode, the efﬁ ciency at light loads is

lower than in pulse-skipping operation. However, continu-

ous mode has the advantages of lower output ripple and

less interference with audio circuitry.

When the SYNC/FCB pin is tied to a DC voltage above

0.6V or when it is clocked by an external clock source to

use the phase-locked loop (see Frequency Selection and

Phase-Locked Loop), the LTC3736-2 operates in PWM

pulse-skipping mode at light loads. In this mode, the

current comparator ICMP may remain tripped for several

cycles and force the external P-channel MOSFET to stay

off for the same number of cycles. The inductor current is

not allowed to reverse, though (discontinuous operation).

This mode, like forced continuous operation, exhibits low

output ripple as well as low audio noise and reduced RF

interference. However, it provides low current efﬁ ciency

(Refer to Functional Diagram)

LTC3736-2

37362fb

OPERATION

higher than forced continuous mode. During start-up or

a short-circuit condition (VFB1 or VFB2 ≤ 0.54V), the

LTC3736-2 operates in pulse-skipping mode (no current

reversal allowed), regardless of the state of the SYNC/

FCB pin.

Short-Circuit Protection

When an output is shorted to ground (VFB < 0.12V), the

switching frequency of that controller is reduced to one

ﬁ fth of the normal operating frequency. The other controller

is unaffected and maintains normal operation.

The short-circuit threshold on VFB2 is based on the smaller

of 0.12V and a fraction of the voltage on the TRACK pin.

This also allows VOUT2 to start up and track VOUT1 more

easily. Note that if VOUT1 is truly short-circuited (VOUT1 =

VFB1 = 0V), then the LTC3736-2 will try to regulate VOUT2

to 0V if a resistor divider on VOUT1 is connected to the

TRACK pin.

Output Overvoltage Protection

As a further protection, the overvoltage comparator (OV)

guards against transient overshoots, as well as other more

serious conditions that may overvoltage the output. When

the feedback voltage on the VFB pin has risen 13.33%

above the reference voltage of 0.6V, the external P-chan-

nel MOSFET is turned off and the N-channel MOSFET is

turned on until the overvoltage is cleared.

Frequency Selection and Phase-Locked Loop (PLLLPF

and SYNC/FCB Pins)

The selection of switching frequency is a tradeoff between

efﬁ ciency and component size. Low frequency opera-

tion increases efﬁ ciency by reducing MOSFET switching

losses, but requires larger inductance and/or capacitance

to maintain low output ripple voltage.

The switching frequency of the LTC3736-2’s controllers

can be selected using the PLLLPF pin.

If the SYNC/FCB is not being driven by an external

clock source, the PLLLPF can be ﬂ oated, tied to VIN

or tied to SGND to select 550kHz, 750kHz or 300kHz,

respectively.

A phase-locked loop (PLL) is available on the LTC3736-2

to synchronize the internal oscillator to an external clock

source that is connected to the SYNC/FCB pin. In this

case, a series RC should be connected between the

PLLLPF pin and SGND to serve as the PLL’s loop ﬁ lter.

The LTC3736-2 phase detector adjusts the voltage on the

PLLLPF pin to align the turn-on of controller 1’s external

P-channel MOSFET to the rising edge of the synchronizing

signal. Thus, the turn-on of controller 2’s external P-chan-

nel MOSFET is 180 degrees out-of-phase with the rising

edge of the external clock source.

The typical capture range of the LTC3736-2’s phase-locked

loop is from approximately 200kHz to 1MHz, and is guaran-

teed over temperature to be between 250kHz and 850kHz.

In other words, the LTC3736-2’s PLL is guaranteed to lock

to an external clock source whose frequency is between

250kHz and 850kHz.

Dropout Operation

When the input supply voltage (VIN) decreases towards

the output voltage, the rate of change of the inductor

current while the external P-channel MOSFET is on (ON

cycle) decreases. This reduction means that the P-channel

MOSFET will remain on for more than one oscillator cycle

if the inductor current has not ramped up to the threshold

set by the EAMP on the ITH pin. Further reduction in the

input supply voltage will eventually cause the P-channel

MOSFET to be turned on 100%, i.e., DC. The output volt-

age will then be determined by the input voltage minus

the voltage drop across the P-channel MOSFET and the

inductor.

Undervoltage Lockout

To prevent operation of the external MOSFETs below safe

input voltage levels, an undervoltage lockout is incorpo-

rated in the LTC3736-2. When the input supply voltage

(VIN) drops below 2.3V, the external P- and N-channel

MOSFETs and all internal circuitry are turned off except

for the undervoltage block, which draws only a few

microamperes.

(Refer to Functional Diagram)

LTC3736-2

37362fb

Peak Current Sense Voltage Selection and Slope

Compensation (IPRG1 and IPRG2 Pins)

When a controller is operating below 20% duty cycle, the

peak current sense voltage (between the SENSE+ and SW

pins) allowed across the external P-channel MOSFET is

determined by:

Δ=

()

VAV V

SENSE MAX ITH

()

–.07

where A is a constant determined by the state of the IPRG

pins. Floating the IPRG pin selects A = 1.875; tying IPRG

to VIN selects A = 2.7; tying IPRG to SGND selects A = 1.3.

The maximum value of VITH is typically about 1.98V, so

the maximum sense voltage allowed across the external

P-channel MOSFET is 240mV, 345mV, or 167mV for the

three respective states of the IPRG pin. The peak sense

voltages for the two controllers can be independently

selected by the IPRG1 and IPRG2 pins.

However, once the controller’s duty cycle exceeds 20%,

slope compensation begins and effectively reduces the

peak sense voltage by a scale factor given by the curve

in Figure 1.

The peak inductor current is determined by the peak sense

voltage and the on-resistance of the external P-channel

MOSFET:

PK SENSE MAX

DS ON

=Δ()

()

Power Good (PGOOD) Pin

A window comparator monitors both feedback voltages

and the open-drain PGOOD output pin is pulled low when

either or both feedback voltages are not within ±10% of the

0.6V reference voltage. PGOOD is low when the LTC3736-2

is shut down or in undervoltage lockout.

2-Phase Operation

Why the need for 2-phase operation? Until recently,

constant-frequency dual switching regulators operated

both controllers in phase (i.e., single-phase operation).

This means that both topside MOSFETs (P-channel) are

turned on at the same time, causing current pulses of up

to twice the amplitude of those from a single regulator to

be drawn from the input capacitor. These large amplitude

pulses increase the total RMS current ﬂ owing in the input

capacitor, requiring the use of larger and more expensive

input capacitors, and increase both EMI and power losses

in the input capacitor and input power supply.

With 2-phase operation, the two controllers of the LTC3736-2

are operated 180 degrees out-of-phase. This effectively

interleaves the current pulses coming from the topside

MOSFET switches, greatly reducing the time where they

overlap and add together. The result is a signiﬁ cant reduc-

tion in the total RMS current, which in turn allows the

use of smaller, less expensive input capacitors, reduces

shielding requirements for EMI and improves real world

operating efﬁ ciency.

OPERATION

Figure 1. Maximum Peak Current vs Duty Cycle

DUTY CYCLE (%)

SF = I/IMAX (%)

110

100

37362 F01

030 50 70

200 40 60 80 100

(Refer to Functional Diagram)

LTC3736-2

37362fb

OPERATION

Figure 2 shows example waveforms for a single-phase

dual controller versus a 2-phase LTC3736-2 system. In this

case, 2.5V and 1.8V outputs, each drawing a load current

of 2A, are derived from a 7V (e.g., a 2-cell Li-Ion battery)

input supply. In this example, 2-phase operation would

reduce the RMS input capacitor current from 1.79ARMS

to 0.91ARMS. While this is an impressive reduction by

itself, remember that power losses are proportional to

IRMS2, meaning that actual power wasted is reduced by

a factor of 3.86.

The reduced input ripple current also means that less

power is lost in the input power path, which could include

batteries, switches, trace/connector resistances, and

protection circuitry. Improvements in both conducted

and radiated EMI also directly accrue as a result of the

reduced RMS input current and voltage. Signiﬁ cant cost

and board footprint savings are also realized by being able

to use smaller, less expensive, lower RMS current-rated

input capacitors.

Of course, the improvement afforded by 2-phase operation

is a function of the relative duty cycles of the two control-

lers, which in turn are dependent upon the input supply

voltage. Figure 3 depicts how the RMS input current varies

for single-phase and 2-phase dual controllers with 2.5V

and 1.8V outputs over a wide input voltage range.

It can be readily seen that the advantages of 2-phase op-

eration are not limited to a narrow operating range, but in

fact extend over a wide region. A good rule of thumb for

most applications is that 2-phase operation will reduce the

input capacitor requirement to that for just one channel

operating at maximum current and 50% duty cycle.

Figure 2. Example Waveforms for a Single-Phase

Dual Controller vs the 2-Phase LTC3736-2

Figure 3. RMS Input Current Comparison

Single-Phase

Dual Controller

2-Phase

Dual Controller

SW1 (V)

SW2 (V)

IL1

IL2

IIN

37362 F02

INPUT VOLTAGE (V)

INPUT CAPACITOR RMS CURRENT

0.2

0.6

0.8

1.0

2.0

1.4

467

37362 F03

0.4

1.6

1.8

1.2

35 8910

SINGLE-PHASE

DUAL CONTROLER

2-PHASE

DUAL CONTROLER

VOUT1 = 2.5V/2A

VOUT2 = 1.8V/2A

(Refer to Functional Diagram)

LTC3736-2

37362fb

The typical LTC3736-2 application circuit is shown in

Figure 13. External component selection for each of the

LTC3736-2’s controllers is driven by the load requirement

and begins with the selection of the inductor (L) and the

power MOSFETs (MP and MN).

Power MOSFET Selection

Each of the LTC3736-2’s two controllers requires two

external power MOSFETs: a P-channel MOSFET for the

topside (main) switch and an N-channel MOSFET for the

bottom (synchronous) switch. Important parameters for

the power MOSFETs are the breakdown voltage VBR(DSS),

threshold voltage VGS(TH), on-resistance RDS(ON), reverse

transfer capacitance CRSS, turn-off delay tD(OFF) and the

total gate charge QG.

The gate drive voltage is the input supply voltage. Since

the LTC3736-2 is designed for operation down to low input

voltages, a sublogic level MOSFET (RDS(ON) guaranteed at

VGS = 2.5V) is required for applications that work close to

this voltage. When these MOSFETs are used, make sure that

the input supply to the LTC3736-2 is less than the absolute

maximum MOSFET VGS rating, which is typically 8V.

The P-channel MOSFET’s on-resistance is chosen based on

the required load current. The maximum average output

load current IOUT(MAX) is equal to the peak inductor cur-

rent minus half the peak-to-peak ripple current IRIPPLE.

The LTC3736-2’s current comparator monitors the drain-

to-source voltage VDS of the P-channel MOSFET, which

is sensed between the SENSE+ and SW pins. The peak

inductor current is limited by the current threshold, set by

the voltage on the ITH pin of the current comparator. The

voltage on the ITH pin is internally clamped, which limits

the maximum current sense threshold ΔVSENSE(MAX) to

approximately 240mV when IPRG is ﬂ oating (167mV when

IPRG is tied low; 345mV when IPRG is tied high).

The output current that the LTC3736-2 can provide is

given by:

OUT MAX

SENSE MAX

DS ON

RIPPL

()

–=Δ

APPLICATIONS INFORMATION

A reasonable starting point is setting ripple current IRIPPLE

to be 40% of IOUT(MAX). Rearranging the above equation

yields:

DS ON MAX

SENSE MAX

OUT MAX

()( )

()

•=Δ

or Duty Cycle < 20%.

However, for operation above 20% duty cycle, slope

compensation has to be taken into consideration to select

the appropriate value of RDS(ON) to provide the required

amount of load current:

RSF

DS ON MAX

SENSE MAX

OUT MAX

()( )

()

••=Δ

where SF is a scale factor whose value is obtained from

the curve in Figure 1.

These must be further derated to take into account the

signiﬁ cant variation in on-resistance with temperature.

The following equation is a good guide for determin-ing

the required RDS(ON)MAX at 25°C (manufacturer’s speciﬁ ca-

tion), allowing some margin for variations in the LTC3736-2

and external component values:

RSF

DS ON MAX

SENSE MAX

OUT MAX

()( )

()

(

•.• •=Δ

609

)) •ρT

The

T is a normalizing term accounting for the tem-

perature variation in on-resistance, which is typically

about 0.4%/ °C, as shown in Figure 4. Junction-to-case

temperature TJC is about 10°C in most applications. For

a maximum ambient temperature of 70°C, using

80°C ~

1.3 in the above equation is a reasonable choice.

The power dissipated in the top and bottom MOSFETs

strongly depends on their respective duty cycles and load

current. When the LTC3736-2 is operating in continuous

mode, the duty cycles for the MOSFETs are:

Top P Channel Duty Cycle V

Bottom N C

OUT

hhannel Duty Cycle VV

IN OUT

=–

LTC3736-2

37362fb

The MOSFET power dissipations at maximum output

current are:

VIRV

TOP OUT

IN OUT MAX T DS ON IN

=+••• •

•

() ()

2ρ

OOUT MAX RSS OSC

BOT IN OUT

IN OUT MA

PVV

()

(

••

–•=XX T DS ON

)()

••

2ρ

Both MOSFETs have I2R losses and the PTOP equation

includes an additional term for transition losses, which are

largest at high input voltages. The bottom MOSFET losses

are greatest at high input voltage or during a short-circuit

when the bottom duty cycle is nearly 100%.

The LTC3736-2 utilizes a nonoverlapping, antishoot-

through gate drive control scheme to ensure that the

P- and N-channel MOSFETs are not turned on at the same

time. To function properly, the control scheme requires

that the MOSFETs used are intended for DC/DC switching

applications. Many power MOSFETs, particularly P-channel

MOSFETs, are intended to be used as static switches and

therefore are slow to turn on or off.

Reasonable starting criteria for selecting the P-channel

MOSFET are that it must typically have a gate charge (QG)

Figure 4. RDS(ON) vs Temperature

JUNCTION TEMPERATURE (°C)

–50

RT NORMALIZED ON RESISTANCE

1.0

1.5

150

37362 F04

0.5

0050 100

2.0

less than 25nC to 30nC (at 4.5VGS) and a turn-off delay

(tD(OFF)) of less than approximately 140ns. However, due

to differences in test and speciﬁ cation methods of various

MOSFET manufacturers, and in the variations in QG and

tD(OFF) with gate drive (VIN) voltage, the P-channel MOSFET

ultimately should be evaluated in the actual LTC3736-2

application circuit to ensure proper operation.

Shoot-through between the P-channel and N-channel

MOSFETs can most easily be spotted by monitoring the

input supply current. As the input supply voltage increases,

if the input supply current increases dramatically, then the

likely cause is shoot-through. Note that some MOSFETs

that do not work well at high input voltages (e.g., VIN >

5V) may work ﬁ ne at lower voltages (e.g., 3.3V). Table 1

shows a selection of P-channel MOSFETs from different

manufacturers that are known to work well in LTC3736-2

applications.

Selecting the N-channel MOSFET is typically easier, since for

a given RDS(ON), the gate charge and turn-on and turn-off

delays are much smaller than for a P-channel MOSFET.

Table 1. Selected P-Channel MOSFETs Suitable for LTC3736-2

Applications

PART

NUMBER MANUFACTURER TYPE PACKAGE

Si7540DP Siliconix Complementary

P/N

PowerPak

SO-8

Si9801DY Siliconix Complementary

P/N

SO-8

FDW2520C Fairchild Complementary

P/N

TSSOP-8

FDW2521C Fairchild Complementary

P/N

TSSOP-8

Si3447BDV Siliconix Single P TSOP-6

Si9433BDY Siliconix Single P SO-8

FDC602P Fairchild Single P TSOP-6

FDC606P Fairchild Single P TSOP-6

FDC638P Fairchild Single P TSOP-6

FDW2502P Fairchild Dual P TSSOP-8

FDS6875 Fairchild Dual P SO-8

HAT1054R Hitachi Dual P SO-8

NTMD6P02R2-D On Semiconductor Dual P SO-8

APPLICATIONS INFORMATION

LTC3736-2

37362fb

APPLICATIONS INFORMATION

Operating Frequency and Synchronization

The choice of operating frequency, fOSC, is a trade-off

between efﬁ ciency and component size. Low frequency

operation improves efﬁ ciency by reducing MOSFET

switching losses, both gate charge loss and transition

loss. However, lower frequency operation requires more

inductance for a given amount of ripple current.

The internal oscillator for each of the LTC3736-2’s control-

lers runs at a nominal 550kHz frequency when the PLLLPF

pin is left ﬂ oating and the SYNC/FCB pin is a DC low or

high. Pulling the PLLLPF to VIN selects 750kHz operation;

pulling the PLLLPF to GND selects 300kHz operation.

Alternatively, the LTC3736-2 will phase-lock to a clock

signal applied to the SYNC/FCB pin with a frequency be-

tween 250kHz and 850kHz (see Phase-Locked Loop and

Frequency Synchronization).

Inductor Value Calculation

Given the desired input and output voltages, the inductor

value and operating frequency fOSC directly determine the

inductor’s peak-to-peak ripple current:

RIPPLE OUT

IN OUT

OSC

=⎛

⎝

⎜⎞

⎠

⎟

–

•

Lower ripple current reduces core losses in the inductor,

ESR losses in the output capacitors, and output voltage

ripple. Thus, highest efﬁ ciency operation is obtained at

low frequency with a small ripple current. Achieving this,

however, requires a large inductor.

A reasonable starting point is to choose a ripple current

that is about 40% of IOUT(MAX). Note that the largest ripple

current occurs at the highest input voltage. To guarantee

that ripple current does not exceed a speciﬁ ed maximum,

the inductor should be chosen according to:

LVV

IN OUT

OSC RIPPLE

OUT

≥–

••

Inductor Core Selection

Once the inductance value is determined, the type of in-

ductor must be selected. Core loss is independent of core

size for a ﬁ xed inductor value, but it is very dependent

on inductance selected. As inductance increases, core

losses go down. Unfortunately, increased inductance

requires more turns of wire and therefore copper losses

will increase.

Ferrite designs have very low core loss and are preferred

at high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates “hard,” which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

Schottky Diode Selection (Optional)

The Schottky diodes D1 and D2 in Figure 16 conduct

current during the dead time between the conduction of

the power MOSFETs . This prevents the body diode of the

bottom N-channel MOSFET from turning on and storing

charge during the dead time, which could cost as much as

1% in efﬁ ciency. A 1A Schottky diode is generally a good

size for most LTC3736-2 applications, since it conducts

a relatively small average current. Larger diodes result in

additional transition losses due to their larger junction

capacitance. This diode may be omitted if the efﬁ ciency

loss can be tolerated.

CIN and COUT Selection

The selection of CIN is simpliﬁ ed by the 2-phase architec-

ture and its impact on the worst-case RMS current drawn

through the input network (battery/fuse/capacitor). It can be

shown that the worst-case capacitor RMS current occurs

when only one controller is operating. The controller with

the highest (VOUT)(IOUT) product needs to be used in the

formula below to determine the maximum RMS capacitor

LTC3736-2

37362fb

APPLICATIONS INFORMATION

current requirement. Increasing the output current drawn

from the other controller will actually decrease the input

RMS ripple current from its maximum value. The out-of-

phase technique typically reduces the input capacitor’s RMS

ripple current by a factor of 30% to 70% when compared

to a single-phase power supply solution.

In continuous mode, the source current of the P-channel

MOSFET is a square wave of duty cycle (VOUT)/(VIN). To

prevent large voltage transients, a low ESR capacitor sized

for the maximum RMS current of one channel must be

used. The maximum RMS capacitor current is given by:

VVVV

IN MAX

OUT IN OUT

Required IRMS ≈

()( )

[]

–/12

This formula has a maximum at VIN = 2VOUT, where IRMS

= IOUT /2. This simple worst-case condition is commonly

used for design because even signiﬁ cant deviations do not

offer much relief. Note that capacitor manufacturers’ ripple

current ratings are often based on only 2000 hours of life.

This makes it advisable to further derate the capacitor, or

to choose a capacitor rated at a higher temperature than

required. Several capacitors may be paralleled to meet

size or height requirements in the design. Due to the high

operating frequency of the LTC3736-2, ceramic capacitors

can also be used for CIN. Always consult the manufacturer

if there is any question.

The beneﬁ t of the LTC3736-2 2-phase operation can be

calculated by using the equation above for the higher

power controller and then calculating the loss that would

have resulted if both controller channels switched on at

the same time. The total RMS power lost is lower when

both controllers are operating due to the reduced overlap of

current pulses required through the input capacitor’s ESR.

This is why the input capacitor’s requirement calculated

above for the worst-case controller is adequate for the dual

controller design. Also, the input protection fuse resistance,

battery resistance, and PC board trace resistance losses

are also reduced due to the reduced peak currents in a

2-phase system. The overall beneﬁ t of a multiphase design

will only be fully realized when the source impedance of the

power supply/battery is included in the efﬁ ciency testing.

The sources of the P-channel MOSFETs should be placed

within 1cm of each other and share a common CIN(s).

Separating the sources and CIN may produce undesirable

voltage and current resonances at VIN.

A small (0.1μF to 1μF) bypass capacitor between the chip

VIN pin and ground, placed close to the LTC3736-2, is

also suggested. A 10Ω resistor placed between CIN (C1)

and the VIN pin provides further isolation between the

two channels.

The selection of COUT is driven by the effective series

resistance (ESR). Typically, once the ESR requirement

is satisﬁ ed, the capacitance is adequate for ﬁ ltering. The

output ripple (ΔVOUT) is approximated by:

Δ≈ +

⎛

⎝

⎜⎞

⎠

⎟

V I ESR fC

OUT RIPPLE

OUT

where f is the operating frequency, COUT is the output

capacitance and IRIPPLE is the ripple current in the induc-

tor. The output ripple is highest at maximum input voltage

since IRIPPLE increases with input voltage.

Setting Output Voltage

The LTC3736-2 output voltages are each set by an exter-

nal feedback resistor divider carefully placed across the

output, as shown in Figure 5. The regulated output voltage

is determined by:

OUT B

⎛

⎝

⎜⎞

⎠

⎟

06 1.•

To improve the frequency response, a feedforward ca-

pacitor, CFF, may be used. Great care should be taken to

route the VFB line away from noise sources, such as the

inductor or the SW line.

LTC3736-2

37362fb

APPLICATIONS INFORMATION

Run/Soft-Start Function

The RUN/SS pin is a dual purpose pin that provides the

optional external soft-start function and a means to shut

down the LTC3736-2.

Pulling the RUN/SS pin below 0.65V puts the LTC3736-2

into a low quiescent current shutdown mode (IQ = 9μA). If

RUN/SS has been pulled all the way to ground, there will

be a delay before the LTC3736-2 comes out of shutdown

and is given by:

AsFC

DELAY SS SS

=μ=μ065 07 093.•

../•

This pin can be driven directly from logic as shown in

Figure 6. Diode D1 in Figure 6 reduces the start delay

but allows CSS to ramp up slowly providing the soft-start

function. This diode (and capacitor) can be deleted if the

external soft-start is not needed.

During soft-start, the start-up of VOUT1 is controlled by

slowly ramping the positive reference to the error ampli-

ﬁ er from 0V to 0.6V, allowing VOUT1 to rise smoothly from

0V to its ﬁ nal value. The default internal soft-start time

is 1ms.

Figure 5. Setting Output Voltage

1/2 LTC3736-2

VFB

VOUT

RBCFF

37362 F05

This can be increased by placing a capacitor between the

RUN/SS pin and SGND. In this case, the soft-start time

will be approximately:

tC mV

SS SS1 600

=μ

•.

Tracking

The start-up of VOUT2 is controlled by the voltage on the

TRACK pin. Normally this pin is used to allow the start-up

of VOUT2 to track that of VOUT1 as shown qualitatively in

Figures 7a and 7b. When the voltage on the TRACK pin

is less than the internal 0.6V reference, the LTC3736-2

regulates the VFB2 voltage to the TRACK pin voltage in-

stead of 0.6V. The start-up of VOUT2 may ratiometrically

track that of VOUT1, according to a ratio set by a resistor

divider (Figure 7c):

RB RA

OUT

OUT TRACKA

TRACKA TRACKB1

•

For coincident tracking (VOUT1 = VOUT2 during start-up),

R2A = RTRACKA

R2B = RTRACKB

The ramp time for VOUT2 to rise from 0V to its ﬁ nal value

is:

RA RB

SS SS TRACKA

TRACKA TRACKB

211

••

Figure 6. RUN/SS Pin Interfacing

Figure 7a. Using the TRACK Pin

3.3V OR 5V RUN/SS RUN/SS

CSS

(INTERNAL SOFT-START)

37362 F06

VDD ≤ VIN RUN/SS

LTC3736-2

VFB2

VOUT2

VOUT1

VFB1

TRACK

R2B

R2A

37362 F07a

R1B

R1A

RTRACKA

RTRACKB

LTC3736-2

37362fb

APPLICATIONS INFORMATION

For coincident tracking,

SS SS OUT F

OUT F

21 2

=•

where VOUT1F and VOUT2F are the ﬁ nal, regulated values

of VOUT1 and VOUT2. VOUT1 should always be greater than

VOUT2 when using the TRACK pin. If no tracking function is

desired, then the TRACK pin may be tied to VIN. However,

in this situation there would be no (internal nor external)

soft-start on VOUT2.

Phase-Locked Loop and Frequency Synchronization

The LTC3736-2 has a phase-locked loop (PLL) comprised of

an internal voltage-controlled oscillator (VCO) and a phase

detector. This allows the turn-on of the external P-channel

MOSFET of controller 1 to be locked to the rising edge

of an external clock signal applied to the SYNC/FCB pin.

The turn-on of controller 2’s external P-channel MOSFET

is thus 180 degrees out-of-phase with the external clock.

The phase detector is an edge sensitive digital type that

provides zero degrees phase shift between the external

and internal oscillators. This type of phase detector does

not exhibit false lock to harmonics of the external clock.

The output of the phase detector is a pair of complementary

current sources that charge or discharge the external ﬁ lter

network connected to the PLLLPF pin. The relationship

between the voltage on the PLLLPF pin and operating

frequency, when there is a clock signal applied to SYNC/

FCB, is shown in Figure 8 and speciﬁ ed in the Electrical

Characteristics table. Note that the LTC3736-2 can only be

synchronized to an external clock whose frequency is within

range of the LTC3736-2’s internal VCO, which is nominally

200kHz to 1MHz. This is guaranteed, over temperature and

variations, to be between 300kHz and 750kHz. A simpliﬁ ed

block diagram is shown in Figure 9.

If the external clock frequency is greater than the internal

oscillator’s frequency, fOSC, then current is sourced con-

tinuously from the phase detector output, pulling up the

PLLLPF pin. When the external clock frequency is less

Figures 7b and 7c. Two Different Modes of Output Voltage Tracking

TIME

(7b) Coincident Tracking

VOUT1

VOUT2

OUTPUT VOLTAGE

TIME 37362 F07b,c

(7c) Ratiometric Tracking

VOUT1

VOUT2

OUTPUT VOLTAGE

Figure 8. Relationship Between Oscillator Frequency and Voltage

at the PLLLPF Pin When Synchronizing to an External Clock

PLLLPF PIN VOLTAGE (V)

FREQUENCY (kHz)

0.5 1 1.5 2

37362 F08

2.4

200

400

600

800

1000

1200

1400

LTC3736-2

37362fb

APPLICATIONS INFORMATION

than fOSC, current is sunk continuously, pulling down

the PLLLPF pin. If the external and internal frequencies

are the same but exhibit a phase difference, the current

sources turn on for an amount of time corresponding to

the phase difference. The voltage on the PLLLPF pin is

adjusted until the phase and frequency of the internal and

external oscillators are identical. At the stable operating

point, the phase detector output is high impedance and

the ﬁ lter capacitor CLP holds the voltage.

The loop ﬁ lter components, CLP and RLP, smooth out the

current pulses from the phase detector and provide a

stable input to the voltage-controlled oscillator. The ﬁ lter

components CLP and RLP determine how fast the loop

acquires lock. Typically RLP = 10k and CLP is 2200pF to

0.01μF.

Typically, the external clock (on SYNC/FCB pin) input high

level is 1.6V, while the input low level is 1.2V.

Table 2 summarizes the different states in which the

PLLLPF pin can be used.

Table 2

PLLLPF PIN SYNC/FCB PIN FREQUENCY

0V DC Voltage 300kHz

Floating DC Voltage 550kHz

VIN DC Voltage 750kHz

RC Loop Filter Clock Signal Phase-Locked to External Clock

Auxiliary Winding Control Using SYNC/FCB Pin

The SYNC/FCB can be used as an auxiliary feedback to

provide a means of regulating a ﬂ yback winding output.

When this pin drops below its ground-referenced 0.6V

threshold, continuous mode operation is forced.

During continuous mode, current ﬂ ows continuously in the

transformer primary. The auxiliary winding draws current

only when the bottom, synchronous N-channel MOSFET is

on. When primary load currents are low and/or the VIN /V

OUT

ratio is close to unity, the synchronous MOSFET may not be

on for a sufﬁ cient amount of time to transfer power from

the output capacitor to the auxiliary load. Forced continu-

ous operation will support an auxiliary winding as long

as there is a sufﬁ cient synchronous MOSFET duty factor.

The FCB input pin removes the requirement that power

must be drawn from the transformer primary in order to

extract power from the auxiliary winding. With the loop in

continuous mode, the auxiliary output may nominally be

loaded without regard to the primary output load.

The auxiliary output voltage VAUX is normally set as shown

in Figure 10 by the turns ratio N of the transformer:

AUX ≅ (N + 1) VOUT

However, if the controller goes into pulse-skipping operation

and halts switching due to a light primary load current, then

VAUX will droop. An external resistor divider from VAUX to

the FCB sets a minimum voltage VAUX(MIN):

AUX MIN() .=+

⎛

⎝

⎜⎞

⎠

⎟

06 1 6

Figures 9. Phase-Locked Loop Block Diagram

DIGITAL

PHASE/

FREQUENCY

DETECTOR OSCILLATOR

2.4V

RLP

CLP

37362 F09

PLLLPF

EXTERNAL

OSCILLATOR

SYNC/

FCB

LTC3736-2

37362fb

APPLICATIONS INFORMATION

If VAUX drops below this value, the FCB voltage forces

temporary continuous switching operation until VAUX is

again above its minimum.

Table 3 summarizes the different states in which the

SYNC/FCB pin can be used.

Table 3

SYNC/FCB PIN CONDITION

0V to 0.5V Forced Continuous Mode

Current Reversal Allowed

0.7V to VIN Pulse-Skipping Operation Enabled

No Current Reversal Allowed

Feedback Resistors Regulate an Auxiliary Winding

External Clock Signal Enable Phase-Locked Loop

(Synchronize to External CLK)

Pulse-Skipping at Light Loads

No Current Reversal Allowed

Fault Condition: Short-Circuit and Current Limit

To prevent excessive heating of the bottom MOSFET, fold-

back current limiting can be added to reduce the current

in proportion to the severity of the fault.

Foldback current limiting is implemented by adding

diodes DFB1 and DFB2 between the output and the ITH

pin as shown in Figure 11. In a hard short (VOUT = 0V),

the current will be reduced to approximately 50% of the

maximum output current.

Low Supply Operation

Although the LTC3736-2 can function down to below

2.4V, the maximum allowable output current is reduced

as VIN decreases below 3V. Figure 12 shows the amount

of change as the supply is reduced down to 2.4V. Also

shown is the effect on VREF.

Figures 10. Auxiliary Output Loop Connection

LTC3736-2

1μF

VOUT

VAUX

COUT

1:N

SYNC/FCB

37362 F10

VIN

Figures 11. Foldback Current Limiting

Figures 12. Line Regulation of VREF and

Maximum Sense Voltage for Low Input Supply

1/2 LTC3736-2

VFB

ITH

R2 DFB1

VOUT

DFB2

37362 F11

INPUT VOLTAGE (V)

NORMALIZED VOLTAGE OR CURRENT (%)

105

100

2.2 2.4 2.6 2.8

37362 F12

3.02.12.0 2.3 2.5 2.7 2.9

VREF

MAXIMUM

SENSE VOLTAGE

Minimum On-Time Considerations

Minimum on-time, tON(MIN), is the smallest amount of time

that the LTC3736-2 is capable of turning the top P-chan-

nel MOSFET on and then off. It is determined by internal

timing delays and the gate charge required to turn on the

top MOSFET. Low duty cycle and high frequency applica-

tions may approach the minimum on-time limit and care

should be taken to ensure that:

ON MIN OUT

OSC IN

() •

If the duty cycle falls below what can be accommodated

by the minimum on-time, the LTC3736-2 will begin to

skip cycles (unless forced continuous mode is selected).

The output voltage will continue to be regulated, but the

ripple current and ripple voltage will increase. The mini-

mum on-time for the LTC3736-2 is typically about 200ns.

However, as the peak sense voltage (IL(PEAK) • RDS(ON))

decreases, the minimum on-time gradually increases up

to about 250ns. This is of particular concern in forced

LTC3736-2

37362fb

APPLICATIONS INFORMATION

continuous applications with low ripple current at light

loads. If forced continuous mode is selected and the duty

cycle falls below the minimum on-time requirement, the

output will be regulated by overvoltage protection.

Efﬁ ciency Considerations

The efﬁ ciency of a switching regulator is equal to the output

power divided by the input power times 100%. It is often

useful to analyze individual losses to determine what is

limiting efﬁ ciency and which change would produce the

most improvement. Efﬁ ciency can be expressed as:

Efﬁ ciency = 100% – (L1 + L2 + L3 + …)

where L1, L2, etc. are the individual losses as a percent-

age of input power.

Although all dissipative elements in the circuit produce

losses, ﬁ ve main sources usually account for most of the

losses in LTC3736-2 circuits: 1) LTC3736-2 DC bias cur-

rent, 2) MOSFET gate charge current, 3) I2R losses, and

4) transition losses.

1. The VIN (pin) current is the DC supply current, given

in the electrical characteristics, excluding MOSFET

driver currents. VIN current results in a small loss that

increases with VIN.

2. MOSFET gate charge current results from switching the

gate capacitance of the power MOSFETs. Each time a

MOSFET gate is switched from low to high to low again,

a packet of charge dQ moves from SENSE+ to ground.

The resulting dQ/dt is a current out of SENSE+, which

is typically much larger than the DC supply current. In

continuous mode, IGATECHG = f • QP.

3. I2R losses are calculated from the DC resistances of

the MOSFETs and inductor. In continuous mode, the

average output current ﬂ ows through L but is “chopped”

between the top P-channel MOSFET and the bottom

N-channel MOSFET. The MOSFET RDS(ON)s multiplied

by duty cycle can be summed with the resistance of L

to obtain I2R losses.

4. Transition losses apply to the top external P-channel

MOSFET and increase with higher operating frequencies

and input voltages. Transition losses can be estimated

from:

Transition Loss = 2 (VIN)2IO(MAX)CRSS(f)

Other losses, including CIN and COUT ESR dissipative losses

and inductor core losses, generally account for less than

2% total additional loss.

Checking Transient Response

The regulator loop response can be checked by looking

at the load transient response. Switching regulators take

several cycles to respond to a step in load current. When

a load step occurs, VOUT immediately shifts by an amount

equal to (ΔILOAD)(ESR), where ESR is the effective series

resistance of COUT. ΔILOAD also begins to charge or dis-

charge COUT, which generates a feedback error signal.

The regulator loop then returns VOUT to its steady-state

value. During this recovery time, VOUT can be monitored

for overshoot or ringing. OPTI-LOOP

compensation al-

lows the transient response to be optimized over a wide

range of output capacitance and ESR values.

The ITH series RC-CC ﬁ lter (see Functional Diagram) sets the

dominant pole-zero loop compensation. The ITH external

components shown in the Typical Application on the front

page of this data sheet will provide an adequate starting

point for most applications. The values can be modiﬁ ed

slightly (from 0.2 to 5 times their suggested values) to

optimize transient response once the ﬁ nal PC layout is done

and the particular output capacitor type and value have

been determined. The output capacitors need to be decided

upon because the various types and values determine the

loop feedback factor gain and phase. An output current

pulse of 20% to 100% of full load current having a rise

time of 1μs to 10μs will produce output voltage and ITH

pin waveforms that will give a sense of the overall loop

stability. The gain of the loop will be increased by increas-

ing RC, and the bandwidth of the loop will be increased

by decreasing CC. The output voltage settling behavior is

OPTI-LOOP is a registered trademark of Linear Technology Corporation.

LTC3736-2

37362fb

APPLICATIONS INFORMATION

Figures 13. LTC3736-2 Layout Diagram

related to the stability of the closed-loop system and will

demonstrate the actual overall supply performance. For

a detailed explanation of optimizing the compensation

components, including a review of control loop theory,

refer to Application Note 76.

A second, more severe transient is caused by switching

in loads with large (>1μF) supply bypass capacitors. The

discharged bypass capacitors are effectively put in parallel

with COUT, causing a rapid drop in VOUT. No regulator can

deliver enough current to prevent this problem if the load

switch resistance is low and it is driven quickly. The only

solution is to limit the rise time of the switch drive so that

the load rise time is limited to approximately (25)(CLOAD).

Thus a 10μF capacitor would require a 250μs rise time,

limiting the charging current to about 200mA.

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the LTC3736-2. These items are illustrated in the layout

diagram of Figure 13. Figure 14 depicts the current wave-

forms present in the various branches of the 2-phase dual

regulator.

1. The power loop (input capacitor, MOSFETs, inductor,

output capacitor) of each channel should be as small

as possible and isolated as much as possible from the

power loop of the other channel. Ideally, the drains of

the P- and N-channel FETs should be connected close

to one another with an input capacitor placed across

the FET sources (from the P-channel source to the N-

channel source) right at the FETs. It is better to have

two separate, smaller valued input capacitors (e.g., two

10μF—one for each channel) than it is to have a single

larger valued capacitor (e.g., 22μF) that the channels

share with a common connection.

2. The signal and power grounds should be kept separate.

The signal ground consists of the feedback resistor divid-

ers, ITH compensation networks and the SGND pin.

The power grounds consist of the (–) terminal of the

input and output capacitors and the source of the N-

channel MOSFET. Each channel should have its own

power ground for its power loop (as described above

in item 1). The power grounds for the two channels

should connect together at a common point. It is most

important to keep the ground paths with high switching

currents away from each other.

The PGND pins on the LTC3736-2 IC should be shorted

together and connected to the common power ground

connection (away from the switching currents).

3. Put the feedback resistors close to the VFB pins. The

trace connecting the top feedback resistor (RB) to

the output capacitor should be a Kelvin trace. The ITH

compensation components should also be very close

to the LTC3736-2.

4. The current sense traces (SENSE+ and SW) should

be Kelvin connections right at the P-channel MOSFET

source and drain.

5. Keep the switch nodes (SW1, SW2) and the gate driver

nodes (TG1, TG2, BG1, BG2) away from the small-signal

components, especially the opposite channel’s feedback

resistors, ITH compensation components, and the cur-

rent sense pins (SENSE+ and SW).

SW1

IPRG1

VFB1

ITH1

IPRG2

PLLLPF

SGND

VIN

TRACK

VFB2

ITH2

PGOOD

SENSE1+

PGND

BG1

SYNC/FCB

TG1

PGND

TG2

RUN/SS

BG2

PGND

SENSE2+

SW2

LTC3736EGN-2

COUT1

COUT2

CVIN1

CVIN

VOUT1

VOUT2

BOLD LINES INDICATE HIGH CURRENT PATHS

37362 F13

MN1 MP1

MN2 MP2

VIN

CVIN2

LTC3736-2

37362fb

APPLICATIONS INFORMATION

Figures 14. Branch Current Waveforms

RL1

MP1 VOUT1

COUT1

MN1

MN2

VIN

CIN

RIN +

RL2

BOLD LINES INDICATE

HIGH, SWITCHING

CURRENT LINES.

KEEP LINES TO A

MINIMUM LENGTH

MP2

37362 F14

VOUT2

COUT2

LTC3736-2

37362fb

TYPICAL APPLICATIONS

Figures 15. 2-Phase, 550kHz, Dual Output Synchronous DC/DC Converter

Figures 16. 2-Phase, 750kHz, Dual Output Synchronous DC/DC Converter

SGND

PLLLPF

IPRG2

IPRG1

VFB1

ITH1

SW1

RVIN 10Ω

RITH2

15k

CITH2

220pF

CSS

10nF

CIN

10μF

s2CVIN

1μF

VIN

5V VIN

CITH2B

100pF

RITH1

15k

CITH1

220pF

CITH1A

100pF

RFB1B

187k

RFB1A

59k

PGOOD

VFB2

TRACK

ITH2

TG2

LTC3736EUF-2

PGND

TG1

SYNC/FCB

BG1

PGND

22 21

SENSE1+MP1

MP2

1.5μH

MN1

Si7540DP

MN2

Si7540DP

RUN/SS

BG2

PGND

SW2

SENSE2+

RTRACKB

118k

RTRACKA

59k

RFB2A

59k

RFB2B

118k

COUT2

150μF

COUT1

150μF

VOUT1

2.5V

VOUT2

1.8V

37362 F15

SGND

PLLLPF

IPRG2

IPRG1

VFB1

ITH1

SW1

RVIN 10Ω

RITH2

22k

CITH2

1000pF

CSS

10nF

CIN

22μF CVIN

1μF

VIN

3.3V VIN

CITH2A

100pF

RITH1

22k

CITH1

1000pF

CITH1A

100pF

RFB1B

187k

RFB1A

59k

PGOOD

VFB2

TRACK

PGND

ITH2

TG2

LTC3736EUF-2

PGND

TG1

SYNC/FCB

BG1

PGND

22 21

SENSE1+

MP1

Si3447BDV

MP2

Si3447BDV

1.5μH

MN1

Si3460DV

MN2

Si3460DV

RUN/SS

BG2

PGND

SW2

SENSE2+

RTRACKB

118k

RTRACKA

59k

RFB2A

59k

RFB2B

118k

COUT2

47μF

COUT1

47μF

VOUT1

2.5V

VOUT2

1.8V

37362 F16

CFF1

22pF

L1, L2: VISHAY IHLP-2525CZ-01

D1, D2: OPTIONAL

LTC3736-2

37362fb

Figures 17. 2-Phase, Synchronizable, Dual Output Synchronous DC/DC Converter

TYPICAL APPLICATIONS

SGND

PLLLPF

IPRG2

IPRG1

VFB1

ITH1

SW1

RVIN 10Ω

RITH2

22k

CITH2

1nF

CIN

22μF CVIN

1μF

VIN

3.3V VIN

RITH1

22k

CITH1

1nF

CFF1

100pF

CFF1

100pF

CLP

10nF RLP

15k

RFB1B

187k

RFB1A

59k

PGOOD

VFB2

TRACK

ITH2

TG2

LTC3736EGN-2

PGND

TG1

SYNC/FCB

BG1

PGND

124

L1, L2: VISHAY IHLP-2525CZ-01

SENSE1+MP1 SW1

SW2

CLK IN

MP2

1.5μH

MN1

Si7540DP

MN2

Si7540DP

RUN/SS

BG2

PGND

SW2

SENSE2+

RTRACKB

118k

RTRACKA

59k

RFB2A

59k

RFB2B

118k

COUT2

100μF

COUT1

100μF

VOUT1

2.5V

VOUT2

1.8V

37362 F17

LTC3736-2

37362fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

.337 – .344*

(8.560 – 8.738)

GN24 (SSOP) 0204

345678 9 10 11 12

.229 – .244

(5.817 – 6.198)

.150 – .157**

(3.810 – 3.988)

161718192021222324 15 1413

.016 – .050

(0.406 – 1.270)

.015 ± .004

(0.38 ± 0.10) × 45°

0° – 8° TYP

.0075 – .0098

(0.19 – 0.25)

.0532 – .0688

(1.35 – 1.75)

.008 – .012

(0.203 – 0.305)

TYP

.004 – .0098

(0.102 – 0.249)

.0250

(0.635)

BSC

.033

(0.838)

REF

.254 MIN

RECOMMENDED SOLDER PAD LAYOUT

.150 – .165

.0250 BSC.0165 ±.0015

.045 ±.005

INCHES

(MILLIMETERS)

NOTE:

1. CONTROLLING DIMENSION: INCHES

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

4.00 p 0.10

(4 SIDES)

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE

MO-220 VARIATION (WGGD-X)—TO BE APPROVED

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1

TOP MARK

(NOTE 6)

0.40 p 0.10

2423

BOTTOM VIEW—EXPOSED PAD

2.45 p 0.10

(4-SIDES)

0.75 p 0.05 R = 0.115

TYP

0.25 p 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

(UF24) QFN 0105

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

0.70 p0.05

0.25 p0.05

0.50 BSC

2.45 p 0.05

(4 SIDES)

3.10

p 0.05

4.50

p 0.05

PACKAGE

OUTLINE

PIN 1 NOTCH

R = 0.20 TYP OR

0.35 s 45o CHAMFER

GN Package

24-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

UF Package

24-Lead Plastic QFN (4mm × 4mm)

(Reference LTC DWG # 05-08-1697)

LTC3736-2

37362fb

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 0109 REV B • PRINTED IN USA

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2-Phase, 750kHz, Dual Output Synchronous DC/DC Converter

SGND

PLLLPF

IPRG2

IPRG1

VFB1

ITH1

SW1

RVIN 10Ω

RITH2

22k

CITH2

1000pF

CSS

10nF

CIN

22μF CVIN

1μF

VIN

3.3V VIN

CITH2A

100pF

RITH1

22k

CITH1

1000pF

CITH1A

100pF

RFB1B, 187kRFB1A, 59k

PGOOD

VFB2

TRACK

PGND

ITH2

TG2

LTC3736EUF-2

PGND

TG1

SYNC/FCB

BG1

PGND

22 21

SENSE1+

MP1

Si3447BDV

MP2

Si3447BDV

1.5μH

MN1

Si3460DV

MN2

Si3460DV

RUN/SS

BG2

PGND

SW2

SENSE2+

RTRACKB, 118kRTRACKA, 59k

RFB2A, 59k RFB2B, 118k

COUT2

47μF

COUT1

47μF

VOUT1

2.5V

VOUT2

1.8V

37362 TA02

CFF1

22pF

L1, L2: VISHAY IHLP-2525CZ

D1, D2: OPTIONAL