PRELIMINARY DATA SHEET MICRONAS Edition March 12, 2004 6251-615-1PD CDC 3272G-C Automotive Controller MICRONAS CDC 3272G-C PRELIMINARY DATA SHEET Contents Page Section Title 3 3 5 6 1. 1.1. 1.2. 1.3. Introduction Features Abbreviations Block Diagram 7 7 8 8 9 2. 2.1. 2.2. 2.3. 2.4. Packages and Pins Package Outline Dimensions Pin Assignment Pin Function Description External Components 11 11 12 13 15 3. 3.1. 3.2. 3.3. 3.4. Electrical Data Absolute Maximum Ratings Recommended Operating Conditions Characteristics Recommended Quartz Crystal Characteristics 17 4. CPU and Clock System 19 5. Memory and Special Function ROM (SFR) System 21 21 6. 6.1. Core Logic Control Word (CW) 23 7. IRQ Interrupt Controller Unit (ICU) 25 25 8. 8.1. Hardware Options Functional Description 27 27 32 33 9. 9.1. 9.2. 9.3. Register Cross Reference Table 8-Bit I/O Region 32-Bit I/O Region Modified Registers 35 10. Differences 36 11. Data Sheet History 2 March 12, 2004; 6251-615-1PD Micronas CDC 3272G-C PRELIMINARY DATA SHEET 1. Introduction Release Note: Revision bars changes to the previous edition. indicate significant interfaces and PWM outputs and a crystal clock multiplying PLL. The device is a microcontroller for use in automotive applications. The on-chip CPU is an ARM processor ARM7TDMI with 32-bit data and address bus, which supports Thumb format instructions. This document provides Mask ROM-derivative-specific information. General information on operating the IC can be found in the document "CDC32xxG-C Automotive Controller - Family User Manual, CDC3205G-C Automotive Controller" (6251-579-1PD)". The chip contains timer/counters, interrupt controller, multi channel AD converter, stepper motor and LCD driver, CAN 1.1. Features Table 1-1: CDC32xxG-C Family Feature List This Device: Item CDC3205G-C EMU CDC3207G-C MCM Flash CDC3257G-C2 MCM Flash CDC3272G-C Mask ROM CDC3231G-C Mask ROM 12 kByte 16 kByte 6 kByte 256 kByte Flash (128K x 16) top boot conf. 384 kByte (96K x 32/ 192K x 16) 128 kByte (32K x 32/ 64K x 16) Core CPU 32-bit ARM7TDMI CPU-Active Operation Modes DEEP SLOW, SLOW, FAST and PLL Power Saving Modes (CPU Inactive) IDLE, WAKE and STANDBY CPU clock multiplication PLL delivering up to 50 MHz EMI Reduction Mode selectable in PLL mode Oscillators 4 to 5 MHz Quartz and 20 to 50 kHz Internal RC RAM, zero wait state, 32 bit wide 32 kByte ROM ROMless, ext. up to 4M x 32/ 8M x 16 Boot ROM 8 kByte (Special Function ROM) Digital Watchdog Central Clock Divider Interrupt Controller expanding IRQ 40 inputs, 16 priority levels 26 inputs, 16 priority levels Port Interrupts including Slope Selection 6 inputs 5 inputs Port Wake-Up Inputs including Slope / Level Selection 10 inputs Patch Module 10 ROM locations Boot System allows in-system downloading of external code to Flash memory via JTAG - Device Lock Module Inhibits Access to internal Firmware, Lock settable by Customer - Micronas 512 kByte Flash (256K x 16) top boot conf. March 12, 2004; 6251-615-1PD 3 CDC 3272G-C PRELIMINARY DATA SHEET Table 1-1: CDC32xxG-C Family Feature List, continued This Device: Item CDC3205G-C EMU CDC3207G-C MCM Flash CDC3257G-C2 MCM Flash CDC3272G-C Mask ROM CDC3231G-C Mask ROM Analog Reset/Alarm Combined Input for Regulator Input Supervision Clock and Supply Supervision 10-bit ADC, charge balance type 16 channels (each selectable as digital input) ADC Reference VREF Pin, P1.0 Pin, P1.1 Pin or VREFINT Internal Bandgap selectable Comparators P06COMP with 1/2 AVDD reference, WAITCOMP with Internal Bandgap reference LCD Internal processing of all analog voltages for the LCD driver Communication DMA 3 DMA Channels, one each for serving the Graphics Bus interface, SPI0 and SPI1 - UART 2: UART0 and UART1 UART0 Synchronous Serial Peripheral Interfaces 2: SPI0 and SPI1, DMA supported Full CAN modules V2.0B with 512-byte object RAM each (LCAN000E) 4: CAN0, CAN1, CAN2 and CAN3 DIGITbus 1 master module - I2C 2 master modules: I2C0 and I2C1 I2C0 Graphics Bus Interface 8-bit data bus, DMA supported, e.g., for connection of EPSON SED 1560 LCD controller - Universal Ports selectable as 4:1 mux LCD Segment/Backplane lines or Digital I/O Ports up to 52 I/O or 48 LCD segment lines (= 192 segments), individually configurable as I/O or LCD up to 50 I/O or 46LCD segment lines (=184 segments) Universal Port Slew Rate SW-selectable Stepper Motor Control Modules with High-Current Ports 7 Modules, 32 dI/dt controlled ports 4 Modules 23 dI/dt controlled ports PWM Modules, each configurable as two 8-bit PWMs or one 16-bit PWM 6 Modules: PWM0/1, PWM2/3, PWM4/5, PWM6/7, PWM8/9 and PWM10/11 5 Modules: PWM0/1, PWM2/3, PWM4/5, PWM6/7, PWM8/9 Phase-Frequency Modulator 2: PFM0 and PFM1 - Audio Module with auto-decay SW selectable Clock outputs 2 2: CAN0 and CAN1 1: CAN0 Input & Output 4 March 12, 2004; 6251-615-1PD Micronas CDC 3272G-C PRELIMINARY DATA SHEET Table 1-1: CDC32xxG-C Family Feature List, continued This Device: Item CDC3205G-C EMU CDC3207G-C MCM Flash CDC3257G-C2 MCM Flash CDC3272G-C Mask ROM Polling / Flash Timer Output 1 High-Current Port output operable in Power Saving Modes CDC3231G-C Mask ROM Timers & Counters 16-bit free running counters with Capture/Compare modules CCC0 with 4 CAPCOM CCC1 with 2 CAPCOM 16-bit timers 1: T0 8-bit timers 4: T1, T2, T3 and T4 Real Time Clock, Delivering Hours, Minutes and Seconds CCC0 with 4 CAPCOM Miscellaneous Scalable layout in CAN, RAM and ROM - Various randomly selectable HW options Set by copy from user program storage during system start-up JTAG interface allows Flash programming On Chip Debug Aids Embedded Trace Module, JTAG JTAG Core Bond-Out - Supply Voltage 3.5 to 5.5 V (limited I/O performance below 4.5 V) Case Temperature Range 0 to +70 C -40 to +105 C Type Ceramic 257PGA Plastic 128QFP 0.5 mm pitch Bonded Pins 256 128 126 111 Package 128 ARM and Thumb are the registered trademarks of ARM Limited. ARM7TDMI is the trademark of ARM Limited. 1.2. Abbreviations ADC AM CAN CAPCOM CCC CPU DMA ERM ETM I2C LCD P06COMP PWM Micronas Analog-to-Digital Converter Audio Module Controller Area Network Module Capture/Compare Module Capture/Compare Counter Central Processing Unit Direct Memory Access Module EMI Reduction Mode Embedded Trace Module I2C Interface Module Liquid Crystal Display Module P0.6 Alarm Comparator Pulse Width Modulator Module SM SPI T UART WAITCOMP March 12, 2004; 6251-615-1PD Stepper Motor Control Module Serial Synchronous Peripheral Interface Timer Universal Asynchronous Receiver Transmitter Wait Comparator 5 CDC 3272G-C PRELIMINARY DATA SHEET 1.3. Block Diagram UVDD UVSS VDD VSS Reset/Alarm Test 2.5V Reg. Watchdog Clock PLL/ERM ARM7TDMI CPU RTC Power Saving 2.5V Reg. JTAG Test and Debug Interface PPort0 SRAM 4k x 32 UPort0 HPort4 HVDD0 HVSS0 HVDD1 HVSS1 HVDD2 HVSS2 HVDD3 HVSS3 UPort1 4 UPort2 HPort1 HPort2 4 HPort5 4 HPort6 4 7 UPort3 Bridge 8 4 4 3 4 6 8 UART 0 LCD Control Stepper Motor Control UART 1 Audio Module 8Bit PWM 0 8/16B PWM 1 SPI 0 16Bit Timer 0 16Bit CCC 0 8Bit Timer 1 CAPCOM 0 8Bit Timer 2 CAPCOM 1 CAPCOM 2 Clock Out 0 8Bit PWM 2 8Bit Timer 3 Clock Out 1 8/16B PWM 3 8Bit Timer 4 8Bit PWM 4 CAN 0 Phase-Freq.Modulator 0 CAN 1 Phase-Freq.Modulator 1 SPI 1 8/16B PWM 5 CAPCOM 3 16Bit CCC 1 CAPCOM 4 CAPCOM 5 8Bit PWM 6 8/16B PWM 7 8Bit PWM 8 HPort7 4 HPort3 4 Patch 10 Locations UPort4 HPort0 Bandgap Ref. 8 UPort5 Special Function ROM 4k x 16 8 UPort6 ROM 96k x 32 UPort7 Memory Controller Wait Comp. 16/32 Bridge 32 10Bit ADC 4 5 DMA Logic P06 Comp. 4 XTAL1 XTAL2 UPort8 2 40 Input Interrupt Controller PPort1 8 PPort2 8 TEST TEST2 RC Oscillator WAIT WAITH VREFINT VREF AVDD AVSS BVDD RESETQ 8/16B PWM 9 8Bit PWM 10 DIGITbus 8/16B PWM 11 I2 C 0 I2 C 1 Fig. 1-1: CDC3272G-C block diagram 6 March 12, 2004; 6251-615-1PD Micronas CDC 3272G-C PRELIMINARY DATA SHEET 2. Packages and Pins 2.1. Package Outline Dimensions Fig. 2-1: PMQFP128-2: Plastic Metric Quad Flat Package, 128 leads, 14 x 20 x 2.7 mm3 Ordering code: QK Weight approximately 1.8 g Micronas March 12, 2004; 6251-615-1PD 7 CDC 3272G-C PRELIMINARY DATA SHEET 2.2. Pin Assignment Pin Functions LCD Port Port Basic Mode Special Out Special In Function SEG3.1 CC1-OUT CC1-IN / TMS U3.1 SEG3.0 CC2-OUT CC2-IN / TDI U3.0 TEST2 UVDD UVSS SEG2.6 DIGIT-OUT DIGIT-IN U2.6 SEG2.5 CC1-OUT UART0-RX U2.5 SEG2.4 UART0-TX DIGIT-IN/CC1-IN U2.4 SEG2.3 CC2-OUT UART1-RX U2.3 SEG2.2 UART1-TX CC2-IN U2.2 SEG7.7 CO0 U7.7/GD7 SEG7.6 CO1 U7.6/GD6 SEG7.5 LCK/PFM1 U7.5/GD5 SEG7.4 CC5-OUT CC5-IN U7.4/GD4 NC NC SEG5.3 CC4-OUT CC4-IN U5.3/GD3 SEG5.2 SDA1 SDA1 U5.2/GD2 SEG5.1 SCL1 SCL1 U5.1/GD1 SEG5.0 PFM0 U5.0/GD0 SEG2.1 SDA0 WP6/SDA0/CAN0U2.1 RX SEG2.0 SCL0/CAN0-TX SCL0 U2.0 SEG1.7 PFM0 WP0/PINT0 U1.7 SEG1.6 INTRES/CO0 PINT1 U1.6 SEG1.5 CO1/CO0Q PINT2 U1.5 TEST RESETQ/ALARMQ XTAL2 XTAL1 VSS VDD SEG1.4 ITSTOUT/AM-OUT U1.4 SEG1.3 MTO/AM-PWM WP3 U1.3 SEG1.2 INTRES/T0-OUT MTI/ITSTIN U1.2 SEG1.1 T1-OUT U1.1 SEG1.0 T2-OUT U1.0 SEG0.7 T3-OUT WP4 U0.7 SEG0.6 CC3-OUT/T4-OUT CC3-IN U0.6 SEG0.5 CC3-OUT PINT4 U0.5 SEG0.4 CO1 PINT5 U0.4 SEG0.3 PWM0 U0.3 SEG0.2 PWM1 U0.2 SEG0.1 PWM2 U0.1 SEG0.0 PWM3 U0.0 SME1+/PWM4 SME-COMP3 H7.3 SME1-/PWM6 SME-COMP2 H7.2 SME2+/PWM8 SME-COMP1 H7.1 SME2-/PWM9 SME-COMP0 H7.0 HVDD2 HVSS2 PWM8 H6.3 PWM9 H6.2 PWM10 H6.1 PWM11 H6.0 SMD1+ SMD-COMP3 H5.3 SMD1SMD-COMP2 H5.2 HVDD0 HVSS0 SMD2+ SMD-COMP1 H5.1 SMD2SMD-COMP0 H5.0 SMA1+ SMA-COMP3 H4.3 SMA1SMA-COMP2 H4.2 SMA2+ SMA-COMP1 H4.1 SMA2SMA-COMP0 H4.0 Not Pin e No. 1,2 1,2 1,2 1,2 1,2 1,2 1 1 1 1 1 1 1 1 1,2 1,2 1,2 1,2 1,2 1,2 116 117 118 119 120 121 122 123 124 125 126 127 128 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 128 116 115 103 1 102 38 65 39 51 52 64 NC = not connected, leave vacant (...) = future usage Pin Not No. e Basic Function 115 U3.2 114 U3.3 113 U3.4 112 U3.5 111 U3.6 110 U3.7 109 U4.0 108 U4.1 107 U4.2 106 U4.3 105 1,2 U8.0 104 1,2 U8.1 103 1,2 U8.2 102 1,2 U8.3 101 1,2 U8.4 100 1,2 U8.5 99 1 U6.0 98 1 U6.1 97 1 U6.2 96 1 P2.0 95 P2.1 94 P0.0 93 P0.1 92 P0.2 91 P0.3 90 P0.4 89 P0.5 88 P0.6 87 P0.7 86 WAITH 85 WAIT 84 BVDD 83 AVSS 82 AVDD 81 VREFINT 80 VREF 79 P1.0 78 P1.1 77 P1.2 76 P1.3 75 P1.4 74 P1.5 73 P1.6 72 P1.7 71 1 H0.0 70 1 H0.1 69 1 H0.2 68 1 H0.3 67 1,2 HVSS3 66 1,2 HVDD3 65 1,2 H1.0 64 1,2 H1.1 63 1,2 H1.2 62 1,2 H1.3 61 H2.0 60 H2.1 59 HVSS1 58 HVDD1 57 H2.2 56 H2.3 55 H3.0 54 H3.1 53 H3.2 52 H3.3 Pin Functions Port Port Special In Special Out CC0-IN / TCK CC0-OUT CO0/TDO SPI0-CLK-IN SPI0-CLK-OUT SPI0-D-IN TO3 SPI0-D-OUT SPI1-CLK-IN SPI1-CLK-OUT SPI1-D-IN CC0-OUT CC0-IN SPI1-D-OUT CAN0-TX CAN0-RX/WP5 TO2 CC4-OUT CC3-OUT LCD-CLK-IN WP9 LCD-CLK-OUT LCD-SYNC-IN PINT3/WP8 LCD-SYNC-OUT CAN1-TX CAN1-RX/WP7 GOEQ GWEQ LCD Mode SEG3.2 SEG3.3 SEG3.4 SEG3.5 SEG3.6 SEG3.7 BP0 BP1 BP2 BP3 SEG8.0 SEG8.1 SEG8.2 SEG8.3 SEG8.4 SEG8.5 SEG6.0 SEG6.1 SEG6.2 CC4-IN P0.6 Comp. VREF0/WP1 VREF1/WP2 PINT0 PINT1 PINT2 PINT3 PINT4 PINT5 SMG-COMP0 SMG-COMP1 SMG-COMP2 SMG-COMP3 SMG2-/PWM7 SMG2+/PWM5 SMG1-/PWM3/POL SMG1+/PWM1 SMF-COMP0 SMF-COMP1 SMF-COMP2 SMF-COMP3 SMC-COMP0 SMC-COMP1 SMF2SMF2+ SMF1SMF1+ SMC2SMC2+ SMC-COMP2 SMC-COMP3 SMB-COMP0 SMB-COMP1 SMB-COMP2 SMB-COMP3 SMC1SMC1+ SMB2SMB2+ SMB1SMB1+ Fig. 2-2: Pin Assignment 2.3. Pin Function Description (differing from document "CDC32xxG-C Automotive Controller - Family User Manual, CDC3205G-C Automotive Controller" (6251-579-1PD)) TEST2 For normal operation with internal code connect TEST2 to System Ground (no internal pull-down). 8 March 12, 2004; 6251-615-1PD Micronas CDC 3272G-C PRELIMINARY DATA SHEET 2.4. External Components +5V Supply UVDD 4 x 100n to 150n 100n to 150n 5V System Ground +5V Supply HVDD0 to 3 UVSS HVSS0 to 3 System Ground AVDD Analog Supply 2.5V VDD 10 Tantal Low ESR 220n Ceramic X7R VSS 100n to 150n VREFINT XTAL1 5V 18p 10n, Ceramic 2.5V 18p +5V Supply BVDD XTAL2 4k7 Resetq Analog Ground AVSS 150n Ceramic X7R 47n RESETQ Fig. 2-3: CDC3207G-C: Recommended external supply and quartz connection. To provide effective decoupling and to improve EMC behavior, the small decoupling capacitors must be located as close to the supply pins as possible. The self-inductance of these capacitors and the parasitic inductance and capacitance of the interconnecting traces determine the self-resonant frequency of the decoupling network. Too low a frequency will reduce decoupling effectiveness, will increase RF emissions and may adversely affect device operation. XTAL1 and XTAL2 quartz connections are especially sensitive to capacitive coupling from other pc board signals. It is strongly recommended to place quartz and oscillation capacitors as close to the pins as possible and to shield the XTAL1 and XTAL2 traces from other signals by embedding them in a VSS trace. The RESETQ pin adjacent to XTAL2 should be supplied with a 47 nF capacitor, to prevent fast RESETQ transients from being coupled into XTAL2, to prevent XTAL2 from coupling into RESETQ, and to guarantee a time constant of 200 s sufficient for proper Wake Reset functionality. Micronas March 12, 2004; 6251-615-1PD 9 CDC 3272G-C 10 PRELIMINARY DATA SHEET March 12, 2004; 6251-615-1PD Micronas CDC 3272G-C PRELIMINARY DATA SHEET 3. Electrical Data 3.1. Absolute Maximum Ratings Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these conditions is not implied. Exposure to absolute maximum ratings conditions for extended periods will affect device reliability. This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than absolute maximum-rated voltages to this high-impedance circuit. Table 3-1: Absolute Maximum Ratings (All voltages listed are referenced to ground (UVSS = HVSSn = AVSS = 0 V), except where noted. All GND pins except VSS must be connected to a low-resistive ground plane close to the IC). Symbol Parameter Pin Name Limit Values Min. Max. Unit VSUP Main Supply Voltage Analog Supply Voltage SM Supply Voltage UVDD AVDD HVDDn -0.3 6.0 V VREG Core Supply Voltage PLL Supply Voltage VDD BVDD -0.3 3.0 V ISUP Core Supply Current Main Supply Current VDD, VSS, UVDD, UVSS -100 100 mA Analog Supply Current AVDD, AVSS -20 20 mA SM Supply Current @TCASE=105C, Duty Factor=0.71 1) HVDDn HVSSn -250 250 mA PLL Supply Current BVDD -20 20 mA Input Voltage U-Ports, XTAL,RESETQ, TEST, TEST2 UVSS-0.5 UVDD+0.7 V P-Ports VREF UVSS-0.5 AVDD+0.7 V H-Ports HVSS-0.5 HVDD+0.7 V Vin Iin Input Current all Inputs 0 2 mA Io Output Current U-Ports, RESETQ, WAITH -5 5 mA H-Ports -60 60 mA indefinite s toshsl Duration of Short Circuit to UVSS or UVDD, Port SLOW Mode enabled Tj Junction Temperature under Bias -45 115 C Ts Storage Temperature -45 125 C Pmax Maximum Power Dissipation 0.8 W 1) U-Ports, except in DP Mode This condition represents the worst case load with regard to the intended application Micronas March 12, 2004; 6251-615-1PD 11 CDC 3272G-C PRELIMINARY DATA SHEET 3.2. Recommended Operating Conditions Do not insert the device into a live socket. Instead, apply power by switching on the external power supply. Keep UVDD=AVDD during all power-up and power-down sequences. Functional operation of the device beyond those indicated in the "Recommended Operating Conditions/Characteristics" is not implied and may result in unpredictable behavior, reduce reliability and lifetime of the device. Table 3-2: Recommended Operating Conditions (All voltages listed are referenced to ground (UVSS = HVSSn = AVSS = 0 V), except where noted. All GND pins except VSS must be connected to a low-resistive ground plane close to the IC). Symbol Parameter Pin Name Limit Values Min. Typ. Unit Max. dVDD Ripple, Peak to Peak UVDD AVDD BVDD VDD 200 mV dVDD/dt Supply Voltage Up/Down Ramping Rate UVDD AVDD 20 V/s fXTAL XTAL Clock Frequency XTAL1 5 MHz fSYS CPU Clock Frequency, PLL on fBUS Program Storage Clock Frequency, PLL on Vil (see Table 2-2 for a list of input types and their supply voltages) Automotive Low Input Voltage U-Ports H-Ports P-Ports 0.5*xVDD V CMOS Low Input Voltage U-Ports, TEST, TEST2 H-Ports P-Ports 0.3*xVDD V Vih (see Table 2-2 for a list of input types and their supply voltages) Automotive High Input Voltage U-Ports H-Ports P-Ports 0.86*xVDD V CMOS High Input Voltage U-Ports,TEST, TEST2 H-Ports P-Ports 0.7*xVDD V RVil Reset Active Input Voltage RESETQ 0.75 V WRVil Reset Active Input Voltage during Power Saving Modes and Wake Reset RESETQ 0.4 V RVim Reset Inactive and Alarm Active Input Voltage RESETQ 1.5 2.3 V RVih Reset Inactive and Alarm Inactive Input Voltage RESETQ 3.2 V WRVih Reset Inactive Input Voltage during Power Saving Modes and Wake Reset RESETQ UVDD-0.4V V 12 4 4 For a list of available settings see Tables 4-1 and 4-2. March 12, 2004; 6251-615-1PD Micronas CDC 3272G-C PRELIMINARY DATA SHEET Table 3-2: Recommended Operating Conditions, continued (All voltages listed are referenced to ground (UVSS = HVSSn = AVSS = 0 V), except where noted. All GND pins except VSS must be connected to a low-resistive ground plane close to the IC). Symbol Parameter Pin Name Limit Values Min. Typ. Unit Max. VREFi Ext. ADC Reference Input Voltage VREF 2.56 AVDD V PVi ADC Port Input Voltage referenced to int. VREF Reference P-Ports 0 VREFi V 0 VREFINT ADC Port Input Voltage referenced to ext. VREFINT Reference 3.3. Characteristics Listed are only those characteristics that differ from Chapter 3.3 of Document "CDC32xxG-C Automotive Controller - Family User Manual, CDC3205G-C Automotive Controller" (6251-579-1PD). All not differing characteristics, that are not listed here, apply, but in a TCASE temperature range extended to -40 C to +105 C Table 3-3: Characteristics UVSS = HVSSn = AVSS = 0 V, 3.5 V < AVDD = UVDD < 5.5 V, 4.75 V < HVDDn < 5.25 V, TCASE = -40 C to +105 C, fXTAL = 5 MHz, external components according to Fig. 2-3 (unless otherwise noted) Symbol Parameter Limit Values Pin Name Min. Typ.1) Unit Test Conditions measured on Micronas typical 2-layer board, 1s1p, described in document "Integrated Circuits - Thermal Characterization of Packages" (6200-2661E) (modified JESD51.3) Max. Package Rthjc Thermal Resistance from Junction to Case 10 C/W Rthja Thermal Resistance from Junction to Ambient 36 C/W Supply Currents (CMOS levels on all inputs, i.e. Vil=xVSS0.3V and Vih=xVDD0.3V, no loads on outputs) UIDDp UVDD PLL Mode Supply Current UVDD 50 mA fSYS=24MHz UIDDf UVDD FAST Mode Supply Current UVDD 22 mA all Modules OFF, 2) UIDDs UVDD SLOW Mode Supply Current UVDD see Fig. 3-1 1.4 mA all Modules OFF 2) 3) UIDDd UVDD DEEP SLOW Mode Supply Current UVDD see Fig. 3-1 0.9 mA all Modules OFF 3) UIDDw UVDD WAKE Mode Supply Current UVDD 20 50 A RC and XTAL oscillators OFF 0 1) Typical values describe typical behavior at room temperature (25 C, unless otherwise noted), with typical Recommended Operating Conditions applied, and are not 100% tested. 2 ) Value may be exceeded with unusual Hardware Option setting 3) Measured with external clock. Add 120 A for operation on typical quartz with SR0.XTAL = 0 (Oscillator RUN mode). Micronas March 12, 2004; 6251-615-1PD 13 CDC 3272G-C PRELIMINARY DATA SHEET Table 3-3: Characteristics, continued UVSS = HVSSn = AVSS = 0 V, 3.5 V < AVDD = UVDD < 5.5 V, 4.75 V < HVDDn < 5.25 V, TCASE = -40 C to +105 C, fXTAL = 5 MHz, external components according to Fig. 2-3 (unless otherwise noted) Symbol Parameter Limit Values Pin Name UIDDi AIDDa AIDDq UVDD STANDBY Mode Supply Current UVDD IDLE Mode Supply Current AVDD Active Supply Current Quiescent Supply Current HIDDq Test Conditions Typ.1) Max. UVDD 35 75 A RC oscillator ON, XTAL OFF UVDD 60 100 A XTAL oscillator ON, RC OFF 3) UVDD 50 TBD A RC oscillator ON, XTAL OFF 75 TBD A XTAL oscillator ON, RC OFF 3) 0.35 0.6 mA ADC ON, PLL OFF 1 2 mA ADC and PLL ON, fSYS=24MHz Min. UIDDst Unit AVDD AVDD 0 1 10 A SLOW, DEEP SLOW and power saving modes, ADC and PLL OFF Sum of all HVDDn 0 1 40 A no Output Activity, SM Module OFF TEST2 -1 1 A 0<Vi<UVDD Inputs Ii Input Leakage Current 1) Typical values describe typical behavior at room temperature (25 C, unless otherwise noted), with typical Recommended Operating Conditions applied, and are not 100% tested. 2) 3 14 Value may be exceeded with unusual Hardware Option setting ) Measured with external clock. Add 120 A for operation on typical quartz with SR0.XTAL = 0 (Oscillator RUN mode). March 12, 2004; 6251-615-1PD Micronas CDC 3272G-C PRELIMINARY DATA SHEET A 900 800 700 UIDDs (SLOW mode) 600 UIDD 500 400 UIDDd (DEEP SLOW mode) 300 200 UIDDi (IDLE mode) 100 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 C TCASE Fig. 3-1: Typical UIDD characteristics over temperature @ fXTAL=4MHz, 5V 3.4. Recommended Quartz Crystal Characteristics See Chapter 3.4 of document "CDC32xxG-C Automotive Controller - Family User Manual, CDC3205G-C Automotive Controller" (6251-579-1PD). Micronas March 12, 2004; 6251-615-1PD 15 CDC 3272G-C 16 PRELIMINARY DATA SHEET March 12, 2004; 6251-615-1PD Micronas CDC 3272G-C PRELIMINARY DATA SHEET 4. CPU and Clock System 4.1. Recommended Register Settings Suppression Strength (SUP) and Clock Tolerance (TOL) may be varied between zero and the values for strong settings according to the rules in Section 4.4.2 of the document "CDC32xxG-C Automotive Controller - Family User Manual, CDC3205G-C Automotive Controller" (6251-579-1PD). The given limits must not be exceeded. Other settings for PMF, IOP and WSR than those given in Tables 4-1 and 4-2 shall not be used and may result in undefined behaviour. It is required not to operate I/O faster than ROM. Table 4-1: PLL and ERM Modes: Recommended Settings and Resulting Operating Frequencies (MHz) 4 Strong SUP TOL Normal TOL Weak SUP Strong TOL TOL Normal fSYS PLLC. PMF fBUS WSR fIO= f0 IOC. IOP 8 1 8 0x00 8 0 0 4 0 7 0 11 4 2 7 4 11 6 16 3 8 0x11 8 1 0 8 0 14 0 15 8 4 14 7 22 11 24 5 8 0x22 8 2 0 12 0 15 0 15 12 6 21 11 31 12 12 0x11 0 10 0 10 0 10 12 2 21 2 33 2 8 0x33 0 12 0 12 0 12 16 8 28 12 31 12 10.67 0x22 0 12 0 12 0 12 16 8 19 23 28 9 7 6 19 23 37 9 7 6 32 5 SUP Weak ERMC.EOM = 2 or 3 SUP ERMC.EOM = 1 TOL I/O SUP ROM TOL CPU SUP fXTAL 7 8 3 40 9 10 0x33 8 4 0 6 0 6 0 6 21 6 35 6 37 6 48 11 12 0x33 8 5 0 1 0 1 0 1 25 1 42 1 42 1 10 1 10 0x00 10 0 0 5 0 8 0 14 5 3 8 4 14 7 20 3 10 0x11 10 1 0 10 0 15 0 15 10 5 17 8 28 8 30 5 10 0x22 10 2 0 14 0 14 0 14 15 8 24 26 12 11 28 30 35 10 9 8 40 7 10 0x33 10 3 0 6 0 6 0 6 21 6 35 6 37 6 50 9 12.5 0x33 10 4 set ERMC.EOM=0 set ERMC.EOM=0 Table 4-2: PLL2 and ERM Modes: Settings Sacrificing Unlimited Operation of Peripheral Modules and Resulting Operating Frequencies (MHz) 4 5 Micronas 12 2 6 0x11 4 2 12 0x00 Strong TOL IOC. IOP Normal SUP fIO= f0 Weak TOL WSR Strong SUP fBUS Normal TOL PLLC. PMF TOL fSYS SUP Weak ERMC.EOM = 2 or 3 SUP ERMC.EOM = 1 TOL I/O SUP ROM TOL CPU SUP fXTAL 0 6 0 10 0 15 6 3 10 5 16 8 0 5 0 5 0 5 6 2 10 2 16 2 20 4 10 0x11 4 4 0 10 0 15 0 15 10 5 17 8 28 8 15 2 7.5 0x11 5 2 0 7 0 13 0 15 7 4 13 7 21 11 March 12, 2004; 6251-615-1PD 17 CDC 3272G-C 18 PRELIMINARY DATA SHEET March 12, 2004; 6251-615-1PD Micronas CDC 3272G-C PRELIMINARY DATA SHEET 5. Memory and Special Function ROM (SFR) System RESETQ = 1 address range (16M) CR.MAP = 00 CR.MAP = 01 RESETQ = 0 CR.MAP = 1x TEST2-Pin = 0 TEST2-Pin = 1 00FF.FFFF .5M I/O I/O I/O SFR SFR SFR RAM 16KB RAM 16KB RAM 16KB F8.0000 F0.0000 E0.0000 .5M rsvd debug 2M C0.4000 C0.0000 A0.0000 8M 26.0000 ROM 384KB ROM 384KB 20.0000 6.0000 4000 2M RAM 16KB ROM 384KB 0 ROM 384KB SFR SFR Fig. 5-1: Address Map. Most Common Settings Micronas March 12, 2004; 6251-615-1PD 19 CDC 3272G-C 20 PRELIMINARY DATA SHEET March 12, 2004; 6251-615-1PD Micronas CDC 3272G-C PRELIMINARY DATA SHEET 6. Core Logic 6.1. Control Word (CW) A number of important system configuration properties are selectable during device start-up by means of a unique Control Word (CW). 6.1.1. Reset Active At the end of the reset period, the device fetches this CW from address locations 0x20 to 0x23 of a source that is determined by the state of pins TEST and TEST2 and flag MFPLR.MFPL, see Table 6-1 for MCM parts, Table 6-2 for ROM parts. Table 6-1: CW fetch in MCM parts (QFP128) Control Word Fetch desired from As can be seen from Table 6-1, the device disables external access (through the Multi Function port) to internal code, as long as MFPLR.MFPL is 1 (= state after UVDD power-up). Setting it to 0 requires internal SW. By this means, an effective device lock mechanism is implemented, that prevents unauthorized access to internal SW. In ROM parts, flag MFPLR.MFPL is available, but does not lock the Multi Function port. Thus Table 6-1 reduces to Table 6-2. Table 6-2: CW fetch in ROM parts (QFP128) Control Word Fetch desired from Necessary Reset configuration Necessary Reset config. of pins TEST2 TEST TEST2 TEST MFPL Internal ROM 0 0 Int. Flash 0 0 x External via Multi Function port 0 1 Int. Flash 0 1 1 Int. Special Function ROM 1 x 0 1) Ext. via Multi Function port Int. Special Function ROM 1 x 6.1.2. Reset Inactive x When exiting Reset, the CW is read and stored in the Control Register (CR) and the system will start up according to the configuration defined therein. 1) Only available after a non-Power-On RESET with MFPL = 0 set before Normally the CW is fetched from the same memory that the system will start executing code from. Table 6-3 gives fix CWs for a list of the most commonly used configurations. Table 6-3: Some common system configurations and the corresponding CW setting Part Type Program Start desired from Additional desired properties Necessary CW 31:16 15:0 MCM int. 16-Bit Flash (Am29LV400BT) - Don't care 0x7F5F ROM int. 32-Bit ROM, 16-Bit mode - Don't care 0x7F5F ROM int. 32-Bit ROM, 32-Bit mode - 0xFFBA 0x775F Micronas March 12, 2004; 6251-615-1PD 21 CDC 3272G-C 22 PRELIMINARY DATA SHEET March 12, 2004; 6251-615-1PD Micronas CDC 3272G-C PRELIMINARY DATA SHEET 7. IRQ Interrupt Controller Unit (ICU) Table 7-1: ICU Input Availability Table 7-1: ICU Input Availability ISN Interrupt Source ISN Interrupt Source 30 Timer 4 0 Default vector, not connected 31 UART1 1 CC0OR 32 (Not connected) 2 CC1OR 33 (Not connected) 3 PINT0 34 CC0COMP 4 PINT1 35 CC1COMP 5 CAN0 36 CC2COMP 6 SPI0 37 CC3COMP 7 Timer 1 38 PINT4 8 Timer 0 39 GBus 9 P06 COMP 10 RESET/ALARM 11 WAIT COMP 12 UART0 13 PINT2 14 WAPI 15 CC2OR 16 CC3OR 17 Timer 2 18 RTC 19 I2C0 20 Timer 3 21 SPI1 22 COMMRX/TX 23 PINT5 24 PINT3 25 DIGITbus 26 I2C1 27 CAN1 28 CC4OR 29 CC5OR Micronas March 12, 2004; 6251-615-1PD 23 CDC 3272G-C 24 PRELIMINARY DATA SHEET March 12, 2004; 6251-615-1PD Micronas CDC 3272G-C PRELIMINARY DATA SHEET 8. Hardware Options 8.1. Functional Description Hardware Options are available in several areas to adapt the IC function to the host system requirements. For details see the document "CDC32xxG-C Automotive Controller - Family User Manual, CDC3205G-C Automotive Controller" (6251579-1PD). Hardware Option setting requires two steps: 1. selection is done by programming dedicated address locations in the HW Options field with the desired options' code. 2. activation is done by copying the HW Options field to the corresponding HW Options registers at least once after each reset. In this device, as in EMU and MCM devices, all HW Options are SW progammable. In future mask ROM derivatives the clock options and the Watchdog, Clock and Supply Monitors may be hard wired according to the HW Options field of the ROM code hex file. Those options can only be altered by changing a production mask. To ensure compatible option settings in this IC and future mask ROM derivatives when run with the same ROM code, it is mandatory to always write the HW Options field to the HW option registers directly after reset. Micronas March 12, 2004; 6251-615-1PD 25 CDC 3272G-C 26 PRELIMINARY DATA SHEET March 12, 2004; 6251-615-1PD Micronas CDC 3272G-C PRELIMINARY DATA SHEET 9. Register Cross Reference Table 9.1. 8-Bit I/O Region Table 9-1: Base address 0x00F80000 Offs. Byte Address 3 Remarks 2 1 0 0xFFC 0x400 0x3FC 0x200 0x1FC 0x000 6 CAN reserved Module CAN RAM CAN 1 CAN 0 Table 9-2: Base address 0x00F81000 Offs. 0x1FC 0x080 0x07C 0x054 0x050 0x04C 0x048 0x044 0x040 0x03C 0x014 0x010 0x00C 0x008 0x004 0x000 Micronas Byte Address 3 Remarks 2 1 0 6 CAN reserved Module CAN register CAN1 ESM ICR IDM IDX REC BT3 CTIM TEC BT2 OCR BT1 ESTR STR CTR CAN0 ESM ICR IDM IDX REC BT3 CTIM TEC BT2 OCR BT1 ESTR STR CTR March 12, 2004; 6251-615-1PD 27 CDC 3272G-C PRELIMINARY DATA SHEET Table 9-3: Base address 0x00F90000 (formerly 1F00) Offs. 0x0FC 0x0F8 0x0F4 0x0F0 0x0EC 0x0B0 0x0AC 0x0A8 0x0A4 0x0A0 0x09C 0x080 0x07C 0x078 0x074 0x070 0x06C 0x068 0x064 0x060 0x05C 0x058 0x054 0x050 0x04C 0x048 0x044 0x040 0x03C 0x030 0x02C 0x028 0x024 0x020 0x01C 0x018 0x014 0x010 0x00C 0x008 0x004 0x000 28 Byte Address 3 TST2 TST5 DGRTMA DGRTMD Remarks 2 TST1 DGTD DGS0 1 TST3 TSTAD3 DGS1TA DGC1 0 TST4 TSTAD2 DGTL DGC0 Module Test DIGITBus 64 byte UA0BR1 UA0IF UA0BR0 AD1 UA0CA UA0C ANAA AD0 UA0IM UA0D ADC UART0 32 byte CC3H CC2H CC1H CC0H CC3L CC2L CC1L CC0L SMVMUX SMVSIN TIM4 SMVC TIM3 TIM0H TIM0L CC5H CC4H CC5L CC4L AMDEC IRPM1 AMF IRPM0 CCC0H CC3I CC2I CC1I CC0I CCC0L CC3M CC2M CC1M CC0M CAPCOM0 DBG SMVCMP CSW1 SMVCOS Core Logic Stepper Motor Module VDO TIM2 TIM1 Timer CCC1H CC5I CC4I CCC1L CC5M CC4M AMAS AMPRE CC3 CC2 CC1 CC0 8 byte Timer0 CAPCOM1 CC5 CC4 16 byte Audio Module Port Interrupt 8 byte UA1BR1 SPI1M SR1 SR0 UA1IF UA1BR0 UA1CA UA1C SPI1D SPI0M UA1IM UA1D CO0SEL SPI0D UART1 Core Logic SPI Core Logic ANAU CSW0 March 12, 2004; 6251-615-1PD Micronas CDC 3272G-C PRELIMINARY DATA SHEET Table 9-4: Base address 0x00F90100 (formerly 1E00) Offs. 0x0FC 0x0F0 0x0EC 0x0E8 0x0E4 0x0E0 0x0DC 0x0D8 0x0D4 0x0D0 0x0CC 0x0C8 0x0C4 0x0C0 0x0BC 0x060 0x05C 0x058 0x054 0x050 0x04C 0x048 0x044 0x040 0x03C 0x020 0x01C 0x018 0x014 0x010 0x00C 0x008 0x004 0x000 Micronas Byte Address 3 Remarks 2 1 0 16 byte P7P P3P P11P SP2C PF0C C1C RZPC T3C P7C P3C P11C SP1C AC C0C CO01C T2C UA1 PM UA0 P5P P1P P9P SP0C LC CO1C CO00C T1C P5C P1C P9C SMC DC DMAC T4C T0C Module HW Options 96 byte PFM PFM1 PFM0 PWMC PWM11 PWM7 PWM3 PWM PWM10 PWM6 PWM2 PWM9 PWM5 PWM1 PWM8 PWM4 PWM0 32 byte I2C1 I2CM1 I2CRS1 I2CWD11 I2CRD1 I2CWD01 I2CWP11 I2CWS11 I2C I2CWP01 I2CWS01 I2C0 I2CM0 I2CRS0 I2CWD10 I2CRD0 I2CWD00 I2CWP10 I2CWS10 I2CWP00 I2CWS00 March 12, 2004; 6251-615-1PD 29 CDC 3272G-C PRELIMINARY DATA SHEET Table 9-5: Base address 0x00F90400 Offs. 0x0FC 0x0F8 0x0F4 0x0F0 0x0EC 0x0E8 0x0E4 0x0E0 0x0DC 0x0D8 0x0D4 0x0D0 0x0CC 0x0C8 0x0C4 0x0C0 0x0BC 0x0B8 0x0B4 0x0B0 0x0AC 0x090 0x084 0x080 0x074 0x070 0x064 0x060 0x054 0x050 0x044 0x040 0x034 0x030 0x024 0x020 0x014 0x010 0x004 0x000 30 Byte Address 3 Remarks 2 1 HxLVL HxNS HxTRI HxLVL HxNS HxTRI HxLVL HxNS HxTRI HxLVL HxNS HxTRI HxLVL HxNS HxTRI HxLVL HxNS HxTRI HxLVL HxNS HxTRI HxLVL HxNS HxTRI 0 HxPIN HxD HxPIN HxD HxPIN HxD HxPIN HxD HxPIN HxD HxPIN HxD HxPIN HxD HxPIN HxD P2IE P1IE P0IE P2PIN P1PIN P0PIN H-Port7 Module H-Ports H-Port6 H-Port5 H-Port4 H-Port3 H-Port2 H-Port1 H-Port0 P-Ports P2LVL P1LVL P0LVL UxMODE UxDPM UxMODE UxDPM UxMODE UxDPM UxMODE UxDPM UxMODE UxDPM UxMODE UxDPM UxMODE UxDPM UxMODE UxDPM UxMODE UxDPM UxPIN UxNS UxPIN UxNS UxPIN UxNS UxPIN UxNS UxPIN UxNS UxPIN UxNS UxPIN UxNS UxPIN UxNS UxPIN UxNS UxLVL UxTRI UxLVL UxTRI UxLVL UxTRI UxLVL UxTRI UxLVL UxTRI UxLVL UxTRI UxLVL UxTRI UxLVL UxTRI UxLVL UxTRI UxSLOW UxD UxSLOW UxD UxSLOW UxD UxSLOW UxD UxSLOW UxD UxSLOW UxD UxSLOW UxD UxSLOW UxD UxSLOW UxD March 12, 2004; 6251-615-1PD P-Port 2 P-Port1 P-Port 0 reserved U-Ports U-Port 8 U-Port 7 U-Port 6 U-Port 5 U-Port 4 U-Port 3 U-Port 2 U-Port 1 U-Port 0 Micronas CDC 3272G-C PRELIMINARY DATA SHEET Table 9-6: Base address 0x00F90500 Offs. 0x0FC 0x080 0x07C 0x078 0x074 0x070 0x06C 0x068 0x064 0x060 0x05C 0x058 0x054 0x050 0x04C 0x048 0x044 0x040 0x03C 0x030 0x02C 0x028 0x024 0x020 0x01C 0x014 0x010 0x00C 0x008 0x004 0x000 Micronas Byte Address 3 Remarks 2 1 0 128 Bytes SMX POL RTCC OSC WPM6 RTC SSC SSR WPM4 WPM2 WSC WPM8 WPM0 Module reserved Power Saving Polling RTC Wake Ports mode RTC WUS Wake-up source reserved GBus GC GD MDL MFPLR WSR IOC Memory Ctrl. DLM Clock, PLL, ERM Core Logic reserved LCD ERMC PLLC ULCDLD Patch PER PDR PAR March 12, 2004; 6251-615-1PD 31 CDC 3272G-C PRELIMINARY DATA SHEET 9.2. 32-Bit I/O Region Table 9-7: Base address 0x00FFFD00 Offs. 0x0FC 0x004 0x000 Byte Address 3 Remarks 2 1 0 252 bytes reserved CR Module Core Logic Control Register Table 9-8: Base address 0x00FFFE00 Offs. 0x0FC 0x020 0x018 0x010 0x008 0x004 0x000 Byte Address 3 Remarks 2 1 0 rsvd Channel 4 to 31 DC3M DC2M DC1M DST Module DMA Channel 3 Channel 2 Channel 1 Control DVB Table 9-9: Base address 0x00FFFF00 Offs. 0x0FC 0x0F4 0x0F0 0x0EC 0x0C8 0x0C4 0x0C0 0x0BC 0x040 0x03C 0x028 0x024 : 0x004 0x000 32 Byte Address 3 Remarks 2 1 0 12 bytes reserved VTB PESRC CRF PRF AFP CRI FIQ registers 40 bytes reserved Module IRQ and FIQ Interrupt Controller IRQ registers PEPRIO 128 bytes reserved Interrupt source nodes ISN39 : ISN7 ISN3 ISN38 : ISN6 ISN2 ISN37 : ISN5 ISN1 ISN36 : ISN4 ISN0 March 12, 2004; 6251-615-1PD Micronas CDC 3272G-C PRELIMINARY DATA SHEET 9.3. Modified Registers Listed are only those registers that are differing from document "CDC32xxG-C Automotive Controller - Family User Manual, CDC3205G-C Automotive Controller" (6251-5791PD). 9.3.1. Standby Registers (cf. chapter 6.3 in User Manual) SR0 Standby Register 0 7 6 5 4 3 2 1 0 r/w I2C1 I2C0 x x x x x CAN1 3 r/w TIM2 TIM3 TIM4 UART1 x DGB CCC1 x 2 r/w LCD x PSLW UART0 ADC x TIM1 XTAL 1 r/w SM x x x SPI1 CAN0 CCC0 SPI0 0 0x00000100 Offs Res Standby Register 0 (SR0) flags CAN2 and CAN3 at byte offest 3, bit number 1 and 2 are not available in this part. 9.3.2. UVDD Analog Registers (cf. chapter 6.4.9 in User Manual) ANAU r/w Analog UVDD Register 7 6 EAL x 0 5 4 LS 0 0 3 2 1 0 x x x VE 0 0 Analog UVDD Register flag FVE at bit number 1 is not available in this part. Micronas March 12, 2004; 6251-615-1PD 33 CDC 3272G-C 34 PRELIMINARY DATA SHEET March 12, 2004; 6251-615-1PD Micronas CDC 3272G-C PRELIMINARY DATA SHEET 10. Differences This chapter describes differences of this document to predecessor document "CDC32xxG-C Automotive Controller - Section Description 1. Introduction Table 1-1 extended, editorial corrections 2. Pins and Packages Editorial corrections. Family User Manual, CDC3205G-C Automotive Controller" (6251-579-1PD). Figure 2-1: changed. 3. Electrical Characteristics Absolute Maximum Ratings: Revised introduction. Recommended Operating Conditions: Revised introduction. Characteristics: Revised introduction. Values added: AIDDq, HIDDq Values changed: Rthjc, Rthja, Added conditions: Rthjc, Rthja, 4. CPU and Clock System Editorial corrections. 8. Hardware Options Editorial corrections. 9. Register Cross Reference Table Editorial corrections. Micronas March 12, 2004; 6251-615-1PD 35 CDC 3272G-C PRELIMINARY DATA SHEET 11. Data Sheet History 1. Advance Information: "CDC 3272G-C Automotive Controller", April 15, 2003, 6251-615-1AI. First release of the advance information. Originally created for HW version CDC3272G-C1. 2. Preliminary Data Sheet: "CDC 3272G-C Automotive Controller", March 12, 2004, 6251-615-1PD. First release of the preliminary data sheet. Originally created for HW version CDC3272G-C1. Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-615-1PD 36 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH. March 12, 2004; 6251-615-1PD Micronas