Enpirion® Power Datasheet
EP53A7LQI/EP53A7HQI 1A Pow er SoC
Light Load M ode Buck Regulator
with I ntegr at ed Inductor
Description
The EP53A7xQI (x = L or H) is a 1000mA
PowerSOC. The EP53A7xQI integrates MOSFET
switches, control, compensation, and the
magnetics in an advanced 3mm x 3mm QFN
Package.
Integrated magnetics enables a tiny solution
footprint, low output ripple, low part-count, and
high reliability, while maintaining high efficiency.
The complete solution can be implemented in as
little as 21mm2.
A proprietary light load mode (LLM) provides high
effic ienc y in light load c onditions .
The EP53A7xQI uses a 3-pin VID to eas ily s elec t
the output voltage setting. Output voltage
settings are available in 2 optimized ranges
providing c over age for typic al VOUT s ettings .
The VID pins can be changed on the fly for fast
dynamic voltage scaling. EP53A7LQI further has
the option to us e an external voltage divider.
The EP53A7xQI offers the optimal combination
of very small solution footprint and advanced
perfor m anc e features .
EP53A7xQI
4.7uF
10uF
6mm
3.5mm
100 Ohm
Figure 1: Total Sol uti on Footpri nt
Features
•Integrated Inductor Technology
•3mm x 3mm x 1.1mm QFN package
•Total Solution Footprint < 21mm2
•Low VOUT ripple for RF compatibility
•High efficiency, up to 94%
•1000mA continuous output current
•55µA quiescent current
•Less than 1µA standby current
•5 MHz switching frequency
•3 pin VID for glitc h free voltage s c aling
•VOUT Range 0.6V to VIN – 0.5V
•Short c ir c uit and over c ur rent pr otec tion
•UVLO and therm al protec tion
•IC level r eliability in a PowerSOC solution
Application
•Portable wireless and RF applications
•Solid state storage applications
•Spac e c ons tr ained applic ations requir ing high
effic ienc y and very s m all s olution s iz e
V
IN
V
SENSE
PVIN
V
S1
V
S2
V
S0
10µF
4.7µF
VOUT
V
OUT
AGND
ENABLE
V
FB
PGND
AVIN
LLM
100 ohm
Figure 2: Typica l Appl i ca ti on S che m ati c
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01543 October 11, 2013 Rev D
EP53A7LQI/EP53A7HQI
Ordering Information
Part Num ber
Comment
Package
EP53A7LQI LO W VID Range 16-pin QF N T&R
EP53A7HQI
HIGH VID Rang e
16-pi n QF N T&R
EVB-EP53A7LQI EP53A7LQI Evaluati on Board
EVB-EP53A7HQI EP53A7HQI E val uat i on Board
Pin Assignments (Top View)
Figure 3: EP53A7LQI P in Out Di agram (Top Vi e w)
Figure 4: EP53A7HQI P i n Out Di agram (Top V i ew)
Pin Description
PIN
NAME
FUNCTION
1, 15,
16 NC(SW)
NO CONNECT – T hese pins are internally connected to the com mo n switchi ng node of the
internal MOSFET s. NC (SW) pins are not to be electricall y connec ted to any external sign al ,
ground, or voltage. However, they must be soldered to the PCB . Failure to follow this
guideline may result in part malfunct ion or damage to the device.
2 PGND
Power ground. Connect this pin to the ground electrode of the I nput and output filter
capacitors.
3 LLM
LLM ( Light load mode – “LLM ”) pi n. Logi c-High enables auto matic LLM/PWM and logic-
low places the device in fixed PWM operation.
4
VFB
NC
EP53A7LQI: Feed back pin f or external resistor divider option.
EP53A7HQI: No Connect
5
VSENSE
Sense pin f or preset output voltages. Ref er to applicati on secti on for proper configuration.
6 AGND
Analog ground. T his is the quiet ground for the internal control circuitry, and the ground
return for external feedback voltage divider
7, 8
VOUT
Regulated Output Voltage. Ref er to application sect ion f or proper layout and decoupling.
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01543 October 11, 2013 Rev D
EP53A7LQI/EP53A7HQI
PIN
NAME
FUNCTION
9, 10,
11 VS2, VS1,
VS0
Output voltage select. VS2 = pin 9, VS1 = pin 10, VS0 = pin 11.
EP53A7LQI: Selects one of seven preset output voltages or an external resistor divider.
EP53A7HQI: Selects one of eight preset output voltages.
(R efer to section on output voltage select for more details.)
12
ENABLE
Output Enable. Enable = logic high; Disable = logic low
13
AVIN
I nput power supply for the controller circuitry. Connect to PV IN through a 100 Ohm resistor.
14
PVIN
I nput Voltage for the MOSFET switches.
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the
recommended operating conditions is not im plied. S tres s beyond the abs olute m axim um ratings m ay
cause permanent damage to the device. Exposure to absolute maximum rated conditions for
extended periods m ay affec t devic e reliability.
PARAMETER
SYMBOL
MIN
MAX
UNITS
I nput Supply Voltage
V
IN
-0.3
6.0
V
Voltages on: ENABLE, VSENSE, VSO – VS2 -0.3 VIN+ 0.3 V
Voltages on: VFB (EP53A7LQI) -0.3 2.7 V
Maximum Operating Junc tion T emperature
T
J-ABS
150
°C
Storage T emperature Range
T
STG
-65
150
°C
Ref low T emp, 10 Sec, MSL3 JEDEC J -STD-020C
260
°C
ESD Rating (based on Human Body Mode)
2000
V
Recommended Operating Conditions
PARAMETER
SYMBOL
MIN
MAX
UNITS
I nput Voltage Range
V
IN
2.4
5.5
V
Operating Ambient T emperature
T
A
- 40
+85
°C
Operating Junction T emperature
T
J
- 40
+125
°C
Thermal Characteristics
PARAMETER
SYMBOL
TYP
UNITS
T hermal Resistance: Junction to A mbie nt –0 LFM (Note 1)
θ
JA
80
°C/W
T hermal Overload T rip Point
T
J-TP
+155
°C
T hermal Overload T rip Point Hyster esis
25
°C
No te 1: B ased on a four l ayer copper board and proper t herm al desi gn per JEDEC EIJ/JESD51 standards
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01543 October 11, 2013 Rev D
EP53A7LQI/EP53A7HQI
Electrical Characteristics
NOTE: TA = -40°C to +85°C unless otherwise noted. Typi cal val ues are at TA = 25° C, V IN = 3.6V.
CIN = -4.7µF MLCC, COUT = 10µF MLCC
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Operating I nput Voltage
V
IN
2.4
5.5
V
Under Voltage Lock-out –
VIN Rising VUVLO_R 2.0 V
Under Voltage Lock-out –
VIN Falling VUVLO_F 1.9 V
Drop Out Resistance
R
DO
I nput to Output Resistance
350
500
mΩ
Output Voltage Range VOUT EP53A7LQI (VDO = I LOAD X RDO)
EP53A7HQI 0.6
1.8 VIN-VDO
3.3 V
Dynamic Voltage Slew
Rate VSLEW
EP53A7LQI
EP53A7HQI
4
8 V/mS
VID Preset VOUT Initial
Accuracy ∆VOUT
T
A
= 25°C, V
IN
= 3.6V;
ILOAD = 100mA ;
0.8V ≤ VOUT ≤ 3.3V -2 +2 %
Feedback Pin Volt age
I nitial Accuracy VFB
T
A
= 25°C, V
IN
= 3.6V;
ILOAD = 100mA ;
0.8V ≤ VOUT ≤ 3.3V .588 0.6 0.612 V
Line Regulation
∆VOUT_LINE
2.4V ≤ V
IN
≤ 5.5V
0.03
%/V
Load Regulation ∆VOUT_LOAD 0A ≤ ILOAD ≤ 1000mA 0.6 %/A
Temperature Variation ∆VOUT_TEMPL -40°C ≤ T
A
≤ +85°C 30 ppm/°C
Output Current
I
OUT
1000
mA
Shut-down C urrent
I
SD
Enable = Low
0.75
µA
EP53A7HQI Operating
Quiescent Current IQ ILOAD=0; Preset Output Volt ages,
LLM=High 55 µA
EP53A7LQI Operating
Quiescent Current IQ ILOAD=0; Preset Output Volt ages,
LLM=High 65 µA
OCP T hreshold ILIM
2.4V ≤ V
IN
≤ 5.5V
0.6V ≤ VOUT ≤ 3.3V 1.25 1.4 A
Feedback Pin Input
Current IFB N ote 1 <100 nA
VS0-VS2, Pi n Logic Low
V
VSLO
0.0
0.3
V
VS0-VS2 , Pin Logic High
V
VSHI
1.4
V
IN
V
VS0-VS2, Pi n Input
Current IVSX Note 1 <100 nA
Enable Pin Logic Low
V
ENLO
0.3
V
Enable Pin Logic High
V
ENHI
1.4
V
Enable Pin Current
I
ENABLE
Note 1
<100
nA
LLM Engage Headroom Minimum diff erence between VIN
and VOUT to ensure proper LLM
operation 700 mV
LLM Pin Logic Low
V
LLMLO
0.3
V
LLM Pin Logic High
V
LLMHI
1.4
V
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01543 October 11, 2013 Rev D
EP53A7LQI/EP53A7HQI
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
LLM Pin Curr ent
I
LLM
<100
nA
Operating Frequency
F
OSC
5
MHz
Soft Start Operation
Soft Start Slew Rate ∆VSS
EP53A7LQI (VID only)
EP53A7HQI (VID only)
4
8 V/mS
Soft Start Rise T ime ∆TSS EP53A7LQI ( VFB mode); Note 2 170 225 280 µS
No te 1: P aram eter guarant eed by desi gn
No te 2: M easured from when V IN ≥ VUVLO_R & ENA B LE pi n crosses i ts l ogi c Hi gh t hreshol d.
Typical Performance Characteristics
Efficiency vs. Loa d Current: VOUT = 1.2V, VIN (from
top to bottom) = 2.5, 3.3, 3.7, 4.3, 5.0V
Efficiency vs. Loa d Current: VOUT = 1.8V, VIN (from
top to bottom) = 2.5, 3.3, 3.7, 4.3, 5.0V
Efficiency vs. Loa d Current: VOUT = 2.5V, VIN (from
top to bottom) = 3.3, 3.7, 4.3, 5.0V
Efficiency vs. Loa d Current: VOUT = 3.3V, VIN (from
top to bottom) = 3.7, 4.3, 5.0V
45
50
55
60
65
70
75
80
85
90
95
10 100 1000
Load Current (mA)
Efficiency (%)
45
50
55
60
65
70
75
80
85
90
95
10 100 1000
Load Current (m A)
Efficiency (%)
45
50
55
60
65
70
75
80
85
90
95
10 100 1000
Load Current (mA)
Efficiency (%)
45
50
55
60
65
70
75
80
85
90
95
10 100 1000
Load Current (mA )
Eff ici ency (% )
LLM
LLM
PWM
PWM
LLM
PWM
V
OUT
=1.2V
VOUT=1.8V
V
OUT
=2.5V
LLM
PWM
V
OUT
=3.3V
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01543 October 11, 2013 Rev D
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S tar t Up Wavefo rm: VIN = 5.0V, VOUT = 3.3V;
ILOAD = 10mA; V I D Mode
S tar t Up Wavefo rm: VIN = 5.0V, VOUT = 3.3V;
ILOAD = 1000mA; V I D Mode
Shut-down Wave form : VIN = 5.0V, VOUT = 3.3V;
ILOAD = 10mA, PWM
Shut-down Wave form : VIN = 5.0V, VOUT = 3. 3V;
ILOAD = 1000mA, PW M
Out put Ripple: VIN = 5.0V, VOUT = 1.2V , Load = 10mA
LLM enabl ed
Output Ri ppl e: VIN = 5.0V, VOUT = 1. 2V,
Load = 1A
50mV/Div
5mV/Div
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01543 October 11, 2013 Rev D
EP53A7LQI/EP53A7HQI
Out put Ripple: VIN = 5.0V, VOUT = 3.3V, Load = 10mA
LLM enabl ed
Output Ri ppl e: VIN = 5.0V, VOUT = 3.3V,
Loa d = 1A
Out put Ripple: VIN = 3.3V, VOUT = 1.8V, Load = 10mA
LLM enabl ed
Output Ri ppl e: VIN = 3.3V, VOUT = 1.8V
Loa d = 1A
Out put Ripple: VIN = 3.3V, VOUT = 1.2V, Load = 10mA
LLM enabl ed
Output Ri ppl e: VIN = 3.3V, VOUT = 1.2V,
Loa d = 1A
5mV/Div
50mV/Div
5mV/Div
50mV/Div
50mV/Div
5mV/Div
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01543 October 11, 2013 Rev D
EP53A7LQI/EP53A7HQI
Loa d Transi ent: VIN = 5.0V , VOUT = 3.3V
Loa d stepped from 0mA to 1000mA
Loa d Transi ent: VIN = 5.0V , VOUT = 3.3V
Load stepped f rom 10 mA to 1000m A, LLM enabl ed
Loa d Transi ent: VIN = 5.0V, VOUT = 1.2V
Loa d stepped from 0mA to 1000mA
Loa d Transi ent: VIN = 5.0V, VOUT = 1.2V
Load stepped f rom 10 mA to 1000mA, LLM enabl ed
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01543 October 11, 2013 Rev D
EP53A7LQI/EP53A7HQI
Loa d Transi ent: VIN = 3.7V, VOUT = 1.2V
Loa d stepped from 0mA to 1000m A
Loa d Transi ent: VIN = 3.7V, VOUT = 1.2V
Loa d stepped from 10m A to 1000m A, LLM enabl ed
Loa d Transi ent: VIN = 3.3V, VOUT = 1.8V
Loa d stepped from 0mA to 1000mA
Loa d Transi ent: VIN = 3.3V, VOUT = 1.8V
Loa d stepped from 10m A to 1000m A, LLM enabl ed
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01543 October 11, 2013 Rev D
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Functional Block Diagram
Figure 5: Functional Bl ock Di a gram
DAC
Switch
VREF
(+)
(-)
Error
Amp
V
SENSE
V
FB
V
OUT
Package Boundry
P-Drive
N-Drive
UVLO
Thermal Limit
Current Limit
Soft Start
Sawtooth
Generator
(+)
(-)PWM
Comp
PVIN
ENABLE
PGND
Logic
Compensation
Network
NC(SW)
Voltage
Select
VS0VS1
AVIN VS2AGND
Mode Logic
LLM
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01543 October 11, 2013 Rev D
EP53A7LQI/EP53A7HQI
Detailed Description
Functional Overview
The EP53A7xQI requires only 2 small MLCC
capacitors and an 0201 resistor for a c om plete
DC-DC converter solution. The device
integrates MOSFET switches, PWM controller,
Gate-drive, compensation, and inductor into a
tiny 3mm x 3mm x 1.1mm QFN package.
Advanced package design, along with the high
level of integration, provides very low output
ripple and noise. The EP53A7xQI uses
voltage mode control for high noise immunity
and load matching to advanced ≤90nm loads.
A 3-pin VID allows the us er to c hoos e from one
of 8 output voltage settings. The EP53A7xQI
comes with two VID output voltage ranges.
The EP53A7HQI provides VOUT settings from
1.8V to 3.3V, the EP53A7LQI provides VID
settings from 0.8V to 1.5V, and also has an
external resistor divider option to program
output setting over the 0.6V to VIN-0.5V range.
The EP53A7xQI provides the industry’s highest
power density of any 1A DCDC converter
solution.
The key enabler of this revolutionary
integration is Altera Enpirion’s proprietary
power MOSFET technology. The advanced
MOSFET switches are implemented in deep-
submicron CMOS to supply very low switching
loss at high switching frequencies and to allow
a high level of integration. The semiconductor
process allows seamless integration of all
s witc hing, c ontrol, and c om pens ation c ir c uitry.
The proprietary magnetics design provides
high-density/high-value magnetics in a very
small footprint. Altera Enpirion magnetics are
carefully matched to the control and
compensation circuitry yielding an optimal
solution with assured performance over the
entire operating range.
Protection features include under-voltage lock-
out (UVLO), over-current protection (OCP),
short circuit protection, and thermal overload
protection.
Integrated Inductor
The EP53A7xQI utilizes a proprietary low loss
integrated inductor. The integration of the
inductor greatly simplifies the power supply
design process. The integrated inductor
provides the optimal solution to the complexity,
output ripple, and noise that plague low power
DCDC converter design.
Voltage Mode Control
The EP53A7xQI utilizes an integrated type III
compensation network. Voltage mode control
is inherently impedance matched to the sub
90nm process technology that is used in
today’s advanced ICs. Voltage mode control
also provides a high degree of noise immunity
at light load c ur rents s o that low r ipple and high
accuracy are maintained over the entire load
range. The very high switching frequency
allows for a very wide control loop bandwidth
and henc e exc ellent trans ient perfor m anc e.
Light Load Mode (LLM) Operation
The EP53A7xQI uses a proprietary light load
mode to provide high efficiency in the low load
operating condition. When the LLM pin is high,
the device is in automatic LLM/PWM mode.
When the LLM pin is low , the devic e is in PWM
mode. In automatic LLM/PWM mode, when a
light load condition is detected, the device will
(1) step VOUT up by approximately 1.5% above
the nominal operating output voltage setting,
VNOM, and then (2) shut down unnecessary
c irc uitr y, and (3) m onitor VOUT. When VOUT falls
below VNOM, the device will repeat (1), (2), and
(3). The voltage step up, or pre-positioning,
improves transient droop when a load transient
causes a transition from LLM mode to PWM
mode. If a load transient occurs, causing VOUT
to fall below the threshold VMIN, the device will
exit LLM operation and begin normal PWM
operation. Figure 6 demonstrates VOUT
behavior during transition into and out of LLM
operation.
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01543 October 11, 2013 Rev D
EP53A7LQI/EP53A7HQI
Figure 6: VOUT Behavior i n LLM Ope ration
Figure 7: VOUT Droop during P e ri odi c LLM Exi t
Many multi-m ode D CD C c onverter s s uffer fr om
a condition that occurs when the load current
increases only slowly so that there is no load
transient driving VOUT below the VMIN threshold
(shown in Figure 6). In this condition, the
device would never exit LLM operation. This
could adversely affect efficiency and cause
unwanted ripple. To prevent this from
occurring, the EP53A7xQI periodically exits
LLM mode into PWM mode and measures the
load current. If the load current is above the
LLM threshold current, the device will remain in
PWM mode. If the load current is below the
LLM threshold, the device will re-enter LLM
operation. There will be a small droop in VOUT
at the point where the device exits and re-
enters LLM, as s how n in Figure 7.
The load current at which the device will enter
LLM mode is a function of input and output
voltage. Figure 8 s hows the typic al value at
Figure 8: Typical load current for LLM engage and
di se ngage ve rsus VOUT for se l ecte d i nput vol tages
Table 1: Load cur rent belo w which the device can b e
ce rtai n to be i n LLM opera tion. These va l ues are
gua rante ed by de si gn
which the device will enter LLM operation. The
actual load current at which the device will
enter LLM operation can vary by +/-30%. Table
1 s how s the m inim um load c urrent below which
the device is guaranteed to be in LLM
operating mode.
To ensure normal LLM operation, LLM mode
should be enabled/disabled with specific
sequencing. For applications with explicit LLM
pin control, enable LLM after VIN ramp up
complete; disable LLM before VIN ramp down.
For applications with ENABLE control, tie LLM
to ENABLE; enable device after VIN ramp up
complete and disable device before VIN ramp
V
OUT
I
OUT
LLM
Ripple
PWM
Ripple
VMAX
VNOM
VMIN
Load
Step
LLM Thresh old Current vs. VOUT
0
50
100
150
200
250
0.8 1.1 1.4 1.7 2.0 2.3 2.6 2.9 3.2
VOUT (V )
LLM Threshold (mA)
VIN=5 V (to p c urve)
VIN=4.2V
VIN=3.7V
VIN= 3.3V (bottom curve)
3.3 3.7 4.3 5.0
3.30 105 147
3.00 62 122 156
2.90 89 126 158
2.60 56 106 136 162
2.50 69 111 138 162
2.20 101 120 141 160
2.10 105 122 141 158
1.80 111 124 138 150
1.50 111 120 130 138
1.45 111 119 128 136
1.20 105 111 117 122
1.15 103 108 114 119
1.10 101 106 111 116
1.05 99 104 108 113
0.80 87 89 92 94
VIN
VOUT
Devic e exits LLM,
tests load current
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01543 October 11, 2013 Rev D
EP53A7LQI/EP53A7HQI
down begins. For devices with ENABLE and
LLM tied to VIN, contact Altera Applications
engineering for specific recommendations.
Increased output filter capacitance and/or
increased bulk capacitance at the load will
decrease the magnitude of the LLM ripple.
Refer to the s ec tion on output filter c apac itanc e
for maximum values of output filter c apac itanc e
and the Soft-Start section for maximum bulk
c apac itanc e at the load.
NOTE: For proper LLM operation the
EP53A7xQI requires a minimum difference
between VIN and VOUT of 700mV. If this
condition is not met, the device cannot be
as s ured proper LLM oper ation.
NOTE: Automatic LLM/PWM is not available
when using the external resistor divider option
for VOUT programming.
S o ft S ta rt
Internal soft start circuits limit in-rush current
when the device starts up from a power down
condition or when the “ENABLE” pin is
asserted “high”. Digital control circuitry limits
the VOUT ramp rate to levels that are safe for
the Power MOSFETS and the integrated
inductor.
The EP53A7HQI has a soft-start slew rate that
is twice that of the EP53A7LQI.
When the EP53A7LUI is configured in external
resistor divider mode, the device has a fixed
VO UT r am p tim e. Therefore, the ram p rate w ill
vary with the output voltage setting. Output
voltage ramp time is given in the Electrical
Characteristics Table.
Excess bulk capacitance on the output of the
device can cause an over-current condition at
startup. The maximum total capacitance on
the output, including the output filter capacitor
and bulk and decoupling capacitance, at the
load, is given as:
EP53A7LQI:
COUT_TOTAL_MAX = COUT_Filter + COUT_BULK = 200uF
EP53A7HQI:
COUT_TOTAL_MAX = COUT_Filter + COUT_BULK = 100uF
EP53A7LUI in external divider mode:
COUT_TOTAL_MAX = 2.25x10-4/VOUT Farads
The nominal value for COUT is 10uF. See the
applic ations s ec tion for m ore details .
Over Current/Short Circuit Protection
The current limit function is achieved by
sensing the current flowing through a sense P-
MOSFET which is compared to a reference
current. When this level is exceeded the P-
FET is turned off and the N-FET is turned on,
pulling VOUT low. This condition is maintained
for approximately 0.5mS and then a normal
soft start is initiated. If the over current
c ondition s till pers is ts , this c yc le w ill repeat.
Under Vol t age Lockout
During initial power up, an under voltage
lockout circuit will hold-off the switching
circuitry until the input voltage reaches a
sufficient level to insure proper operation. If
the voltage drops below the UVLO threshold,
the lockout circuitry will again disable the
switching. Hysteresis is included to prevent
chattering between states.
Enable
The ENABLE pin provides a means to shut
down the converter or enable normal
operation. A logic low will disable the
converter and cause it to shut down. A logic
high will enable the converter into normal
operation.
NOTE: The ENABLE pin must not be left
floating.
Thermal Shutdown
When excessive power is dissipated in the
chip, the junction temperature rises. Once the
junction temperature exceeds the thermal
shutdown temperature, the thermal shutdown
circuit turns off the converter output voltage
thus allowing the device to cool. When the
junction temperature decreases by 25C°, the
device will go through the normal startup
process.
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01543 October 11, 2013 Rev D
EP53A7LQI/EP53A7HQI
Application Information
V
IN
VSENSE
PVIN
VS1
VS2
VS0
10µF
4.7µF
V
OUT
VOUT
AGND
ENABLE
PGND
AVIN
LLM
100 ohm
Figure 9: A p plica t ion Cir c uit , EP53A7HQI. Note th at
al l control si gnal s shoul d be conne cted to an
exte rna l control si gnal , AVIN o r AGND.
V
IN
VSENSE
PVIN
VS1
VS2
VS0
10µF
4.7µF
V
OUT
VOUT
AGND
ENABLE
VFB
PGND
AVIN
LLM
100 ohm
Figure 10: Appl ica ti on Ci rcuit, EP53A7LQI showing
th e VFB function.
Output Voltage Programming
The EP53A7xQI utilizes a 3-pin VID to program
the output voltage value. The VID is available
in two sets of output VID programming ranges.
The VID pins should be connected either to an
external control signal, AVIN or to AGND to
avoid noise coupling into the device. The VID
pins m us t not be left floating.
The “Low” range is optimized for low voltage
applications. It comes with preset VID settings
ranging from 0.80V and 1.5V. This VID set
als o has an external divider option.
To specify this VID range, order part number
EP53A7LQI.
The “High” VID set provides output voltage
settings ranging from 1.8V to 3.3V. This
version does not have an external divider
option. To specify this VID range, order part
num ber EP53A7HQI.
Internally, the output of the VID multiplexer
sets the value for the voltage reference DAC,
which in turn is connected to the non-inverting
input of the er ror am plifier. This allow s the us e
of a single feedback divider with constant loop
gain and optimum compensation, independent
of the output voltage s elec ted.
NOTE: The VID pins m us t not be left floating.
EP53A7L Low VI D Range Progr a m m i ng
The EP53A7LQI is designed to provide a high
degree of flexibility in powering applications
that require low VOUT settings and dynamic
voltage scaling (DVS). The device employs a
3-pin VID architecture that allows the user to
choose one of seven (7) preset output voltage
settings, or the user can select an external
voltage divider option. The VID pin settings
can be changed on the fly to implement glitch-
free voltage s c aling.
Table 2: EP53A7LQI VID Voltage Select Settings
Table 2 s hows the VS2-VS0 pin logic s tates for
the EP53A7LQI and the associated output
voltage levels. A logic “1” indicates a
connection to AVIN or to a “high” logic voltage
level. A logic “0” indicates a connection to
AGND or to a “low” logic voltage level. These
pins can be either hardwired to AVIN or AGND
or alternatively can be driven by standard logic
levels. Logic levels are defined in the electrical
characteristics table. Any level between the
logic high and logic low is indeterminate.
EP53A7LQI External V oltage D ivider
The external divider option is chosen by
connecting VID pins VS2-VS0 to AVIN or a
logic “1” or “high”. The EP53A7LQI uses a
separate feedback pin, VFB, when using the
external divider. VSENSE must be connected to
VOUT as indicated in Figure 11.
VS2 VS1 VS0 VOUT
0 0 0 1.50
0 0 1 1.45
0 1 0 1.20
0 1 1 1.15
1 0 0 1.10
1 0 1 1.05
1 1 0 0.8
1 1 1 EXT
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01543 October 11, 2013 Rev D
EP53A7LQI/EP53A7HQI
V
IN
V
Sense
V
S0
V
S2
EP53A7L
10µF
4.7uF
V
OUT
V
OUT
AGND
ENABLE
Ra
Rb
V
FB
V
S1
PGND
AVIN
PVIN
LLM
100 Ohm
Figure 11: EP53A7LQI usi ng external di vider
The output voltage is selected by the following
formula:
( )
Rb
Ra
OUT VV += 16.0
Ra must be chosen as 237KΩ to m aintain loop
gain. Then R b is given as:
Ω
−
=6.0
102.142
3
OUT
b
Vx
R
VOUT can be programmed over the range of
0.6V to (VIN – 0.5V).
NOTE: Dynamic Voltage Scaling is not allowed
between internal preset voltages and external
divider.
NOTE: LLM is not functional when using the
external divider option. Tie the LLM pin to
AGND w hen us ing this option.
EP53A7HQI High VID Range
Programming
The EP53A7HQI VOUT settings are optimized
for higher nominal voltages such as those
required to power IO, RF, or IC memory. The
preset voltages range from 1.8V to 3.3V.
There are eight (8) preset output voltage
settings. The EP53A7HQI does not have an
external divider option. As with the
EP53A7LQI, the VID pin settings can be
c hanged w hile the devic e is enabled.
Table 3 s how s the VS0-VS2 pin logic s tates for
the EP53A7HQI and the associated output
voltage levels. A logic “1” indicates a
connection to AVIN or to a “high” logic voltage
level. A logic “0” indicates a connection to
AGND or to a “low” logic voltage level. These
pins can be either hardwired to AVIN or AGND
or alternatively can be driven by standard logic
levels. Logic levels are defined in the electrical
characteristics table. Any level between the
logic high and logic low is indeterminate.
Thes e pins m us t not be left floating.
Table 3: EP53A7HQI VID Voltage Select Settings
Power-Up/Down Sequencing
During power-up, ENABLE should not be
asserted before PVIN, and PVIN should not be
asserted before AVIN. The PVIN should never
be powered when AVIN is off. During power
down, the AVIN should not be powered down
before the PVIN. Tying PVIN and AVIN or all
three pins (AVIN, PVIN, ENABLE) together
during power up or power down meets these
requirements.
Pre-Bias Start-up
The EP53A7xQI does not support startup into
a pre-biased condition. Be sure the output
capacitors are not charged or the output of the
EP53A7xQI is not pre-biased when the
EP53A7xQI is first enabled.
Input Filter C apacitor
The input filter capacitor requirement is a
4.7µF 0402 or 0603 low ES R MLCC c apac itor .
Output Filter Capacitor
The output filter capacitor requirement is a
minimum of 10µF 0805 MLCC. Ripple
performance can be improved by using 2x10µF
0603 or 2x10µF 0805 MLC C c apac itors .
The maximum output filter capacitance next to
the output pins of the device is 60µF low ESR
MLCC capacitance. VOUT has to be sensed at
the last output filter capacitor next to the
EP53A7xQI.
Additional bulk capacitance for decoupling and
VS2 VS1 VS0 VOUT
0 0 0 3.3
0 0 1 3.0
0 1 0 2.9
0 1 1 2.6
1 0 0 2.5
1 0 1 2.2
1 1 0 2.1
1 1 1 1.8
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01543 October 11, 2013 Rev D
EP53A7LQI/EP53A7HQI
bypass can be placed at the load as long as
there is sufficient separation between the VOUT
Sense point and the bulk capacitance. The
separation provides an inductance that isolates
the c ontrol loop from the bulk c apac itanc e.
NOTE: Excess total capacitance on the output
(Output Filter + Bulk) can cause an over-
current condition at startup. Refer to the
section on Soft-Start for the maximum total
c apac itanc e on the output.
NOTE: The Input and Output capacitors must
use a X5R or X7R or equivalent dielectric
formulation. Y5V or equivalent dielectric
formulations lose capacitance with frequency,
bias, and temperature and are not suitable for
switch-mode DC-DC converter filter applications.
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01543 October 11, 2013 Rev D
EP53A7LQI/EP53A7HQI
Layout Recommendation
Figure 12 shows critical components and layer
1 traces of a recommended minimum footprint
EP53A7LQI/EP53A7HQI layout with ENABLE
tied to VIN. Alternate ENABLE configurations,
and other small signal pins need to be
connected and routed according to specific
customer application. Please see the Gerber
files on the Altera website
www.altera.com/enpirion for exact dimensions
and other layers. Please refer to Figure 12
while reading the layout recommendations in
this s ec tion.
Recommendation 1: Input and output filter
capacitors should be placed on the same side
of the PCB, and as close to the EP53A7QI
package as possible. They should be
connected to the device with very short and
wide traces. Do not use thermal reliefs or
spokes when connecting the capacitor pads to
the respective nodes. The +V and GND traces
between the capacitors and the EP53A7QI
should be as close to each other as possible
so that the gap between the two nodes is
m inim iz ed, even under the c apac itors .
Recommendation 2: Input and output grounds
are separated until they connect at the PGND
pins. The separation shown on Figure 12
between the input and output GND circuits
helps minimize noise coupling between the
c onverter input and output s w itc hing loops .
Recommendation 3: The system ground
plane should be the first layer immediately
below the surface layer. This ground plane
should be continuous and un-interrupted below
the converter and the input/output capacitors.
Please see the Gerber files on the Altera
website www.altera.com/enpirion.
Figure 12:T op PCB L ay er Critical Compon ent s
and C opper for Min im u m Foot pr i n t
Recommendation 4: Multiple small vias
should be used to connect the ground traces
under the device to the system ground plane
on another layer for heat dissipation. The drill
diameter of the vias should be 0.33mm, and
the vias m us t have at leas t 1 oz . c opper plating
on the inside wall, making the finished hole
size around 0.20-0.26mm. Do not use thermal
reliefs or spokes to connect the vias to the
ground plane. It is preferred to put these vias
under the capacitors along the edge of the
GND copper closest to the +V copper. Please
see Figure 12. These vias connect the
input/output filter capacitors to the GND plane
and help reduce parasitic inductances in the
input and output current loops. If the vias
cannot be placed under CIN and COUT, then put
them just outside the capacitors along the
GND. Do not use thermal reliefs or spokes to
c onnec t thes e vias to the gr ound plane.
Recommendation 5: AVIN is the power supply
for the internal small-signal control circuits. It
should be connected to the input voltage at a
quiet point. In Figure 12 this connection is
made with RAVIN at the input capacitor close
to the VIN connection.
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01543 October 11, 2013 Rev D
EP53A7LQI/EP53A7HQI
Package and Mechanical
Figure 14: EP53A7xQI P ackage Dim ensi ons
Contact Information
Altera Corporation
101 Innovation D rive
San Jos e, C A 95134
Phone: 408-544-7000
www.altera.com
© 2013 Alter a C or por ati on —C onf id en tial. All r igh ts reserved. ALTERA, AR RIA, C YCLONE, ENPIRION , HAR DC OPY, MAX, MEGACOR E , N IOS,
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01543 October 11, 2013 Rev D
