DSPIC30F6014A-30I/PT - Microchip Technology

dsPIC30F6011A/

6012A/6013A/6014A

The dsPIC30F6011A/6012A/6013A/6014A (Rev. B0)

sample s that you hav e received were found to co nform

to the specifications and functionality described in the

following documents:

• DS70157 – “dsPIC30F/33F Programmer’s

Reference Manual”

• DS70143 –

“dsPIC30F6011A/6012A/6013A/6014A Data

Sheet”

• DS70046 – “ds PIC30F F amily Re fere nc e Ma nua l”

The exceptions to the specifications in the documents

listed above are described in this section. The specific

devices for which these exceptions are described are

listed bel ow :

• dsPIC30F6011A

• dsPIC30F6012A

• dsPIC30F6013A

• dsPIC30F6014A

dsPIC30F601XA Rev. B0 silicon is identified by

performing a “Reset and Connect” operation to the

device using MPLAB® ICD 2 within the MPLAB IDE.

The f ollowing text is then visibl e under the MPLAB ICD 2

section in the output window within MPLAB IDE:

MPLAB ICD 2 Ready

Connecting to MPLAB ICD 2

...Connected

Setting Vdd source to target

Target Device dsPIC30F6014A found,

revision = Rev 0x1040

...Reading ICD Product ID

Running ICD Self Test

...Passed

MPLAB ICD 2 Ready

The errata described in this section will be addressed

in future revisions of dsPIC30F6011A,

dsPIC30F6012A, dsPIC30F6013A and

dsPIC30F6014A silicon.

Silicon Errata Summary

The following list summarizes the errata described in

further detail through the remainder of this document:

1. Decimal Adju st Instruction

The Decimal Adjust instruction, DAW.b, may

improperly clear the Carry bit, C (SR<0>).

2. Output Compare Module in PWM Mode

Output co mpare will produ ce a glitch when loa ding

0% duty cycle in PWM mode. It will also miss the

next compare after the glitch.

3. Sleep Mode

Execution of the Sleep instruction (PWRSAV #0)

may cause incorrect program operation after the

device wakes up from Sleep. The current

consumption during Sleep may also increase

beyond the specifications listed in the device data

sheet.

4. I2C™ Module

The I2C module loses incoming data bytes when

operating as an I2C slave.

5. I/O Port – Port Pin Multiplexed with IC1

The Port I/O pin multiplex ed with the Input Ca pture

1 (IC1) function cannot be used as a digital input

pin when the UART auto-baud feature is enabled.

6. I2C Module: 10-bit Addressing Mode

When the I2C module is configured for 10-bit

addressing using the same address bits (A10 and

A9) as othe r I2C devic es, the A10 and A9 bit s ma y

not work as expected.

7. Timer Module

Clock switching prevents the device from waking

up from Sleep.

dsPIC30F6011A/6012A/6013A/6014A Rev. B0 Silicon Errata

dsPIC30F6011A/6012A/6013A/6014A

8. PLL Lock Status Bit

The PLL LOCK Status bit (OSCCON<5>) can

occasionally get cleared and generate an

oscillator failure trap even when the PLL is still

locked and functioning correctly.

9. PSV Operat ion s

An address error trap occurs in certain addressing

modes when accessing the first four bytes of any

PSV page.

10. I2C Module: 10- bit Addressing Mode

The 10-bit slave does not set the RBF flag or load

the I2CxRCV register, on address match if the

Least S i gni fi c an t bi ts of th e a d dre ss a re t h e sa me

as the 7-bit reserved addresses.

11. I2C Module: 10-bit Addressing Mode

When the I2C module is configured as a 10-bit

slave with an address of 0x102, the I2CxRCV

rather than 0x02.

12. I2C Mo du le

When t he I2C m odule is enab led, the dsPI C® DSC

device generates a glitch on the SDA and SCL

pins, causing a false communication start in a

single-master configuration or a bus collision in a

multi-master configuration.

The following sections describe the errata and work

around to these errata, where they may apply.

1. Module: CPU – DAW.b Instruction

The Decimal Adjust instruction, DAW.b, may

improperly clear the Carry bit, C (SR<0>), when

executed.

Work around

Check the state of the Carry bit prior to executing

the DAW.b instructi on. If the Carry bit is set, set the

Carry bit again after executing the DAW.b

instruction. Example 1 shows how the application

should pr ocess the Carry bit during a BCD addition

operation.

EXAMP LE 1: CHEC K CARR Y BIT BE FOR E

DAW.b

2. Module: Output Compare in PWM Mode

If the desired duty cycle is ‘0’ (OCxRS = 0), the

module will generate a high level glitch of 1 TCY.

Additionally, on the next cycle after the glitch, the

OC pin does not go high, or, in other words, it

misses the next compare for any value written on

OCxRS.

Work around

There are two possible solutions to this problem:

1. Load a value greater than ‘0’ to the OCxRS

case, no 0% duty cycle is achievable.

2. If the application requires 0% duty cycles, the

output compare module can be disabled for

0% duty cycles, and re-enabled for non-zero

percent duty cycles.

.include “p30fxxxx.inc”

.......

mov.b #0x80, w0 ;First BCD number

mov.b #0x80, w1 ;Second BCD number

add.b w0, w1, w2 ;Perform addition

bra NC, L0 ;If C set go to L0

daw.b w2 ;If not,do DAW and

bset.b SR, #C ;set the carry bit

bra L1 ;and exit

L0:daw.b w2

L1: ....

dsPIC30F6011A/6012A/6013A/6014A

3. Module: Sleep Mode

Execution of the Sleep instruction (PWRSAV #0)

may cause incorrect program operation after the

device wakes up from Sleep. The current

consumption during Sleep may also increase

bey ond th e s pe ci f ic at i ons lis te d i n t h e d ev ic e d ata

sheet.

Work arounds

To avoid thi s iss ue, any of the follow ing th ree work

arounds can be implemented, depending on the

application requirements.

Work around 1:

Ensure that the PWRSAV #0 instructi on is lo cated

at the end of the last row of Program Flash

Memory available on the target device and fill the

remainder of the row with NOP instructions.

This can be accomplished by replacing all

occurrences of the PWRSAV #0 instruction with a

function call to a suitably aligned subroutine. The

address( ) attribute provided by the MPLAB

ASM30 as sembler can be u tilized to c orrectly align

the instructions in the subroutine. For an

application written in C, the function call would be

GotoSleep( ), whil e for an as sembly la nguage

application, the function call would be

CALL _GotoSleep.

The Address Error Trap Service Routine software

can then replace the invalid return address saved

on the stack with the address of the instruction

immediately following the _GotoSleep or

GotoSleep( ) function call. This ensures that

the device continues executing the correct code

sequence after waking up from Sleep mode.

Example 2 demonstrates the work around

described above, as it would apply to a

dsPIC30F6014A device.

EXAMPLE 2:

Work around 2:

; ----------------------------------------------------------------------------------------------

.global __reset

.global _main

.global _GotoSleep

.global __AddressError

.global __INT1Interrupt

; ----------------------------------------------------------------------------------------------

.section *, code

_main:

BSET INTCON2, #INT1EP ; Set up INT pins to detect falling edge

BCLR IFS1, #INT1IF ; Clear interrupt pin interrupt flag bits

BSET IEC1, #INT1IE ; Enable ISR processing for INT pins

CALL _GotoSleep ; Call function to enter SLEEP mode

_continue:

BRA _continue

; ----------------------------------------------------------------------------------------------

; Address Error Trap

__AddressError:

BCLR INTCON1, #ADDRERR

; Set program memory return address to _continue

POP.D W0

MOV.B #tblpage (_continue), W1

MOV #tbloffset (_continue), W0

PUSH.D W0

RETFIE

; ----------------------------------------------------------------------------------------------

__INT1Interrupt:

BCLR IFS1, #INT1IF ; Ensure flag is reset

RETFIE ; Return from Interrupt Service Routine

; ----------------------------------------------------------------------------------------------

.section *, code, address (0x17FC0)

_GotoSleep:

; fill remainder of the last row with NOP instructions

.rept 31

NOP

.endr

; Place SLEEP instruction in the last word of program memory

PWRSAV #0

dsPIC30F6011A/6012A/6013A/6014A

Instead of executing a PWRSAV #0 instruction to

put the device into Sleep mode, perform a clock

switch to the 512 kHz Low-Power RC (LPRC)

Oscillator with a 64:1 postscaler mode. This

enables the device to operate at 0.002 MIPS,

thereby significantly reducing the current

consumption of the device. Similarly, instead of

using an interrupt to wake-up the device from

Sleep mode, perform an other clock sw it ch bac k to

the original oscillator source to resume normal

operation. Depending on the device, refer to

Section 7. “Oscillator” (DS70054) or Section

29. “Oscillator” (DS70268) in the “dsPIC30F

Family Reference Manual” (DS70046) for more

details on performing a clock switch operation.

Work around 3:

Instead of executing a PWRSAV #0 instruction to

put the device into Sleep mode, perform a clock

switch to the 32 kHz Low-Power (LP) Oscillator

with a 64:1 postscaler mode. This enables the

device to operate at 0.000125 MIPS, thereby

significantly reducing the current consumption of

the device. Similarly, instead of using an interrupt

to wake-up the device from Sleep mode, perform

another clock switch back to the original oscillator

source to res ume normal op eration. Depen ding on

the device, refer to Section 7. “Oscillator”

(DS70054) or Section 29. “Oscillator”

(DS70268) in the “dsPIC30F Family Reference

Manual” (DS 70046) for more de tails on perform ing

a clock switch operation.

Note: The above work around is recommended

for users for whom application hardware

changes are not possible. Note: The above work around is recommended

for users for whom application hardware

changes are possible, and also for users

whose application hardware already

includes a 32 kHz LP Oscillator crystal.

dsPIC30F6011A/6012A/6013A/6014A

4. Module: I2C

When the I2C module is configured as a slave,

either in single-master or multi-master mode, the

I2C receiver buffer is filled whether a valid slave

address is detected or not. Therefore, an I2C

receiver overflow condition occurs and this

condition is indicated by the I2COV flag in the

I2CSTAT register.

This ov erflow conditio n inhibit s the ability to set the

I2C receive interrupt flag (SI2CF) when the last

valid data byte is received. Therefore, the I2C

slave Interrupt Service Routine (ISR) is not called

and the I2C receiver buffer is not read prior

receiving the next data byte .

Work arounds

To avoid this i ssue, either of the following two work

arounds can be implemented, depending on the

application requirements.

Work around 1:

For appli ca tions in wh ich the I2C receiver in terru pt

is not required, the following procedure can be

used to receive valid data bytes:

1. Wait until the RBF flag is set.

2. Poll the I2C receiver interrupt SI2CIF flag.

3. If SI2CF is not set in the corresponding

Interrupt Flag Status (IFSx) register, a valid

address or da t a byte h as no t been re ceive d for

the current slave. Execute a dummy read of

the I2C receiver buffer, I2CRCV; this will cl ear

the RBF flag. Go back to step 1 until SI2CF is

set and then continue to Step 4.

4. If the SI2CF is set in the corresponding

Interrupt Flag Status (IFSx) register, valid data

has been received. Check the D_A flag to

verify that an address or a data byte has been

received.

5. R ead the I 2CRCV b uffer to rec over va lid data

bytes. This will also clear the RBF flag.

6. Clear the I2C receiver interrupt flag SI2CF.

7. Go back to step 1 to continue receiving

incoming data bytes.

Work around 2:

Use this work around for applications in which the

I2C receiver interrupt is required. Assuming that

the RBF and the I2COV flags in the I2CSTAT

the I2C bus (i.e., between master and other

slaves); the following procedure can be used to

receive valid data bytes:

1. When a valid slave address byte is detected,

SI2CF bit is set and the I2C slave interrupt

service routine is calle d; however , the RBF and

I2COV bits are already set due to data

transfers between other I2C nodes.

2. Check the status of the D_A flag and the

I2COV flag in the I2CSTAT register when

executing the I2C slave service routine.

3. If the D_A flag is cleared and the I2COV flag

are se t, an i nvalid data byte wa s recei ved but a

valid add res s by te was rec ei ved . The ov erfl ow

condition occurred because the I2C receive

buffer was overflowing with previous I2C data

transfers between other I2C nodes. This

condition only occurs after a valid slave

address was detected.

4. Clear the I2COV flag and perform a dummy

read of the I2C receiver buffer, I2CRCV, to

clear the RBF bit and recov er the valid a ddress

byte. This action will also avoid the loss of the

next data byte due to an overflow condition.

5. Verify that the recovered address byte

matche s the current slave addres s byte. If they

match, the next data to be received is a valid

data by te.

6. If the D_A fl ag and the I2CO V flag are both se t,

a valid data byte was received and a previous

valid dat a byte was lost. It will be neces sa ry to

code for handling this overflow condition.

5. Module: I/O Port – Port Pin Multiplexed

with IC1

If the user application enables the auto-baud

feature in the UART module, the I/O pin

multiplexed with the IC1 (Input Capture) pin cannot

be used as a digital input.

Work around

None.

dsPIC30F6011A/6012A/6013A/6014A

6. Module: I2C

If there are two I2C devices on the bus, one of

them is acting as t he Master receiv er and the oth er

as the Sl ave transmitter. If both devic es are confi g-

ured for 10-bit addressing mode, and have the

same value in the A10 and A9 bits of their

addresses, then when the Slave select address is

sent from the Master, both the Master and Slave

acknowledge it. When the Master sends out the

read operation, both the Master and the Slave

enter into Read mode and both of them transmit

the data. The resultant data will be the ANDing of

the two transmissions.

Work around

In all I2C devices, the addresses as well as bits

A10 and A9 should be different.

7. Module: Timer

When the timer is being o perated in Asy nchronous

mode using the secondary oscillator (32.768 kHz)

and the device is put into Sleep mode, a clock

switch to any other oscillator mode before putting

the devi ce to Sleep prev ents the t imer from wakin g

the device from Sleep.

Work around

Do not clock switch to any other oscillator mode if

the timer is being used in Asynchronous mode

using the secondary oscillator (32.768 kHz).

8. Module: PLL Lock Status Bit

The PLL LOCK Status bit (OSCCON<5>) can

occasionally get cleared and generate an

oscillator failure trap even when the PLL is still

locked and functioning correctly.

Work around

The user application must include an oscillator

failure trap service routine. In the trap service

routine, firs t inspe ct the statu s of the Clock Failu re

Status bit (OSCCON<3>). If this bit is clear, return

from the trap service routine immediately and

continue program execution.

9. Module: PSV O p er ations

An addre ss e rror trap o cc urs i n certain addressin g

modes when accessing the first four bytes of an

PSV page. This only occurs when using the

following addressing modes:

•MOV.D

• Register Indirect Addressing (word or byte

mode) with pre/ pos t-de cre me nt

Work around

Do not perform PSV accesses to any of the first

four byt es using the a bove addres sing modes . For

applications using the C language, MPLAB C30

version 3.11 or higher, provides the following

command-line switch that implements a work

around for the erratum.

-merrata=psv_trap

Refer to the readme.txt file in the MPLAB C30

v3.11 tool suite for further details.

10. Module: I2C

In 10-bit Addressing mode, some address

matche s d on' t s et the RB F fla g or load t he r eceive

matches the reserved addresses. In particular,

these include all addresses with the form

XX0000XXXX and XX1111XXXX, with the

following exceptions:

• 001111000X

• 011111001X

• 101111010X

• 111111011X

Work around

Ensure that the lower address byte in 10-bit

Addressing mode does not match any 7-bit

reserved addresses.

11. Module: I2C

When the I2C module is configured as a 10-bit

slave with and address of 0x102, the I2CxRCV

rather than 0x02; however, the module

acknowledges both address bytes.

Work around

None.

dsPIC30F6011A/6012A/6013A/6014A

12. Module: I2C

When the I2C module is enabled by setting the

I2CEN bit in the I2CCON register, the dsPIC DSC

device generates a glitch on the SDA and SCL

pins. This glitch falsely indicates “Communication

Start” to all device s o n t he I2C bus , a nd c an c aus e

a bus collision in a multi-master configuration.

Additionally, when the I2CEN bit is set, the S and

P bits of the I2C module a re set to va lues ‘1’ and

‘0’, respectively, which indicate a “Communication

Start” condition.

Work arounds

To avoid this i ssue, either of the following two work

arounds can be implemented, depending on the

application requirements.

Work around 1:

In a single-master environment, add a delay

between enabling the I2C module and the first data

transmission. The delay should be equal to or

greater than the time it takes to transmit two data

bits.

In the mult i-mas ter confi gur ation, in additi on to the

delay, all other I2C masters should be synchro-

niz ed and wa it fo r the I2C modu le to be in itia lized

before initiating any kind of communication.

Work around 2:

In dsPIC DSC devices in which the I2C module is

multiplexed with other modules that have

precedence in the use of the pin, it is possible to

avoid this glitch by enabling the higher priority

module before enabling the I2C module.

Use the following procedure to implement this

work around:

1. Enable the higher priority peripheral module

that is mu ltiple xe d on the sa me pin s as the I2C

module.

2. Set up and enable the I2C module.

Disable the higher priority peripheral module that

was enabled in step 1.

Note: W ork a r oun d 2 work s only for dev ic es th at

share the SDA and SCL pins with another

peripheral that has a higher precedence

over the port latc h, such as the UAR T. The

priori ty is shown i n the pin diagram loc ated

in the data sheet. For example, if the SD A

and SCL pins are shared with the UART

and SPI pins, and the UART has higher

precedence on the port latch pin.

dsPIC30F6011A/6012A/6013A/6014A

APPENDIX A: REVISION HISTORY

Revision A (2/2007)

Original version of this document.

Revision B (9/2007)

Added silicon issue 3 (Sleep Mode).

Revision C (12/2007)

Added silicon issues 4 and 5 (I2C), and 6 (I/O Port –

Port Pin Multiplexed with IC1).

Revision D (5/2008)

Added silicon issues 7 and 8 (I2C), and 9 (Timer) .

Revision E (9/2008)

Replaced issues 5 and 7 (I2C) with issue 12 (I2C).

Added silicon issues 8 (PLL Lock Status Bit), 9 (PSV

Operations) and 10-12 (I2C).

Information contained in this publication regarding device

applications a nd the lik e is provid ed only for your convenien ce

and may be supers ed ed by u pdates. It is y our responsibil it y to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTA RT, rfPIC, SmartShunt and UNI/O are registered

trademarks of Microchip Technology Incorporat ed in the

U.S.A. and other countries.

FilterLab, Linear Active Thermistor, MXDEV, MXLAB,

SEEV AL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, In-Circuit Serial

Prog ra m ming , IC S P, IC EPIC , Mi n d i , M iW i , M PASM , MPLAB

Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,

PICDEM.net, PICtail , PIC32 logo, PowerCal, PowerInfo,

PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total

Endurance, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that it s family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

AMERICAS

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Chicago

Itasc a , IL

Tel: 630-285-0071

Fax: 630-285-0075

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

Los A n ge les

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

ASIA/PACIFIC

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

ASIA/PACIFIC

India - Bangalore

Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Korea - Seoul

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

Taiwan - Kaohs iung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

EUROPE

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Cop e nha gen

Tel: 45-4450-2828

Fax: 45-4485-2829

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-14 4-44

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08 -91

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921- 5820

Worldwide Sales and Service

01/02/08