EM78870 8-Bit Microcontroller Product Specification DOC. VERSION 2.3 ELAN MICROELECTRONICS CORP. August 2004[CY1] Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation. Copyright (c) 2005 by ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan The contents of in this specification are subject to change without notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible to any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising out of the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESS WRITTEN PERMISSION OF ELAN MICROELECTRONICS. ELAN MICROELECTRONICS CORPORATION Headquarters: Hong Kong: USA: No. 12, Innovation Road 1 Science-based Industrial Park Hsinchu, Taiwan 308 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Elan (HK) Microelectronics Corporation, Ltd. Elan Information Technology Group Rm. 1005B, 10/F Empire Centre 68 Mody Road, Tsimshatsui Kowloon , HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 elanhk@emc.com.hk 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 USA Tel: +1 408 366-8223 Fax: +1 408 366-8220 Europe: Shenzhen: Shanghai: Elan Microelectronics Corp. (Europe) Elan Microelectronics Shenzhen, Ltd. Elan Microelectronics Shanghai Corporation, Ltd. Siewerdtstrasse 105 8050 Zurich, SWITZERLAND Tel:+41 43 299-4060 Fax:+41 43 299-4079 http://www.elan-europe.com SSMEC Bldg., 3F, Gaoxin S. Ave. Shenzhen Hi-Tech Industrial Park Shenzhen, Guandong, CHINA Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 23/Bldg. #115 Lane 572, Bibo Road Zhangjiang Hi-Tech Park Shanghai, CHINA Tel: +86 021 5080-3866 Fax: +86 021 5080-4600 Contents Contents 1 2 3 4 5 6 7 General Description ...................................................................................... 1 Feature ........................................................................................................... 1 2.1 CPU.................................................................................................................... 1 2.2 Programmable Tone Generators ........................................................................ 2 2.3 LCD (8x80, 9x80, 16x80, 24x72)........................................................................ 2 2.4 Package type...................................................................................................... 2 Application ..................................................................................................... 3 Pin Configuration .......................................................................................... 4 Functional Block Diagram ............................................................................ 6 Pin Descriptions ............................................................................................ 7 Functional Descriptions................................................................................ 8 7.1 Operational Registers......................................................................................... 8 7.2 Operational Register Table List .......................................................................... 9 7.2.1 7.3 Paged registers (R PAGE0, RPAGE1, IOC PAGE0, IOC PAGE1) R0~R4 and RF are unpaged registers..........................................................................................9 Operational Register Detail Description ........................................................... 15 7.3.1 R0 (Indirect Addressing Register) .....................................................................15 7.3.2 R1 (TCC) ...........................................................................................................16 7.3.3 R2 (Program Counter).......................................................................................16 7.3.4 R3 (Status Register) ..........................................................................................17 7.3.5 R4 (RAM selection for common registers R20 ~ R3F, SPI control) ..................17 7.3.6 R5 (PORT5 I/O data, Program page selection, SPI data).................................22 7.3.7 R6 (PORT6 I/O data).........................................................................................23 7.3.8 R7 (PORT7 I/O data).........................................................................................23 7.3.9 R8 (PORT8 I/O data).........................................................................................24 7.3.10 R9 (PORT9 I/O data, extra LCD address bit)....................................................24 7.3.11 RA (CPU power saving, PLL, Main clock selection, Watchdog timer, LCD address).........................................................................................................................24 7.3.12 RB (PORTB I/O data, LCD data).......................................................................27 7.3.13 RC (PORTC I/O data, Data RAM data).............................................................28 7.3.14 RD (Comparator control, Data RAM address(0 ~ 7))........................................29 7.3.15 RE (Key sacn, LCD control, Data RAM addresss(8 ~ 10)) ...............................31 7.3.16 R10~R3F (General Purpose Register)..............................................................38 7.4 Special Purpose Registers ............................................................................... 38 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 A (Accumulator).................................................................................................38 CONT (Control Register)...................................................................................38 IOC5 (PORT5 I/O control, PORT switch, Key tone,LCD bias)..........................40 IOC6 (PORT6 I/O control, PORT switch, LCD driving control) .........................45 IOC7 (PORT7 I/O control, Key strobe(8~15)) ...................................................46 Product Specification (V2.3) 08.19.2004 * iii Contents 7.4.6 7.4.7 7.4.8 7.4.9 7.4.10 7.4.11 7.4.12 7.4.13 IOC8 (PORT8 I/O control, , Key strobe(16~23)) ...............................................46 PORT9 I/O control)............................................................................................47 IOCA (CN1's and CN2's clock and scaling, PORT7 pull high control)..............47 IOCB (PORTB I/O control, PORT6 pull high control)........................................49 IOCC (PORTC I/O control, TONE1 control) ......................................................49 IOCD (Counter1 data, TONE2 control) .............................................................51 IOCE (Counter2 data, Comparator and OP control) .........................................51 IOCF (Interrupt Mask Register).........................................................................52 7.5 I/O Port ............................................................................................................. 53 7.6 RESET ............................................................................................................. 53 7.7 wake-up............................................................................................................ 54 7.8 Interrupt ............................................................................................................ 55 7.9 Instruction Set .................................................................................................. 55 7.10 CODE Option Register ..................................................................................... 57 8 9 10 11 Absolute Operation Maximum Ratings...................................................... 58 DC Electrical Characteristic........................................................................ 58 AC Electrical Characteristic........................................................................ 59 Timing Diagrams ......................................................................................... 60 APPENDIX A. User Application Note ................................................................................. 61 B. Function control list .................................................................................... 62 C. Application Circuit....................................................................................... 63 iv * Product Specification (V2.3) 08.19.2004 Contents Specification Revision History Doc. Version Revision Description Date 2.3 Remove Idle mode 2004/8/19 Product Specification (V2.3) 08.19.2004 *v EM78870 8-Bit Micorcontroller 1 General Description The EM78870 is an 8-bit RISC microprocessor with low-power, high-speed CMOS technology. Integrated onto a single chip are on-chip watchdog timer (WDT), RAM, ROM, programmable real-time clock /counter, internal interrupt, power-down mode, LCD driver, build-in KEY TONE clock generation, Programming Tone generators, Serial Peripheral Interface(SPI), comparator and tri-state I/O. The EM78870 provides a single-chip solution to designing a message display. 2 Feature 2.1 CPU Operating voltage range : 2.2V~5.5V(Normal mode), 2.0V~5.5V(Green mode) Thirteen 32K on-chip Program ROM Eight 2.5Kon-chip data RAM 144-byte working register Up to 51 bi-directional tri-state I/O ports (32 shared with LCD Segment pins) IO with internal Pull high, wake-up and interrupt functions STACK: 32 stack levels for subroutine nesting TCC: 8-bit real time clock/counter (TCC) with 8-bit prescaler COUNTER1: 8-bit counter with 8-bit prescaler which can also be an interrupt source COUNTER2: 8-bit counter with 8-bit prescaler which can also be an interrupt source Watch Dog : on-chip watchdog timer CPU modes: Mode CPU status Main clock 32.768kHz clock status Sleep mode Green mode Normal mode Off On On Off Off On Off On On 12 interrupt sources : 8 external , 4 internal Key Scan : Port key scan function scans up to 64 (16x4) keys Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) *1 EM78870 8-Bit Micorcontroller Sub-clock: 32.768kHz crystal Main-clock: 3.5826MHz multiplied by 0.25, 0.5, 1 or 3 generated by the internal PLL Key tone output (shared with IO) : 4kHz, 2kHz, 1kHz Comparator: 3-channel comparators, internal (16 levels) or external reference voltage (shared with IO) Serial Peripheral Interface (SPI) : Interrupt flag (when the read buffer is full), programmable baud rates, and three-wire synchronous communication. (shared with IO) 2.2 Programmable Tone Generators Operating voltage range: 2.2V5.5V Two programmable generators: Tone1 and Tone2 Independent single tone generation for Tone1 and Tone2 Mixed dual tone generation by Tone1 and Tone2 (differs by 2dB) 2.3 LCD (8x80, 9x80, 16x80, 24x72) Maximum common driver pins : 16/24 Maximum segment driver pins : 80(SEG0..SEG79)/72(SEG8..SEG79) Shared COM16 ~ COM23 pins with SEG0 ~ SEG7 pins 1/4 bias for 8, 9 and 16 common mode and 1/5 bias for 24 common mode 1/8, 1/9, 1/16, 1/24 duty 16 levels of LCD contrast control (software) Internal resistor circuit for LCD bias Internal voltage follower for better display 2.4 Package type 128-pin QFP : EM78870AQ (POVD disabled), EM78870BQ (POVD enabled), EM78P870H 130-pin die 2* Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller 3 Application Cordless phones or any telephone product where a large LCD is needed. Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) *3 EM78870 8-Bit Micorcontroller Pin Configuration COM 20/SEG4 COM 22/SEG6 COM 21/SEG5 COM 23/SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 120 119 118 116 117 115 114 123 112 111 108 109 110 107 COM 19/SEG3 121 105 106 COM 18/SEG2 123 SEG17 SEG16 COM 17/SEG1 124 SEG15 COM 16/SEG0 COM 15 125 SEG14 COM 14 127 SEG13 COM 13 128 122 COM 12 COM 11 126 COM 10 SEG31 VC1 XIN 15 90 SEG32 16 89 SEG33 XOUT VDD 17 88 SEG34 87 SEG35 AVDD 18 18 86 SEG36 PLLC 19 85 SEG37 TONE 20 88 SEG38 AVSS GND 21 83 SEG39 21 22 82 SEG40 81 SEG41 23 80 SEG42 24 79 SEG43 P71/INT0 25 78 SEG44 P72/INT0 26 77 SEG45 P73/INT0 27 76 SEG46 P74/INT1 28 75 SEG47 P75/INT1 29 74 SEG48/PB0 P76/INT1 30 73 SEG49/PB1 P77/INT2 P60/SCK 31 72 SEG50/PB2 32 71 SEG51/PB3 P61/SDO 33 70 SEG52/PB4 P62/SDI 34 69 SEG53/PB5 P63/CM P1 35 68 SEG54/PB6 P64/CM P2 P65/CM P3 36 67 SEG55/PB7 37 66 SEG56/PC0 P66 38 65 SEG57/PC1 P67/KTONE 39 64 SEG58/PC2 SEG78/P96 P57 SEG79/P97 TEST /RESET P70/INT0 63 91 SEG59/PC3 14 61 62 SEG30 VC2 60 92 59 13 SEG62/PC6 SEG61/PC5 SEG60/PC4 SEG29 VC3 58 93 57 12 SEG64/P80 SEG63/PC7 SEG28 VC4 56 94 SEG65/P81 11 55 SEG27 VC5 SEG66/P82 95 54 10 SEG67/P83 SEG26 COM 0 53 96 SEG68/P84 9 52 SEG25 COM 1 SEG69/P85 97 51 8 SEG70/P86 SEG24 COM 2 50 98 SEG71/P87 7 49 COM 3 SEG72/P90 6 48 SEG22 COM 4 100 99 SEG73/P91 5 47 SEG21 COM 5 SEG74/P92 101 46 4 SEG75/P93 SEG20 COM 6 45 102 SEG76/P94 3 SEG77/P95 SEG19 COM 7 43 44 SEG18 103 40 104 2 41 42 1 COM 8 P56 COM 9 P55 4 SEG23 Fig.1.1 Pin assignment (128-pin QFP ) 4* Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller COM 17/SEG1 COM 16/SEG0 COM 18/SEG2 COM 19/SEG3 COM 20/SEG4 COM 21/SEG5 COM 22/SEG6 COM 23/SEG7 SEG9 SEG8 SEG10 SEG11 SEG12 SEG13 126 125 123 124 122 121 120 119 118 117 115 116 114 113 112 110 111 107 COM 15 127 108 109 COM 14 129 SEG17 SEG16 SEG15 COM 13 130 SEG14 COM 12 COM 11 128 COM 10 106 SEG18 COM 9 1 105 SEG19 COM 8 2 104 SEG20 COM 7 3 103 SEG21 COM 6 4 102 SEG22 COM 5 5 SEG23 COM 4 6 101 100 COM 3 7 99 SEG25 COM 2 8 98 SEG26 COM 1 9 97 SEG27 COM 0 10 96 SEG28 VC5 11 95 SEG29 VC4 12 94 SEG30 VC3 13 93 SEG31 VC2 14 92 SEG32 VC1 XIN 15 91 SEG33 16 90 SEG34 XOUT VDD 17 89 SEG35 88 SEG36 AVDD 18 18 87 SEG37 PLLC 19 86 SEG38 TONE 20 85 SEG39 NC 21 84 SEG40 NC 22 83 AVSS 82 SEG41 SEG42 GND 23 23 81 SEG43 TEST 24 80 SEG44 /RESET P70/INT0 25 79 SEG45 26 78 SEG46 P71/INT0 P72/INT0 27 77 SEG47 28 76 SEG48/PB0 P73/INT0 29 75 P74/INT1 30 74 SEG49/PB1 SEG50/PB2 P75/INT1 31 73 SEG51/PB3 P76/INT1 32 72 SEG52/PB4 P77/INT2 P60/SCK 33 71 SEG53/PB5 34 70 SEG54/PB6 P61/SDO 35 69 SEG55/PB7 P62/SDI 36 68 SEG56/PC0 SEG24 SEG59/PC3 P66 40 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 P57 SEG79/P97 SEG78/P96 SEG77/P95 SEG76/P94 SEG75/P93 SEG74/P92 SEG73/P91 SEG72/P90 SEG71/P87 SEG70/P86 SEG69/P85 SEG68/P84 SEG67/P83 SEG66/P82 SEG65/P81 SEG64/P80 SEG63/PC7 SEG62/PC6 SEG61/PC5 SEG60/PC4 43 44 65 42 SEG58/PC2 39 P56 SEG57/PC1 66 41 67 38 P55 37 P67/KTONE P63/CM P1 P64/CM P2 P65/CM P3 Fig.1.2 Pin assignment (130-pin die ) Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) *5 EM78870 8-Bit Micorcontroller 5 Functional Block Diagram CPU DATA RAM CONTROL REGISTER TIMING CONTROL LCD LCD DRIVER TIMER TCC COUNTER 1 COUNTER 2 WDT IO PORT I/O KEY TONE COMPARATOR SERIAL I/O PROG. TONE GEN. PROGRAM ROM Fig.2 Block diagram1 Xin Xout PLLC ROM W DT timer Oscillator timing control STACK R2 prescalar R1(TCC) GENERAL RAM Control sleep and wake-up on I/O port Interruption control Instruction register ALU R3 R5 Instruction decoder R4 ACC DATA & CONTROL BUS DATA RAM KEY TONE PROG. TONE GEN. COMPARATOR SERIAL I/O PORT5 IOC5 R5 P55~P57 PORT6 PORT7 IOC7 R7 IOC6 R6 P60~P67 P70~P77 PORT8 PORT9 PORTB IOC8 R8 IOC9 R9 IOCB RB P80~P87 P90~P97 PB0~PB7 PORTC IOCC RC PC0~PC7 Fig.3 Block diagram2 6* Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller 6 Pin Descriptions PIN POWER VDD AVDD GND AVSS CLOCK XIN XOUT PLLC LCD COM0..COM15 COM16..COM2 3 SEG0..SEG7 SEG8...SEG47 SEG48..SEG55 SEG56..SEG63 SEG64..SEG71 SEG72..SEG79 I/O POWER POWER I O I DESCRIPTION Digital power Analog power Digital ground Analog ground Input pin for the 32.768kHz oscillator Output pin for the 32.768kHz oscillator Phase loop lock. Connects to a capacitor (between 0.01uF and 0.1uF ) to GND. O O (SEG0..SEG7) Common driver pins for the LCD drivers COM16 to COM23 are shared with SEG0 to SEG7 O (COM16..COM23) O O (I/O : PORTB) O (I/O : PORTC) O (I/O : PORT8) O (I/O : PORT9) Segment driver pins for theLCD drivers SEG0 to SEG7 are shared with COM16 to COM23 SEG48 to SEG79 are shared with IO PORT VC1..VC5 I Reference voltage input. Each one connects to one 0.1u capacitor with GND. TONE, KTONE TONE KTONE SERIAL IO O O (PORT67) Programmable tone output pin Key tone output. Shared with PORT67 SCK IO (PORT60) SDO SDI COMPARATOR CMP1 CMP2 CMP3 IO P55 ~P57 O (PORT61) I (PORT62) Master : output pin, Slave : input pin. This pin is shared with PORT60. Output pin for serial data transfer. This pin is shared with PORT61. Input pin for receiving data. This pin is shared with PORT62. I (PORT63) I (PORT64) I (PORT65) Comparator input pins. Shared with PORT63, PORT64 and PORT65. I/O Each bit of PORT5 can be an INPUT or OUTPUT port. P60 ~P67 I/O Each bit of PORT6 can be an INPUT or OUTPUT port. Internal pull high. P70 ~ P77 I/O P80 ~ P87 I/O P90 ~ P97 I/O PB0 ~ PB7 I/O PC0 ~ PC7 I/O INT0 PORT70..73 Each bit of PORT7 can be an INPUT or OUTPUT port. Internal Pull high function. Auto key scan function. Interrupt function. Each bit of PORT8 can be an INPUT or OUTPUT port. Shared with LCD Segment signal. Each bit of PORT9 can be an INPUT or OUTPUT port. Shared with LCD Segment signal. Each bit of PORTB can be an INPUT or OUTPUT port. Shared with LCD Segment signal. Each bit of PORTC can be an INPUT or OUTPUT port. Shared with LCD Segment signal. Interrupt source which has the same interrupt flag. A falling edge signal on any pin from PORT70 to PORT73 generates an interrupt. Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) *7 EM78870 8-Bit Micorcontroller PIN 7 I/O INT1 PORT74..76 INT2 PORT77 TEST I /RESET I DESCRIPTION Interrupt source which has the same interrupt flag. A falling edge signal on any pin from PORT74 to PORT76 generates an interrupt. Interrupt source. An edge triggering signal (controlled by CONT register) on PORT77 generates an interrupt. Sets the device to test mode for testing purposes only. Connect it to GND. Reset pin. Functional Descriptions 7.1 Control Registers ADDRESS REGISTER (PAGE0) REGISTER (PAGE1) CONTROL REGISTER (PAGE0) R0 01 R1(TCC buffer) 02 R2(PC) 03 R3(STATUS ) 04 R4(RSR, BANK SELECT) R4(SPI status and control) 05 R5(PORT57.. PORT55, Program ROM PAGE) R6(PORT6) R6 (Unused) IOC5(IOC55,56,57, P8S,P9S,PBS PCS) IOC6(PORT6 IO control) IOC5(Key tone, LCD bias bias) 06 07 R7(PORT7) R7(Unused) IOC7 (PORT7 IO control) IOC7(key strobe , seg15 .. seg8) 08 R8(PORT8) R8(Unused) IOC8 (PORT8 IO control) IOC8(key strobe, seg23.. seg16) 09 R9(PORT9) R9(LCDA8) IOC9 (PORT9 IO control) 0A RA(LCD RAM address) 0B RA(CPU MODE,CLOCK, WDT control) RB(PORTB) IOCA(COUNTER1,2 prescaler and source) IOCB(PORTB IO control) R3(7) R3(5,6) R5(SPI data buffer) RB (LCD RAM data buffer) IOC6(Port s/w, LCDDV, CDAL) IOCA(PORT7 pull high) IOCB(PORT6 pull high) 0C RC(PORTC) RC(DATA RAM data buffer) IOCC(PORTC IO control) IOCC(Tone1) 0D RD(Comparator control) IOCD(COUNTER1 PRESET) IOCD(Tone2) 0E RE(Key scan , LCD control) RD(DATA RAM address address7..address0) RE(DATA RAM address address12..address8) IOCE(COUNTER2 PRESET) IOCE(Com parator ref., PORT switch) 0F RF(Interrupt flag) 10 : 1F 16-byte GENERAL REGISTERS 20 : 3F BANK0 , BANK1, BANK2 , BANK3 32X8 32X8 32x8 32x8 COMMOM REGISTERS IOCF(Interrupt control) CONTROL REGISTER (PAGE2) R3(5,6) LCD RAM R4(7,6) CONTROL REGISTER (PAGE1) 00 DATA RAM RD PAGE1 => address7..0 RA PAGE1 => address RB PAGE1 =>data IOC6(Port s/w, LCDDV, CDAL) RE PAGE1 => address12..8 RC PAGE1 =>data Fig.4 control register configuration 8* Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller 7.2 Control Register List 7.2.1 Paged registers (R PAGE0, RPAGE1, IOC PAGE0, IOC PAGE1) R0~R4 and RF are unpaged registers. 7.2.1.1 R PAGE0 Addr 00 01 02 03 Name 04 05 06 07 08 09 0A R0 R1 R2 R3 C DC Z P T IOCPAGE IOC6P1S PAGE R4 RSR0~RSR5 RB0~ RB1 R5 PAGE0 PS0~PS4 P55~P57 R6 PAGE0 P60~P67 R7 PAGE0 P70~P77 R8 PAGE0 P80~P87 R9 PAGE0 P90~P97 0C 0D 0 1 2 3 4 5 6 7 0~5 6~7 0~4 5~7 0~7 0~7 0~7 0~7 RA PAGE0 WDTEN 1 0 CLK0~CLK1 0B Bit 0 1~2 3 4~5 PLLEN 6 0 RB PAGE0 PB0~PB7 RC PAGE0 PC0~PC7 RD PAGE0 CMP_B0~CMP_B 3 CMPS0~CMPS1 CMPFLAG CMPEN 7 0~7 0~7 0~3 4~5 6 7 Function Indirect addressing register TCC Program counter Status, Page selection Carry flag Auxiliary carry flag Zero flag Power down bit Time-out bit Change IOC5 ~ IOCE to PAGE0/PAGE1 Change IOC6 PAGE1 to option-A/option-B Change R4 ~ RE to PAGE0/PAGE1 RAM selection for common registers Indirect addressing for common registers R20 ~ R3F Bank selection bits for common registers R20 ~ R3F PORT5 I/O data register, Program page selection Program page selection bits 3-bit PORT5(5~7) I/O data register PORT6 I/O data register 8-bit PORT6(0~7) I/O dada register PORT7 I/O data register 8-bit PORT7(0~7) I/O dada register PORT8 I/O data register 8-bit PORT8(0~7) I/O dada register PORT9 I/O data register 8-bit PORT9(0~7) I/O dada register CPU power saving, PLL, Main clock selection, Watchdog timer Watchdog control bit Unused Unused Main clock selection bits Power control bit for PLL. It is also a CPU mode control register Please clear this bit to 0 PORTB I/O dada register 8-bit PORTB(0~7) I/O dada register PORTC I/O dada register 8-bit PORTC(0~7) I/O dada register Comparator control Reference voltage selection of the internal bias circuit for the comparator Channel selection from CMP1 to CMP3 for the comparator Comparator output flag Enable control bit for the comparator Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) *9 EM78870 8-Bit Micorcontroller 10 * Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller Addr 0E 0F Name RE PAGE0 Bit LCDM0~LCDM1 0~1 LCD0~LCD1 KEYSCAN KEYSTRB KEYCHK 1 RF TCIF CNT1 CNT2 INT0 INT1 INT2 0 RBF 2~3 4 5 6 7 7.2.1.2 05 06 07 08 09 0A 0B 0C 0D Name R4 PAGE1 SBR0~SBR2 SCES SE SRO SPIE RBF R5 PAGE1 SPIB0~SPIB7 R9 PAGE1 0 LCDA8 RA PAGE1 LCDA0~LCDA7 RB PAGE1 LCDD0~LCDD7 RC PAGE1 RAMD0~RAMD7 RD PAGE1 RAMA0~RAMA7 0E Key scan, LCD control LCD common mode, bias selection and COM/SEG switch control LCD operation function definition Key scan function enable control bit Key strobe enable control bit Key check enable control bit Unused Interrupt status register Timer overflow interrupt flag for TCC Timer overflow interrupt flag for COUNTER1 Timer overflow interrupt flag for COUNTER2 Interrupt flag for the external INT0 pin Interrupt flag for the external INT1 pin Interrupt flag for the external INT2 pin Unused Interrupt flag when the SPI data transfer is complete R PAGE1 Addr 04 0 1 2 3 4 5 6 7 Function Bit 0~2 3 4 5 6 7 0~7 0~6 7 0~7 0~7 0~7 0~7 RE PAGE1 RAMA8~RAMA11 0 0~3 5 Function SPI control register SPI baud rate selection bits SPI clock edge selection bit SPI shift enable bit SPI read overflow bit SPI enable bit SPI read buffer full flag SPI data buffer SPI data buffer LCD address MSB bit Unused MSB of LCD address for reading from or writing to LCD RAM LCD address LCD address for reading from or writing to LCD RAM LCD data buffer LCD data buffer for reading from or writing to LCD RAM Data RAM data buffer for reading from or writing to RAM Data RAM address0 ~ address7 Data RAM address0 ~ address7 for reading from or writing to RAM Data RAM address8 ~ address11 Data RAM address8 ~ address11 for reading from or writing to RAM Unused Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) * 11 EM78870 8-Bit Micorcontroller 12 * Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller 7.2.1.3 IOC PAGE0 Addr Name 05 07 08 09 0A 0B 0C 0D 0E 0F Function IOC5 PAGE0 P8SL 0 P8SH 1 P9SL 2 Switch high nibble I/O PORT8 or LCD segment output Switch low nibble I/O PORT9 or LCD segment output P9SH 3 Switch high nibble I/O PORT9 or LCD segment output 0 4 Unused IOC55~IOC57 06 Bit IOC6 PAGE0 IOC60~IOC67 IOC7 PAGE0 IOC70~IOC77 IOC8 PAGE0 IOC80~IOC87 IOC9 PAGE0 IOC90~IOC97 IOCA PAGE0 C1P0~C2P2 CNT1S C2P0~C2P2 CNT2S IOCB PAGE0 IOCB0~IOCB7 IOCC PAGE0 IOCC0~IOCC7 IOCD PAGE0 CN10~CN17 IOCE PAGE0 CN20~CN27 IOCF TCIF CNT1 CNT2 INT0 INT1 INT2 0 RBF 5~7 0~7 0~7 0~7 0~7 0~2 3 4~6 7 0~7 0~7 0~7 0~7 PORT5 I/O control register, PORT switch Switch low nibble I/O PORT8 or LCD segment output PORT5(5~7) I/O direction control register PORT6 I/O control register PORT6(0~7) I/O direction control register PORT7 I/O control register PORT7(0~7) I/O direction control register PORT8 I/O control register PORT8(0~7) I/O direction control register PORT9 I/O control register PORT9(0~7) I/O direction control register Counter1 and Counter2 clock and scale setting Counter1 scaling Counter1 clock source Counter2 scaling Counter2 clock source PORTB I/O control register PORTB(0~7) I/O direction control register PORTC I/O control register PORTC(0~7) I/O direction control register Counter1 data buffer Counter1 data buffer that you can read from and write to Counter2 data buffer Counter2 data buffer that you can read from and write to Interrupt mask register 0 1 2 3 4 5 6 7 Interrupt enable bit for TCC Interrupt enable bit for COUNTER1 Interrupt enable bit for COUNTER2 Interrupt enable bit for the external INT0 pin Interrupt enable bit for the external INT1 pin Interrupt enable bit for the external INT2 pin Unused Interrupt enable bit when the SPI data transfer is complete Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) * 13 EM78870 8-Bit Micorcontroller 7.2.1.4 IOC PAGE1 Addr 05 Name 06 IOC5 PAGE1 BIAS0~BIAS3 0 KTS KT0~KT1 IOC6 PAGE1 07 IOC7 PAGE1 STRB8~STRB15 08 0~3 4 5 6~7 Function Key tone control, LCD bias control LCD operation voltage selection Unused Key tone output switch Key tone output frequency and power control Empty Key strobe control register 0~7 IOC8 PAGE1 STRB16~STRB23 Key strobe control bits Key strobe control register 0~7 Key strobe control bits 09 - - 0A IOCA PAGE1 PORT7 pull high control register PH70~PH77 0B 0C 0E 0~7 0~7 Tone generator1's frequency divider and power control TONE2 control register 0~7 IOCE PAGE1 0 PORT6(0~7) pull high control register TONE1 control register IOCD PAGE1 T20~T27 PORT7(0~7) pull high control register PORT6 pull high control register IOCC PAGE1 T10~T17 0D 0~7 IOCB PAGE1 PH60~PH67 Tone generator2's frequency divider and power control Comparator reference voltage type, PORT switch 0~3 Unused Switch for controlling PORT63 IO PORT or a comparator input Switch for controlling PORT64 IO PORT or a comparator input Switch for controlling PORT65 IO PORT or a comparator input CMPIN1 4 CMPIN1 5 CMPIN1 6 CMPREF 7 Switch for comparator reference voltage type Bit 0~2 Function PORT switch, LCD driving ability control Unused 3~4 LCD driver's driving ability control 7.2.1.5 IOC PAGE 2 Addr 06 Name IOC6 PAGE2 0E 0 LCDDV0~LCDDV 1 PBS PCSL PCSH IOCE PAGE2 0 14 * Bit 5 6 7 Switch I/O PORTB or LCD segment output Switch low nibble I/O PORTC or LCD segment output Switch high nibble I/O PORTC or LCD segment output 7 This bit must clear to 0 Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller A Unpage registers (Common registers) In addition to R0~R4 and RF, other unpaged registers are listed below. Addr Name 10 : 1F 20 : 3F R10 : R1F R20 : R3F B Function Common register : Common register 4 - bank common register : 4 - bank common register Unaddressable register Name ACC CONT PSR0~PSR2 PAB TS INT INT_EDGE 7.3 Bit Bit 0~2 3 4 5 6 7 Function Accumlator : Internal data transfer and instruction operand holding Control register TCC/WDT prescaler bits Prescaler assignment bit (unused) TCC signal source INT enable flag Interrupt edge type of P70 Operational Register Detail Description 7.3.1 R0 (Indirect Addressing Register) R0 is not a physically-implemented register. It is useful as an indirect addressing pointer. Any instruction using R0 as a register accesses data pointed by the RAM Select Register (R4). Example: Mova,@0x20;store an address at R4 for indirect addressing Mov0x04,A Mova,@0xAA;write data 0xAA to R20 at bank0 through R0 Mov0x00,A Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) * 15 EM78870 8-Bit Micorcontroller 7.3.2 R1 (TCC) TCC data buffer. Increased by 16.384kHz or by the instruction clock cycle (controlled by the CONT register). Written and read by the program as any other register. 7.3.3 R2 (Program Counter) The structure is depicted in Fig. 5. Generates thirteen 32K instruction codes. on-chip PROGRAM ROM addresses to the corresponding "JMP" directly loads the low 10 program counter bits. "CALL" loads the low 10 bits of the PC, PC+1, and then pushes them into the stack. "RET'' ("RETL k", "RETI") loads the program counter with the contents at the top of stack. "MOV R2,A" allows the loading of an address from the A register to the PC, and the ninth and tenth bits are cleared to "0''. "ADD R2,A" allows a relative address be added to the current PC, and contents of the ninth and tenth bits are cleared to "0''. "TBL" allows a relative address be added to the current PC, without changing the contents of the ninth and tenth bits. The most significant bit (A10~A14) will be loaded with the content of bit PS0~PS3 in the status register (R5) upon the execution of a "JMP'', "CALL'', "ADD R2,A'', or "MOV R2,A'' instruction. If an interrupt is triggered, PROGRAM ROM will jump to address8 at page0. The CPU will store ACC, R3 status and R5 PAGE automatically. it will be restored after instruction RETI. R5(PAGE) PC CALL and INTERRUPT A14 A13 A12 A11 A10 A9 A8 A7~A0 00000 PAGE0 0000~03FF 00001 PAGE1 0400~07FF 00010 PAGE2 0800~0BFF 11110 PAGE30 7800~7BFF RET RETL RETI STACK1 STACK2 STACK3 STACK4 STACK5 STACK6 STACK7 STACK8 STACK9 : : STACK30 STACK31 STACK32 store ACC,R3,R5(PAGE) restore 11111 PAGE31 7C00~7FFF 16 * Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller Fig.5 Program counter organization 7.3.4 R3 (Status Register) 7 PAGE 6 IOC6P1S 5 IOCPAGE 4 T 3 P 2 Z 1 DC 0 C Bit 0 (C) : Carry flag Bit 1 (DC) : Auxiliary carry flag Bit 2 (Z) : Zero flag Bit 3 (P) : Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command. Bit 4 (T) : Time-out bit. Set to 1 by the "SLEP" and "WDTC" commands, or during power up and reset to 0 when WDT times out. EVENT T P WDT wake up from sleep mode 0 0 WDT times out (when not in sleep mode) 0 1 /RESET wake up from sleep Power up Low pulse on /RESET 1 1 x 0 1 X REMARK x = don't care Bit 5(IOCPAGE) : change IOC5 ~ IOCE to another page Please refer to Fig.4 control register configuration for details. 0/1 page0 / page1 Bit 6(IOC6P1S) : change IOC6 PAGE1 to another option register Please refer to Fig.4 control register configuration for details. 0/1 page1 option-A/page1 option-B Bit 7(PAGE) : change R4 ~ RE to another page Please refer to Fig.4 control register configuration for details. 0/1 7.3.5 page0 / page1 R4 (RAM selection for common registers R20 ~ R3F, SPI control) Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) * 17 EM78870 8-Bit Micorcontroller 7.3.5.1 7 RB1 PAGE0 (RAM selection register) 6 RB0 5 RSR5 4 RSR4 3 RSR3 2 RSR2 1 RSR1 0 RSR0 Bit 0 ~ Bit 5 (RSR0 ~ RSR5) : Indirect addressing for common registers R20 ~ R3F RSR bits are used to select up to 32 registers (R20 to R3F) in the indirect addressing mode. Bit 6 ~ Bit 7 (RB0 ~ RB1) : Bank selection bits for common registers R20 ~ R3F These selection bits are used to determine which bank is activated among the 4 banks for 32 registers (R20 to R3F). Please refer to Fig.4 control register configuration for details. 7.3.5.2 7 RBF PAGE1 (SPI control register) 6 SPIE 5 SRO 4 SE 3 SCES 2 SBR2 1 SBR1 0 SBR0 Fig. 6 shows how SPI communicates with the other devices using the SPI module. If SPI is a master controller, it sends the clock rate through the SCK pin. An 8-bit data is transmitted and received at the same time. If SPI is defined as a slave, its SCK pin could be programmed as an input pin. Data will continue to be shifted depending on the clock rate and the selected edge. SDO SDI Master Device Salve Device R5 page1 SPIR register SPIW register SPIS Reg Bit7 SDI SDO SCK SCK SPI module Bit 0 Fig.6 Single SPI Master / Salve Communication 18 * Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller Bit 0 ~ Bit 2 (SBR0 ~ SBR2) : SPI baud rate selection bits SBRS2(Bit 2) SBRS1(Bit 1) SBRS0(Bit 0) Mode Band rate 0 0 0 Master Fsco 0 0 1 Master Fsco/2 0 1 0 Master Fsco/4 0 1 1 Master Fsco/8 1 0 0 Master Fsco/16 1 0 1 Master Fsco/32 1 1 0 Slave 1 1 1 x x Note Fsco = CPU instruction clock For example : If PLL is enabled and RA PAGE0 (Bit5,Bit4)=(1,1), then the instruction clock is 3.58MHz/2 Fsco=3.5862MHz/2 If PLL is enabled and RA PAGE0 (Bit5,Bit4)=(0,0), then the instruction clock is 0.895MHz/2 Fsco=0.895MHz/2 If PLL is disabled, then the instruction clock is 32.768kHz/2 Fsco=32.768kHz/2. Bit 3 (SCES) : SPI clock edge selection bit 1 Data shifts out on falling edge, and shifts in on rising edge. Data is held during high level. 0 Data shifts out on rising edge, and shifts in on falling edge. Data is held during low level. Bit 4 (SE) : SPI shift enable bit 1 Start to shift, and stay on 1 while the current byte is still being transmitted. 0 Reset as soon as the data shift is complete, and the next byte is ready to be shifted. Note This bit has to be reset in software. Bit 5 (SRO) : SPI read overflow bit Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) * 19 EM78870 8-Bit Micorcontroller 1 New data is received while there is still data in the SPIB register. In this situation, data in the SPIS register will be discarded. To avoid setting this bit, you must read data from the SPIB register first before each data write action. 0 No overflow Note This can only occur in slave mode. Bit 6 (SPIE) : SPI enable bit 1 Enable SPI mode 0 Disable SPI mode Bit 7 (RBF) : SPI read buffer full flag 1 Finished receving data and SPIB is full. 0 Data reception not complete and SPIB is empty. Write R5 Read R5 RBF RBFI SPIWC SPIR reg. SPIW reg. set to 1 SPIE SDI/P62 Buffer Full Detector SDI MUX shift right SPIS reg. PORT62 bit 7 bit 0 SPIC reg. (R4 page1) SDO SDO/P61 MUX PORT61 Edge Select SPIE 0 3 SBR0 ~SBR2 Noise Filter SBR2~SBR0 3 2 Clock Select Tsco Prescaler 4, 8, 16, 32, 64, 128 Edge Select 16.38kHz SCK PORT60 MUX SCK/P60 SCK SPIE Fig.7 SPI structure 20 * Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller SPIC reg. : SPI control register SDO/P61 : Serial data out SDI/P62 : Serial data in SCK/P60 : Serial clock. RBF : Set by the buffer full detector, and reset in software. RBFI : Interrupt flag. Set by the buffer full detector, and reset in software. Buffer Full Detector : Set to 1, when an 8-bit data shifti is complete. SE : Loads the data in the SPIW register, and begin to shift data SPIE : SPI control register SPIS reg. : Shift data in and out. The MSB will be shifted first. Both the SPIS and the SPIW registers are loaded at the same time. Once data is being written to, SPIS starts data transmission. The received data will be moved to the SPIR register, after the the 8-bit data shift is complete. The RBF (Read Buffer Full ) flag and the RBFI(Read Buffer Full Interrupt) flag are set. SPIR reg. : Read buffer. The buffer will be updated when the 8-bit data shift is complete. The data must be read before the next reception is finished. The RBF flag is cleared as the SPIR register is read. SPIW reg. : Write buffer. The buffer will deny any write operation until the 8-bit data shift is complete. The SE bit will stay on 1 if data transmission is still in progress. This flag must be cleared after the data shift is finished. Users can determine if the next write operation attempt is available. SBR2 ~ SBR0: Set the clock frequency/rates and sources. Clock select : Select either the internal instruction clock or the external 16.338KHz clock as the clock rate for performing a data shift. Edge Select : Select the appropriate clock edges by setting the SCES bit. Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) * 21 EM78870 8-Bit Micorcontroller SCK (SCES=0) SCK (SCES=1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SDO SDI RBF Shift data in Shift data out Clear by software Fig.8 SPI timing 7.3.6 R5 (PORT5 I/O data, Program page selection, SPI data) 7.3.6.1 PAGE0 (PORT5 I/O data register, Program page register) 7 6 5 4 3 2 1 0 R57 R56 R55 PS4 PS3 PS2 PS1 PS0 Bit 0 ~ Bit 4 (PS0 ~ PS4) : Program page selection bits 22 * PS4 PS3 PS2 PS1 PS0 Program memory page (Address) 0 0 0 0 : : 1 1 0 0 0 0 : : 1 1 0 0 0 0 : : 1 1 0 0 1 1 : : 1 1 0 1 0 1 : : 0 1 Page 0 Page 1 Page 2 Page 3 : : Page 30 Page 31 Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller User can use the PAGE instruction to maintain the program page. Otherwise, user can use the far jump (FJMP) or far call (FCALL) instructions to access code blocks. And the program page is maintained by the compiler in EMC. It changes the program by inserting instructions within a program. Bit 5 ~ Bit 7 (P55 ~ P57) : 3-bit PORT5(5~7) I/O data register You can use the IOC register to set each bit for input or output 7.3.6.2 PAGE1 (SPI data buffer) 7 6 5 4 3 2 1 0 SPIB7 SPIB6 SPIB5 SPIB4 SPIB3 SPIB2 SPIB1 SPIB0 Bit 0 ~ Bit 7 (SPIB0 ~ SPIB7) : SPI data buffer If you write data to this register, data will be written to the SPIW register. If you read this data, it will be read from the SPIR register. Please refer to figure7 7.3.7 R6 (PORT6 I/O data) 7.3.7.1 PAGE0 (PORT6 I/O data register) 7 6 5 4 3 2 1 0 P67 P66 P65 P64 P63 P62 P61 P60 Bit 0 ~ Bit 8 (P60 ~ P67) : 8-bit PORT6(0~7) I/O data register You can use the IOC register to set each bit for input or output. 7.3.8 R7 (PORT7 I/O data) 7.3.8.1 PAGE0 (PORT7 I/O data register) 7 6 5 4 3 2 1 0 P77 P76 P75 P74 P73 P72 P71 P70 Bit 0 ~ Bit 7 (P70 ~ P77) : 8-bit PORT7(0~7) I/O data register You can use the IOC register to set each bit for input or output . Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) * 23 EM78870 8-Bit Micorcontroller 7.3.9 R8 (PORT8 I/O data) 7.3.9.1 PAGE0 (PORT8 I/O data register) 7 6 5 4 3 2 1 0 P87 P86 P85 P84 P83 P82 P81 P80 Bit 0 ~ Bit 7 (P80 ~ P87) : 8-bit PORT8(0~7) I/O data register You can use the IOC register to set each bit for input or output. 7.3.10 R9 (PORT9 I/O data, extra LCD address bit) 7.3.10.1 PAGE0 (PORT9 I/O data register) 7 6 5 4 3 2 1 0 P97 P96 P95 P94 P93 P92 P91 P90 Bit 0 ~ Bit 7 (P90 ~ P97) : 8-bit PORT9(0~7) I/O data register You can use the IOC register to set each bit for input or output. 7.3.10.2 PAGE1 (LCD address MSB bit) 7 6 5 4 3 2 1 0 LCDA8 0 0 0 0 0 0 0 Bit 0 ~ Bit6 = 0 : unused Bit 7 (LCDA8) : MSB of the LCD address for reading from and writing to LCD RAM . Other LCD address bits LCDA7 ~ LCDA0 are set from RA PAGE1 Bit 7 ~ Bit 0. For LCD address access over 0xFFH, set this bit to "1"; otherwise set this bit to "0". 7.3.11 24 * RA (CPU power saving, PLL, Main clock selection, Watchdog timer, LCD address) Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller 7.3.11.1 PAGE0 (CPU power saving bit, PLL, Main clock selection bits, Watchdog timer enable bit) 7 6 5 4 3 2 1 0 0 PLLEN CLK1 CLK0 0 1 1 WDTEN Bit 0 (WDTEN) : Watchdog control register You can use the WDTC instruction to clear the watchdog counter. The counter 's clock source is 32768/2 Hz. If the prescaler assigns to TCC, the watchdog counter will time out by (1/32768 )*2 * 256 = 15.616ms. If the prescaler assigns to WDT, the timeout period will be longer depending on the ratio of the prescaler. 0/1 disable/enable Bit 1~ Bit 2 = 1 : unused Bit 3 = 0 : unused Bit 4 ~ Bit 5 (CLK0 ~ CLK1) : Main clock selection bits User can choose different frequencies for the main clock by setting CLK1 and CLK2.The following lists the various clock frequencies. PLLEN CLK1 CLK0 Sub clock MAIN clock CPU clock 1 1 1 1 0 0 0 0 0 0 1 1 Don't care Don't care Don't care Don't care 0 1 0 1 don't care don't care don't care don't care 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 895.658kHz 1.7913MHz 10.7479MHz 3.5826MHz don't care don't care don't care don't care 895.658kHz (Normal mode) 1.7913MHz (Normal mode) 10.7479MHz (Normal mode) 3.5826MHz (Normal mode) 32.768kHz (Green mode) 32.768kHz (Green mode) 32.768kHz (Green mode) 32.768kHz (Green mode) Bit 6 (PLLEN) : PLL enable control bit It is the CPU mode control register. If PLL is enabled, the CPU will operate at normal mode (high frequency, main clock); otherwise, it will run at green mode (low frequency, 32768 Hz). 0/1 disable/enable Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) * 25 EM78870 8-Bit Micorcontroller 3.5826MHz to analog circuit / / x x PLL Sub-clock 32.768kHz 4 =>895.658kHz 2 =>1.7913M Hz 1 =>3.5826M Hz 3 =>10.7479M Hz 1 switch System clock ENPLL 0 CLK1 ~ CLK0 Fig.9. The relation between 32.768kHz and PLL Note Bit 7: Unused register. Always keep this bit to 0. Otherwise, unexpected error may occur. The status after wake-up and the wake-up sources are listed in the following table. Wakeup signal GREEN mode RA(7,6)=(x,0) no SLEP NORMAL mode RA(7,6)=(x,1) no SLEP No function Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0) No function Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0) No function Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0) WDT time out RESET and Jump to address 0 RESET and Jump to address 0 RESET and Jump to address 0 PORT7 IOCF bit3 or bit4 or bit5 =1 And "ENI" RESET and Jump to address 0 Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0) TCC time out IOCF bit0=1 And "ENI" COUNTER1 time out IOCF bit1=1 And "ENI" COUNTER2 time out IOCF bit2=1 And "ENI" SLEEP mode RA(7,6)=(0,0) + SLEP Note PORT70 ~ PORT73 's wakeup function is controlled by IOCF bit3 and ENI instruction. They are falling edge triggers. PORT74 ~ PORT76 's wakeup function is controlled by IOCF bit4 and ENI instruction. They are falling edge triggers. PORT77 's wakeup function is controlled by IOCF bit5 and ENI instruction. It's a falling edge or rising edge trigger (controlled by CONT register). 26 * Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller 7.3.11.2 PAGE1 (LCD address) 7 6 5 4 3 2 1 0 LCDA7 LCDA6 LCDA5 LCDA 4 LCDA 3 LCDA 2 LCDA 1 LCDA 0 Bit 0 ~ Bit 7 (LCDA0 ~ LCDA7) : LCD address for LCD RAM reading or writing The data in the LCD RAM correspond to the COMMON and SEGMENT signals as shown in the following table . COM23 ~ COM16 (set R9 PAGE1 bit7=1) COM15 ~COM8 (set R9 PAGE1 bit7=0) COM7 ~ COM0 (set R9 PAGE1 bit7=0) Address 100H Address 101H Address 102H : : : Address 14EH Address 14FH Address 150H : Address 17FH Address 80H Address 81H Address 82H : : : Address CEH Address CFH Address D0H : Address FFH Address 00H Address 01H Address 02H : : : Address 4EH Address 4FH Address 50H : Address 7FH 7.3.12 SEG0 SEG1 SEG1 : : : SEG78 SEG79 Empty : Empty RB (PORTB I/O data, LCD data) 7.3.12.1 PAGE0 (PORTB I/O data register) 7 6 5 4 3 2 1 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Bit 0 ~ Bit 7 (PB0 ~ PB7) : 8-bit PORTB(0~7) I/O data register User can use the IOC register to set each bit for input or output. 7.3.12.2 PAGE1 (LCD data buffer) 7 6 5 4 3 2 1 0 LCDD7 LCDD6 LCDD5 LCDD4 LCDD3 LCDD2 LCDD1 LCDD0 Bit 0 ~ Bit 7 (LCDD0 ~ LCDD7) : LCD data buffer for LCD RAM reading or writing For example: MOVA,@0 Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) * 27 EM78870 8-Bit Micorcontroller MOV R9_PAGE1,A MOVRA_PAGE1,A;ADDRESS MOVA,@0XAA MOVRB_PAGE1,A;WRITE DATA 0XAA TO LCD RAM MOVA,RB_PAGE1;READ DATA FROM LCD RAM : 7.3.13 RC (PORTC I/O data, Data RAM data) 7.3.13.1 PAGE0 (PORTC I/O data register) 7 6 5 4 3 2 1 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Bit 0 ~ Bit 7 (PC0 ~ PC7) : 8-bit PORTC(0~7) I/O data register User can use the IOC register to set each bit for input or output. 7.3.13.2 PAGE1 (Data RAM data buffer) 7 6 5 4 3 2 1 0 RAMD7 DRAMD6 RAMD5 RAMD4 RAMD3 RAMD2 RAMD1 RAMD0 Bit 0 ~ Bit 7 (RAMD0 ~ RAMD7) : Data RAM data buffer for reading from or writing to RAM. For example: MOVA,@1 MOVRD_PAGE1,A MOVA,@0 MOVRE_PAGE1,A MOVA,@0x55 MOVRC_PAGE1,A;write data 0x55 to DATA RAM whose address is "0001". MOV A,RC_PAGE1;read data : 28 * Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller 7.3.14 RD (Comparator control, Data RAM address(0 ~ 7)) 7.3.14.1 PAGE0 (Comparator control bits) 7 6 5 4 3 2 1 0 CMPEN CMPFLAG CMPS1 CMPS0 CMP_B3 CMP_B2 CMP_B1 CMP_B0 If you define PORT63 , PORT64 or PORT65 (by CMPIN1, CMPIN2, CMPIN3 at IOCE page1) as a comparator input or PORT6, you can use this register to control the function of the comparator. Bit 0 ~ Bit 3 (CMP_B0 ~ CMP_B3) : Reference voltage selection of the internal bias circuit for the comparator. Reference voltage for the comparator = VDD x ( n + 0.5 )/ 16 , n = 0 to 15 Bit 4 ~ Bit 5 (CMPS0 ~ CMPS1) : Channel selection from CMP1 to CMP3 for the comparator CMPS1 CMPS0 Input 0 0 1 1 0 1 0 1 CMP1 CMP2 CMP3 Reserved Bit 6 (CMPFALG) : Comparator output flag 0 Input voltage < reference voltage 1 Input voltage > reference voltage Bit 7 (CMPEN) : Enable control bit for the comparator. 0/1 disable/enable The relation between these registers are shown in Fig.10. Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) * 29 EM78870 8-Bit Micorcontroller P63/CMP1 CMP1 MUX PORT63 CMPIN1 P64/CMP2 CMP2 MUX + MUX CMPFLAG PORT64 2 CMPIN2 P65/CMP3 CMPS1 CMPS0 CMP3 MUX PORT65 1 VDD MUX 0 CMPIN3 VR CMPREF CMPEN 1/2R 1111 R 1110 R MUX 0000 1/2R 4 CMP_B3 to CMP_B0 Fig.10. Comparator circuit CMPEN CMP1 to CMP3 reference voltage Setup time 10us CPU clock CMPFLAG Compare start Compare end Fig.11. Comparator timing 30 * Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller 7.3.14.2 PAGE1 (Data RAM address0 ~ address7) 7 6 5 4 3 2 1 0 RAMA7 RAMA6 RAMA5 RAMA4 RAMA3 RAMA2 RAMA1 RAMA0 Bit 0 ~ Bit 7 (RAMA0 ~ RAMA7) : Data RAM address (address0 to address7) for reading from or writing to RAM 7.3.15 RE (Key sacn, LCD control, Data RAM addresss(8 ~ 10)) 7.3.15.1 PAGE0 (Key scan control, LCD control) 7 6 5 4 3 2 1 0 1 KEYCHK KEYSTRB KEYSCAN LCD1 LCD0 LCDM1 LCDM0 Bit 0 ~ Bit 1 (LCDM0 ~ LCDM1) : LCD common mode, bias select and COM/SEG switch control bits LCDM1, LCDM0 COM output mode LCD bias COM/SEG switch 0,0 0,1 1,0 1,1 16 common 9 common 8 common 24 common 1/4 bias 1/4 bias 1/4 bias 1/5 bias SEG0 ~ SEG7 select SEG0 ~ SEG7 select SEG0 ~ SEG7 select COM16 ~ COM23 select Note When 8, 9 and 16 LCD common mode are set, COM16/SEG0 pin ~ COM23/SEG7 pin are also set to SEG0 ~ SEG7 and LCD bias is 1/4 bias. When 24 LCD common mode is set, COM16/SEG0 pin ~ COM23/SEG7 pin are also set to COM16 ~ COM23 and LCD bias is 1/5 bias. Bit 2 ~ Bit 3 (LCD0 ~ LCD1) : LCD operation function definition. LCD1, LCD0 LCD operation 0,0 Disable 0,1 Blanking 1,0 Reserved 1,1 LCD enable Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) * 31 EM78870 8-Bit Micorcontroller Note Key strobe and key check functions should be enabled regardless of whether the LCD is enabled or not. The controller can control the LCD directly. The LCD block is made up of the LCD driver, display RAM, segment output pins, common output pins and LCD operating bias pins. Duty, the number of segment , the number of common and frame frequency are determined by the LCD mode register RE PAGE0 Bit 0~ Bit 1. When 8, 9 or 16 LCD commons are used, LCD operating bias pins VC1, VC2, VC4 and VC5 need to be connected to 0.1uF capacitors to the ground (VC3 is not necessary). When 24 LCD commons are used, all LCD operating bias pins VC1 ~ VC5 need to be connected to the 0.1uF capacitors to the ground. The LCD driver can be controlled as different driving ability (refer to IOC6 PAGE1 Option-B register). The basic structure contains a time controler which uses the basic frequency of 32.768kHz to generate the proper timing for different duty and display access. The RE PAGE1 register is a command register for the LCD driver and display. The LCD display (disable, enable, blanking) is controlled by RE PAGE0 Bit 2 ~ Bit 3 and the driving duty is decided by RE PAGE Bit 0 ~ Bit 2. LCD display data is stored in data RAM whose address and data access function are controlled by registers R9, RA PAGE1 and RB PAGE1. You can set the contrast of the LCD display using IOC5 PAGE1 (BIAS3..BIAS0). Up to 16 levels of contrast is available. In addition, the internal voltage follower allows greater driving source. COM signal : The number of COM pins varies depending on the duty cycle used, as follows: in 1/8 duty mode COM8 ~ COM15 must be open. In 1/9 duty mode COM9~ COM15 must be open in 1/16 duty mode COM0 ~ COM15 pins must be used. in 1/24 duty mode COM0 ~ COM23 pins must be used. 32 * duty COM0 ~ COM7 COM8 COM9 .. COM15 COM15 ~ COM23 1/8 1/9 1/16 o o o x o o x x o .. .. .. x x o x x x Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller 1/24 o o o .. o o x : open, o : select SEG signal: The segment signal pins are connected to the corresponding display RAM. The high byte to the low byte Bit 0 ~ Bit 7 correspond to COM0 ~ COM23 respectively . When a bit of display RAM is set to 1, a select signal is sent to the corresponding segment pin, and when the bit is 0 , a non-select signal is sent to the corresponding segment pin. Bit 4 (KEYSCAN) : Key scan function enable control bit 0/1 disable/enable If you enable the key scan function, the LCD waveform will include periodic pulses for each cycle as shown in Fig.12. V1 V2 V4 V5 GND COM2 V1 V2 V4 V5 GND SEG 30us V1 V2 V4 V5 GND Fig.12. key scan waveform for 1/8, 1/9, 1/16 duty Bit 5 (KEYSTRB) : Key strobe enable control bit 0/1 disable/enable If you set the key strobe signal bit , the segment will switch to strobe signal temporally and output zero signal ( one instruction long ) one by one from segment 8 to segment Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) * 33 EM78870 8-Bit Micorcontroller 23. During one segment strobe time, the CPU will check whether port7(0:3) is equal to "1111" or not. If not, CPU will latch a zero at IOC7 PAGE1 and IOC8 PAGE1 one by one depending on which segment triggered the strobe. After "strobing", this bit will be cleared . Fig.13 shows a key strobe signal. One instruction REGISTER STROBE SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 IOC7(0) IO C7(1) IOC7(2) IOC7(3) IOC7(4) IOC7(5) IO C7(6) IO C7(7) IOC8(0) IOC8(1) IOC8(2) IOC8(3) IO C8(4) IO C8(5) IOC8(6) IOC8(7) 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 Fig.13 key strobe signal Bit 6 (KEYCHK) : Key check enable control bit 0 disable key check function. 1 enable key check function. SEG8 to SEG23 will stay at low level. Figure 14 shows the relationship between KEYSCAN, KEYSTROBE , KETCHECK and the segments. Figure 16 shows the flow of a key scan interrupt trigger. RELATION BETWEEN S(8:23) , KEYSCAN, KEY STROBE, KEY CHECK KEY SCAN PULSE SEGMENT(8:23) KEY SCAN CONTROL 0 0 MUX KEY STROBE SIGNAL 1 GND MUX 1 KEYSTROBE KEYCHECK Fig.14 KEYSCAN, KEYSTROBE , KETCHECK and segments. 34 * Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) * 35 EM78870 8-Bit Micorcontroller Bit 7 = 1 : unused Set port7(3:0) input (IOC7 (7:0) = " 0x0f " ) set IOC page1 (BS R3,IOC_PAGE) port7 pull high (IOCA=0x0f) set IOC page0 (BC R3,IOC_PAGE) enable key scan signal (RE bit4=1) set INT0 interrupt ENI N Interrupt occur? Y Enable main clock (Normal mode) program delay enable RE(6) key check Read port7 ( column key ) disable RE(6) key check set strobe function enable RE (5) keystrobe program delay read IOC7,IOC8 (row key) Execution key function Get the key location Fig.15 key scan flow by interrupt trigger 7.3.15.2 PAGE1 (Data RAM address8 ~ address11) 7 6 5 4 3 2 1 0 0 0 RAM11 RAMA10 RAMA9 RAMA8 Bit 0 ~ Bit 3 (RAMA8 ~ RAMA11) : Data RAM address (address8 to address11) for reading from RAM. Bit 4 , Bit 7 = 0 : unused 36 * Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller 7.3.15.3 RF (Interrupt flags) 7 6 5 4 3 2 1 0 RBF 0 INT2 INT1 INT0 CNT2 CNT1 TCIF "1" means interrupt request, "0" means non-interrupt Bit 0 (TCIF) : TCC timer overflow interrupt flag Set when TCC timer overflows. Bit 1 (CNT1) : Counter1 timer overflow interrupt flag Set when counter1 timer overflows . Bit 2 (CNT2) : Counter2 timer overflow interrupt flag Set when counter2 timer overflows . Bit 3 (INT0) : External INT0 pin interrupt flag If PORT70 ,PORT71,PORT72 or PORT73 has a falling edge trigger signal, the CPU will set this bit. Bit 4 (INT1) : External INT1 pin interrupt flag If PORT74 ,PORT75 or PORT76 has a falling edge trigger signal, the CPU will set this bit. Bit 5 (INT2) : External INT2 pin interrupt flag If PORT77 has a falling edge or rising edge (controlled by CONT register) trigger signal, the CPU will set this bit. Bit 6 = 0 : unused Bit 7 ( RBF) : Interrupt flag for SPI data complete If the serial IO 's RBF signal has a rising edge signal (RBF set to "1" when data transfer is complete), the CPU will set this bit. IOCF is the interrupt mask register that you can read and clear. The following table lists the trigger edge. Signal TCC COUNTER1 COUNTER2 INT0 INT1 INT2 RBF Trigger Time out Time out Time out Falling edge Falling edge Falling/Falling&rising edge Rising edge Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) <Note> Controlled by CONT register * 37 EM78870 8-Bit Micorcontroller 7.3.16 R10~R3F (General Purpose Register) 7.3.16.1 R10~R3F (Banks 0 ~ 3) : All of them are general purpose registers. 7.4 Special Purpose Registers 7.4.1 A (Accumulator) Internal data transfer, or hold instruction operand It's not an addressable register. 7.4.2 CONT (Control Register) 7 6 5 4 3 2 1 0 INT_EDGE INT TS - PAB PSR2 PSR1 PSR0 Bit 0 ~ Bit 2 (PSR0 ~ PSR2) : TCC/WDT prescaler bits PSR2 PSR1 PSR0 TCC rate WDT rate 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 Bit 3(PAB) : Prescaler assignment bit 0/1 TCC/WDT Bit 4 : undefined Bit 5(TS) : TCC signal source 0 Instruction clock 1 16.384kHz Instruction clock = MCU clock/2, Refer to RA Bit 4 ~ Bit 6 for PLL and Main clock selection. See Fig.16. 38 * Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller Bit 6 (INT) : INT enable flag 0 interrupt masked by DISI or hardware interrupt 1 interrupt enabled by ENI/RETI instructions Bit 7(INT_EDGE) : interrupt edge type of P70 0 => P70 's interrupt source is a rising edge signal or falling edge signal. 1 P70 's interrupt source is a falling edge signal. CONT register is readable (CONTR) and writable (CONTW). TCC and WDT : There is an 8-bit counter available as a prescaler for the TCC or WDT. The prescaler is available for either TCC or WDT at a time. An 8-bit counter is available for TCC or WDT depending on the status of bit 3 (PAB) of the CONT register. See the prescaler ratio in the CONT register. Fig.16 shows the circuit diagram of TCC/WDT. Both TCC and the prescaler will be cleared by instructions which write to TCC each time. The prescaler will be cleared by the WDTC and SLEP instructions when set to WDT mode. The prescaler will not be cleared by the SLEP instructions when set to TCC mode. Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) * 39 EM78870 8-Bit Micorcontroller Data Bus Instruction clock 16.384kHz M U X M U X TS SYNC 2 cycles TCC(R1) TCC overflow interrupt PAB WDT M U X WDTE PAB 8-bit Counter PSR0 ~ PSR2 8-to-1 MUX MUX PAB WDT timeout Fig.16 Block diagram of TCC WDT 7.4.3 IOC5 (PORT5 I/O control, PORT switch, Key tone,LCD bias) 7.4.3.1 PAGE0 (PORT5 I/O control register, PORT switch) 7 6 5 4 3 2 1 0 IOC57 IOC56 IOC55 0 P9SH P9SL P8SH P8SL Bit 0 (P8SL) : Switch low nibble I/O PORT8 or LCD segment output for the shared pins SEGxx/P8x 0 select normal P80 ~ P83 for low nibble on PORT8 1 select SEG64 ~ SEG67 output for LCD SEGMENT output. Bit 1 (P8SH) : Switch high nibble I/O PORT8 or LCD segment output for the shared pins SEGxx/P8x 0 select normal P84 ~ P87 for high nibble on PORT8 1 select SEG68 ~ SEG71 output for LCD SEGMENT output. Bit 2 (P9SL) : Switch low nibble I/O PORT9 or LCD segment output for the shared pins SEGxx/P9x 40 * 0 select normal P90 ~ P93 for low nibble on PORT9 1 select SEG72 ~ SEG75 output for LCD SEGMENT output. Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller Bit 3 (P9SH) : Switch high nibble I/O PORT9 or LCD segment output for the shared pins SEGxx/P9x 0 select normal P94 ~ P97 for high nibble on PORT9 1 select SEG76 ~ SEG79 output for LCD SEGMENT output.*Bit 4 is a general register Bit 4 = 0 : unused Bit 5 ~ Bit 7 (IOC55 ~ IOC57) : PORT5 I/O direction control registers. 0 set the relative I/O pin as output 1 set the relative I/O pin to high impedance 7.4.3.2 PAGE1 (Key tone control, LCD bias control) 7 6 5 4 3 2 1 0 KT1 KT0 KTS 0 BIAS3 BIAS2 BIAS1 BIAS0 Bit 0 ~ Bit 3 (BIAS0 ~ BIAS3) : LCD operation voltage selection V1 = VDD * (5 - n/15)/5 Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) * 41 EM78870 8-Bit Micorcontroller (BIAS3 to BIAS0) V1 voltage Example (VDD=5V) 0000 0001 0010 0011 0100 : 1101 1110 1111 VDD * (5-0/15)/5 VDD * (5-1/15)/5 VDD * (5-2/15)/5 VDD * (5-3/15)/5 VDD * (5-4/15)/5 : VDD * (5-13/15)/5 VDD * (5-14/15)/5 VDD * (5-15/15)/5 5V 4.93V 4.86V 4.80V 4.73V : 4.13V 4.07V 4.0V COMs BIAS MUX LCD driver for COM and SEG VC1 ~ VC5 generator SEGs 4 BIAS3 to BIAS0 VC1 ~ VC5 Fig.17. The relation between bias and V1 to V5 42 * Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller FRAME V1 V2 V4 V5 GND COM0 V1 V2 V4 V5 GND COM1 V1 V2 V4 V5 GND COM2 V1 V2 V4 V5 GND SEG dark V1 V2 V4 V5 GND SEG light Fig.18a LCD waveform (1/4 bias) for 1/8 duty, 1/9 duty, 1/16 duty Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) * 43 EM78870 8-Bit Micorcontroller frame V1 v2 v3 v4 v5 Gnd com0 V1 v2 v3 v4 v5 Gnd com1 com2 V1 v2 v3 v4 v5 Gnd seg V1 v2 v3 v4 v5 Gnd dark V1 v2 v3 v4 v5 Gnd seg light Fig.18b LCD waveform (1/5 bias) for 1/24 duty Bit 4 = 0 : unused Bit 5 (KTS) : Key tone output switch 0 normal on PORT67 1 key tone output . Bit 6 ~ Bit 7 (KT0 ~ KT1) : Key tone output frequency and its power control 44 * KT1 KT0 0 0 1 1 0 1 0 1 Key tone frequency and power 32.768KHz/32 = 1.024kHz clock and enable 32.768KHz/16 = 2.048kHz clock and enable 32.768KHz/8 = 4.096kHz clock and enable Power off key tone Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller 7.4.4 IOC6 (PORT6 I/O control, PORT switch, LCD driving control) 7.4.4.1 PAGE0 (PORT6 I/O control register) 7 6 5 4 3 2 1 0 IOC67 IOC66 IOC65 IOC64 IOC63 IOC62 IOC61 IOC60 Bit 0 ~ Bit 7 (IOC60 ~ IOC67) : PORT6(0~7) I/O direction control register 0 set the relative I/O pin as output 1 set the relative I/O pin to high impedance 7.4.4.2 PAGE1 (empty register) 7.4.4.3 PAGE 2 (PORT switch, LCD driving ability control) 7 6 5 4 3 2 1 0 PCSH PCSL PBS LCDDV1 LCDDV0 0 0 0 Bit 0 ~ Bit 2 = 0 : unused Bit 3 ~ Bit 4 (LCDDV0 ~ LCDDV1) : LCD driver's driving ability control LCDDV1 LCDDV0 0 0 1 1 0 1 0 1 Driving mode Normal mode (ratio = 1) Weak mode (ratio = 1/2) Strong mode (ratio = 2) Maximum mode (ratio = 4) LCDDV0 ~ LCDDV1 are used to select the driving ability of the LCD driver. The driving ability modes are maximum mode, strong mode, normal mode and weak mode. The maximum mode is 2 times the strong mode, the strong mode is 2 times the weak mode and so on. The larger driving ability selected, the larger output loading of LCD driver output is allowed and the more power is consumed. It depends on the user's application. Bit 5 (PBS) : Switch I/O PORTB or LCD segment output for share pins SEGxx/PBx 0 select normal PB0 ~ PB7 for PORTB 1 select SEG48 ~ SEG55 output for LCD SEGMENT output. Bit 6 (PCSL) : Switch low nibble I/O PORTC or LCD segment output for the shared pins SEGxx/PCx Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) * 45 EM78870 8-Bit Micorcontroller 0 select normal PC0 ~ PC3 for low nibble PORTC 1 select SEG56 ~ SEG59 output for LCD SEGMENT output. Bit 7 (PCSH) : Switch high nibble I/O PORTC or LCD segment output for the shared pins SEGxx/PCx 0 select normal PC4 ~ PC7 for high nibble PORTC 1 select SEG60 ~ SEG63 output for LCD SEGMENT output. 7.4.5 IOC7 (PORT7 I/O control, Key strobe(8~15)) 7.4.5.1 PAGE0 (PORT7 I/O control register) 7 6 5 4 3 2 1 0 IOC77 IOC76 IOC75 IOC74 IOC73 IOC72 IOC71 IOC70 Bit 0 ~ Bit 7 (IOC70 ~ IOC77) : PORT7(0~7) I/O direction control register 0 set the relative I/O pin as output 1 set the relative I/O pin to high impedance 7.4.5.2 PAGE1 (Key strobe control register) 7 6 5 4 3 2 1 0 STRB15 STRB14 STRB13 STRB12 STRB11 STRB10 STRB9 STRB8 Bit 0 ~ Bit 7 (STRB8 ~ STRB15) : Key strobe control bits These key strobe control registers correspond to SEGMENT8 through SEGMENT15. Please refer to the description on KEYSTOBE (RE page0). 46 * 7.4.6 IOC8 (PORT8 I/O control, , Key strobe(16~23)) 7.4.6.1 PAGE0 (PORT8 I/O control register) 7 6 5 4 3 2 1 0 IOC87 IOC86 IOC85 IOC84 IOC83 IOC82 IOC81 IOC80 Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller Bit 0 ~ Bit 7 (IOC80 ~ IOC87) : PORT8(0~7) I/O direction control register 0 set the relative I/O pin as output 1 set the relative I/O pin to high impedance 7.4.6.2 PAGE1 (Key strobe control register) 7 6 5 4 3 2 1 0 STRB23 STRB22 STRB21 STRB20 STRB19 STRB18 STRB17 STRB16 Bit 0 ~ Bit 7 (STRB16 ~ STRB23) : Key strobe control bits These key strobe control registers correspond to SEGMENT16 through SEGMENT23. Please refer to the description on KEYSTOBE (RE page0). 7.4.7 PORT9 I/O control) 7.4.7.1 PAGE0 (PORT9 I/O control register) 7 6 5 4 3 2 1 0 IOC97 IOC96 IOC95 IOC94 IOC93 IOC92 IOC91 IOC90 Bit 0 ~ Bit 7 (IOC90 ~ IOC97) : PORT9(0~7) I/O direction control register 0 set the relative I/O pin as output 1 set the relative I/O pin to high impedance 7.4.8 IOCA (CN1's and CN2's clock and scaling, PORT7 pull high control) 7.4.8.1 PAGE0 (Counter1's and Counter2's clock and scale setting) 7 6 5 4 3 2 1 0 CNT2S C2P2 C2P1 C2P0 CNT1S C1P2 C1P1 C1P0 Bit 0 ~ Bit 2 (C1P0 ~ C1P2) : set the Counter1 scale Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) * 47 EM78870 8-Bit Micorcontroller C1P2 C1P1 C1P0 COUNTER1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 Bit 3 (CNT1S) : Counter1 clock source 0/1 16.384kHz/MCU clock Bit 4 ~ Bit 6 (C2P0 ~ C2P2) : set Counter2 scale C2P2 C2P1 C2P0 COUNTER2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 Bit 7 (CNT2S) : Counter2 clock source 0/1 16.384kHz/MCU clock 7.4.8.2 PAGE1 (PORT7 pull high control register) 7 6 5 4 3 2 1 0 PH77 PH76 PH75 PH74 PH73 PH72 PH71 PH70 Bit 0 ~ Bit 7 (PH70 ~ PH77) : PORT7(0~7) pull high control register 48 * 0 disable pull high function 1 enable pull high function Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller 7.4.9 IOCB (PORTB I/O control, PORT6 pull high control) 7.4.9.1 PAGE0 (PORTB I/O control register) 7 6 5 4 3 2 1 0 IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 Bit 0 ~ Bit 7 (IOCB0 ~ IOCB7) : PORTB(0~7) I/O direction control register 0 set the relative I/O pin as output 1 set the relative I/O pin to high impedance 7.4.9.2 PAGE1 (PORT6 pull high control register) 7 6 5 4 3 2 1 0 PH67 PH66 PH65 PH64 PH63 PH62 PH61 PH60 Bit 0 ~ Bit 7 (PH60 ~ PH67) : PORT6(0~7) pull high control register 0 disable pull high function. 1 enable pull high function 7.4.10 IOCC (PORTC I/O control, TONE1 control) 7.4.10.1 PAGE0 (PORT9 I/O control register) 7 6 5 4 3 2 1 0 IOCC7 IOCC6 IOCC5 IOCC4 IOCC3 IOCC2 IOCC1 IOCC0 Bit 0 ~ Bit 7 (IOCC0 ~ IOCC7) : PORTC(0~7) I/O direction control register 0 set the relative I/O pin as output 1 set the relative I/O pin to high impedance 7.4.10.2 PAGE1 (TONE1 control register) 7 6 5 4 3 2 1 0 T17 T16 T15 T14 T13 T12 T11 T10 Bit 0 ~ Bit 7(T10 ~ T17) : Tone generator1`s frequency divider and power control Applicable in Normal mode. Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) * 49 EM78870 8-Bit Micorcontroller Clock source = 111957Hz T17~T10 = `11111111' => Tone generator1 will have 439Hz SIN wave output. : T17~T10 = `00000010' => Tone generator1 will have 55978Hz SIN wave output. T17~T10 = `00000001' => DC bias voltage output T17~T10 = `00000000' => Power off The built-in tone generator can generate dialing tone signals for telephone of dialing tone type or just a single tone. In DTMF application, there are two kinds of tones. One is a group of row frequency (TONE1), the other is a group of column frequency (TONE2). Each group has 4 kinds of frequencies that allow you to have up to16 DTMF frequencies. The tone generator contains a row frequency sine wave generator for generating the DTMF signal which is selected by IOCC and a column frequency sine wave generator for generating the DTMF signal which selected by IOCD. This block can generate a single tone by filling one of these two registers. If all the values are low, the power of tone generators will be turned off. TONE2 (IOCD PAGE1) High group freq. 1203.8(0X5D) 1332.8(0X54) 1473.1(0X4C) 1646.4(0X44) TONE1(IOCC 699.7Hz(0x0A0) PAGE1) 772.1Hz(0x091) Low group 854.6Hz(0x083) freq. 940.8Hz(0x077) 1 4 2 5 3 6 A B 7 8 9 C * 0 # D Also TONE1 and TONE2 are asynchronous tone generators so that both can be used to generate a Caller ID FSK signal. In FSK generator application, TONE1 or TONE2 can generate 1200Hz Mark bit and 2200Hz Space bit for Bell202 or 1300Hz Mark bit and 2100Hz Space bit for V.23. See the following table. 50 * TONE1(IOCC PAGE1) or TONE2(IOCD PAGE1) Freq. (Hz) 0x5D 0x33 0x56 0x35 1203.8 2195.2 1301.8 2112.4 Bell202 FSK Mark bit Bell202 FSK Space bit V.23 FSK Mark bit V.23 FSK Space bit Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller 7.4.11 IOCD (Counter1 data, TONE2 control) 7.4.11.1 PAGE0 (Counter1 data buffer) 7 6 5 4 3 2 1 0 CN17 CN16 CN15 CN14 CN13 CN12 CN11 CN10 Bit 0 ~ Bit 7 (CN10 ~ CN17) : Counter1's data buffer User can read from and write do this buffer. Counter1 is an 8-bit up-counter with an 8-bit prescaler that you can preset (or write) and read with IOCD. After an interrupt, it will reload the preset value. Example: write: IOW 0x0D ; write data at the accumulator to counter1 (preset) Example: read: IOR 0x0D ;read data from IOCD and write it to the accumulator 7.4.11.2 PAGE1 (TONE2 control register) 7 6 5 4 3 2 1 0 T27 T26 T25 T24 T23 T22 T21 T20 Bit 0 ~ Bit 7(T20 ~ T27) : Tone generator 2`s frequency divider and power control Applicable in Normal mode . Clock source = 111957Hz T27~T20 = `11111111' => Tone generator2 will have 439Hz SIN wave output. : T27~T20 = `00000010' => Tone generator2 will have 55978Hz SIN wave output. T27~T20 = `00000001' => DC bias voltage output T27~T20 = `00000000' => Power off 7.4.12 IOCE (Counter2 data, Comparator and OP control) 7.4.12.1 PAGE0 (Counter2 data buffer, Comparator control, OP control) 7 6 5 4 3 2 1 0 CN27 CN26 CN25 CN24 CN23 CN22 CN21 CN20 Bit 0 ~ Bit 7 (CN20 ~ CN27) : Counter2's data buffer Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) * 51 EM78870 8-Bit Micorcontroller User can read from and write to this buffer. Counter2 is an 8- bit up-counter with an 8-bit prescaler that you can preset (or write) and read with IOCD. After an interrupt, it will reload the preset value. Example: write: IOW 0x0D ; write data at the accumulator to counter1 (preset) Example: read: IOR 0x0D ;read IOCD data and write to the accumulator 7.4.12.2 PAGE1 (Comparator reference voltage type, PORT switch) 7 6 5 4 3 2 1 0 CMPREF CMPIN3 CMPIN2 CMPIN1 0 0 0 0 Bit 0 ~ Bit 3 = 0 : unused Bit 4 (CMPIN1) : Switch for controlling PORT63 as IO PORT or a comparator input. 0 IO PORT63 1 comparator input Bit5 (CMPIN2) : Switch for controlling PORT64 as IO PORT or a comparator input. 0 IO PORT64 1 comparator input Bit 6 (CMPIN3) : Switch for controlling PORT65 as IO PORT or a comparator input. 0 IO PORT65 1 comparator input Bit 7 (CMPREF) : Switch for comparator reference voltage type 0 internal reference voltage (Come from VDD) 1 external reference voltage 7.4.12.3 PAGE2 (Un-exist register) IOCE page2 does NOT exist. Do NOT access this register or another register will be changed. 7.4.13 IOCF (Interrupt Mask Register) 7 6 5 4 3 2 1 0 RBF 0 INT2 INT1 INT0 CNT2 CNT1 TCIF Bit 0 ~ Bit 5,7 are interrupt mask enable bits. 0 52 * disable interrupt Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller 1 enable interrupt Bit 6 = 0 : unused 7.5 I/O Port The I/O registers are bi-directional tri-state I/O ports. The I/O ports can be defined as "input" or "output" pins by the I/O control registers. The I/O registers and the I/O control registers are both readable and writable. The I/O interface circuit is shown in Fig.19. PCRD PORT Q P R Q C L Q P R Q C L D CLK PCWR D CLK IOD PDWR PDRD 0 1 M U X Fig.19 The circuit of I/O port and I/O control register 7.6 RESET One of the following results a RESET: (1) Power on voltage detector reset (POVD) or power on reset (2) WDT timeout. (if enabled and in GREEN or NORMAL mode) (3) /RESET pin pull low Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) * 53 EM78870 8-Bit Micorcontroller Note For case 1, POVD is controlled by CODE OPTION. If you enable POVD, the CPU will reset at 2V or below. Tthe CPU will consume more power(about 15uA) . Therefore the power on reset is talways enabled. It will reset the CPU at about 1.4V and consume about 0.5uA. Once the RESET occurs, the following functions are performed. The oscillator runs, or will be started. The Program Counter (R2) is set to all 0s. When power is on, the upper 3 bits of R3 and the upper 2 bits of R4 are cleared. The Watchdog timer and prescaler counter are cleared. The Watchdog timer is disabled. The CONT register is set to 1s. The values for the other registers (bit7..bit0) are set as shown in the table below. (x = don't care) 7.7 A Address R register Page0 R register Page1 3 4 5 6 7 8 9 A B C D E F 000xxxxx 00xxxxxx xxx00000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00000110 xxxxxxxx xxxxxxxx 00000000 10000000 00000000 00000000 xxxxxxxx xxxxxxxx Xxxxxxxx Xxxxxxxx x0000000 Xxxxxxxx Xxxxxxxx Xxxxxxxx Xxxxxxxx 000xxxxx - IOC Register Page0 IOC Register page1 11100000 11111111 11111111 11111111 11111111 00000000 11111111 11111111 00000000 00000000 00000000 00000000 11111111 11111111 00000000 00000000 00000000 00000000 00000000 - IOC Register Page2 00000000 00000000 Wake-up The controller provides the sleep mode for power saving. SLEEP mode , RA(7)=0 + "SLEP" instruction . The controller will turn off the CPU and crystal. You must also turn off the other circuit with power control such as the key tone or PLL control (which contains an enable register),. 54 * Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller One of the following resultes a wake-up from SLEEP mode (1) WDT timeout (2) external interrupt (3) /RESET pull low All these cases will reset the controller and run the program at address zero. The result is the same as power on reset. Be sure to enable the WDT timer and the external register for cases (1) and (2) respectively. 7.8 Interrupt RF is the interrupt status register which records the interrupt request in flag bits. IOCF is the interrupt mask register. TCC timer, Counter1 and Counter2 are the internal interrupt sources. P70 ~ P77(INT0 ~ INT1) are external interrupt inputs with external interrupt sources. If interrupts occur at these interrupt sources and the IOCF register is also enabled, then the RF register will generate '1' flag to the corresponding register. Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. When one of the interrupts (when enabled) is generated, the next instruction will be fetched from address 008H. Once in the interrupt service routine, the source of the interrupt can be determined by polling the flag bits in the RF register. The interrupt flag bit must be cleared before leaving the interrupt service routine and enabling interrupts to avoid recursive interrupts. 7.9 Instruction Set Instruction set has the following features: (1) Every bit of any register can be set, cleared, or tested directly. (2) The I/O register can be regarded as a general register. That is, the same instruction can operate on the I/O register. The symbol "R" represents a register designator which specifies which one of the 64 registers (including operational registers and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4 determine the selected register bank. "b'' represents a bit field designator which selects the number of the bit, located in the register "R'', affected by the operation. "k'' represents an 8 or 10-bit constant or literal value. Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) * 55 EM78870 8-Bit Micorcontroller INSTRUCTION BINARY HEX MNEMONIC 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0010 0011 0100 rrrr 0000 0001 0010 0000 0001 0002 0003 0004 000r 0010 0011 0012 NOP DAA CONTW SLEP WDTC IOW R ENI DISI RET 0 0000 0001 0011 0013 RETI 0 0000 0001 0100 0 0000 0001 rrrr 0014 001r CONTR IOR R 0 0000 0010 0000 0020 TBL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rrrr 0000 rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr 00rr 0080 00rr 01rr 01rr 01rr 01rr 02rr 02rr 02rr 02rr 03rr 03rr 03rr 03rr 04rr 04rr 04rr 04rr 05rr 05rr 05rr 05rr MOV R,A CLRA CLR R SUB A,R SUB R,A DECA R DEC R OR A,R OR R,A AND A,R AND R,A XOR A,R XOR R,A ADD A,R ADD R,A MOV A,R MOV R,R COMA R COM R INCA R INC R DJZA R DJZ R 0 0110 00rr rrrr 06rr RRCA R 0 0110 01rr rrrr 06rr RRC R 0 0110 10rr rrrr 06rr RLCA R 0 0110 11rr rrrr 06rr RLC R 0 0111 00rr rrrr 07rr SWAPA R 0 0111 01rr 0 0111 10rr rrrr rrrr 07rr 07rr SWAP R JZA R 0 0 0 0 0 0 0 0 0 56 * 0000 0000 0000 0001 0001 0001 0001 0010 0010 0010 0010 0011 0011 0011 0011 0100 0100 0100 0100 0101 0101 0101 0101 0000 0000 0000 0000 0000 0000 0001 0001 0001 01rr 1000 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr OPERATION No Operation Decimal Adjust A A CONT 0 WDT, Stop oscillator 0 WDT A IOCR Enable Interrupt Disable Interrupt [Top of Stack] PC [Top of Stack] PC Enable Interrupt CONT A IOCR A R2+A R2 bits 9,10 do not clear AR 0A 0R R-A A R-A R R-1 A R-1 R ARA ARR A&RA A&RR ARA ARR A+RA A+RR RA RR /R A /R R R+1 A R+1 R R-1 A, skip if zero R-1 R, skip if zero R(n) A(n-1) R(0) C, C A(7) R(n) R(n-1) R(0) C, C R(7) R(n) A(n+1) R(7) C, C A(0) R(n) R(n+1) R(7) C, C R(0) R(0-3) A(4-7) R(4-7) A(0-3) R(0-3) R(4-7) R+1 A, skip if zero None C None T,P T,P None None None None Instructio n cycle 1 1 1 1 1 1 1 1 2 None 2 None None 1 1 Z,C,DC 2 None Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z None None 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 if skip 2 if skip C 1 C 1 C 1 C 1 None 1 None None 1 2 if skip STATUS AFFECTED Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller INSTRUCTION BINARY HEX MNEMONIC 0111 100b 101b 110b 111b 07rr 0xxx 0xxx 0xxx 0xxx JZ R BC R,b BS R,b JBC R,b JBS R,b 1 00kk kkkk kkkk 1kkk CALL k 1 1 1 1 1 1 1 1kkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk JMP k MOV A,k OR A,k AND A,k XOR A,k RETL k SUB A,k 1 1110 0000 0001 1E01 INT 1 1110 100k kkkk 1 1111 kkkk kkkk 1E8k 1Fkk PAGE k ADD A,k 0 0 0 0 0 01kk 1000 1001 1010 1011 1100 1101 11rr bbrr bbrr bbrr bbrr kkkk kkkk kkkk kkkk kkkk kkkk kkkk rrrr rrrr rrrr rrrr rrrr kkkk kkkk kkkk kkkk kkkk kkkk kkkk None None None None None Instructio n cycle 2 if skip 1 1 2 if skip 2 if skip None 2 None None Z Z Z None Z,C,DC 2 1 1 1 1 2 1 None 1 None Z,C,DC 1 1 STATUS AFFECTED OPERATION R+1 R, skip if zero 0 R(b) 1 R(b) if R(b)=0, skip if R(b)=1, skip PC+1 [SP] (Page, k) PC (Page, k) PC kA AkA A&kA AkA k A, [Top of Stack] PC k-A A PC+1 [SP] 001H PC K->R5(4:0) k+A A 7.10 CODE Option Register The controller has one CODE option register which is not part of the normal program memory. The option bits cannot be accessed during normal program execution. 7 6 5 4 3 2 1 0 /POVD Bit 0 (/POVD) : Power on voltage detector, 0/1 => enable/disable /POVD 2.2V /POVD reset 2.2V power on reset sleep mode current 1 0 No Yes (2.2V) Yes (2.2V) No 1uA 15uA Bit 1 ~ Bit 7 : unused. Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) * 57 EM78870 8-Bit Micorcontroller 8 Absolute Operation Maximum Ratings RATING DC SUPPLY VOLTAGE INPUT VOLTAGE OPERATING TEMPERATURE RANGE 9 SYMBOL Vdd Vin Ta VALUE -0.3 To 6 -0.5 TO Vdd +0.5 0 TO 70 UNIT V V DC Electrical Characteristic (Operation current consumption for Analog circuit under VDD=5V VSS=0V) Symbol I_CMP Parameter Operation current for comparator Condition Min VDD=5V, PT power on Typ Max 0.17 Unit mA (Ta=25C, VDD=5V5%, VSS=0V) Symbol IIL1 IIL2 VIH VIL VIHT VILT VIHX VILX VOH1 VOL1 58 * Parameter Input Leakage Current for input pins Input Leakage Current for bi-directional pins Input High Voltage Input Low Voltage Input High Threshold Voltage Input Low Threshold Voltage Clock Input High Voltage Clock Input Low Voltage Output High Voltage (port5,8,9,B,C) (port6,7) Output Low Voltage (port5,8,9,B,C) (port6,7) IPH Pull-high current ISB1 Power down current (SLEEP mode) ISB2 Low clock current (GREEN mode) Condition Min Typ Max Unit VIN = VDD, VSS 1 A VIN = VDD, VSS 1 A 0.8 V V 2.5 /RESET, TCC, RDET1 2.0 V /RESET, TCC,RDET1 0.8 V 1.5 V V OSCI OSCI 3.5 IOH = -5mA 2.4 V IOH = -8mA 2.4 V IOL = 5mA 0.4 V IOL = 8mA Pull-high active input pin at VSS All input and I/O pin at VDD, output pin floating, WDT disabled CLK=32.768KHz, All analog circuit disable , All input and I/O pin at VDD, output pin floating, WDT disabled, LCD enabled 0.4 V -10 -15 A 1 4 A 50 80 A Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller Symbol Parameter ICC Operating supply current (NORMAL mode) Condition /RESET=High, PLL enable CLK=3.5826MHz, output pin floating, LCD enabled, all analog circuit disabled. Min Typ Max Unit 1.3 1.8 mA 10 AC Electrical Characteristic (Ta=25C, VDD=5V, VSS=0V) Symbol Dclk Parameter Input CLK duty cycle Tins Instruction cycle time Tdrh Device delay time Ttcc TCC input period <Note 1> Twdt Watchdog timer period Ta = 25C Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) Condition Min 45 32.768kHz 3.5826MHz Typ Max 50 55 60 550 16 (Tins +20) /N Unit % us ns ms ns 16 ms * 59 EM78870 8-Bit Micorcontroller 11 Timing Diagrams ins Fig.20 timing 60 * Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller Appendix A. Application Note 1. ROM, OTP, ICE ROM OTP ICE EM78870 EM78P870 EM78808 ICE EM78870 EM78P870 2.5K x 8 4K x 8 2. Main Function Difference RAM 3. While switching the main clock (whether from high frequency to low frequency or vise versa), adding 6 instructions of delay (NOP) is required. 4. Please clear IOCE page2 bit7 to 0 or the result of the comparator will be inaccurate. 5. Please do not directly change the MCU operation mode from normal mode to sleep mode. Before change it to idle or sleep mode, you must first set MCU to green mode. 6. Please always keep RA page0 bit7 = 0 or an unexpected error may result!! 7. RE page1 Bit6~Bit7 are un-defined registers. These two bits are undefined and their values will vary. When performing a calculation, do NOT include these two bits. Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) * 61 EM78870 8-Bit Micorcontroller B. Function control list SPI * SPI control * SPI data buffer R4 page1 bit0~bit7 R5 page1 bit0~bit7 Data RAM access * Data buffer * Address buffer 0~7 RD page1 * Address buffer 8~11 RE page1 bit0~bit3 RC page1 LCD driver * LCD RAM address 0~7 * LCD RAM address 8 * LCD RAM data buffer * LCD mode * SEG pin switch * LCD bias * LCD driver control RA page1 R9 page1 bit7 RB page1 RE page0 bit0~bit3 IOC5 page0 bit0~bit3 ; IOC6 page2 bit5~bit7 IOC5 page1 bit0~bit3 IOC6 page2 bit3~bit4 Comparator * Comparator control RD page0 ; IOCE page1 Key Scan * Key Scan * Key Strobe RE page0 bit5 * Key Check RE page0 bit6 * Key Strobe data IOC7 page1 * Key Strobe data IOC8 page1 RE page0 bit4 Dual Tone Generator * 62 * Tone1 control IOCC page1 Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) EM78870 8-Bit Micorcontroller * Tone2 control IOCD page1 C. Application Circuit LCD pannel COMMON SEGMENT VC1 11 0.1u VC2 12 Key matrix 0.1u VC3 13 0.1u VC4 14 0.1u 0.1u VDD SEG23 VC5 15 SEG10 EM78870 VDD,AVDD 18 XIN 16 27p 27p 0.1u 32.768k SEG9 XOUT 17 SEG8 PLLC 19 AVSS,GND 21 24~27 P70 22 P71 P72 P73 TEST Fig.21 Application circuit Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice) * 63 EM78870 8-Bit Micorcontroller 64 * Product Specification (V2.3) 08.19.2004 (This specification is subject to change without further notice)