FEATURES AND BENEFITS
▪IntegratedboostMOSFET,currentsensing,and
compensation
▪704kHzswitchingfrequencyforsmalllow-cost
components
▪S
¯
¯
L
¯
¯
E
¯
¯
E
¯
¯
P
¯
pinforultralowpowerconsumptionmode
▪AdjustableLNBoutputcurrentlimit(250to950mA*)
limitwithshutdowntimer
▫Coverswidearrayofapplicationrequirements
▫Minimizescomponentsizingtofiteachapplication
▫Forstartup,reconfiguration,andcontinuousoutput
▪BoostpeakcurrentlimitscaleswithLNBcurrentlimit
▪Optionaltemporaryincreasedcurrentlimit(+25%)
▪CompatiblewithDiSEqC1.xcontrol
DESCRIPTION
The A8304 is a single channel low noise block regulator
(LNBR).TheA8304consistsofamonolithicboostconverter
followed by a low-drop linear regulator. It is specifically
designedtoprovidethepowerandtheinterfacesignalstoan
LNBdownconverterviacoaxialcableinsatelliteTVreceiver
systems.
TheA8304requiresfewexternalcomponents,withtheboost
switch and compensation circuitry integrated inside of the
device.The704kHzswitchingfrequencyanduser-controlled
outputcurrentlimitminimizethesizeofthepassivefiltering
components.
TheI2C™-compatibleinterfaceprovidescontrolcapabilitiesfor
complexsystemrequirements,aswellasdiagnosticcapabilities
forsystemfaultreporting.
Asleep pinisavailableto maximize power savings and to
quicklyshutdownthedeviceifneeded,withoutusingI2C™
control.
TheA8304isprovidedinasmall3×3mmQFNpackagewith
exposedpadforthermaldissipation.Itislead(Pb)free,with
100%matte-tinleadframeplating.
8304-DS, Rev. 3
MCO-0000473
Single LNB Supply and Control Voltage Regulator
Functional Block Diagram
A8304
LNB
BOOST
VOUT
D3 and D4 are used for surge protection.
SCL
ADD
SLEEP
SDA
VDD
V
S
IRQ
TONECTRL
10 nF
C9
220 nF
C10
100 nF
C8
C7
100 nF
C3
220 nF
C1
100 nF
R1 R2 R3
L1
10 µH D1
D2
R5
D4
D3
A
A
A
R4
100 µF
C2 100 µF
C5
1 µF
C6
100 nF
C4
I2C™
Interface
Linear
Regulator
Boost
Regulator
Slew
Rate
Limiter
+
IC
Power
704 kHz
Osc
0.8 V
Latched
Faults
UVLO, OCP,
TSD
Unlatched
Status
PNG, CPOK
TSD
DAC
Read
RST
SET
LNBREF
BOOST
REF
OC
LX VCP
GNDLX
VIN
GND
PAD
TCAP
Timer
45 ms
VREG
Ref
VSEL3/2/1/0
VIN
CLK
4
Fault
Charge
Pump
Tone
Generator
+
ISET
RSET
ILIM
VFB
VIN
For recommended external components, refer to table 5
PACKAGE:
3mm×3mm×0.75mm
16-contactQFN(suffixES)
Continued on the next page…
Not to scale
July 9, 2018
Single LNB Supply and Control Voltage Regulator
A8304
2
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Package Thermal Characteristics
[4]
Package RθJA
(°C/W) PCB
ES 47 4-layer
[4] Additional information is available on the Allegro website.
SELECTION GUIDE
Part Number Packing
[1] Description
A8304SESTR-T 7 in. reel, 1500 pieces/reel
12 mm carrier tape QFN surface mount
3 mm × 3 mm × 0.75 mm nominal height
[1] Contact Allegro for additional packing options.
ABSOLUTE MAXIMUM RATINGS
Characteristic Symbol Conditions Rating Unit
Load Supply Voltage, VIN pin VIN 18 V
Output Current
[2] ILNB Internally
Limited A
Output Voltage; BOOST pin –0.3 to 32 V
Output Voltage; LNB pin Surge
[3] –1.0 to 32 V
Output Voltage; LX pin –0.3 to 30 V
Output Voltage; VCP pin –0.3 to 37 V
TCAP, ISET, VREG Pins –0.3 to 6 V
Logic Input Voltage –0.3 to 5.5 V
Logic Output Voltage –0.3 to 5.5 V
Operating Ambient Temperature TARange S –20 to 85 °C
Junction Temperature TJ(max) 150 °C
Storage Temperature Tstg –55 to 150 °C
[2] Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the
specified current ratings, or a junction temperature, TJ, of 150°C.
[3] Use Allegro recommended application circuit.
▪2-wireI2C™-compatibleinterfaceforcontrolandstatus
▫ ProgrammableLNBoutputvoltagelevels(2%accuracy)
▫ Enable/disableoutput
▫ Flexible22kHztonegenerationmethods
▫ SINK_DISbitforcontrollingthepush-pulloutputsink
currentthreshold
▪Diagnosticfeatures:PNG
▪Extensiveprotectionfeatures:UVLO,OCP,TSD
FEATURES AND BENEFITS (CONTINUED)
*MaximumvaluedependsonPCBthermaldesign
Single LNB Supply and Control Voltage Regulator
A8304
3
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
PAD
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
BOOST
GNDLX
LX
VIN
SCL
SDA
TONECTRL
SLEEP
GND
VREG
ISET
TCAP
VCP
LNB
ADD
IRQ
Terminal List Table
Name Number Function
ADD 3 Address select
BOOST 16 Tracking supply voltage to linear regulator
GND 12 Signal ground
GNDLX 15 Boost switch ground
IRQ 4 Interrupt request
ISET 10 Output current limit set via external resistor
LNB 2 Output voltage to LNB
LX 14 Inductor drive point
PAD Pad Exposed pad; connect to the ground plane, for thermal dissipation
SCL 5 I2C™-compatible clock input
SDA 6 I2C™-compatible data input/output
¯
S
¯
¯
L
¯
¯
E
¯
¯
E
¯
¯
P
¯ 8
When this pin is pulled low, the A8304 enters sleep mode; LNB output,
boost, I2C™ communication, and charge pump disabled to reduce input
quiescent current to less than 15 µA
TCAP 9 Capacitor for setting the rise and fall time of the LNB output
TONECTRL 7 Apply external 22 kHz tone or tone on-and-off signal to enable/disable
internal tone
VCP 1 Gate supply voltage
VIN 13 Input supply voltage
VREG 11 Analog supply
PINOUT DIAGRAMS AND TERMINAL LIST TABLE
Single LNB Supply and Control Voltage Regulator
A8304
4
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
ELECTRICAL CHARACTERISTICS
[1] at TA = 25°C, VIN = 10 to 16 V, ¯
S
¯
¯
L
¯
¯
E
¯
¯
E
¯
¯
P
¯
= 1, • as noted
[2]; unless noted otherwise
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
GENERAL
Output Voltage Accuracy %VLNB
VIN = 12 V, ILNB = 10 mA, see table 2 for
DAC settings •–2 – +2 %
Load Regulation ΔVLNB(Load)
VIN = 12 V, VLNB = 13.667 V,
ΔILNB = 10 to 450 mA •– 38 76 mV
VIN = 12V, VLNB = 19.000 V,
ΔILNB = 10 to 450 mA •– 45 90 mV
Line Regulation ΔVLNB(Line)
VIN = 10 to 16 V, VLNB = 13.667 V,
ILNB = 10 mA •–10 0 10 mV
VIN = 10 to 16 V, VLNB = 19.000 V,
ILNB = 10 mA •–10 0 10 mV
Supply Current (Off) IIN(OFF)
¯
S
¯
¯
L
¯
¯
E
¯
¯
E
¯
¯
P
¯
= 0, VIN = 12 V •– – 15 µA
ENB = 0, VIN = 12 V •– 4 7 mA
Supply Current (On)
[3] IIN(ON)
ENB = 1, VIN = 12 V, VLNB = 19 V,
ILOAD = 0 mA, TONECTRL = 0 – 9 – mA
ENB = 1, VIN = 12 V, VLNB = 19 V,
ILOAD = 0 mA, TONECTRL = 1 – 15 – mA
Boost Switch On Resistance RDS(on)
BOOST
ISW = 450 mA – 400 – mΩ
Switching Frequency fSW 633 704 774 kHz
Linear Regulator Voltage Drop ∆VLR
VBOOST – VLNB, no tone signal,
ILOAD = 425 mA 600 800 1000 mV
TCAP Pin Current ITCAP
TCAP capacitor (C7) charging –13 –10 –7 µA
TCAP capacitor (C7) discharging 7 10 13 µA
Output Voltage Rise Time
[3] tr(VLNB)
For VLNB 13 → 19 V; C7 = 100 nF,
ILOAD = 500 mA – 10 – ms
Output Voltage Pull-Down Time
[3] tf(VLNB)
For VLNB 19 → 13 V; CLOAD = 100 µF,
ILOAD = 0 mA, SINK_DIS = 0 – 20 – ms
Output Reverse Current3IRLNB
ENB = 0 – 2 6 mA
SINK_DIS = 1, ENB = 1, TONECTRL = 0 – 7 10 mA
SINK_DIS = 0, ENB = 1, TONECTRL = 0,
Absolute(VLNB-VSEL setting) < 1.5 V – 30 50 mA
SINK_DIS = 0, ENB = 1, TONECTRL = 1,
Absolute(VLNB-VSEL setting) < 1.5 V – 60 150 mA
SINK_DIS = 0, ENB = 1, TONECTRL = 0 or 1,
Absolute(VLNB-VSEL setting) > 1.5 V – 7 15 mA
Ripple and Noise on LNB Output [4] Vrip,n(pp)
20 MHz BWL; reference circuit shown in
Functional Block diagram; contact Allegro
for additional information on application
circuit board design
– 30 – mVPP
Continued on the next page…
Single LNB Supply and Control Voltage Regulator
A8304
5
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
GENERAL (continued)
VREG Voltage VVREG VIN = 10 V 4.97 5.25 5.53 V
ISET Voltage VISET VIN = 10 V 3.4 3.5 3.6 V
TCAP Pin Voltage VTCAP
VIN = 10 V, VLNB = 13.667 V – 2.28 – V
VIN = 10 V, VLNB = 19.000 V – 3.17 – V
PROTECTION CIRCUITRY
Output Overcurrent Limit5ILNB(MAX) RSET = 60.4 kΩ •450 500 600 mA
Overcurrent Disable Time tDIS – 45 – ms
Boost MOSFET Current Limit IBOOST(MAX) RSET = 60.4 kΩ – 2600 – mA
VIN Undervoltage Lockout Threshold VUVLO VIN falling 8.05 8.35 8.65 V
VIN Turn On Threshold VIN(th) VIN rising 8.40 8.70 9.00 V
Undervoltage Hysteresis VUVLOHYS – 350 – mV
Thermal Shutdown Threshold
[3] TJ– 165 – °C
Thermal Shutdown Hysteresis
[3] ∆TJ– 20 – °C
Power Not Good (Low)
PNGLOSET
With respect to VLNB setting; VLNB low,
PNG set to 1 88 91 94 %
PNGLORESET
With respect to VLNB setting; VLNB low,
PNG reset to 0 92 95 98 %
Power Not Good (Low) Hysteresis PNGLOHYS With respect to VLNB setting – 4 – %
Power Not Good (High)
PNGHISET
With respect to VLNB setting; VLNB high,
PNG set to 1 106 109 112 %
PNGHIRESET
With respect to VLNB setting; VLNB high,
PNG reset to 0 102 105 108 %
Power Not Good (High) Hysteresis PNGHIHYS With respect to VLNB setting – 4 – %
TONE
Amplitude VTONE(PP) ILNB = 0 to 350 mA, CLNB = 100 nF •650 750 850 mVPP
Frequency fTONE ILNB = 0 to 350 mA, CLNB = 100 nF •20 22 24 kHz
Duty Cycle DCTONE ILNB = 0 to 350 mA, CLNB = 100 nF 40 50 60 %
Rise Time tR(TONE) ILNB = 0 to 350 mA, CLNB = 100 nF 5 10 15 μs
Fall Time tF(TONE) ILNB = 0 to 350 mA, CLNB = 100 nF 5 10 15 μs
TONE
[3]
Amplitude VTONE(PP) ILNB = 425 mA, CLNB = 750 nF •500 650 900 mVPP
Frequency fTONE ILNB = 425 mA, CLNB = 750 nF •20 22 24 kHz
Duty Cycle DCTONE ILNB = 425 mA, CLNB = 750 nF 40 50 60 %
Rise Time tR(TONE) ILNB = 425 mA, CLNB = 750 nF 5 10 15 μs
Fall Time tF(TONE) ILNB = 425 mA, CLNB = 750 nF 5 10 15 μs
Continued on the next page…
ELECTRICAL CHARACTERISTICS
[1] (continued) at TA = 25°C, VIN = 10 to 16 V, ¯
S
¯
¯
L
¯
¯
E
¯
¯
E
¯
¯
P
¯
= 1, as noted
[2]; unless noted otherwise
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
Single LNB Supply and Control Voltage Regulator
A8304
6
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
ELECTRICAL CHARACTERISTICS
[1] (continued) at TA = 25°C, VIN = 10 to 16 V, ¯
S
¯
¯
L
¯
¯
E
¯
¯
E
¯
¯
P
¯
= 1, as noted
[2]; unless noted otherwise
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
TONE CONTROL (TONECTRL PIN)
Logic Input VH2.0 – – V
VL– – 0.8 V
Input Leakage V(lkg) –1 – 1 μA
SLEEP MODE CONTROL ( ¯
S
¯
¯
L
¯
¯
E
¯
¯
E
¯
¯
P
¯
PIN)
Logic Input VSLP(H) 2.0 – – V
VSLP(L) – – 0.8 V
Input Leakage ISLP(lkg) – 50 – μA
I2C™-COMPATIBLE INTERFACE
Logic Input (SDA,SCL) Low Level VSCL(L) – – 0.8 V
Logic Input (SDA,SCL) High Level VSCL(H) 2.0 – – V
Logic Input Hysteresis VI2CIHYS – 150 – mV
Logic Input Current II2CI VI2CI = 0 to 5 V –1 <±1.0 1 µA
Logic Output Voltage SDA and IRQ VSDA
, VIRQ ILOAD = 3 mA – – 0.4 V
Logic Output Leakage SDA and IRQ ILEAK VLNB = 0 to 5 V – – 10 µA
SCL Clock Frequency fCLK – – 400 kHz
I2C™ ADDRESS SETTING
ADD Voltage for Address 0001,000 VADD1 0 – 0.7 V
ADD Voltage for Address 0001,001 VADD2 1.3 – 1.7 V
ADD Voltage for Address 0001,010 VADD3 2.3 – 2.7 V
ADD Voltage for Address 0001,011 VADD4 3.0 – 5.0 V
[1] Operation at 16 V may be limited by power loss in the linear regulator.
[2] Indicates specifications guaranteed from 0 ≤ TJ ≤ 125˚CMIN .
[3] Ensured by worst case process simulations and system characterization. Not production tested.
[4] LNB output ripple and noise are dependent on component selection and PCB layout. Refer to the Application Schematic and PCB layout
recommendations. Not production tested.
[5] Current from the LNB output may be limited by the choice of Boost components.
Single LNB Supply and Control Voltage Regulator
A8304
7
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
FUNCTIONAL DESCRIPTION
Boost Converter/Linear Regulator
TheA8304solutioncontainsatrackingcurrent-modeboost
converterandlinearregulator.Theboostconvertertracksthe
requestedLNBvoltagetowithin800mV,tominimizepower
dissipation.Underconditionswheretheinputvoltage,VBOOST
,
isgreaterthantheoutputvoltage,VLNB,thelinearregulatormust
dropthedifferentialvoltage.Whenoperatingintheseconditions,
caremustbetakentoensurethatthesafeoperatingtemperature
rangeoftheA8304isnotexceeded.
Theboostconverteroperatesat704kHztypical.Alltheloop
compensation,currentsensing,andslopecompensationfunctions
areprovidedinternally.
TheA8304hasinternalpulse-by-pulsecurrentlimitingonthe
boostconverterandDCcurrentlimitingontheLNBoutputto
protecttheICagainstshortcircuits.WhentheLNBoutputis
shorted,theLNBoutputcurrentislimited,andiftheovercur-
rentconditionlastsformorethan45ms,theLNBoutputwill
bedisabled.Ifthisoccurs,theA8304outputmustbereenabled
fornormaloperation.Thesystemshouldprovidesufficienttime
betweensuccessiverestartstolimitinternalpowerdissipation;
1to2secondsisrecommended.
Atextremelylightloads,theboostconverteroperatesinapulse-
skippingmode.PulseskippingoccurswhentheBOOSTvoltage
risestoapproximately450mVabovetheBOOSTtargetoutput
voltage.PulseskippingstopswhentheBOOSTvoltagedrops
200mVbelowthepulseskippinglevel.
TwoormoresatellitesettopboxesLNBRoutputsmaybecon-
nectedtogether(forexampleinthecasewhenasplitterisused).
Inthiscase,theA8304thathasthehighestprogrammedvoltage
willsupplytheLNBandallotherA8304swilleffectivelybeoff.
IftheoutputoftheA8304ICsupplyingtheLNBdropsbelow
theprogrammedvalueofthenexthighestvoltageA8304,that
unitwillautomaticallyrecoverfromprovidingno-outputvoltage,
monotonicallystartupandsupplythevoltageatitsprogrammed
level.ThisunitwillsupplytheLNBpower.
Charge Pump. Generatesasupplyvoltageabovetheinternal
trackingregulatoroutputtodrivethelinearregulatorcontrol.
LNB and BOOST Current Limits.TheLNBoutputcurrentlimit,
ILNB(MAX)canbesetbyconnectingaresistor(RSET)fromthe
ISETpintoGNDasshowninthefunctionalblockdiagram.
Forexample300mAand500mAsettingswouldcorrespondto
RSETvaluesof100kΩand60.4kΩrespectively,perequation1.
TheLNBcurrentlimithasasetrangeof250to950mA,with
themaximumvaluedependentonthermaldesignparametersofa
givenapplication.IftheLNBcurrentlimitisexceededformore
thantheOvercurrentDisableTime(tDIS)thentheA8304willbe
shutdownandtheOCPbitset,asshowninfigure1.Thetypical
LNBoutputcurrentlimitcanbesetaccordingtothefollowing
equation:
I
LNB(MAX)=29,925/RSET, (1)
whereILNB(MAX)isinmAandRSETisinkΩ.Ifthevoltageat
theISETpinis0V(thatis,shortedtoGND),ILNB(MAX)will
beclampedtoamoderatelyhighvalue(approximately1.5A).
CareshouldbetakentoensurethatISETisnotinadvertently
grounded.IfnoresistorisconnectedtotheISETpin(thatis,if
ISETisopen-circuit),ILNB(MAX)willbesettoapproximately
0AandtheA8304willnotsupportanyload(OCPwilloccur
prematurely).
TheBOOSTpulse-by-pulsecurrentlimit,IBOOST(MAX),isauto-
maticallyscaledalongwiththeLNBoutputcurrentlimit.The
typicalBOOSTcurrentlimitissetaccordingtothefollowing
equation:
I
BOOST(MAX)=3×ILNB(MAX)+1100mA, (2)
wherebothIBOOST(MAX)andILNB(MAX)areinmA.
AutomaticallyscalingtheBOOSTcurrentlimitallowsthe
designertochoosethelowestpossiblesaturationcurrentofthe
boostinductor,reducingitsphysicalsizeandPCBarea,thus
minimizingcost.
Protection
TheA8304hasawiderangeofprotectionfeaturesandfaultdiag-
nosticswhicharedetailedintheStatusRegistersection.
Slew Rate Control.Duringeitherstart-up,orwhentheoutput
voltageattheLNBpinistransitioning,theoutputvoltagerise
andfalltimescanbesetbythevalueofthecapacitorconnected
fromtheTCAPpintoGND(C7inthefunctionalblockdiagram).
Notethatduringstart-up,theBOOSTpinispre-chargedtothe
inputvoltageminusavoltagedrop.Asaresult,theslewrate
controlfortheBOOSTpinoccursfromthisvoltage.
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Figure 1. Startup, Reconfiguration, and Short Circuit operation using RSET = 60.4 kΩ, and a capacitive load
(OCP_25P bit = 0).
I
LNB
V
LNB
I
LNB
(MAX)
I
LNB
(MAX)
0 V
0 mA
13.3 to 15.6 V
18.6 to 19.6 V
ENB
PNG
DIS
OCP
Startup
t < t
DIS
Reconfiguration
t < t
DIS
t > t
DIS
500 mA
Short Circuit
or Overload
ThevalueofC7canbecalculatedusingthefollowingformula:
C7=(ITCAP×6)/SR, (3)
whereSRistherequiredslewrateoftheLNBoutputvoltage,in
V/s,andITCAPistheTCAPpincurrentspecifiedintheElectrical
Characteristicstable.TherecommendedvalueforC7,100nF,
shouldprovidesatisfactoryoperationformostapplications.
TheminimumvalueofC7is10nF.Thereisnotheoreticalmaxi-
mumvalueofC7,howevertoolargeavaluewillprobablycause
thevoltagetransitionspecificationtobeexceeded.Tonegenera-
tionisunaffectedbythevalueofC7.
Pull-Down Rate Control. Inapplicationsthathavetooperateat
verylightloadsandthatrequirelargeloadcapacitances(inthe
orderoftenstohundredsofmicrofarads),theoutputlinearstage
providesapproximately30mAofpull-downcapability,with
TONECTRL=0.ThisensuresthattheLNBoutputvoltageis
rampedfrom18to13Vinareasonableamountoftime.When
thetoneison(TONECTRL=1),theoutputlinearstagemust
increaseitspull-downcapabilitytoapproximately60mA.This
ensuresthatthetonesignalmeetsallspecifications,evenwithno
loadontheLNBoutput.
ODT (Overcurrent Disable Time)
IftheLNBoutputcurrentexceedsthesetoutputcurrent,formore
thantDIS,thentheLNBoutputwillbedisabledandtheOCPbit
willbeset.Seefigure1.
Short Circuit Handling
A8304hasoptional25%bump-uponcurrentlimitfortDIS/4
period.Thisfeatureisenabled/disabledbysettingorreset-
tingControlRegisterbit0.Whenthisbitisenabled,theoutput
currentlimitwillbe25%morethansetcurrentlimitfortDIS/4
period.AftertDIS
/4period,outputcurrentlimitcomesdownto
thesetlimitandtheOCP_25Pbitisresettozero,Theusermust
setthisbitagaintoenable25%bump-uponthenextcurrentlimit
event.IftheOCP_25PbitiszerowhenLNBoutputisshortedto
ground,theLNBoutputcurrentwillbeclampedtoILNB(MAX).
Iftheshortcircuitconditionlastsformorethan45ms,the
A8304willbedisabledandtheOCPbitwillbeset.Referto
figures9and10.
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In-Rush Current
Atstart-uporduringanLNBreconfigurationevent,atransient
surgecurrentabovethenormalDCoperatinglevelcan
beprovidedbytheA8304.Thiscurrentincreasecanbeashigh
asthesetoutputcurrent,foraslongasrequired,uptoamaxi-
mumof45ms.
TONE GENERATION
TheA8304offerstwooptionsfortonegeneration(figure2).The
TONECTRLpinwiththeTMODEcontrolbitprovidestheneces-
sarycontrol.TheTMODEbitcontrolswhetherthetonesourceis
internalorexternal.
Whentheinternalsourceisused(TMODEbitsetto0),thetone
isgatedwiththeTONECTRLpin.Theinternaltonefrequencyis
22kHz.Note:Thistonecanbegeneratedunderno-loadcondi-
tionsanddoesnotrequireanexternalDiSEqC™filter.
WhentheTMODEbitissetto1,anexternal22-kHztonesignal
canbeappliedtotheTONECTRLpin.Thistonefrequency
appearsattheLNBoutput,VLNBreachestheVLNBreflevelafter
TONECTRLhasbeenlowforlongerthan42µs.
Component Selection
BOOST INDUCTOR
TheA8304isdesignedtooperatewithaboostinductorvalue
of10µH±50%.Theerroramplifierloopcompensation,current
sensegain,andPWMslopecompensationwerechosenforthis
valueofinductor.Theboostinductormustbeabletosupportthe
peakcurrentsrequiredtomaintainthemaximumLNBoutput
currentwithoutsaturating.Figure3canbeusedtodeterminethe
peakcurrentintheinductorgiventheLNBloadcurrent.The
“typical”curveusesVIN=12V,VLNB=19V,L=10µH,and
f=704kHz,whilethe“maximum”curveassumesVIN=9V,
VLNB=20V,L=8µH,andf=633kHz.
BOOST ELECTROLYTIC CAPACITOR
TheA8304isdesignedtooperatewithalow-ESRelectrolytic
boostcapacitorof100µF±25%.TheESRoftheboostcapacitor-
mustbelessthan140mΩortheboostconverterwillbeunstable.
Generalpurposeelectrolyticcapacitorsthatdonotspecifyan
ESRshouldbeavoided.Allegrorecommendsanelectrolytic
capacitorthatisratedtosupportatleast35Vandhasanrmscur-
rentratingtosupportthemaximumLNBload.
Figure 2. Tone generation options
TMODE
TONECTRL
Option 1. TMODE = 0, internal tone gated with TONECTRL.
(V
LNBRef)
(Low)
TMODE
TONECTRL
Option 2. TMODE = 1, external tone applied on TONECTRL pin.
V
LNB
reaches preset level if external tone low for > 42 µs.
(V
LNBRef)
(High)
42 µs
V
LNB
V
LNB
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3500
3250
3000
2750
2500
2250
2000
1750
1500
1250
1000
750
500
250
100 400200 300
Maximum
Output Current (mA)
IBOOST_PEAK (mA)
Typical
500 600 700 800 900 1000
Figure4canbeusedtodeterminethenecessaryrmscurrent
ratingoftheboostcapacitorgiventheLNBloadcurrent.The
“typical”curveusesVIN=12V,VLNB=19V,L=10µH,and
f=704kHzwhilethe“maximum”curveassumesVIN=9V,
VLNB=20V,L=8µH,andf=633kHz.
BOOST FILTERING AND LNB NOISE
TheLNBoutputnoisedependsontheamountofhigh-frequency
noiseattheBOOSTpin.Tominimizethehigh-frequencynoise
attheBOOSTpin,ahighqualityceramiccapacitorshouldbe
placedascloseaspossibletotheBOOSTpin.Allegrorecom-
mendsa1µF,10%or20%,X5RorX7R,1206sizecapacitor,
withatleasta25Vrating.
Forverynoise-sensitiveapplications,asecondaryinductorcan
beaddedbetweenthe100µFandthe1µFboostcapacitors,as
showninfigure5.Thisinductorshouldbeapproximately1µH
andhaveaDCcurrentratingofatleast1ADC.Addingthe1µH
inductorhasbeenshowntoreducetheLNBoutputnoisebyas
muchas50%.Allegrostronglyrecommendshavingprovisions
forthis1µHinductorinthePCBlayout,butonlypopulatingitif
theLNBoutputisfoundtohavetoomuchnoiseaftermeasuring
attheset-topboxF-connector,atfull-load.
SURGE COMPONENTS
Thecircuitshownonpage1ofthisdatasheetincludesD3and
D4forsurgeprotection.ComponentrecommendationsforD3
andD4aregiveninthebill-of-materialsattheendofthisdata-
Figure 5. Application of the secondary boost inductor
BOOSTVCPGNDLX
A8304
Secondary Inductor
13
14 15 161
LX
10 µH 1 µH
100 nF
1206
1.0 µF/ 25 V (min)
100 µF
<140 mΩ
VIN
Figure 3. Boost inductor peak current versus ILNB
Figure 4. Boost capacitor rms current versus ILNB
1200
1100
1000
900
800
700
600
500
400
300
200
100
300200100 400
Maximum
Output Current (mA)
IBOOST_CAP_RMS (mA )
Typical
500 600 700 800 900 1000
sheet.Thisconfigurationandthesecomponentshavesuccess-
fullypassedsurgetestsupto±1000V/500A,witha1.2/50µs
−8/20µscombinationwave.Everyapplicationwillhaveits
ownsurgerequirementsandthesurgesolutioncanbechanged.
However,Allegrostronglyrecommendsincorporatingaformof
surgeprotectiontopreventanypinoftheA8304fromexceeding
itsAbsoluteMaximumvoltageratingsshowninthisdatasheet.
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I2C™-Compatible Interface
TheI2C™interfaceisusedtoaccesstheinternalControland
StatusregistersoftheA8304.Thisisaserialinterfacethatuses
twolines,serialclock(SCL)andserialdata(SDA),connectedto
apositivesupplyvoltageviaacurrentsourceorapull-upresis-
tor.Dataisexchangedbetweenamicrocontroller(master)and
theA8304(slave).ThemasteralwaysgeneratestheSCLsignal.
EitherthemasterortheslavecangeneratetheSDAsignal.The
SDAandSCLlinesfromtheA8304areopen-drainsignalsso
multipledevicesmaybeconnectedtotheI2C™bus.Whenthe
busisfree,boththeSDAandtheSCLlinesarehigh.
SDA and SCL Signals.SDAcanonlybechangedwhileSCLis
low.SDAmustbestablewhileSCLishigh.However,anexcep-
tionismadewhentheI2C™StartorStopconditionisencoun-
tered.SeetheI2C™Communicationsectionforfurtherdetails.
Acknowledge (AK) Bit.TheAcknowledge(AK)bitindicatesa
“goodtransmission”andcanbeusedtwoways.First,iftheslave
hassuccessfullyreceivedeightbitsofeitheranaddressorcontrol
data,itwillpulltheSDAlinelow(AK=0)fortheninthSCL
pulsetosignal“goodtransmission”tothemaster.Second,ifthe
masterhassuccessfullyreceivedeightbitsofstatusdatafromthe
A8304,itwillpulltheSDAlinelowfortheninthSCLpulseto
signal“goodtransmission”totheslave.Thereceiver(eitherthe
masterortheslave)shouldsettheAKbithigh(AK=1orNAK)
fortheninthSCLpulseifeightbitsofdataarenotreceivedsuc-
cessfully.
AK Bit During a Write Sequence.Whenthemastersendscon-
troldata(writes)totheA8304therearethreeinstanceswhereAK
bitsaretoggledbytheA8304.First,theA8304usestheAKbit
toindicatereceptionofavalidseven-bitchipaddressplusaread/
writebit(R/W=0forwrite).Second,theA8304usestheAKbit
toindicatereceptionofavalideight-bitControlregisteraddress.
Third,theA8304usestheAKbittoindicatereceptionofeight
bitsofcontroldata.Thisprotocolisshowninfigure6(A).
AK Bit During a Read Sequence.Whenthemasterreadsstatus
datafromtheA8304therearefourinstanceswhereAKbitsare
sent–threesentbytheA8304andonesentbythemaster.First,
theA8304usestheAKbittoindicatereceptionofavalidseven-
bitchipaddressplusaread/writebit(R/W=0forwrite).Sec-
ond,theA8304usestheAKbittoindicatereceptionofavalid
eight-bitStatusregisteraddress.Third,theA8304usestheAK
bittoindicatereceptionofavalidseven-bitchipaddressplusa
read/writebit(R/W=1forread).Finally,themasterusestheAK
bittoindicatereceivingeightbitsofstatusdatafromtheA8304.
Thisprotocolisshowninfigure6(B).
Figure 6. I2C™ Interface Read and Write Sequences. (A) for the I2C™ Write cycle and (B) for the I2C™ Read cycle.
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
A1 A2 A3 A4 A5 A6 A0 0 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0
AK
AK
Control Register Address
Chip Address
Start
W
SDA
SCL
AK
acknowledge
from LNBR (slave)
acknowledge
from LNBR (slave)
acknowledge
from LNBR (slave)
1
2
3
4
5
6
7
8
9
Control Data
(A) Write to Control Register
D6
D5
D4
D3
D2
D0
D7
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
A1 A2 A3 A4 A5 A6 A0 0 RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0
AK
AK
Status Register Address
Chip Address
Start
W
SDA
SCL
acknowledge
from LNBR (slave)
acknowledge
from LNBR (slave)
1
2
3
4
5
6
7
8
9
1
2
3
4
6
7
8
9
A1 A2 A3 A4 A5 A6 A0 1 RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0
AK
AK
Status Data
Chip Address
Start R
acknowledge
from LNBR (slave)
acknowledge
from master
(B) Read from Status Register
Single LNB Supply and Control Voltage Regulator
A8304
12
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I2C™ Communications
I2C™ Start and Stop Conditions.TheI2C™Startconditionis
definedbyanegativeedgeontheSDAlinewhileSCLishigh.
Conversely,theStopconditionisdefinedbyapositiveedgeon
theSDAlinewhileSCLishigh.TheStartandStopconditions
areshowninfigure6.ItispossiblefortheStartorStopcondition
tooccuratanytimeduringadatatransfer.IfeitheraStartorStop
conditionisencounteredduringadatatransfer,theA8304will
respondbyresettingthedatatransfersequence.
I2C™ Write Cycle Description.WritingtotheA8304Control
registerrequirestransmissionofatotalof27bits—three8-bit
bytesofdataplusanAcknowledgebitaftereachbyte.Writingto
theA8304Controlregisterisshowninfigure6(A).Writingtothe
A8304ControlregisterrequiresachipaddresswithR/W=0,a
Controlregisteraddress,andthecontroldata,asfollows:
• TheChipAddresscycleconsistsofatotalofninebits—
sevenbitsofchipaddress(A6toA0)plusoneread/writebit
(R/W=0)toindicateawritefromthemasterfollowedbyan
Acknowledgebit(AK=
0forreceptionofavalidchipaddress)
fromtheslave.ThechipaddressmustbetransmittedMSB
(A6)first.ThefirstfivebitsoftheA8304chipaddress(A6to
A2)arefixedas00010.Theremainingtwobits(A1andA0)
areusedtoselectoneoffourpossibleA8304chipaddresses.
TheDCvoltageontheADDpinprogramsthechipaddress.
SeetheElectricalCharacteristicstablefortheADDpinvolt-
agesandthecorrespondingchipaddresses.
• TheControlRegisterAddresscycleconsistsofatotalofnine
bits—eightbitsofcontrolregisteraddress(RC7toRC0)from
themasterfollowedbyanAcknowledgebitfromtheslave.The
ControlregisteraddressmustbetransmittedMSB(RC7)first.
TheA8304onlyhasoneControlregistersotheControlregister
addressis00000000.
• TheControlDatacycleconsistsofatotalofninebits—eight
bitsofcontroldata(D7toD0)fromthemasterfollowedby
anAcknowledgebitfromtheslave.Thecontroldatamustbe
transmittedMSBfirst(D7).TheControlregisterbitsareidenti-
fiedintheControlRegistersectionofthisdatasheet.
I2C™ Read Cycle Description.ReadingfromtheA8304Status
registerrequirestransmissionofatotalof36bits—four8-bit
bytesofdataplusanAcknowledgebitaftereachbyte.Reading
theA8304StatusregisterrequiresachipaddresswithR/W=0,a
Statusregisteraddress,anI2C™Stopcondition,anI2C™Start
condition,a“repeated”chipaddresswithR/W=1,andfinally
thestatusdatafromtheA8304.ReadingfromtheA8304Status
registerisshowninfigure6(B).
• This9-bitChipAddresscycleisidenticaltotheChipAd-
dresscyclepreviouslydescribedfortheWriteControlRegis-
tersequence.ItconsistsofA6toA0,plusoneread/writebit
(R/W=0)fromthemaster,followedbyanAcknowledgebit
fromtheslaveandfinallyanI2C™Stopcondition.
• TheStatusRegisterAddresscycleconsistsofatotalofnine
bits—eightbitsofStatusregisteraddress(RS7toRS0)from
themaster,followedbyanAcknowledgebitfromtheslave.
The StatusregisteraddressmustbetransmittedMSB(RS7)
first.TheA8304onlyhasoneStatusregister,sotheStatus
registeraddressisfixedat00000000.
• The“Repeated”ChipAddresscyclebeginswithanI2C™
Startconditionfollowedbya9-bitcycleidenticaltotheChip
AddresscyclepreviouslydescribedfortheWriteControl
Registersequence.ItconsistsofA6toA0,plusoneread/write
bit(R/W=1)fromthemaster,followedbyanAcknowledgebit
fromtheslave.
• TheStatusDatacycleconsistsofatotalofninebits—eightbits
ofstatusdata(RD7toRD0)fromtheslave,followedbyan
Acknowledgebitfromthemaster.Thestatusdataistransmit-
tedMSB(RD7)first.TheStatusregisterbitsareidentifiedin
theStatusRegistersectionofthisdatasheet.
Interrupt Request (IRQ) pin
TheA8304providesaninterruptrequestpin(IRQ),whichisan
open-drain,activelowoutput.Thisoutputmaybeconnected
toacommonIRQlinewithasuitableexternalpull-upresistor
andcanbeusedwithotherI2C™compatibledevicestorequest
attentionfromthemastercontroller.
TheIRQoutputbecomesactive(logiclow)whentheA8304rec-
ognizesafaultcondition.ThefaultconditionsthatwillforceIRQ
activeincludeundervoltagelockout(UVLO),overcurrent
Single LNB Supply and Control Voltage Regulator
A8304
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protection(OCP),andthermalshutdown(TSD).TheUVLO,
OCP,andTSDfaultsarelatchedintheStatusregisterandwill
notbeunlatcheduntiltheA8304Statusregisterissuccessfully
transmittedtothemastercontroller(anAKbitmustbereceived
fromthemaster).SeethedescriptionintheStatusRegistersec-
tionandfigure7forfurtherdetails.
Whenthemasterdevicereceivesaninterrupt,itshouldaddress
allslavesconnectedtotheinterruptlineinsequenceandreadthe
statusregisterofeachtodeterminewhichdeviceisrequesting
attention.Asshowninfigure7,theA8304latchesallconditions
intheStatusregisterandsetstheIRQtologiclowwhenafault
occurs.TheIRQbitisresettologichighandtheStatusregisteris
unlatchedwhenthemasteracknowledgesthestatusdatafromthe
A8304(anAKbitmustbereceivedfromthemaster).
Thedisable(DIS)andPowerNotGood(PNG)conditionsdonot
causeaninterruptandarenotlatchedintheStatusregister.
Stop
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
A1 A2 A3 A4 A5 A6 A0 0 RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0
AK
AK
Status Register Address
Chip Address
Start
W
SDA
IRQ
FAULT event, IRQ set low, Status register latched
SCL
acknowledge
from LNBR (slave)
acknowledge
from LNBR (slave)
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
A1 A2 A3 A4 A5 A6 A0 1 RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0
AK
AK
Status Data
Chip Address
Start R
acknowledge
from LNBR (slave)
acknowledge
from master
Stop
IRQ reset
STATUS
register
unlatched
Figure 7. Fault, IRQ, and Status Register Timing. When a FAULT occurs, the IRQ bit is set to low and the Status
register is latched. The IRQ bit is reset to high when the A8304 acknowledges it is being read. The Status register is
unlatched when the master acknowledges the status data from the A8304.
Figure 8. IRQ and Fault Clearing in Response to Undervoltage at VIN (UVLO),the I2C™ port is active when VIN is
above I2C™ UVLO (6 V when VIN is rising). IRQ transitions low when VIN goes above I2C™ UVLO (6 V, VIN rising),
and the I2C™ Read cycle resets IRQ to logic high even if VIN is below UVLO. Even though IRQ is cleared below
UVLO, one more Read cycle is required after VIN goes above UVLO, to re-enable the A8304. While VIN is falling, IRQ
transitions low when VIN goes below UVLO, and the I2C™ Read cycle resets IRQ to logic high.
V
IN
t
I
2
C™ UVLO (typ),
rising: 6 V, falling: 4.2 V
V
LNB
I
2
C™ Read Cycle
I
2
C™
Inactive
ENABLE Bit
(via I
2
C™)
I
2
C™
Inactive
UVLO
Thresholds
IRQ (active low)
Single LNB Supply and Control Voltage Regulator
A8304
14
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Figure 10. IRQ and Fault Clearing in Response to Thermal Shutdown (TSD). If the LNB junction temperature
rises above 165°C (typ), the LNB output will be shut off, a thermal shutdown fault (TSD) will be latched in the
Status Register, and the IRQ pin will transition low. After a TSD fault, the LNB output does not respond to the
Enable (ENB) bit until an I2C™ Read cycle is executed to report and clear the TSD fault. After a successful I2C™
Read, the IRQ pin transitions high and the A8304 can be re-enabled, provided the junction temperature is below
145°C (typ).
Figure 9. IRQ and Fault Clearing in Response to Overcurrent (OCP). If the LNB output is grounded for more than
45 ms, the LNB output will be shut off, an overcurrent fault (OCP) will be latched in the Status Register, and the IRQ
pin will transition low. After an OCP fault, the LNB output does not respond to the Enable (ENB) bit until an I2C™
Read cycle is executed to report and clear the OCP fault. After a successful I2C™ Read, the IRQ pin transitions high
and the A8304 can be re-enabled, provided the LNB output is no longer grounded. (OCP_25P bit set to 0)
I
LNB
V
LNB
I
LNB(MAX)
45 ms
45 ms
LNB shorted to GND
I
2
C™ Read Cycle
IRQ (acve low)
Enable
(ENB bit, via I
2
C™)
T
J
t
I
2
C™ Read Cycle
IRQ
(active low)
LNB O/P
TSD
Threshold
ENABLE Bit
(via I
2
C™)
TSD Bit
(via I
2
C™)
165°C
145°C
Loss of cooling
or STB overload
Single LNB Supply and Control Voltage Regulator
A8304
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Allegro MicroSystems, LLC
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tDIS
/4
tDIS tDIS tDIS
ILNB
OCP_25P
Bit
I2C™ Read
I2C™ Write
OCP_25P
bit cleared
VLNB
LNB
Shorted
to GND
LNB
Shorted
to GND
LNB
Shorted
to GND
LNB
Shorted
to GND
removed
LNB
Shorted
to GND
removed
1.25 × ILNB(MAX)
ILNB(MAX)
tDIS
/4
Figure 11. Initial 25% current limit bump up with OCP_25P bit enabled, disabled, and changed during current limit condition
with OCP period > tDIS .
Single LNB Supply and Control Voltage Regulator
A8304
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Allegro MicroSystems, LLC
955 Perimeter Road
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tDIS /4
<tDIS <tDIS <tDIS
ILNBx
OCPx_25P
Bit
I2C™ Read
I2C™ Write
VLNB
LNB
Shorted
to GND
LNB
Shorted
to GND
LNB
Shorted
to GND
LNB
Shorted
to GND
removed
LNB
Shorted
to GND
removed
LNB
Shorted
to GND
LNB
Shorted
to GND
removed
1.25 × ILNBx(MAX)
ILNBx(MAX)
LNB
Shorted
to GND
removed
tDIS /4<tDIS /4
Figure 12. Initial 25% current limit bump up with OCP_25P bit enabled, disabled, and changed during current limit condition
with OCP period < tDIS .
Single LNB Supply and Control Voltage Regulator
A8304
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Allegro MicroSystems, LLC
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I2C™-Compatible Interface Timing Diagram
t
SU:STA
t
HD:STA
t
SU:DAT
t
HD:DAT
t
BUF
t
SU:STO
t
HIGH
t
LOW
SD
A
SC
L
I2C™-Compatible Timing Requirements
Characteristics Symbol Min. Typ. Max. Units
Bus Free Time Between Stop/Start tBUF 1.3 – – µs
Hold Time Start Condition tHD:STA 0.6 – – µs
Setup Time for Start Condition tSU:STA 0.6 – – µs
SCL Low Time tLOW 1.3 – – µs
SCL High Time tHIGH 0.6 – – µs
Data Setup Time tSU:DAT 100 – – ns
Data Hold Time [1] tHD:DAT 0 – 900 ns
Setup Time for Stop Condition tSU:STO 0.6 – – µs
Output Fall Time (VfI2COut(H) to VfI2COut(L)) tfI2COut – – 250 ns
[1] For tHD:DAT(min)
, the master device must provide a hold time of at least 300 ns for the SDA
signal in order to bridge the undefined region of the SCL signal falling edge.
Single LNB Supply and Control Voltage Regulator
A8304
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Control Register (I2C™-Compatible Write Registers)
AllmainfunctionsoftheA8304arecontrolledthroughtheI2C™
compatibleinterfaceviathe8-bitControlregister.Table1shows
thefunctionalityandbitdefinitionsoftheControlregister.At
power-up,theControlregisterisinitializedtoall0s.
TheLNBoutputwillbeprogrammedaccordingthestatusofthe
VSEL3,VSEL2,VSEL1,andVSEL0bitsintheI2C™Control
register0asoutlinedintable2.
Table 1. Control Register 0 Definition, Address: 0000 0000
Bit Name Function Description
0 VSEL0 The available voltages provide levels for all the common
standards plus the ability to add line compensation.
VSEL0 is the LSB and VSEL3 is the MSB to the internal
DAC.
LNB output voltage control
See table 2 for available output voltage selections
1 VSEL1
2 VSEL2
3 VSEL3
4 ENB Turns the LNB output on or off. 0: Disable LNB Output
1: Enable LNB Output
5 TMODE Controls tone mode. 0: Internal tone, gated with TONECTRL pin
1: External 22 kHz logic pulse, on TONECTRL pin
6 OCP_25P 25% bump up over the current limit for tDIS / 4 period;
bit resets automatically after tDIS / 4 period
7 SINK_DIS Controls use of internal sinks. 0: Enable internal sinks
1: Disable internal sinks
Table 2. Output Voltage Selection
VSEL3 VSEL2 VSEL1 VSEL0 LNB (V)
0 0 0 0 11.000
0 0 0 1 13.000
0 0 1 0 13.333
0 0 1 1 13.667
0 1 0 1 14.333
0 1 1 1 15.667
1 0 0 1 18.000
1 0 1 1 18.667
1 1 0 0 19.000
1 1 0 1 19.333
1 1 1 0 19.667
Single LNB Supply and Control Voltage Regulator
A8304
19
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Status Registers (I2C™-Compatible Read Register)
Themainfaultconditions:undervoltagelockout(UVLO),over-
current(OCP),andthermalshutdown(TSD)areallindicatedby
settingtherelevantbitsintheStatusregister.Inallfaultcases,
afterthebitisset,itremainslatcheduntiltheI2C™master
hassuccessfullyreadtheA8304,assumingthefaulthasbeen
resolved.
Theundervoltagelockout(UVLO)bitindicateseithertheinput
voltageattheVINpinistoolowortheA8304internalsupply
voltage(VREG)istoolow.
TheDisablebit(DIS)indicatesthestatusoftheLNBoutput.
TheDISissetwheneitherafaultoccurs(UVLO,OCP,TSD,or
CPOK)orwhentheLNBoutputisturnedoffusingtheEnable
bit(ENB)viatheI2C™interface.TheDISbitislatchedandis
onlyresetwhentherearenofaultsandtheA8304outputisturned
backonusingtheEnable(ENB)bitviatheI2C™interface.
ThePowerNotGood(PNG)andChargePumpOK(CPOK)bits
aresetbasedontheconditionssensedattheLNBoutputand
VCPpins,respectively.Thesebitsarenotlatchedand,unlike
theotherfaultbits,maybecomeresetwithoutanI2C™read
sequence.ThePNGandCPOKbitsarecontinuouslyupdated.
TherearethreemethodstodetectwhentheStatusregister
changes:respondingtotheinterruptrequest(IRQ)pingoinglow,
continuouslypollingtheStatusregisterviatheI2C™interface,or
detectingafaultconditionexternaltotheA8304andperforming
adiagnosticpolloftheA8304.Inanycase,themastershould
readandre-readtheStatusregisteruntilthestatuschanges.
Table 3. Status Register Description and IRQ Operation
Bit Name Function Latched? Reset Condition Effect on IRQ Pin
0 DIS LNB output disabled Yes LNB enabled and no faults None
1 CPOK Charge pump OK No VCP > VBOOST + 5 V None
2 OCP Overcurrent Yes I2C™ read and fault removed IRQ set low
3 – Not used – – –
4 PNG Power Not Good No LNB voltage within range None
5 – Not used – – –
6 TSD Thermal shutdown Yes I2C™ read and fault removed IRQ set low
7 UVLO VIN or VREG undervoltage Yes I2C™ read and fault removed IRQ set low
Table 4. Status Register Bit Descriptions
Bit Name Description
0 DIS The DIS bit is set to 1 when the A8304 is disabled, (ENB = 0) or there is a fault: UVLO, OCP, CPOK, or TSD.
1 CPOK If this bit is set low, the internal charge pump is not operating correctly (VCP). If the charge pump voltage is
too low, the LNB output is disabled and the DIS bit is set.
2 OCP This bit will be set to a 1 if the LNB output current exceeds the overcurrent threshold (ILNB(MAX)) for more than
the overcurrent disable time (tDIS). If the OCP bit is set to 1, then the DIS bit is also set to 1.
3 – Not used.
4 PNG
Set to 1 when the A8304 is enabled and the LNB output voltage is either too low or too high (nominally ±9%
from the LNB DAC setting). Set to 0 when the A8304 is enabled and the LNB voltage is within the acceptable
range (nominally ±5% from the LNB DAC setting).
5 – Not used.
6 TSD The TSD bit is set to 1 if the A8304 has detected an overtemperature condition. If the TSD bit is set to 1, then
the DIS bit is also set to 1.
7 UVLO The UVLO bit is set to 1 if either the voltage at the VIN pin or the voltage at the VREG pin is too low. If the
UVLO bit is set to 1, then the DIS bit is also set to 1.
Single LNB Supply and Control Voltage Regulator
A8304
20
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Table 5. Component Selection Table
Component Characteristics Manufacturer Device
C1, C4, C7, C8 100 nF, 50 V, X5R or X7R, 0603
C2, C5 100 µF, 35 VMIN , ESR < 140 mΩ, IRIPPLE > 550 mA
Panasonic: EEU-FM1H101B
ChemiCon: EKZE500ELL101MHB5D
Nichicon: UHC1V101MPT
C3 220 nF, 10 VMIN, X5R or X7R, 0402 or 0603
C6 1.0 µF, 25 VMIN, X5R or X7R, 1206
TDK: C3216X7R1E105K
Murata: GRM31MR71E105KA01
Taiyo Yuden: TMK316BJ105KL-T
Kemet: C1206C105K3RACTU
C9 10 nF, 50 V, X5R or X7R, 0402 or 0603
C10 220 nF, 50 V, X5R or X7R, 0805
D1, D2 Schottky diode, 40 V, 1 A, SOD-123 Diodes, Inc: B140HW-7
Central Semi: CMMSH1-40
D3 Schottky diode, 40 V, 3 A, SMA
Sanken: SFPB-74
Vishay: B340A-E3/5AT
Diodes, Inc.: B340A-13-F
Central Semi: CMSH3-40MA
D4 TVS, 20 VRM, 32 VCL at 500 A (8/20 µs), 3000 W ST: LNBTVS6-221S,
Littelfuse: 3.0SMCJ20A
L1 10 µH, ±20%, 3.4 ASAT
, 45 mΩ Taiyo Yuden- NR8040T100M
R1 to R5 Determined by VDD, bus capacitance, etc.
Single LNB Supply and Control Voltage Regulator
A8304
21
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Package ES 16-Pin QFN
C0.08
17X
ATerminal #1 mark area
BExposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
For reference only, not for tooling use (reference JEDEC MO-220WEED)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
CReference land pattern layout (reference IPC7351
QFN50P300X300X80-17W4M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
16
2
1
A
16
1
2
PCB Layout Reference View
B
1.70
1.70
1.70
1.70
0.30
1
16 0.50
0.90
3.10
3.10
C
C
SEATING
PLANE
0.25 +0.05
–0.07
0.40±0.10
0.50
0.75 ±0.05
3.00 ±0.15
3.00 ±0.15
D
DCoplanarity includes exposed thermal pad and terminals
Single LNB Supply and Control Voltage Regulator
A8304
22
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
I2C™isatrademarkofPhilipsSemiconductors.
DiSEqC™isatrademarkofEutelsatS.A.
For the latest version of this document, visit our website:
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Copyright ©2018, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
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use; nor for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
Revision History
Number Date Description
– August 20, 2013 Initial release
1 July 19, 2016 Updated IRLNB max value for 5th test condition (page 4);
Updated ILNB(MAX) max value (page 5).
2 January 30, 2017 Updated Table 2: Output Voltage Selection (page 18).
3 July 9, 2018 Minor editorial updates