List of Figures
Figure 1: 1Gb Mobile LPDDR Part Numbering .................................................................................................. 2
Figure 2: Functional Block Diagram (x16) ......................................................................................................... 9
Figure 3: Functional Block Diagram (x32) ....................................................................................................... 10
Figure 4: 60-Ball VFBGA – Top View, x16 only .................................................................................................. 11
Figure 5: 90-Ball VFBGA – Top View, x32 only .................................................................................................. 12
Figure 6: 168-Ball FBGA – 12mm x 12mm (Top View), x32 only ........................................................................ 13
Figure 7: 60-Ball VFBGA (8mm x 9mm), Package Code: BF .............................................................................. 16
Figure 8: 90-Ball VFBGA (8mm x 13mm), Package Code: B5 ............................................................................. 17
Figure 9: 168-Ball WFBGA (12mm x 12mm), Package Code: MA ....................................................................... 18
Figure 10: Typical Self Refresh Current vs. Temperature .................................................................................. 28
Figure 11: ACTIVE Command ........................................................................................................................ 40
Figure 12: READ Command ........................................................................................................................... 41
Figure 13: WRITE Command ......................................................................................................................... 42
Figure 14: PRECHARGE Command ................................................................................................................ 43
Figure 15: DEEP POWER-DOWN Command ................................................................................................... 44
Figure 16: Simplified State Diagram ............................................................................................................... 50
Figure 17: Initialize and Load Mode Registers ................................................................................................. 52
Figure 18: Alternate Initialization with CKE LOW ............................................................................................ 53
Figure 19: Standard Mode Register Definition ................................................................................................. 54
Figure 20: CAS Latency .................................................................................................................................. 57
Figure 21: Extended Mode Register ................................................................................................................ 58
Figure 22: Status Read Register Timing ........................................................................................................... 60
Figure 23: Status Register Definition .............................................................................................................. 61
Figure 24: READ Burst ................................................................................................................................... 64
Figure 25: Consecutive READ Bursts .............................................................................................................. 65
Figure 26: Nonconsecutive READ Bursts ........................................................................................................ 66
Figure 27: Random Read Accesses .................................................................................................................. 67
Figure 28: Terminating a READ Burst ............................................................................................................. 68
Figure 29: READ-to-WRITE ............................................................................................................................ 69
Figure 30: READ-to-PRECHARGE .................................................................................................................. 70
Figure 31: Data Output Timing – tDQSQ, tQH, and Data Valid Window (x16) .................................................... 71
Figure 32: Data Output Timing – tDQSQ, tQH, and Data Valid Window (x32) .................................................... 72
Figure 33: Data Output Timing – tAC and tDQSCK .......................................................................................... 73
Figure 34: Data Input Timing ......................................................................................................................... 75
Figure 35: Write – DM Operation .................................................................................................................... 76
Figure 36: WRITE Burst ................................................................................................................................. 77
Figure 37: Consecutive WRITE-to-WRITE ....................................................................................................... 78
Figure 38: Nonconsecutive WRITE-to-WRITE ................................................................................................. 78
Figure 39: Random WRITE Cycles .................................................................................................................. 79
Figure 40: WRITE-to-READ – Uninterrupting ................................................................................................. 80
Figure 41: WRITE-to-READ – Interrupting ...................................................................................................... 81
Figure 42: WRITE-to-READ – Odd Number of Data, Interrupting ..................................................................... 82
Figure 43: WRITE-to-PRECHARGE – Uninterrupting ....................................................................................... 83
Figure 44: WRITE-to-PRECHARGE – Interrupting ........................................................................................... 84
Figure 45: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting .......................................................... 85
Figure 46: Bank Read – With Auto Precharge ................................................................................................... 88
Figure 47: Bank Read – Without Auto Precharge .............................................................................................. 89
Figure 48: Bank Write – With Auto Precharge .................................................................................................. 90
Figure 49: Bank Write – Without Auto Precharge ............................................................................................. 91
Figure 50: Auto Refresh Mode ........................................................................................................................ 92
1Gb: x16, x32 Mobile LPDDR SDRAM
Features
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1gb_ddr_mobile_sdram_t68m.pdf - Rev. I 10/13 EN 5Micron Technology, Inc. reserves the right to change products or specifications without notice.
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