41 dB Range, 1 dB Step Size,
Programmable Dual VGA
AD8372
Rev. 0
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
FEATURES
Dual independent digitally controlled VGA
Differential input and output
150 Ω differential input
Open-collector differential output
7.8 dB noise figure to 100 MHz @ maximum gain
HD2/HD3 better than 77 dBc for 1 V p-p differential output
−3 dB bandwidth of 150 MHz
41 dB gain range
1 dB step size ± 0.2 dB
Serial 8-bit bidirectional SPI control interface
Wide input dynamic range
Pin-programmable output stage
Power-down feature
Single 5 V supply: 106 mA per channel
32-lead LFCSP, 5 mm × 5 mm package
APPLICATIONS
Differential ADC drivers
CMTS upstream direct sampling receivers
CATV modem signal scaling
Generic RF/IF gain stages
Single-ended-to-differential conversion
FUNCTIONAL BLOCK DIAGRAM
ENB1
IPC1
INC1
CLK1
RXT2
LCH1
IPC2
INC2
REF1
SDI1
SDO1
REF2
OPC1
ONC1
RXT2
SDI2
LCH2
OPC2
ENB2
ONC2
SDO2
CLK2
POSTAMP
CHANNEL 1
POSTAMP
CHANNEL 2
REGISTERS
AND
GAIN DECODER
AD8372
07051-001
Figure 1.
GENERAL DESCRIPTION
The AD8372 is a dual, digitally controlled, variable gain
amplifier that provides precise gain control, high IP3, and
low noise figure. The excellent distortion performance and
moderate signal bandwidth make the AD8372 a suitable
gain control device for a variety of multichannel receiver
applications.
For wide input dynamic range applications, the AD8372
provides a broad 41 dB gain range. The gain is programmed
through a bidirectional 4-pin serial interface. The serial inter-
face consists of a clock, latch, data input, and data output lines
for each channel.
The AD8372 provides the ability to set the transconductance of
the output stage using a single external resistor. The RXT1 and
RXT2 pins provide a band gap derived stable reference voltage
of 1.56 V. Typically 2.0 k shunt resistors to ground are used to
set the maximum gain to a nominal value of 31 dB. The current
setting resistors can be adjusted to manipulate the gain and
distortion performance of each channel. This is a flexible
feature in applications where it is desirable to trade off distortion
performance for lower power consumption.
The AD8372 is powered on by applying the appropriate logic
level to the ENB1, ENB2 pins. When powered down, the AD8372
consumes less than 2.6 mA and offers excellent input-to-output
isolation. The gain setting is preserved when powered down.
Fabricated on an Analog Devices high frequency BiCMOS
process, the AD8372 provides precise gain adjustment capabilities
with good distortion performance. The quiescent current of the
AD8372 is typically 106 mA per channel. The AD8372 amplifier
comes in a compact, thermally enhanced 5 mm × 5 mm 32-lead
LFCSP package and operates over the temperature range of
−40°C to +85°C.
AD8372
Rev. 0 | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Serial Control Interface Timing ................................................. 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ..............................................8
Theory of Operation ...................................................................... 10
Single-Ended and Differential Signals..................................... 10
Passive Filter Techniques........................................................... 10
Digital Gain Control .................................................................. 10
Driving Analog-to-Digital Converters.................................... 10
Evaluation Board Schematic ......................................................... 12
Outline Dimensions ....................................................................... 13
Ordering Guide .......................................................................... 13
REVISION HISTORY
11/07—Revision 0: Initial Version
AD8372
Rev. 0 | Page 3 of 16
SPECIFICATIONS
VS = 5 V, T = 25°C, ZS = 150 Ω, ZL = 250 Ω at 35 MHz, 1 V p-p differential output, RXT1 = RXT2 = 2.0 k, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth VOUT < 1 V p-p, CLOAD < 3pF 130 MHz
INPUT STAGE Pin IPCI, Pin INC1, Pin IPC2, and Pin INC2
Maximum Input Swing at Each Input Pin 5 V p-p
Input Resistance Differential 150 Ω
Common-Mode Input Voltage 2.4 V
CMRR Gain code = 1x101010 (max gain) 55 dB
GAIN
Maximum Voltage Gain Gain code = 1x101010 32 dB
Minimum Voltage Gain Gain code = 1x000001 −9 dB
Gain Step Size From gain code 1x000001 to 1x101010 1.0 dB
Gain Step Accuracy From gain code 1x000001 to 1x101010 ±0.3 dB
Gain Flatness Gain code = 1x101010, from 5 MHz to 65MHz 0.7 dB
Gain Temperature Sensitivity Gain code = 1x101010 7.5 mdB/°C
Step Response For 6 dB gain step, 10% settling 20 ns
OUTPUT STAGE Pin OPCI, Pin ONC1, Pin OPC2, and Pin ONC2
Output Voltage Swing At P1dB, gain code = 1x101010 9 V p-p
Output Resistance Differential 3.5 kΩ
Channel Isolation Measured at differential output for differential input
applied to alternate channel
55 dB
NOISE/HARMONIC PERFORMANCE
5 MHz Gain code = 1x101010 (max gain)
Noise Figure 7.8 dB
Second Harmonic 79 dBc
Third Harmonic 91 dBc
Output IP3 32 dBm
Output 1 dB Compression Point 18.2 dBm
35 MHz Gain code = 1x101010 (max gain)
Noise Figure 7.8 dB
Second Harmonic 79 dBc
Third Harmonic 87 dBc
Output IP3 35 dBm
Output 1 dB Compression Point 18.1 dBm
65 MHz Gain code = 1x101010 (max gain)
Noise Figure 7.9 dB
Second Harmonic 78 dBc
Third Harmonic 85 dBc
Output IP3 35 dBm
Output 1 dB Compression Point 17.9 dBm
85 MHz Gain code = 1x101010
Noise Figure 8.1 dB
Second Harmonic 77 dBc
Third Harmonic 85 dBc
Output IP3 35 dBm
Output 1 dB Compression Point 17.7 dBm
AD8372
Rev. 0 | Page 4 of 16
Parameter Conditions Min Typ Max Unit
POWER INTERFACE
Supply Voltage 4.5 5.5 V
Quiescent Current per Channel Thermal connection made to exposed paddle under
device
106 mA
vs. Temperature −40°C ≤ TA ≤ +85°C 135 mA
Power-Down Current, Both Channels ENB1 and ENB2 low 1.2 mA
vs. Temperature −40°C ≤ TA ≤ +85°C 1.3 mA
ENABLE INTERFACE Pin ENB1 and Pin ENB2
Enable Threshold Minimum voltage to enable the device 0.8 V
ENB1, ENB2 Input Bias Current ENB1, ENB2 = 0 V 400 nA
GAIN CONTROL INTERFACE Pin CLK1, Pin CLK2, Pin SDI1, Pin SDI2, Pin SDO1, Pin
SDO2, Pin LCH1, and Pin LCH2
VIH Minimum voltage for a logic high 2.4 V
Input Bias Current 400 nA
Serial Port Output Feedthrough Worse-case feedthrough from CLK1, CLK2, SDI1,
SDI2, SDO1, SDO2, LCH1, LCH2 to OPC1 and ONC2,
or OPC2 and ONC2
−60 dB
Table 2. Gain Code vs. Voltage Gain Look-Up Table
8-Bit Binary Gain Code1Voltage Gain (dB)
RW DC 000000 < −60
RW DC 000001 −9
RW DC 000010 −8
RW DC 000011 −7
RW DC 000100 −6
RW DC 000101 −5
RW DC 000110 −4
RW DC 000111 −3
RW DC 001000 −2
RW DC 001001 −1
RW DC 001010 0
RW DC 001011 +1
RW DC 001100 +2
RW DC 001101 +3
RW DC 001110 +4
RW DC 001111 +5
RW DC 010000 +6
RW DC 010001 +7
RW DC 010010 +8
RW DC 010011 +9
RW DC 010100 +10
RW DC 010101 +11
1 RW is the Read/Write bit, RW = 0 for read mode, RW = 1 for write mode. DC is
the Don’t Care bit.
8-Bit Binary Gain Code1Voltage Gain (dB)
RW DC 010110 +12
RW DC 010111 +13
RW DC 011000 +14
RW DC 011001 +15
RW DC 011010 +16
RW DC 011011 +17
RW DC 011100 +18
RW DC 011101 +19
RW DC 011110 +20
RW DC 011111 +21
RW DC 100000 +22
RW DC 100001 +23
RW DC 100010 +24
RW DC 100011 +25
RW DC 100100 +26
RW DC 100101 +27
RW DC 100110 +28
RW DC 100111 +29
RW DC 101000 +30
RW DC 101001 +31
RW DC 101010 +32
RW DC 101011 < −60
AD8372
Rev. 0 | Page 5 of 16
SERIAL CONTROL INTERFACE TIMING
07051-003
DON'T CAREWRITE BIT LSB LSB + 1 LSB + 2 MSB – 2 MSB – 1 MSB
t
DH
t
DS
t
LH
t
LS
t
PW
t
CLK
NOTES
1. THE FIRST SDI BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL GAIN WORD REGISTER. FOR A
WRITE OPERATION, THE FIRST BIT SHOULD BE A HIGH LOGIC LEVEL, FOR A READ OPERATION THE FIRST BIT SHOULD BE A LOGIC 1.
THE GAIN WORD BIT IS THEN REGISTERED INTO THE SDI PIN ON THE NEXT RISING CLOCK.
CLK1 OR CLK2
LCH1 OR LCH2
SDI1 OR SDI2
Figure 2. Write Mode Timing Diagram
07051-004
t
LH
t
DH
t
DS
t
LS
t
PW
t
CLK
DCDCREAD BIT DC DC DC DC DC
LSB LSB + 1 LSB + 2 MSB – 2 MSB – 1 MSB
NOTES
1. THE GAIN WORD BIT IS UPDATED AT THE SDO PIN ON THE FALLING CLOCK EDGE.
CLK1 OR CLK2
LCH1 OR LCH2
SDI1 OR SDI2
SDO1 OR SDO2
t
D
Figure 3. Read Mode Timing Diagram
Table 3. Serial Programming Timing Parameters
Parameter Min Unit
Clock Pulse Width (tPW) 10 ns
Clock Period (tCK) 20 ns
Write Mode
Setup Time Data vs. Clock (tDS) 0.0 ns
Hold Time Data vs. Clock (tDH) 1.6 ns
Setup Time Latch vs. Clock (tLS) −1.8 ns
Hold Time Latch vs. Clock (tLH) 2.0 ns
Read Mode
Clock to Data Out (tD) 4.5 ns
AD8372
Rev. 0 | Page 6 of 16
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage, VS 5.5 V
ENB1, ENB2, SDI1, SDI2, SDO1, SDO2,
CLK1, CLK2, LCH1, LCH2
VS + 500 mV
Differential Input Voltage, VIPC1 − VINC1,
VIPC2 − VINC2
V p-p
Internal Power Dissipation 1.4 W
θJA (Exposed Paddle Soldered Down) 34.6°C/W1, 2
θJC (At Exposed Paddle) 3.6°C/W2
Maximum Junction Temperature 150°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
1 Still air.
2 All values are modeled using a standard 4-layer JEDEC test board with the
pad soldered to the board and thermal vias in the board.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD8372
Rev. 0 | Page 7 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1DVS1
2LCH1
3SDI1
4CLK1
5CLK2
6SDI2
7LCH2
8DVS2
24 OPC1
23 ONC1
22 AGD1
21 SDO1
20 SDO2
19 AGD2
18 ONC2
17 OPC2
9
DGD2
10
INC2
11
IPC2
12
REF2
13
RXT2
14
AGD2
15
ENB2
16
AVS2
32 DGD1
31 INC1
30 IPC1
29 REF1
28 RXT1
27 AGD1
26 ENB1
25 AVS1
TOP VIEW
(Not to Scale)
AD8372
07051-002
Figure 4. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 DVS1 Digital Supply Pin for Channel 1
2 LCH1 Latch Input for Channel 1
3 SDI1 Serial Data Input for Channel 1
4 CLK1 Clock Input for Channel 1
5 CLK2 Clock Input for Channel 2
6 SDI2 Serial Data Input for Channel 2
7 LCH2 Serial Data Input for Channel 2 Latch Input for Channel 2
8 DVS2 Digital Supply Pin for Channel 2
9 DGD2 Digital Ground for Channel 2
10 INC2 Negative Input for Channel 2
11 IPC2 Positive Input for Channel 2
12 REF2 Reference Voltage for Channel 2
13 RXT2 External Bias Setting Resistor Connection for Channel 2
14 AGD2 Analog Ground for Channel 2
15 ENB2 Chip Enable Pin for Channel 2
16 AVS2 Analog Supply Pin for Channel 2
17 OPC2 Positive Output for Channel 2
18 ONC2 Negative Output for Channel 2
19 AGD2 Analog Ground for Channel 2
20 SDO2 Serial Data Output for Channel 2
21 SDO1 Serial Data Output for Channel 1
22 AGD1 Analog Ground for Channel 1
23 ONC1 Negative Output for Channel 1
24 OPC1 Positive Output for Channel 1
25 AVS1 Analog Supply Pin for Channel 1
26 ENB1 Chip Enable Pin for Channel 1
27 AGD1 Analog Ground for Channel 1
28 RXT1 External Bias Setting Resistor Connection for Channel 1
29 REF1 Reference Voltage for Channel 1
30 IPC1 Positive Input for Channel 1
31 INC1 Negative Input for Channel 1
32 DGD1 Digital Ground for Channel 1
AD8372
Rev. 0 | Page 8 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25°C, ZS = 150 , ZL = 250 Ω, 1 V p-p differential output, both channels enabled, unless otherwise noted.
07051-005
FREQUENCY (Hz)
VOLTAGE GAIN (dB)
–30
–20
–10
0
10
20
30
40
1M 10M 100M 1G
Figure 5. Gain vs. Frequency by Gain Code (All Codes),
Differential In, Differential Out
–100
–95
–90
–85
–80
–75
–70
–65
–
60
0 102030405060708090
HD3
07051-006
FREQUENCY (MHz)
HARMONIC DISTORTION (dBc)
HD2
Figure 6. 2nd and 3rd Harmonic Distortion
07051-007
0
10
20
30
40
50
60
70
80
90
100
0 102030405060708090
FREQUENCY (MHz)
OIP2/OIP3 (dBm)
OIP3 – A
V
= 32
OIP2 – A
V
= 32
OIP3 – A
V
= 10
OIP3 – A
V
= –9
OIP2 – A
V
= 10
OIP2 – A
V
= –9
Figure 7. OIP2 and OIP3
15
16
17
18
19
20
+25°C
+85°C
–40°C
07051-008
0 102030405060708090
FREQUENCY (MHz)
OUTPUT REFERRED P1dB (dBm)
Figure 8. P1dB, Maximum Gain
07051-009
0
FREQUENCY (MHz)
RESISTANCE (Ω)
0
20
40
60
80
100
120
140
160
180
50000000
100000000
150000000
200000000
250000000
300000000
0
1
2
3
4
5
6
7
8
9
CAPACITANCE (pF)
Figure 9. Input Equivalent Parallel Impedance
07051-010
FREQUENCY (MHz)
CMRR (dB)
0
10
20
30
40
50
60
70
0 102030405060708090100
Figure 10. CMRR vs. Frequency
AD8372
Rev. 0 | Page 9 of 16
0
5
10
15
20
25
30
35
40
45
50
20 40 60 80 100 120 140 160 180 200
A
V
= 10dB
A
V
= 20dB
A
V
= 32dB
07051-012
0
FREQUENCY (MHz)
NOISE FIGURE (dB)
A
V
= 0dB
Figure 11. Noise Figure vs. Frequency
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
07051-013
FREQUENCY (Hz)
(dB)
1M 10M 100M 1G
Figure 12. Isolation, Input to Opposite Output at Maximum Gain
(To calculate output to output gain, subtract 29 dB from this plot)
07051-011
20ns/DIV
Figure 13. AD8372 Response to 6 dB Step Change in Gain (Gain Register
Setting 36 to Setting 42); Falling Edge Shown is Serial Clock Input Edge
AD8372
Rev. 0 | Page 10 of 16
THEORY OF OPERATION
The AD8372 is a dual differential variable gain amplifier. Each
amplifier consists of a 150 digitally controlled 6 dB attenuator
followed by a 1 dB vernier and a fixed gain transconductance
amplifier.
The differential output on each amplifier consists of a pair of
open-collector transistors. It is recommended that each open-
collector output be biased to +5 V with a high value inductor.
A 33 H inductor, such as the Coilcraft® 1812LS-333XJL, is an
excellent choice for this component. A 250 resistor should be
placed across the differential outputs to provide a current-to-
voltage conversion and as a source impedance for passive
filtering, post AD8372.
The gain for each side is based on a 250 differential load and
varies as the RLOAD changes per the following equations:
Gain = 20log(RLOAD/250), for voltage gain
Gain = 10log(RLOAD/250), for power gain
The dependency of the gain on the load is due to the open-
collector output stage that is biased using external chokes. The
inductance of the chokes and the resistance of the load deter-
mine the low frequency pole of the amplifier. The high frequency
pole is set by the parasitic capacitance of the chokes and outputs
in parallel with the output resistance.
The total supply current of 106 mA per side consists of 70 mA
for the combined outputs and about 36 mA through the power
supply pins. Each side has an external resistor (REXT) to ground
to set the transconductance of the output stage. For optimum
distortion, 106 mA total current per side is recommended,
making the REXT value about 2.0 k. Each side has a 2.4 V
reference pin and that same common-mode voltage appears on
the inputs. This reference should be decoupled using a 0.1 F
capacitor. The part can be powered down to less than 2.6 mA by
setting the ENB pin low for the appropriate side.
The noise figure of the AD8372 is 7.8 dB at maximum gain and
increases as the gain is reduced. The increase in noise figure is
equal to the reduction in gain.
The linearity of the part measured at the output is first-order
independent of the gain setting.
Layout considerations should include minimizing capacitance
on the outputs by avoiding ground planes under the chokes, and
equalizing the output line lengths for phase balance.
SINGLE-ENDED AND DIFFERENTIAL SIGNALS
The AD8372 was designed to be used by applying differential
signals to the inputs and using the differential output drive of
the device to drive the next device in the signal chain. The
excellent distortion performance of the AD8372 is due
primarily to the use of differential signaling techniques to
cancel various distortion components in the device. In addition,
all ac characterization was done using differential signal paths.
Using this device with either the input or the output in a single-
ended circuit significantly degrades the overall performance of
the AD8372.
PASSIVE FILTER TECHNIQUES
The AD8372 has a 100 differential input impedance. For
optimal performance, the differential output load should be
250 . When designing passive filters around the AD8372,
these impedances must be taken into account.
DIGITAL GAIN CONTROL
The digital gain control interface consists of four pins: SDI,
SDO, CLK, and LATCH. The interface is active when the
LATCH pin is shifted low. Gain words are written into the
AD8372 via the SDI pin, and read back from the SDO pin. The
first bit clocked into the data input pin determines whether the
interface is in write or read mode. The second bit is a don’t care
bit, while the remaining six bits program the gain. In read
mode, the SDO pin clocks out the 6-bit gain word, LSB to MSB.
The gain can be programmed between −9 dB and 32 dB in 1 dB
steps. Timing details are given in Figure 2 and Figure 3. The
gain code table is given in Table 3.
DRIVING ANALOG-TO-DIGITAL CONVERTERS
The AD8372 was designed with the intention of driving high
speed, high dynamic range ADCs. The circuit in Figure 14
represents a simplified front end of one-half of the AD8372 dual
VGA driving an AD9445 14-bit, 125 MHz analog-to-digital
converter. The input of the AD8372 is driven differentially
using a 1:3 impedance ratio transformer, which also matches
the 150 input resistance to a 50 source. The open-collector
outputs are biased through the 33 H inductors and are ac-
coupled from the 142 load resistors that, in parallel with the
2 k input resistance of the ADC, provide a 250 load for gain
accuracy. The ADC is ac-coupled from the 142 resistors to
negate a dc affect on the input common-mode voltage of the
AD9445. Including the series 33 resistors improves the
isolation of the AD8372 from the switching currents caused by
the ADC input sample and hold. The AD9445 represents a 2 k
differential load and requires a 2 V p-p signal when VREF = 1 V
for a full-scale output. This circuit provides variable gain,
isolation, and source matching for the AD9445. Using this
circuit with the AD8372 in a gain of 32 dB (maximum gain), an
SFDR performance of 74.5 dBc is achieved at 85 MHz. See
Figure 15.
AD8372
Rev. 0 | Page 11 of 16
07051-018
0.1µF
0.1µF
33µH 142Ω
33Ω
33Ω
142Ω
5V
5
V
50Ω
AC
1:3
CKL1
SD01
ENA1
½
AD8372
VGA
0.1µF
0.1µF
0.1µF
0.1µF
33µH
5V
VIN+
VIN–
AD9445
14-BIT ADC
14
Figure 14. AD8372 Driving an AD9445 ADC
–150
–140
–130
–120
–110
–100
–80
–70
–90
–60
–40
–30
–50
–20
–10
0
07051-019
FREQUENCY (MHz)
(dBc)
5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25 52.500
5 6 4
1
2
3
ENCODE: 105MHz
SAMPLES: 32768
ANALOG: 19.8766MHz
FUND: –1.053dBFS
2ND: –74.55dBc
3RD: –86.45dBc
4TH: –91.35dBc
5TH: –89.57dBc
6TH: –91.15dBc
SNR: 58.12dBc
SNRFS: 59.18dBc
THD: –73.99dBc
SINAD: 58.01dBc
SFDR: 74.73dBc
WO SPUR: –85.5dBc
NOISE FLOOR: –101.3dB
FUND LEAK: 100
HARM LEAK: 3
DC LEAK: 6
Figure 15. 74.5 dB SFDR Performance of the AD8372 Driving the AD9445 ADC
AD8372
Rev. 0 | Page 12 of 16
EVALUATION BOARD SCHEMATIC
07051-014
R0603
0
R0603
AGND
0
R0603
AGND
AGND
AGND
0
R0603
0
R0603
AGND
AGND
0
R0603
AGND
AGND
AGND
AGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
0
R0603
AGND
TBD
C0603
AGND
AGND
TBD
C0603
AGND
AGND
R0603
C0603
0.1UF
AGND
TBD
C0603
C0603
0.1UF
TBD
C0603
TBD
C0603
TBD
C0603
TBD
C0603
TBD
C0603
TBD
C0603
C0603
0.1UF TBD
C0603
C0603
0.1UF
C0603
0.1UF
R0603
AGND
AGND
AGND
AGND
DGND
DGND
DGND
DGND
DGND
DGND DGND
DGND DGND
DGND
R0603
TBD
R0603
AGND
TBD
R0603
DGND
DGND
AGND
AGND
TE S TLO OP
ORANGE
TES TLOOP
RED
DGND
SEC PRI
SEC PRI
SEC PRI
SECPRI
R0603
AGND
0
R0603
AGNDAGND
AGND
AGND
TBD
R0603
AGND
R0603
TBD
AGND
R0603
TBD
AGND
R0603
TBD
R0603
TBD
R0603
TBD
0
R0603
R0603
TBD
R0603
TBD
AGND
AD8372
DVS1
2PCO2SVD
ONC2
AGD2
SDO2
SDO1
AGD1
ONC1
OPC1
AVS1
ENB1
AGD1
RXT1
REF1
IPC1
INC1
DGD1
AVS2
ENB2
ADG2
RXT2
REF2
IPC2
INC2
DGD2
LCH2
CLK2
CLK1
SDI1
LCH1
SDI2
C0603
0.1UF
C0603
0.1UF
C0603
0.1UF
C0603
0.1UF
0
R0603
R0603 R0603
R0603
R0603
R0603
R0603 R0603
R0603R0603
0
R0603
0
R0603
0
R0603
AGND
R0603
R0603
100 OHMS
75 OH M S
75 OH M S
75 OHMS
75 OH M S
75 OH M S
100 OH M S
100 O HM S
100 O HM S
100 O HM S
100 O HM S
50 OHMS
50 OHMS
AD8372 CHAR BD
50 OHMS
50 OHMS
50 OH M S
50 OH M S
50 OH M S
50 O HMS
75 OHMS
75 O HMS
75 OH M S
100 OH M S
100 O HM S
100 OHMS
100 O HM S
H1-7
0
R0603
R13
R48
TBD
H1-15
R12
TBD
AGND
R21
W3
W2
H1-15
181 2
L2
33UH
R23
33UH
L1
181 2
R22
R39
TBD
R40
TBD
R32
TBD
R31
TBD
R15
TBD
H1-12
H1-6
H1-1
R19
TBD R20
TBD
R42
TBD
R41
TBD
AGND
IPC2
INC2
INC1
H1-15
181 2
L3
33UH
R24
H1-15
33UH
L4
181 2
C22 C24
C26
C25
1
10 11 12 13 14 15 16
17
18
19
2
20
21
22
23
24
2526272829
3
303132
4
5
6
7
8
9
Z1
OPC2
R28
R38
R26
R37
R36
C29
0.1UF
C0603
C0603
0.1UF
C28
C18
0.1UF
C0603
C0603
0.1UF
C11
C32
0.1UF
C0603
H1-15
R35
R29
R30
R33
IPC1
R3
2.74K
R2
10P1
B20P2
B19P2
B18P2
B17P2
B16P2
B15P2
B14P2
H1-4
3
2
1
4
6
T1
3
2
1
4
6
T3
6
4
1
2
3T4
3
2
1
4
6
T2
C1206
L6
TBD
TBD
L5
C1206
14P1
15P1
16P1
17P1
18P1
19P1
20P1
21P1
22P1
23P1
24P1
25P1
13P1
12P1
11P1
9P1
8P1
7P1
6P1
5P1
4P1
3P1
2P1
1P1
H1-1 H1-15
SSVDDV
C33
10UF
3528
DGNDAGND
C0603
0.1UF
C14
C15
0.1UF
C0603
C13
0.1UF
C0603
R34
10K
R18
ONC1
OPC1
ONC2
R27
SDO2H1-12
SDO1
R14
R0603
0
C0603
0.1UF
C17
H1-5
H1-4
H1-3
H1-1
H1-11
H1-10
H1-9
H1-1
AGND
AGND
AGND
0
R0603
R7
R8
R0603
0
C12
1NF
C0603
R1
2.74K
C19
C23
C1
0
R0603
R4
C20
R5
R0603
0C2
C3
0
R0603
R6
C5
C4
R10
R0603
0C7
C6
0
R0603
R9
C21
R11
R0603
0C8
C27
R17
10K
W1
C9
C10
SDO1
SDO2
C0603
1NF
C16
R16
H1-3
H1-5
H1-6
H1-6
3528
10UF
C34
A1P2
A2P2
A3P2
A4P2
A5P2
A6P2
A7P2
A8P2
A9P2
A10P2
A11P2
A12P2
A13P2
A14P2
A15P2
A16P2
A17P2
A18P2
A19P2
A20P2
B1P2
B2P2
B3P2
B4P2
B5P2
B6P2
B7P2
B8P2
B9P2
B10P2
B11P2
B12P2
B13P2
H1-8
H1-12
H1-10
H1-11
H1-7
H1-9
H1-14
H1-4
H1-16
H1-15
H1-3
H1-5
H1-6
H1-13
H1-8
H1-12
H1-10
H1-11
H1-7
H1-9
H1-14
H1-4
H1-16
H1-15
H1-3
H1-5
H1-6
H1-13
H1-11
H1-12
H1-9
H1-10
R25
H1-1
H1-12
H1-6
H1-15
W4W5W6W7W8
R43
R44
R45
R46
AGND
TBD
R47
H1-7
H1-13
H1-13
R49
R0603
0
Figure 16. AD8372 Evaluation Board Schematic
AD8372
Rev. 0 | Page 13 of 16
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
0.30
0.23
0.18
0.20 REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
12° MAX
1.00
0.85
0.80 SEATING
PLANE
COPLANARITY
0.08
1
32
8
9
25
24
16
17
0.50
0.40
0.30
3.50 REF
0.50
BSC
PIN 1
INDICATOR
TOP
VIEW
5.00
BSC SQ
4.75
BSC SQ
3.25
3.10 SQ
2.95
PIN 1
INDICATOR
0.60 MAX
0.60 MAX
0.25 MIN
EXPOSED
PAD
(BOTTOM VIEW)
Figure 17. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature
Range Package Description
Package
Option
Ordering
Quantity
AD8372ACPZ-WP1−40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ], Waffle Pack CP-32-2
AD8372ACPZ-R71−40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7” Reel CP-32-2 1,500
AD8372-EVALZ1 Evaluation Board
1 Z = RoHS Compliant Part.
AD8372
Rev. 0 | Page 14 of 16
NOTES
AD8372
Rev. 0 | Page 15 of 16
NOTES
AD8372
Rev. 0 | Page 16 of 16
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07051-0-11/07(0)
