Datasheet, V 2.3 , May. 2006 (TM) EiceDRIVER 2ED020I12-F Dual Channel IGBT Driver IC http://www.infineon.com/gatedriver Power Management & Drives N e v e r s t o p t h i n k i n g 2ED020I12-F Edition 2006-05-12 Published by Infineon Technologies AG Am Campeon 1-12 85579 Neubiberg, Germany All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. 2ED020I12-F 2ED020I12-F Confidential Revision History: Previous Version: Page Revision 2.0 Revision 2.1 Revision 2.2 2006-05 none Subjects (major changes since last revision) 2004-05-10: First release 2004-08-20: Chapter 1, 5.3.5, and 6 updated. New chapter 4.7. 2006-01-23: Changed Layout Author(s) Prepared by: Andreas Volke Approved by: Michael Hornkamp S/N: 010-04 Date of publication: 2004-08-20 Status: Preliminary Data Datasheet 3 Rev. 2.3, Aug. 2004 2ED020I12-F Table of Contents 1 Page Overview.................................................................................................................................................. 5 1.1 Coreless transformer (CLT) technology.........................................................................................5 2 Pin configuration and package outline .................................................................................................... 7 3 Block diagram.......................................................................................................................................... 8 4 Functional description ............................................................................................................................. 9 5 6 4.1 Power supply..................................................................................................................................9 4.2 Logic inputs ....................................................................................................................................9 4.3 Gate driver......................................................................................................................................9 4.4 General purpose operational amplifier...........................................................................................9 4.5 General purpose comparator .........................................................................................................9 4.6 CLT.................................................................................................................................................9 4.7 EMI .................................................................................................................................................9 Electrical parameters............................................................................................................................. 10 5.1 Absolute maximum ratings...........................................................................................................10 5.2 Operating range ...........................................................................................................................11 5.3 Electrical characteristics...............................................................................................................11 5.3.1 Voltage Supply...............................................................................................................11 5.3.2 Logic inputs....................................................................................................................12 5.3.3 Gate drivers ...................................................................................................................12 5.3.4 Dynamic characteristics .................................................................................................12 5.3.5 General purpose operational amplifier...........................................................................13 5.3.6 General purpose comparator.........................................................................................13 Diagrams ............................................................................................................................................... 14 Datasheet 4 Rev. 2.3, 2006-05-12 2ED020I12-F 1 Overview The 2ED020I12-F is a high voltage, high speed power IGBT and MOSFET driver of the Infineon EiceDRIVERTM family with interlocking high and low side referenced output channels. The floating high side driver may be supplied directly or by means of a bootstrap diode and capacitor. All logic inputs are compatible with 3.3 V and 5 V TTL. Additionally the 2ED020I12-F is equipped with a dedicated shutdown input. The drivers feature a high pulse current buffer stage. Propagation delays are matched to simplify use in high frequency applications. Both drivers are designed to drive an nchannel power IGBT or MOSFET which operates up to 1200 V. In addition, a general purpose operational amplifier and a general purpose comparator are provided, which may be used e.g. for current measurement or over current detection. Product Highlights * Fully operational to 1200 V * Floating high side driver * Gate drive supply range from 13 to 18 V * Gate drive currents of +1 A / -2 A * Matched propagation delay for both channels * High dV/dt immunity * General purpose operational amplifier * General purpose comparator Features * Under-voltage lockout for both channels * 3.3 V and 5 V TTL compatible inputs * CMOS Schmitt-triggered inputs with internal pull-down * CMOS Schmitt-triggered shutdown with internal pull-up * Non-inverting inputs * Interlocking inputs * Dedicated shutdown input with internal pull-up * UL recognized (pending) 1.1 Coreless transformer (CLT) technology The coreless transformer technology combines almost all advantages of optocouplers, level-shifters, and discrete transformers by avoiding at the same time almost all disadvantages of these devices by a very cost efficient way and high voltage isolation capability. The principle function of the CLT is realized by two coils which are compounded on silicon within one integrated circuit. The isolation between these coils together with the used package dimensions makes this device suitable for 1200 V applications and provides a functional isolation. Figure 1 shows a schematic of the internal stages of the IC. Figure 1 Datasheet IC schematic 5 Rev. 2.3, 2006-05-12 2ED020I12-F Each EiceDRIVERTM has a type number, which can be resolved by the following schemata: EiceDRIVERTM 2 ED 020 I 12 - F Isolation class F = Function isolation S = Safety isolation ST = Safety isolation / Traction application Voltage class: 06 = 600 V 12 = 1200 V 17 = 1700 V 33 = 3300 V 65 = 6500 V Type: C = Board I = IC (Coreless Transformer) L = IC (Level Shifter) Peak output current for Driver: 020 = 2 A 300 = 30 A Maximum Sampling Rate for ADC 010 = 10 MHz Function: EC = Analog-Digital-Converter ED = IGBT/MOSFET Driver Driver Channels: 1 = Driver for one IGBT 2 = Driver for Half-Bridge 6 = Driver for Six-Pack ADC Channels: 1 = Single Channel Converter Datasheet 6 Rev. 2.3, 2006-05-12 2ED020I12-F 2 Pin configuration and package outline P-DSO-18-1 (300 mil) 1) 2) Figure 2 Pin configuration (top view) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Datasheet Symbol InH InL /SD GND /CPO CPCP+ OPO OPOP+ GNDL OutL VSL n.c. n.e. n.e. GNDH VSH OutH GNDH Does not include plastic or metal protrusions of 0.15 max per side Does not include dambar protrusion of 0.05 max per side Figure 3 Package outline (all measures in mm) Function Logic input for high side driver Logic input for low side driver Logic input for shutdown of both drivers Common ground Open drain output of general purpose comparator Inverting input of general purpose comparator Non-inverting input of general purpose comparator Output of general purpose operational amplifier Inverting input of general purpose operational amplifier Non-inverting input of general purpose operational amplifier Low side supply ground Low side gate driver output Low side supply voltage (not connected) (not existing) (not existing) High side supply ground High side supply voltage High side gate driver output High side supply ground 7 Rev. 2.3, 2006-05-12 2ED020I12-F 3 Block diagram Figure 4 Block diagram Datasheet 8 Rev. 2.3, 2006-05-12 2ED020I12-F 4 4.1 Functional description Power supply The power supply of both sides, VSL and VSH, is monitored by an under-voltage lockout block (UVLO) which enables operation of the corresponding side when the supply voltage reaches the "on" threshold of 12 V. Afterwards the internal voltage reference and the biasing circuit are enabled. When the supply voltage (VSL, VSH) drops below the "off" threshold of 11 V the circuit is disabled. 4.2 Logic inputs The logic inputs InH, InL (non-inverting) and /SD (inverting) are fed into Schmitt-Triggers with thresholds compatible to 3.3 V and 5 V TTL. When /SD is enabled (low), inputs InH and InL are disabled. If InH is high while InL is low, OutH is enabled and vice versa. However, if both signals are high, they are internally disabled until both signals get low again. This is due to the interlocking logic of the device (see also Figure 5). 4.3 Gate driver 2ED020I12-F features two hard-switching gate drivers with n-channel output stages capable to source 1 A and to sink 2 A peak current. Both drivers are equipped with active-low-clamping capability. Furthermore, they feature a large ground bounce ruggedness in order to compensate ground bounces caused by a turn-off of the driven IGBT or MOSEFT. 4.4 General purpose operational amplifier The integrated general purpose operational amplifier can be applied for current measurement of the driven low-side IGBT or MOSFET. The OP is equipped with a -0.1 V to 2 V input stage and a rail-to-rail output stage which is capable to drive 5 mA and is dedicated to drive for instance an A/D converter. The OP needs for stable operation a minimum gain of 3 set by the external circuitry. 4.5 General purpose comparator The integrated general purpose comparator can be applied for over-current detection of the low side IGBT or MOSFET. A dedicated offset as well as a pull-up and pull-down resistor have been introduced to its inputs for security reasons. 4.6 CLT In order to enable signal transmission across the isolation barrier between low-side and high-side driver, a coreless transformer is employed. Signals, that are to be transmitted, are specially encoded by the transmitter and correspondingly reconstructed by the receiver. In this way EMI due to variations of GNDH (dVGNDH/dt) or the magnetic flux density (dH/dt) can be suppressed. To compensate the additional propagation delay of transmitter, coreless transformer and receiver, a dedicated propagation delay is introduced into the low-side driver which assures a maximum difference of the propagation delay times of 10 ns. 4.7 EMI The driver was tested according to IEC 61000-4-4 Level 3 (typical industrial environment) in an Infineon reference frequency converter. Datasheet 9 Rev. 2.3, 2006-05-12 2ED020I12-F 5 5.1 Electrical parameters Absolute maximum ratings Absolute maximum ratings are defined as ratings which when being exceeded may lead to destruction of the integrated circuit. Unless otherwise noted all parameters refer to GND. The pins GND and GNDL have to be connected externally through the shortest possible way. Parameter High side ground High side supply voltage High side gate driver output Low side ground Low side supply voltage Low side gate driver output Logic input voltages (InH, InL, /SD) OP input voltages (OP-, OP+) OP output voltage CP input voltages (CP-, CP+) CP output voltage CP output max. sink current High side ground, voltage transient Package power dissipation @TA=25C Thermal resistance (both chips active), junction to ambient Thermal resistance (high side chip), junction to ambient Thermal resistance (low side chip), junction to ambient Junction temperature Storage temperature VGNDH VVSH VOutH VGNDL VVSL VOutL VIn Limit values min. -1200 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 max. 1200 20 VVSH + 0.3 5.3 20 VVSL + 0.3 5.3 V V V V V V V VOP -0.3 5.3 V VOPO VCP -0.3 -0.3 5.3 5.3 V V V/CPO I/CPO dVGNDH/dt -0.3 -50 5.3 5 50 V mA V/ns PD 2 W 5) RTHJA 60 K/W 6) RTHJA(HS) 110 K/W 6) RTHJA(LS) 110 K/W 6) TJ TS -55 150 150 C C Symbol Unit Remark 1) 1) 2) 3) 4) 4) 1) with reference to high side GNDH with reference to both GND and GNDL 3) with reference to low side ground GNDL 4) please note the different specifications for the operating range 5) considering RTHJA = 60 K/W, e.g. both chips active 6) device soldered to reference PCB without cooling area 2) Datasheet 10 Rev. 2.3, 2006-05-12 2ED020I12-F 5.2 Operating range Within the operating range the IC operates as described in the functional description. Unless otherwise noted all parameters refer to GND. Parameter High side ground High side supply voltage Low side supply voltage Logic input voltages (InH, InL, /SD) OP input voltages (OP-, OP+) CP input voltages (CP-, CP+) Switching frequency Ambient temperature 1) 2) VGNDH VVSH VVSL VIn Limit values min. -1200 13 13 0 max. 1200 18 18 5 V V V V VOP -0.1 2 V VCP -0.1 2 V fS TA 0 -40 tbd 105 kHz C Symbol Unit Remark 1) 2) with reference to high side ground GNDH with reference to both GND and GNDL 5.3 Electrical characteristics The electrical characteristics involve the spread of values for the supply voltages, load and junction temperature given below. Typical values represent the median values which are related to production processes. Unless otherwise noted all voltages are given with respect to ground (GND). 1) VVSL = 15 V, VVSH = 15 V , CL = 1 nF, TA = 25C. Positive currents are assumed to be flowing into pins. 5.3.1 Voltage Supply Parameter 1) Symbol High side leakage current IGNDH Limit Values min. typ. 0 Unit Test condition max. A VGNDH = 1.2 kV VGNDL = 0 V VVSH = 15 V1) High side quiescent supply current High side under-voltage lockout, upper threshold High side under-voltage lockout lower threshold High side under-voltage lockout hysteresis Low side quiescent supply current Low side under-voltage lockout, upper threshold Low side under-voltage lockout lower threshold Low side under-voltage lockout hysteresis IVSH VVSH1) 10.9 2.4 12.2 3.2 13.5 mA V VVSH1) 11.2 V VVSH 0.7 1 1.3 IVSL VVSL 10.7 2.4 12 3.2 13.3 mA V VVSL 11 V VVSL 0.7 1 1.3 VVSL = 15 V with reference to high side ground GNDH Datasheet 11 Rev. 2.3, 2006-05-12 2ED020I12-F 5.3.2 Logic inputs Parameter Logic "1" (InH, InL, /SD) Logic "0" (InH, InL, /SD) Logic "1" (InH, InL) Logic "0" (InH, InL) Logic "1" (/SD) Logic "0" (/SD) 5.3.3 Symbol input voltages VIn Limit Values min. typ. 2 input voltages VIn 0.8 V current IIn 40 60 A VIn = 5 V input current IIn 0 A VIn = 0 V input current IIn 0 A VIn = 5 V input current IIn -60 -40 A VIn = 0 V Gate drivers High side high level output voltage VVSH - VOutH Limit Values min. typ. 1.4 High side low level output voltage VOutH1) 0.1 V Low side high level output voltage VVSL - VOutL 1.4 1.7 V Low side low level output voltage VOutL 0.1 V Output high peak current (OutL, OutH) Output low peak current (OutL, OutH) High side active low clamping IOut -1 A IOut 2 A VOutH1) 3 V Low side active low clamping VOutL 3 V Symbol Unit Test condition max. 1.7 V IOutH = -1 mA VInH = 5 V IOutH = 1 mA VInH = 0 V IOutH = -1 mA VInH = 0 V IOutH = 1 mA VInH = 0 V VIn = 5 V VOut = 0 V VIn = 0 V VOut = 15 V VInH = 0V VSH open IOutH = 200 mA VInL = 0V VSL open IOutL = 200 mA with reference to high side ground GNDH 5.3.4 Dynamic characteristics Parameter 1) V Test condition input Parameter 1) Unit max. Symbol Turn-on propagation delay Turn-off propagation delay Shutdown propagation delay Turn-on rise time Turn-off rise time Delay mismatch (high and low side turn-on/off) Minimum turn-on (OutH) ton toff t/SD tr tf t Limit Values min. typ. 55 55 55 40 40 Unit Test condition max. tbd tbd tbd tbd tbd 10 ns ns ns ns ns ns ref. to Figure 6 ref. to Figure 6 ref. to Figure 7 ref. to Figure 6 ref. to Figure 6 ref. to Figure 8 tpON 70 tbd ns ref. to Figure 91) Minimum turn-off (OutH) tpOFF 70 tbd ns ref. to Figure 91) InH pulses shorter than the "minimum turn-on/off input pulse length" are prolonged to 70 ns. The InL input doesn't have this feature. Datasheet 12 Rev. 2.3, 2006-05-12 2ED020I12-F 5.3.5 General purpose operational amplifier Parameter 1) 2) Symbol OP input offset voltage OP input offset voltage drift OP input high currents (OP-, OP+) OP input high currents (OP-, OP+) OP high output voltage VIn VIn/T IIn Limit Values min. typ. -10 0 15 0 Unit Test condition max. 10 0.2 mV V/K A VIn = 2 V IIn -0.2 0 A VIn = 0 V VOPO 4.9 V OP low output voltage VOPO 0.1 V OP output source current IOPO -5 mA OP output sink current IOPO 5 mA VOP= VOP+ = 2 V VOP= VOP+ = 0 V VOP+ = VOP= VOPO = 0V VOP+ = VOP= VOPO = 5V OP open loop gain OP gain-bandwidth product OP phase margin AOL A x BW 120 20 70 dB MHz 0 V 2 V 2 0 V V 0 2 V V 1) 1), 2) design value due to inevitable parasitics a minimum gain A 3 is recommended 5.3.6 General purpose comparator Parameter CP input offset voltage CP input high current CP input low current CP low output voltage VIn ICPICP+ V/CPO Limit Values min. typ. -45 -30 20 -35 -20 CP output leakage current I/CPO 5 A CP switch-on delay td 100 ns CP switch-off delay td 300 ns Datasheet Symbol 13 Unit Test condition max. -15 35 0.2 mV A A V VCP+ = VCPVCP- = 5 V VCP+ = 0 V VCP+ = 2 I/CPO = 1 mA VCP+ = 0 = 2 VCPV/CPO = 5 V R/CPO = 4.7 = 5 Vres V/CPO = 4 V R/CPO = 4.7 = 5 Vres V/CPO = 1 V Rev. 2.3, 2006-05-12 V V V k V k V 2ED020I12-F 6 Diagrams InH InL /SD OutH OutL Figure 5 Input/Output timing diagram Figure 6 : Switching time waveform definition Figure 7 : Shutdown waveform definition Figure 8 : Delay matching waveform definitions Figure 9 : Short InH Pulses Datasheet 14 Rev. 2.3, 2006-05-12