2ED020I12F2XT - INFINEON TECHNOLOGIES AG

Datasheet, V 2.3 , May. 2006

Power Management & Drives

EiceDRIVER(TM)

2ED020I12-F

Dual Channel IGBT Driver IC

http://www.infineon.com/gatedriver

Never stop thinking

2ED020I12-F

Edition 2006-05-12

Published by Infineon Technologies AG

Am Campeon 1-12

85579 Neubiberg, Germany

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee

of characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement,

regarding circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types

in question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express

written approval of Infineon Technologies, if a failure of such components can reasonably be expected to

cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or

system. Life support devices or systems are intended to be implanted in the human body, or to support

and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health

of the user or other persons may be endangered.

2ED020I12-F

Datasheet 3 Rev. 2.3, Aug. 2004

2ED020I12-F

Confidential

Revision History: 2006-05

Previous Version: none

Page Subjects (major changes since last revision)

Revision 2.0 2004-05-10: First release

Revision 2.1 2004-08-20: Chapter 1, 5.3.5, and 6 updated. New chapter 4.7.

Revision 2.2 2006-01-23: Changed Layout

Author(s)

Prepared by: Andreas Volke

Approved by: Michael Hornkamp

S/N: 010-04

Date of publication: 2004-08-20

Status: Preliminary Data

2ED020I12-F

Table of Contents Page

Datasheet 4 Rev. 2.3, 2006-05-12

1 Overview.................................................................................................................................................. 5

1.1 Coreless transformer (CLT) technology.........................................................................................5

2 Pin configuration and package outline .................................................................................................... 7

3 Block diagram.......................................................................................................................................... 8

4 Functional description ............................................................................................................................. 9

4.1 Power supply..................................................................................................................................9

4.2 Logic inputs ....................................................................................................................................9

4.3 Gate driver......................................................................................................................................9

4.4 General purpose operational amplifier...........................................................................................9

4.5 General purpose comparator .........................................................................................................9

4.6 CLT.................................................................................................................................................9

4.7 EMI .................................................................................................................................................9

5 Electrical parameters............................................................................................................................. 10

5.1 Absolute maximum ratings...........................................................................................................10

5.2 Operating range ...........................................................................................................................11

5.3 Electrical characteristics...............................................................................................................11

5.3.1 Voltage Supply...............................................................................................................11

5.3.2 Logic inputs....................................................................................................................12

5.3.3 Gate drivers ...................................................................................................................12

5.3.4 Dynamic characteristics .................................................................................................12

5.3.5 General purpose operational amplifier...........................................................................13

5.3.6 General purpose comparator.........................................................................................13

6 Diagrams ............................................................................................................................................... 14

2ED020I12-F

Datasheet 5 Rev. 2.3, 2006-05-12

1 Overview

The 2ED020I12-F is a high voltage, high speed power IGBT and MOSFET driver of the Infineon EiceDRIVER™ family

with interlocking high and low side referenced output channels. The floating high side driver may be supplied directly or

by means of a bootstrap diode and capacitor. All logic inputs are compatible with 3.3 V and 5 V TTL. Additionally the

2ED020I12-F is equipped with a dedicated shutdown input. The drivers feature a high pulse current buffer stage.

Propagation delays are matched to simplify use in high frequency applications. Both drivers are designed to drive an n-

channel power IGBT or MOSFET which operates up to 1200 V. In addition, a general purpose operational amplifier and a

general purpose comparator are provided, which may be used e.g. for current measurement or over current detection.

Product Highlights

• Fully operational to ±1200 V

• Floating high side driver

• Gate drive supply range from 13 to 18 V

• Gate drive currents of +1 A / –2 A

• Matched propagation delay for both channels

• High dV/dt immunity

• General purpose operational amplifier

• General purpose comparator

Features

• Under-voltage lockout for both channels

• 3.3 V and 5 V TTL compatible inputs

• CMOS Schmitt-triggered inputs with internal pull-down

• CMOS Schmitt-triggered shutdown with internal pull-up

• Non-inverting inputs

• Interlocking inputs

• Dedicated shutdown input with internal pull-up

• UL recognized (pending)

1.1 Coreless transformer (CLT) technology

The coreless transformer technology combines almost all advantages of optocouplers, level-shifters, and discrete

transformers by avoiding at the same time almost all disadvantages of these devices by a very cost efficient way and

high voltage isolation capability.

The principle function of the CLT is realized by two coils which are compounded on silicon within one integrated circuit.

The isolation between these coils together with the used package dimensions makes this device suitable for 1200 V

applications and provides a functional isolation. Figure 1 shows a schematic of the internal stages of the IC.

Figure 1 IC schematic

2ED020I12-F

Datasheet 6 Rev. 2.3, 2006-05-12

Each EiceDRIVER™ has a type number, which can be resolved by the following schemata:

EiceDRIVER™ 2 ED 020 I 12 - F

Isolation class

F = Function isolation

S = Safety isolation

ST = Safety isolation / Traction application

Voltage class:

06 = 600 V

12 = 1200 V

17 = 1700 V

33 = 3300 V

65 = 6500 V

Type:

C = Board

I = IC (Coreless Transformer)

L = IC (Level Shifter)

Peak output current for Driver:

020 = 2 A

300 = 30 A

Maximum Sampling Rate for ADC

010 = 10 MHz

Function:

EC = Analog-Digital-Converter

ED = IGBT/MOSFET Driver

Driver Channels:

1 = Driver for one IGBT

2 = Driver for Half-Bridge

6 = Driver for Six-Pack

ADC Channels:

1 = Single Channel Converter

2ED020I12-F

Datasheet 7 Rev. 2.3, 2006-05-12

2 Pin configuration and package outline

1) Does not include plastic or metal protrusions of 0.15 max per side

2) Does not include dambar protrusion of 0.05 max per side

Figure 2 Pin configuration (top view) Figure 3 Package outline (all measures in mm)

Pin Symbol Function

1 InH Logic input for high side driver

2 InL Logic input for low side driver

3 /SD Logic input for shutdown of both drivers

4 GND Common ground

5 /CPO Open drain output of general purpose comparator

6 CP- Inverting input of general purpose comparator

7 CP+ Non-inverting input of general purpose comparator

8 OPO Output of general purpose operational amplifier

9 OP- Inverting input of general purpose operational amplifier

10 OP+ Non-inverting input of general purpose operational amplifier

11 GNDL Low side supply ground

12 OutL Low side gate driver output

13 VSL Low side supply voltage

14 n.c. (not connected)

15 n.e. (not existing)

16 n.e. (not existing)

17 GNDH High side supply ground

18 VSH High side supply voltage

19 OutH High side gate driver output

20 GNDH High side supply ground

P-DSO-18-1 (300 mil)

2ED020I12-F

Datasheet 8 Rev. 2.3, 2006-05-12

3 Block diagram

Figure 4 Block diagram

2ED020I12-F

Datasheet 9 Rev. 2.3, 2006-05-12

4 Functional description

4.1 Power supply

The power supply of both sides, VSL and VSH, is monitored by an under-voltage lockout block (UVLO) which enables

operation of the corresponding side when the supply voltage reaches the “on” threshold of 12 V. Afterwards the internal

voltage reference and the biasing circuit are enabled. When the supply voltage (VSL, VSH) drops below the “off”

threshold of 11 V the circuit is disabled.

4.2 Logic inputs

The logic inputs InH, InL (non-inverting) and /SD (inverting) are fed into Schmitt-Triggers with thresholds compatible to

3.3 V and 5 V TTL. When /SD is enabled (low), inputs InH and InL are disabled. If InH is high while InL is low, OutH is

enabled and vice versa. However, if both signals are high, they are internally disabled until both signals get low again.

This is due to the interlocking logic of the device (see also Figure 5).

4.3 Gate driver

2ED020I12-F features two hard-switching gate drivers with n-channel output stages capable to source 1 A and to sink 2

A peak current. Both drivers are equipped with active-low-clamping capability. Furthermore, they feature a large ground

bounce ruggedness in order to compensate ground bounces caused by a turn-off of the driven IGBT or MOSEFT.

4.4 General purpose operational amplifier

The integrated general purpose operational amplifier can be applied for current measurement of the driven low-side

IGBT or MOSFET. The OP is equipped with a -0.1 V to 2 V input stage and a rail-to-rail output stage which is capable to

drive ±5 mA and is dedicated to drive for instance an A/D converter. The OP needs for stable operation a minimum gain

of 3 set by the external circuitry.

4.5 General purpose comparator

The integrated general purpose comparator can be applied for over-current detection of the low side IGBT or MOSFET.

A dedicated offset as well as a pull-up and pull-down resistor have been introduced to its inputs for security reasons.

4.6 CLT

In order to enable signal transmission across the isolation barrier between low-side and high-side driver, a coreless

transformer is employed. Signals, that are to be transmitted, are specially encoded by the transmitter and

correspondingly reconstructed by the receiver. In this way EMI due to variations of GNDH (dVGNDH/dt) or the magnetic

flux density (dH/dt) can be suppressed. To compensate the additional propagation delay of transmitter, coreless

transformer and receiver, a dedicated propagation delay is introduced into the low-side driver which assures a maximum

difference of the propagation delay times of 10 ns.

4.7 EMI

The driver was tested according to IEC 61000-4-4 Level 3 (typical industrial environment) in an Infineon reference

frequency converter.

2ED020I12-F

Datasheet 10 Rev. 2.3, 2006-05-12

5 Electrical parameters

5.1 Absolute maximum ratings

Absolute maximum ratings are defined as ratings which when being exceeded may lead to destruction of the integrated circuit. Unless

otherwise noted all parameters refer to GND. The pins GND and GNDL have to be connected externally through the shortest possible

way.

Limit values

Parameter Symbol

min. max.

Unit Remark

High side ground VGNDH -1200 1200 V

High side supply voltage VVSH -0.3 20 V

High side gate driver output VOutH -0.3 VVSH + 0.3 V 1)

Low side ground VGNDL -0.3 5.3 V

Low side supply voltage VVSL -0.3 20 V

Low side gate driver output VOutL -0.3 VVSL + 0.3 V 3)

Logic input voltages

(InH, InL, /SD)

VIn -0.3 5.3 V

OP input voltages

(OP-, OP+)

VOP -0.3 5.3 V

OP output voltage VOPO -0.3 5.3 V

CP input voltages

(CP-, CP+)

VCP -0.3 5.3 V

CP output voltage V/CPO -0.3 5.3 V

CP output max. sink current I/CPO  5 mA

High side ground, voltage

transient

dVGNDH/dt -50 50 V/ns

Package power dissipation

@TA=25°C

PD  2 W

Thermal resistance (both chips

active), junction to ambient

RTHJA  60 K/W

Thermal resistance (high side

chip), junction to ambient

RTHJA(HS)  110 K/W

Thermal resistance (low side

chip), junction to ambient

RTHJA(LS)  110 K/W

Junction temperature TJ  150 °C

Storage temperature TS -55 150 °C

1) with reference to high side GNDH

2) with reference to both GND and GNDL

3) with reference to low side ground GNDL

4) please note the different specifications for the operating range

5) considering RTHJA = 60 K/W, e.g. both chips active

6) device soldered to reference PCB without cooling area

2ED020I12-F

Datasheet 11 Rev. 2.3, 2006-05-12

5.2 Operating range

Within the operating range the IC operates as described in the functional description. Unless otherwise noted all parameters refer to

GND.

Limit values

Parameter Symbol

min. max.

Unit Remark

High side ground VGNDH -1200 1200 V

High side supply voltage VVSH 13 18 V

Low side supply voltage VVSL 13 18 V

Logic input voltages

(InH, InL, /SD)

VIn 0 5 V

OP input voltages

(OP-, OP+)

VOP -0.1 2 V

CP input voltages

(CP-, CP+)

VCP -0.1 2 V

Switching frequency fS 0 tbd kHz

Ambient temperature TA -40 105 °C

1) with reference to high side ground GNDH

2) with reference to both GND and GNDL

5.3 Electrical characteristics

The electrical characteristics involve the spread of values for the supply voltages, load and junction temperature given below. Typical

values represent the median values which are related to production processes. Unless otherwise noted all voltages are given with

respect to ground (GND).

VVSL = 15 V, VVSH = 15 V1), CL = 1 nF, TA = 25°C. Positive currents are assumed to be flowing into pins.

5.3.1 Voltage Supply

Limit Values Parameter Symbol

min. typ. max.

Unit Test condition

High side leakage current IGNDH  0  µA VGNDH = 1.2 kV

VGNDL = 0 V

High side quiescent supply current IVSH  2.4 3.2 mA VVSH = 15 V1)

High side under-voltage lockout,

upper threshold

VVSH1) 10.9 12.2 13.5 V

High side under-voltage lockout

lower threshold

VVSH1)  11.2  V

High side under-voltage lockout

hysteresis ∆VVSH 0.7 1 1.3

Low side quiescent supply current IVSL  2.4 3.2 mA VVSL = 15 V

Low side under-voltage lockout,

upper threshold

VVSL 10.7 12 13.3 V

Low side under-voltage lockout

lower threshold

VVSL  11  V

Low side under-voltage lockout

hysteresis ∆VVSL 0.7 1 1.3

1) with reference to high side ground GNDH

2ED020I12-F

Datasheet 12 Rev. 2.3, 2006-05-12

5.3.2 Logic inputs

Limit Values Parameter Symbol

min. typ. max.

Unit Test condition

Logic “1” input voltages

(InH, InL, /SD)

VIn 2   V

Logic “0” input voltages

(InH, InL, /SD)

VIn   0.8 V

Logic “1” input current

(InH, InL)

IIn  40 60 µA VIn = 5 V

Logic “0” input current

(InH, InL)

IIn  0  µA VIn = 0 V

Logic “1” input current

(/SD)

IIn  0  µA VIn = 5 V

Logic “0” input current

(/SD)

IIn -60 -40

 µA VIn = 0 V

5.3.3 Gate drivers

Limit Values Parameter Symbol

min. typ. max.

Unit Test condition

High side high level output voltage VVSH – VOutH  1.4 1.7 V IOutH = -1 mA

VInH = 5 V

High side low level output voltage VOutH1)   0.1 V

IOutH = 1 mA

VInH = 0 V

Low side high level output voltage VVSL – VOutL  1.4 1.7 V IOutH = -1 mA

VInH = 0 V

Low side low level output voltage VOutL   0.1 V

IOutH = 1 mA

VInH = 0 V

Output high peak current

(OutL, OutH)

IOut   -1 A

VIn = 5 V

VOut = 0 V

Output low peak current

(OutL, OutH)

IOut 2

  A VIn = 0 V

VOut = 15 V

High side active low clamping VOutH1)   3 V

VInH = 0V

VSH open

IOutH = 200 mA

Low side active low clamping VOutL   3 V

VInL = 0V

VSL open

IOutL = 200 mA

1) with reference to high side ground GNDH

5.3.4 Dynamic characteristics

Limit Values Parameter Symbol

min. typ. max.

Unit Test condition

Turn-on propagation delay ton  55 tbd ns ref. to Figure 6

Turn-off propagation delay toff  55 tbd ns ref. to Figure 6

Shutdown propagation delay t/SD  55 tbd ns ref. to Figure 7

Turn-on rise time tr  40 tbd ns ref. to Figure 6

Turn-off rise time tf  40 tbd ns ref. to Figure 6

Delay mismatch (high and low side

turn-on/off) ∆t   10 ns ref. to Figure 8

Minimum turn-on (OutH) tpON  70 tbd ns ref. to Figure 91)

Minimum turn-off (OutH) tpOFF  70 tbd ns ref. to Figure 91)

1) InH pulses shorter than the “minimum turn-on/off input pulse length” are prolonged to 70 ns. The InL input doesn’t have this feature.

2ED020I12-F

Datasheet 13 Rev. 2.3, 2006-05-12

5.3.5 General purpose operational amplifier

Limit Values Parameter Symbol

min. typ. max.

Unit Test condition

OP input offset voltage ∆VIn -10 0 10 mV

OP input offset voltage drift ∆VIn/∆T  15  µV/K

OP input high currents

(OP-, OP+)

IIn  0 0.2 µA VIn = 2 V

OP input high currents

(OP-, OP+)

IIn -0.2 0

 µA VIn = 0 V

OP high output voltage VOPO 4.9   V VOP- = 0 V

VOP+ = 2 V

OP low output voltage VOPO   0.1 V

VOP- = 2 V

VOP+ = 0 V

OP output source current IOPO   -5 mA

VOP+ = 2 V

VOP- = 0 V

VOPO = 0V

OP output sink current IOPO 5   mA VOP+ = 0 V

VOP- = 2 V

VOPO = 5V

OP open loop gain AOL  120  dB

OP gain-bandwidth product A x BW  20  MHz 1)

OP phase margin Φ  70  ° 1), 2)

1) design value

2) due to inevitable parasitics a minimum gain A ≥ 3 is recommended

5.3.6 General purpose comparator

Limit Values Parameter Symbol

min. typ. max.

Unit Test condition

CP input offset voltage ∆VIn -45 -30 -15 mV VCP+ = VCP-

CP input high current ICP-  20 35 µA VCP- = 5 V

CP input low current ICP+ -35 -20

 µA VCP+ = 0 V

CP low output voltage V/CPO   0.2 V

VCP+ = 2 V

I/CPO = 1 mA

CP output leakage current I/CPO   5 µA

VCP+ = 0 V

VCP- = 2 V

V/CPO = 5 V

CP switch-on delay td  100  ns R/CPO = 4.7 kΩ

Vres = 5 V

V/CPO = 4 V

CP switch-off delay td  300  ns R/CPO = 4.7 kΩ

Vres = 5 V

V/CPO = 1 V

2ED020I12-F

Datasheet 14 Rev. 2.3, 2006-05-12

6 Diagrams

InH

InL

/SD

OutH

OutL

Figure 5 Input/Output timing diagram

Figure 6 : Switching time waveform definition Figure 7 : Shutdown waveform definition

Figure 8 : Delay matching waveform definitions Figure 9 : Short InH Pulses