INFINEON Technologies 1 2002-07-18
HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
3.3 V 168-pin Registered SDRAM Modules
PC133 128 MByte Module
PC133 256 MByte module
PC133 512 MByte Module
PC1331GByteModule
PC1332GByteModule
Description
The HYS 72Vxx3xxGR-7 and -7.5 are industry standard 168-pin 8-byte Dual in-line Memory Modules (DIMMs)
organized as 16M ×72, 32M x 72, 64M ×72, 128M ×72 and 256M x 72 high speed memory arrays designed with
Synchronous DRAMs (SDRAMs) for ECC applications. All control and address signals are registered on-DIMM
and the design incorporates a PLL circuit for the Clock inputs. Use of an on-board register reduces capacitive
loading on the input signals but are delayed by one cycle in arriving at the SDRAM devices. Decoupling capacitors
are mounted on the PC board. The DIMMs use a serial presence detects scheme implemented via a serial
E2PROM using the 2-pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second
128 bytes are available to the end user. All Infineon 168-pin DIMMs provide a high performance, flexible 8-byte
interface in a 133.35 mm long footprint.
• 168-pin Registered 8 Byte Dual-In-Line
SDRAM Module for PC and Server main
memory applications
• One bank 16M ×72, 32M x 72, 64M ×72and
128M x 72, two bank 128M ×72 and
256M x 72 organization
• Optimized for ECC applications with very low
input capacitances
• JEDEC standard Synchronous DRAMs
(SDRAM) Programmable CAS Latency, Burst
Length and Wrap Sequence (Sequential &
Interleave)
• Single+3.3V(
±0.3 V) power supply
• Auto Refresh (CBR) and Self Refresh
• Programmable CAS Latency, Burst Length,
and Wrap Sequence (Sequential &
Interleave)
• All inputs and outputs are LVTTL compatible
• Serial Presence Detect with E2PROM
• Utilizes SDRAMs in TSOPII-54 packages
with registers and PLL.
• Card Size: 133.35 mm ×38.10/43.18mm
with Gold contact pads and max. 4.00 / 6.80
mm thickness (JEDEC MO-161)
• These modules all fully compatible with the
current industry standard PC133 and PC100
specifications
• Performance:
speed grade -7 -7.5 Unit
fCK Clock Frequency (max.) @ CL = 3 133 133 MHz
tCK Clock Cycle Time (min.) @ CL = 3 7.5 7.5 ns
tAC Clock Access Time (min.) @ CL= 3 5.4 5.4 ns
fCK Clock Frequency (max.) @ CL = 2 133 100 MHz
tCK Clock Cycle Time (min.) @ CL = 2 7.5 10 ns
tAC Clock Access Time (min.) @ CL= 2 5.4 6 ns
HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
INFINEON Technologies 2 2002-07-18
Ordering Information
.
Partnumber 1) Compliance
Code 2)
Description SDRAM
Technology
PC133-333:
HYS 72V16300GR-7.5-C
HYS 72V16300GR-7.5-E
PC133R-333-542-B2 one bank 128 MB Reg. DIMM 64 MBit (x4)
HYS 72V16301GR-7.5-C2 PC133R-333-542-B2 one bank 128 MB Reg. DIMM 128 MBit (x8)
HYS 72V32301GR-7.5-C2 PC133R-333-542-B2 one bank 256 MB Reg. DIMM 128 Mbit (x4)
HYS 72V32300GR-7.5-C2
HYS 72V32300GR-7.5-D
PC133R-333-542-AA one bank 256 MB Reg. DIMM 256 Mbit (x8)
HYS 72V64300GR-7.5-C2
HYS 72V64300GR-7.5-D
PC133R-333-542-B2 one bank 512 MB Reg. DIMM 256 MBit (x4)
HYS 72V128320/1GR-7.5-C2
HYS 72V128320/1GR-7.5-D
PC133R-333-542-B2 two banks 1 GByte Reg. DIMM 256 MBit
(x4, stacked) 3)
HYS 72V128300GR-7.5-A PC133R-333-542-B2 one bank 1 GByte Reg. DIMM 512 MBit (x4)
HYS 72V256320/1GR-7.5-A PC133R-333-542-B2 two banks 2 GByte Reg. DIMM 512 MBit
(x4, stacked) 3)
PC133-222:
HYS 72V16300GR-7-E PC133R-222-542-B2 one bank 128 MB Reg. DIMM 64 MBit (x4)
HYS 72V16301GR-7-C2 PC133R-222-542-B2 one bank 128 MB Reg. DIMM 128 MBit (x8)
HYS 72V32301GR-7-C2 PC133R-222-542-B2 one bank 256 MB Reg. DIMM 128 Mbit (x4)
HYS 72V32300GR-7-D PC133R-222-542-AA one bank 256 MB Reg. DIMM 256 Mbit (x8)
HYS 72V64300GR-7-D PC133R-222-542-B2 one bank 512 MB Reg. DIMM 256 MBit (x4)
HYS 72V128320/1GR-7-D PC133R-222-542-B2 two banks 1 GByte Reg. DIMM 256 MBit
(x4, stacked) 3)
HYS 72V128300GR-7-A PC133R-222-542-B2 one bank 1 GByte Reg. DIMM 512 MBit (x4)
HYS 72V256320/1GR-7-A PC133R-222-542-B2 two banks 2 GByte Reg. DIMM 512 MBit
(x4, stacked) 3)
Notes:
1.) All part numbers end with a place code, designating the die revision of the components used on the
Registered DIMM module. Consult factory for current revision. Example: HYS 64V32300GR-7.5-D,
indicating Rev.D dies are used for 256Mbit SDRAM components.
2.) The Compliance Code is printed on the modules labels and describes speed sort of the modules,
latencies, access time from clock,SPD revision and Raw Card version acording to the actual JEDEC
standard.
3.) Modules with stacked components are available in two version, with components stacked using a
soldering stacking technique (f.e. HYS72V128320GR-7.5 ) and an welding technique developed by
INFINEON Technologies (f.e. HYS72V128321GR-7.5)
HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
INFINEON Technologies 3 2002-07-18
Pin Definitions and Functions
A0 - A11, A12 Address Inputs (A12 is used for
256Mbit based modules only)
DQMB0 - DQMB7 Data Mask
BA0, BA1 Bank Selects CS0 -CS3 Chip Select
DQ0 - DQ63 Data Input/Output REGE*) Register Enable
“H” or N.C = registered mode
“L” = buffered mode
CB0 - CB7 Check Bits VDD Power (+ 3.3 V)
RAS Row Address Strobe VSS Ground
CAS Column Address Strobe SCL Clock for Presence Detect
WE Read/Write Input SDA Serial Data Out
CKE0 Clock Enable N.C. No Connection
CLK0 - CLK3 Clock Input – –
Note : *) To confirm to this specification, motherboards must pull this pin to high state or no connect.
Address Format
Density Organization Memory
Banks
SDRAMs # of
SDRAMs
#ofrow/bank/
columns bits
Refresh Period Interval
128 MB 16M ×72 1 16M ×4 18 12/2/10 4k 64 ms 15.6 µs
128 MB 16M ×72 1 16M x 8 9 12/2/10 4k 64 ms 15.6 µs
256 MB 32M x 72 1 32M x 4 18 12/2/11 4k 64 ms 15.6 µs
256 MB 32M x 72 1 32M x 8 9 13/2/10 8k 64 ms 7.8 µs
512 MB 64M ×72 1 64M ×4 18 13/2/11 8k 64 ms 7.8 µs
1GB 128M×72 2 64M ×4 36 13/2/11 8k 64 ms 7.8 µs
1GB 128M×72 1 128M ×4 18 13/2/12 8k 64ms 7.8 µs
2GB 256M×72 2 128M ×4 36 13/2/12 8k 64ms 7.8 µs
HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
INFINEON Technologies 4 2002-07-18
Pin Configuration
PIN# Symbol PIN# Symbol PIN# Symbol PIN# Symbol
1VSS 43 VSS 85 VSS 127 VSS
2 DQ0 44 DU 86 DQ32 128 CKE0
3DQ1 45CS2 87 DQ33 129 CS3
4 DQ2 46 DQMB2 88 DQ34 130 DQMB6
5 DQ3 47 DQMB3 89 DQ35 131 DQMB7
6VDD 48 DU 90 VDD 132 N.C.
7DQ4 49
VDD 91 DQ36 133 VDD
8 DQ5 50 N.C. 92 DQ37 134 N.C.
9 DQ6 51 N.C. 93 DQ38 135 N.C.
10 DQ7 52 CB2 94 DQ39 136 CB6
11 DQ8 53 CB3 95 DQ40 137 CB7
12 VSS 54 VSS 96 VSS 138 VSS
13DQ9 55DQ16 97DQ41 139DQ48
14 DQ10 56 DQ17 98 DQ42 140 DQ49
15 DQ11 57 DQ18 99 DQ43 141 DQ50
16 DQ12 58 DQ19 100 DQ44 142 DQ51
17 DQ13 59 VDD 101 DQ45 143 VDD
18 VDD 60 DQ20 102 VDD 144 DQ52
19 DQ14 61 N.C. 103 DQ46 145 N.C.
20 DQ15 62 DU 104 DQ47 146 DU
21 CB0 63 N.C. 105 CB4 147 REGE
22 CB1 64 VSS 106 CB5 148 VSS
23 VSS 65 DQ21 107 VSS 149 DQ53
24 N.C. 66 DQ22 108 N.C. 150 DQ54
25 N.C. 67 DQ23 109 N.C. 151 DQ55
26 VDD 68 VSS 110 VDD 152 VSS
27 WE 69 DQ24 111 CAS 153 DQ56
28 DQMB0 70 DQ25 112 DQMB4 154 DQ57
29 DQMB1 71 DQ26 113 DQMB5 155 DQ58
30 CS0 72 DQ27 114 CS1 156 DQ59
31 DU 73 VDD 115 RAS 157 VDD
32 VSS 74 DQ28 116 VSS 158 DQ60
33 A0 75 DQ29 117 A1 159 DQ61
34 A2 76 DQ30 118 A3 160 DQ62
35 A4 77 DQ31 119 A5 161 DQ63
36 A6 78 VSS 120 A7 162 VSS
37 A8 79 CLK2 121 A9 163 CLK3
38 A10 (AP) 80 N.C. 122 BA0 164 N.C.
39 BA1 81 WP 123 A11 165 SA0
40 VDD 82 SDA 124 VDD 166 SA1
41 VDD 83 SCL 125 CLK1 167 SA2
42 CLK0 84 VDD 126 A12 168 VDD
HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
INFINEON Technologies 5 2002-07-18
Block Diagram: One Bank 16M x 72, 32M x 72, 64M x 72 and 128M x 72 SDRAM DIMM Modules
HYS72V16300GR, HYS72V32301GR, HYS72V64300GR and HYS72V128320GR
using x4 organized SDRAMs
SPB04135
DQM
DQ0-DQ3
CS
D0
DQM
DQ0-DQ3
D1
DQM
DQ0-DQ3
D2
DQM
DQ0-DQ3
D3
DQM
DQ0-DQ3
D16
DQ0-DQ3
DQ4-DQ7
RDQMB1
DQ8-DQ11
DQ12-DQ15
CB0-CB3
RDQMB0
RCS0
DQM
DQ0-DQ3
D8
DQM
DQ0-DQ3
D9
DQM
DQ0-DQ3
D10
DQM
DQ0-DQ3
D11
DQM
DQ0-DQ3
D17
DQ32-DQ35
DQ36-DQ39
RDQMB5
DQ40-DQ43
DQ44-DQ47
CB4-CB7
RDQMB4
DQM
DQ0-DQ3
D4
DQM
DQ0-DQ3
D5
DQM
DQ0-DQ3
D6
DQM
DQ0-DQ3
D7
DQ16-DQ19
DQ20-DQ23
RDQMB3
DQ24-DQ27
DQ28-DQ31
RDQMB2
RCS2
DQM
DQ0-DQ3
D12
DQM
DQ0-DQ3
D13
DQM
DQ0-DQ3
D14
DQM
DQ0-DQ3
D15
DQ48-DQ51
DQ52-DQ55
RDQMB7
DQ56-DQ59
DQ60-DQ63
RDQMB6
CLK0
12 pF
PLL SDRAMs D0-D17
CLK1, CLK2, CLK3
12 pF
Register
CS0/CS2
DQMB0-7
BA0, BA1
A0-A11, A12
RAS
CAS
CKE0
WE
RCS0/RCS2
RDQMB0-7
RBA0, RBA1
RA0-RA11, RA12
RRAS
RCAS
RCKE0
RWE
REGE
10 kΩ
SDRAMs D0-D17
SDRAMs D0-D17
SDRAMs D0-D17
SDRAMs D0-D17
SDRAMs D0-D17
SDRAMs D0-D17
SA0
SDA
SA0
SA1 SA1
SA2
SA2
SCL
SCL
WP
47 kΩ
E2PROM
(256 word x 8 Bit)
VCC
VSS
C
D0-D17, Reg., DLL
D0-D17, Reg., DLL
1) DQ wirding may differ from that decribed
in this drawing; however DQ/DQB relationship
must be maintained as shown
2) All resistors are 10 Ωunless otherwise noted
VCC
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
INFINEON Technologies 6 2002-07-18
Block Diagram: One Bank 16M x72 and 32M x 72 Modules
HYS72V16301 & HYS72V32300GR using x8 organized SDRAMs
SPB04130-2
DQ0-DQ7
CS
D0
DQ0-DQ7
RDQMB0
RCS0
DQ0-DQ7
CS
D4
DQ32-DQ39
CLK0
12 pF
PLL SDRAMs D0-D8
CLK1, CLK2, CLK3
12 pF
Register
CS0/CS2
DQMB0-7
BA0, BA1
A0-A11,12*
)
RAS
CAS
CKE0
WE
RCS0/RCS2
RDQMB0-7
RBA0, RBA1
RA0-11,12
RRAS
RCAS
RCKE0
RW E
REGE
10 k
Ω
SDRAMs D0-D8
SDRAMs D0-D8
SDRAMs D0-D8
SDRAMs D0-D8
SDRAMs D0-D8
SDRAMs D0-D8
SA0
SDA
SA0
SA1 SA1
SA2
SA2
SCL
SCL
WP
47 k
Ω
E
2
PROM
(256 word x 8 Bit)
V
CC
V
SS
C
D0-D8, Reg., DLL
D0-D8, Reg., DLL
Notes:
1)
DQ wirding may differ from that
decribed in this drawing;
however DQ/DQB relationship
m ust be m ain tained as show n
2)
All resistors are 10
Ω
unless
otherwise noted
*
)
A12 is only for 32 M x 72
organisation
V
CC
DQM RDQMB4 DQM
DQ0-DQ7
CS
D1
DQ8-DQ15
RDQMB1
DQ0-DQ7
CS
D5
DQ40-DQ47
DQM RDQMB5 DQM
DQ0-DQ7
CS
D8
DQM
WE
DQ0-DQ7
CS
D2
DQ16-DQ23
RDQMB2
RCS2
DQ0-DQ7
CS
D6
DQ48-DQ55
DQM RDQMB4 DQM
DQ0-DQ7
CS
D3
DQ24-DQ31
RDQMB3
DQ0-DQ7
CS
D7
DQ56-DQ63
DQM RDQMB7 DQM
CB7CB0-
HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
INFINEON Technologies 7 2002-07-18
Block Diagram: Two Bank 128M x 72 and 256M x 72 SDRAM DIMM Modules
HYS 72V128320GR and HYS72V256320GR Using Stacked x4 Organized SDRAMs
SPB04136
DQM
DQ0-DQ3
D0
DQM
DQ0-DQ3
D0
DQM
DQ0-DQ3
D1
DQM
DQ0-DQ3
D1
DQM
DQ0-DQ3
D2
DQM
DQ0-DQ3
D2
DQM
DQ0-DQ3
D3
DQM
DQ0-DQ3
D3
DQM
DQ0-DQ3
D16
DQM
DQ0-DQ3
D16
DQ0-DQ3
DQ4-DQ7
RDQMB1
DQ8-DQ11
DQ12-DQ15
CB0-CB3
RDQMB0
RCS1
RCS0
DQM
DQ0-DQ3
D8
DQM
DQ0-DQ3
D8
DQM
DQ0-DQ3
D9
DQM
DQ0-DQ3
D9
DQM
DQ0-DQ3
D10
DQM
DQ0-DQ3
D10
DQM
DQ0-DQ3
D11
DQM
DQ0-DQ3
D11
DQM
DQ0-DQ3
D17
DQM
DQ0-DQ3
D17
DQ32-DQ35
DQ36-DQ39
RDQMB5
DQ40-DQ43
DQ44-DQ47
CB4-CB7
RDQMB4
DQM
DQ0-DQ3
D4
DQM
DQ0-DQ3
D4
DQM
DQ0-DQ3
D5
DQM
DQ0-DQ3
D5
DQM
DQ0-DQ3
D6
DQM
DQ0-DQ3
D6
DQM
DQ0-DQ3
D7
DQM
DQ0-DQ3
D7
DQ16-DQ19
DQ20-DQ23
RDQMB3
DQ24-DQ27
DQ28-DQ31
RDQMB2
RCS3
RCS2
DQM
DQ0-DQ3
D12
DQM
DQ0-DQ3
D12
DQM
DQ0-DQ3
D13
DQM
DQ0-DQ3
D13
DQM
DQ0-DQ3
D14
DQM
DQ0-DQ3
D14
DQM
DQ0-DQ3
D15
DQM
DQ0-DQ3
D15
DQ48-DQ51
DQ52-DQ55
RDQMB7
DQ56-DQ59
DQ61-DQ63
RDQMB6
CLK0
12 pF
PLL Stacked SDRAMs D0-D17
CLK1, CLK2, CLK3
12 pF
Register
CS0-CS3
DQMB0-7
BA0, BA1
A0-A11, A12* )
RAS
CAS
CKE0
WE
RCS0-RCS3
RDQMB0-7
RBA0, RBA1
RA0-RA11
RRAS
RCAS
RCKE0
RWE
REGE
10 k
Ω
Stacked SDRAMs D0-D17
Stacked SDRAMs D0-D17
Stacked SDRAMs D0-D17
Stacked SDRAMs D0-D17
Stacked SDRAMs D0-D17
Stacked SDRAMs D0-D17
*)A12 is only used for
128Mx72organisation
SA0
SDA
SA0
SA1 SA1
SA2
SA2
SCL
SCL
WP
E2PROM
(256 word x 8 Bit)
V
CC
V
SS
C
D0-D17, Reg. DLL
D0-D17, Reg. DLL
1.) DQ wirding may differ from that decribed
in this drawing; however DQ/DQB relationship
must be maintained as shown
2.) All resistors are 10
Ω
unless otherwise noted
V
CC
47 k
Ω
CSCS
CSCS
CSCS
CSCS
CSCS
CSCS
CSCS
CSCS
CSCS
CSCS
CSCS
CSCS
CSCS
CSCS
CSCS
CSCS
CSCS
CSCS
HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
INFINEON Technologies 8 2002-07-18
Absolute Maximum Ratings
DC Characteristics
TA=0to70°C1);VSS =0V;VDD =3.3V±0.3 V
Capacitance
TA=0to70°C1);VDD =3.3V±0.3 V, f=1MHz
Parameter Symbol Limit Values Unit
min. max.
Input / Output voltage relative to VSS VIN, VOUT –1.0 4.6 V
Power supply voltage on VDD VDD –1.0 4.6 V
Storage temperature range TSTG -55 +150 oC
Power dissipation (per SDRAM component) PD–1W
Data out current (short circuit) IOS –50mA
Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to recommended operation conditions.
Exposure to higher than recommended voltage for extended periods of time affect device reliability
Parameter Symbol Limit Values Unit
min. max.
Input High Voltage VIH 2.0 VDD +0.3 V
Input Low Voltage VIL –0.5 0.8 V
Output High Voltage (IOUT =–4.0mA) VOH 2.4 – V
Output Low Voltage (IOUT =4.0mA) VOL –0.4V
Input Leakage Current, any input
(0 V < VIN < 3.6 V, all other inputs = 0 V)
II(L) –10 10 µA
Output Leakage Current
(DQ is disabled, 0 V < VOUT <VDD)
IO(L) –10 10 µA
Parameter Symbol Limit Values Unit
One Bank
Modules
Two Bank
Modules
Input Capacitance
(all inputs except CLK and CKE)
CIN 10 20 pF
Input Capacitance (CLK) CCLK 30 30 pF
Input Capacitance (CKE) CCKE 17 30 pF
Input/Output Capacitance(DQ0 - DQ63, CB0 - CB7) CIO 10 17 pF
Input Capacitance (SCL, SA0 - 2) CSC 88pF
Input/Output Capacitance (SDA) CSD 88pF
HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
INFINEON Technologies 9 2002-07-18
Operating Currents per SDRAM Component
TA=0to70°C1),VDD =3.3V±0.3 V
Parameter Test Condition Symbol 64
Mb
128
Mb
256
Mb
512
Mb
Unit Note
max.
Operating current
tRC =tRC(MIN.),tCK =tCK(MIN.)
Outputs open, Burst Length = 4,
CL = 3. All banks operated in
random access, all banks
operated in ping-pong manner
to maximize gapless data
access
–
ICC1 110 160 270 tbd. mA
2)
Precharge stand-by current
in Power Down Mode
CS =VIH(MIN.),CKE≤VIL(MAX.)
tCK =min. ICC2P 21.52tbd.mA
2)
Precharge Stand-by Current
in Non-Power Down Mode
CS =VIH (MIN.),CKE≥VIH(MIN.)
tCK =min. ICC2N 40 40 25 tbd. mA 2)
No operating current
tCK =min.,CS=VIH(MIN.),
active state (max. 4 banks)
CKE ≥VIH(MIN.) ICC3N 50 50 50 tbd. mA 2)
CKE ≤VIL(MAX.) ICC3P 8 1010tbd.mA
2)
Burst operating current
tCK =min.,
Read command cycling
–ICC4
70 100 170 tbd. mA
2), 3)
Auto refresh current
tCK =min.,
Auto Refresh command cycling
–ICC5 140 230 240 tbd. mA 2)
Self refresh current
Self Refresh Mode,CKE = 0.2 V
–ICC6 1 1.5 2.5 tbd. mA 2)
HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
INFINEON Technologies 10 2002-07-18
AC Characteristics (SDRAM Device Specification) 4), 5)
TA=0to70°C1);VSS =0V;VDD =3.3V±0.3 V, tT=1ns
Parameter Symbol Limit Values Unit Note
-7
PC133-222
-7.5
PC133-333
min. max. min. max.
Clock and Access Time
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
tCK
7.5
7.5
–
–
7.5
10
–
–
ns
ns
–
Clock Frequency
CAS Latency = 3
CAS Latency = 2
fCK
–
–
133
133
–
–
133
100
MHz
MHz
–
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
tAC
–
–
5.4
5.4
–
–
5.4
6
ns
ns
–
Clock High Pulse Width tCH 2.5 – 2.5 – ns –
Clock Low Pulse Width tCL 2.5 – 2.5 – ns –
Transition Time tT0.5 7.5 0.5 10 ns –
Setup and Hold Parameters
Input Setup Time tIS 1.5 – 1.5 – ns –
Input Hold Time tIH 0.8 – 0.8 – ns –
Power Down Mode Entry Time tSB –1–1CLK–
Power Down Mode Exit Setup Time tPDE 1–1–CLK–
Mode Register Setup Time tRCS 2–2–CLK–
Common Parameters
Row to Column Delay Time tRCD 15 – 20 – ns –
Row Precharge Time tRP 15 – 20 – ns –
Row Active Time tRAS 37 – 45 100k ns –
Row Cycle Time tRC 60 – 67.5 – ns –
Activate (a) to Activate (b) Command
Period
tRRD 2–2–CLK–
CAS(a) to CAS(b) Command Period tCCD 1–1–CLK–
HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
INFINEON Technologies 11 2002-07-18
Refresh Cycle
Refresh Period
64&128MBit SDRAM Based Modules
256&512MBit SDRAM Based Modules
tREF
–
–
15.6
7.8
–
–
15.6
7.8
µs
µs
–
Self Refresh Exit Time tSREX 1–1–CLK
6)
Read Cycle
Data Out Hold Time tOH 3–3–ns–
Data Out to Low Impedance Time tLZ 0–0–ns
7)
Data Out to High Impedance Time tHZ 3737ns
7)
DQM Data Out Disable Latency tDQZ –2–2CLK–
Write Cycle
Data Input to Precharge
(write recovery)
tWR 2–2–CLK–
DQM Write Mask Latency tDQW 0–0–CLK–
AC Characteristics (SDRAM Device Specification) (cont’d) 4), 5)
TA=0to70°C1);VSS =0V;VDD =3.3V±0.3 V, tT=1ns
Parameter Symbol Limit Values Unit Note
-7
PC133-222
-7.5
PC133-333
min. max. min. max.
HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
INFINEON Technologies 12 2002-07-18
Notes
1. The registered DIMM modules are designed to operate under system operating conditions
between 0-55 deg C ambient, maximum sustained bandwidth and 0 LFM airflow. Operating at
higher ambient temperatures needs sufficient air flow to limit the case temperature of the
SDRAM components do not exceed 85oC.
2. These parameters depend on the cycle rate. All values are measured at 133 MHz operation
frequency. Input signals are changed once during tck excepts for Icc6 and for standby currents
when tck = infinity.
3. These parameters are measured with continous data stream during read access and all DQ
toggling. CL=3 and BL=4 is assumed and the data-out current is excluded.
4. An initial pause of 100 µs is required after power-up. Then a Precharge All Banks command must
be given followed by eight Auto Refresh (CBR) cycles before the Mode Register Set Operation
can begin. Also the on-DIMM PLL must be given enough clock cycles to stabilize (tSTAB) before
any operation can be guaranteed.
5. AC timing tests have VIL =0.8VandVIH = 2.0 V with the timing referenced to the 1.4 V crossover
point.ThetransitiontimeismeasuredbetweenVIH and VIL. All AC measurements assume
tT= 1 ns with the AC output load circuit shown. Specified tAC and tOH parameters are measured
with a 50 pF only, without any resistive termination and with a input signal of 1 V/ns edge rate
between 0.8 V and 2.0 V.
6. Self Refresh Exit is a synchronous operation and begins on the second positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied
after the Self Refresh Exit command is registered.
7. Referenced to the time at which the output achieves the open circuit condition, not to output
voltage levels.
Serial Presence Detect
A serial presence detect storage device - E2PROM 34C02 - is assembled onto the module.
Information about the module configuration, speed, etc. is written into the E2PROM device during
module production using a serial presence detect protocol (I2C synchronous 2-wire bus).The first
128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end
user.
50 pF
I/O
Measurement conditions for
tAC and tOH
CLOCK 2.4 V
0.4 V
IN PU T
IS
t
t
T
OUTPUT 1.4 V
t
LZ
AC
t t
AC
OH
t
HZ
t
1.4 V
CL
t
CH
t
IH
t
1.4 V
IO.vsd
HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
INFINEON Technologies 13 2002-07-18
SPD-Table for -7.5 Registered DIMM Modules
Byte
#
Description SPD
Entry
Value
Hex
128 MB,1Bnk,64Mb based
HYS 72V16300GR-7.5-C/E
128 MB,1Bnk,128Mb based
HYS 72V16301GR-7.5-C2
256 MB,1Bnk,128Mb based
HYS 72V32301GR-7.5-C2
256 MB,1Bnk,256Mb based
HYS 72V32300GR-7.5-C2
256 MB,1Bnk,256Mb based
HYS 72V32300GR-7.5-D
512 MB,1Bnk,256Mb based
HYS 72V64300GR-7.5-C2
512 MB,1Bnk,256Mb based
HYS 72V64300GR-7.5-D
1 GB,2Bnks,256Mb based
HYS 72V128320/1GR-7.5-C2
1 GB,2Bnks,256Mb based
HYS 72V128320/1GR-7.5-D
1 GB,1Bnk,512Mb based
HYS 72V128300GR-7.5-A
2 GB,2Bnks, 512Mb based
HYS 72V256320/1GR-7.5-A
0Number of SPD Bytes 128 80
1Total Bytes in Serial PD 256 08
2Memory Type SDRAM 04
3NumberofRowAddresses12/13 0C0C0C0D0D0D0D0D0D0D0D
4Number of Column
Addresses
10/11/12 0A 0A 0B 0A 0A 0B 0B 0B 0B 0C 0C
5Number of DIMM Banks 1/2 01 01 01 01 01 01 01 02 02 01 02
6Module Data Width 72 48
7Module Data Width (cont’d) 0 00
8Module Interface Levels LVTTL 01
9CycleTimeatCL=3 7.5ns 75
10 Access Time from Clock at
CL = 3
5.4 ns 54
11 DIMM Config (Error Det/
Corr.)
ECC 02
12 Refresh Rate/Type 15.6/7.8 µs8080808282828282828282
13 SDRAMWidth,Primary x4/x8 0408040808040404040404
14 Error Checking SDRAM
Data Width
x4/x8 0408040808040404040404
15 Minimum tCCD 1 CLK 01
16 Burst Length Supported 1, 2, 4, 8 &
(full page)
8F 0F 0F 0F 8F 0F 8F 0F 8F 8F 8F
17 Number of SDRAM Banks 4 04
18 SDRAM Supported CAS
Latencies
2&3 06
19 SDRAM CS Latencies 0 01
20 SDRAM WE Latencies 0 01
21 SDRAM DIMM Module
Attributes
with PLL 1F
22 SDRAM Device Attributes VDD tol +/–
10%
0E
23 Min. Clock Cycle Time at
CL = 2
10 ns A0
24 Max. Data Access Time from
Clock for CL = 2
6.0 ns 60
HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
INFINEON Technologies 14 2002-07-18
25 Min. Clock Cycle Time at
CL = 1
not
supported
00
26 Max. Data Access Time from
Clock at CL = 1
not supp. 00
27 SDRAM Minimum tRP 20 ns 14
28 SDRAM Minimum tRRD 15 ns 0F
29 SDRAM Minimum tRCD 20 ns 14
30 SDRAM Minimum tRAS 45 ns 2D
31 Module Bank Density (per
bank)
128 MByte
256 Mbyte
512 MByte
1GByte
20 20 40 40 40 80 80 80 80 01 01
32 SDRAM Input Setup Time 1.5 ns 15
33 SDRAM Input Hold Time 0.8 ns 08
34 SDRAM Data Input Setup
Time
1.5 ns 15
35 SDRAM Data Input Hold
Time
0.8 ns 08
36-61 Superset Information
(may be used in future)
–00
62 SPD Revision JEDEC 2 12
63 Checksum for Bytes 0 - 62 – D8 60 79 83 03 BC 3C BD 3D BE BF
64-
125
Manufacturer’s Information –
126 Frequency Specification – 64
127 Details of Clocks – 8F
128+ Unused Storage Locations – FF
SPD-Table for -7.5 Registered DIMM Modules (cont’d)
Byte
#
Description SPD
Entry
Value
Hex
128 MB,1Bnk,64Mb based
HYS 72V16300GR-7.5-C/E
128 MB,1Bnk,128Mb based
HYS 72V16301GR-7.5-C2
256 MB,1Bnk,128Mb based
HYS 72V32301GR-7.5-C2
256 MB,1Bnk,256Mb based
HYS 72V32300GR-7.5-C2
256 MB,1Bnk,256Mb based
HYS 72V32300GR-7.5-D
512 MB,1Bnk,256Mb based
HYS 72V64300GR-7.5-C2
512 MB,1Bnk,256Mb based
HYS 72V64300GR-7.5-D
1 GB,2Bnks,256Mb based
HYS 72V128320/1GR-7.5-C2
1 GB,2Bnks,256Mb based
HYS 72V128320/1GR-7.5-D
1 GB,1Bnk,512Mb based
HYS 72V128300GR-7.5-A
2 GB,2Bnks, 512Mb based
HYS 72V256320/1GR-7.5-A
HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
INFINEON Technologies 15 2002-07-18
SPD-Table for -7 Registered DIMM Modules
Byte# Description SPD
Entry
Value
Hex
128 MB,1Bnk,64Mb based
HYS 72V16300GR-7-E
128 MB,1Bnk,128Mb based
HYS 72V16301GR-7-C2
256 MB,1Bnk,128Mb based
HYS 72V32301GR-7-C2
256 MB,1Bnk,256Mb based
HYS 72V32300GR-7-D
512 MB,1Bnk,256Mb based
HYS 72V64300GR-7-D
1 GB,2Bnks,256Mb based
HYS 72V128320/1GR-7-D
1 GB,1Bnk,512Mb based
HYS 72V128300GR-7-A
2 GB,2Bnks,512Mb based
HYS 72V256320/1GR-7-A
0Number of SPD Bytes 128 80
1Total Bytes in Serial PD 256 08
2Memory Type SDRAM 04
3Number of Row Addresses 12/13 0C 0C 0C 0D 0D 0D 0D 0D
4Number of Column
Addresses
10/11/12 0A0A0B0A0B0B0C0C
5Number of DIMM Banks 1/2 01 01 01 01 01 02 01 02
6Module Data Width 72 48
7Module Data Width (cont’d) 0 00
8Module Interface Levels LVTTL 01
9CycleTimeatCL=3 7.5ns 75
10 Access Time from Clock at
CL = 3
5.4 ns 54
11 DIMM Config (Error Det/
Corr.)
ECC 02
12 Refresh Rate/Type 15.6/7.8 µs8080808282828282
13 SDRAMWidth,Primary x4/x8 0408040804040404
14 Error Checking SDRAM Data
Width
x4/x8 0408040804040404
15 Minimum tCCD 1 CLK 01
16 Burst Length Supported 1, 2, 4, 8 &
(full page)
8F 0F 0F 8F 8F 8F 8F 8F
17 Number of SDRAM Banks 4 04
18 SDRAM Supported CAS
Latencies
2&3 06
19 SDRAM CS Latencies 0 01
20 SDRAM WE Latencies 0 01
21 SDRAMDIMMModule
Attributes
with PLL 1F
22 SDRAM Device Attributes VDD tol +/–
10%
0E
23 Min. Clock Cycle Time at
CL = 2
7.5 ns 75
24 Max. Data Access Time from
Clock for CL = 2
5.6 ns 54
HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
INFINEON Technologies 16 2002-07-18
25 Min. Clock Cycle Time at
CL = 1
not
supported
00
26 Max. Data Access Time from
Clock at CL = 1
not supp. 00
27 SDRAM Minimum tRP 15 ns 0F
28 SDRAM Minimum tRRD 14 ns 0E
29 SDRAM Minimum tRCD 15 ns 0F
30 SDRAM Minimum tRAS 37 ns 25
31 Module Bank Density (per
bank)
128 MByte
256 Mbyte
512 MByte
1024 MByte
20 20 40 40 80 80 01 01
32 SDRAM Input Setup Time 1.5 ns 15
33 SDRAM Input Hold Time 0.8 ns 08
34 SDRAM Data Input Setup
Time
1.5 ns 15
35 SDRAM Data Input Hold
Time
0.8 ns 08
36-61 Superset Information
(may be used in future)
–00
62 SPD Revision JEDEC 2 12
63 Checksum for Bytes 0 - 62 – 8E 16 2F B9 F2 F3 74 75
64-125 Manufacturer’s Information –
126 Frequency Specification – 64
127 Details of Clocks – 8F
128+ Unused Storage Locations – FF
Byte# Description SPD
Entry
Value
Hex
128 MB,1Bnk,64Mb based
HYS 72V16300GR-7-E
128 MB,1Bnk,128Mb based
HYS 72V16301GR-7-C2
256 MB,1Bnk,128Mb based
HYS 72V32301GR-7-C2
256 MB,1Bnk,256Mb based
HYS 72V32300GR-7-D
512 MB,1Bnk,256Mb based
HYS 72V64300GR-7-D
1 GB,2Bnks,256Mb based
HYS 72V128320/1GR-7-D
1 GB,1Bnk,512Mb based
HYS 72V128300GR-7-A
2 GB,2Bnks,512Mb based
HYS 72V256320/1GR-7-A
HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
INFINEON Technologies 17 2002-07-18
Package Outlines for Raw Card AA
Module Package
JEDEC MO-161
Registered DIMM Modules Raw Card AA (L-DIM168-44)
note: all outline dimensions and tolerances are in accordance with the JEDEC standard
133.35
10 11
36.35 6.35
4140
42.18
84
127.35
3
1.27
0.1
±
85 94 95 124 125 168
2
17.78
3.125
±0.1
4
4max.
38.10
Detail of Contacts
2.55
1
+0.5
1.27
1
1.27
66.68
0.25
PLL Register
Register
L-DIM-168-44
0.15
±
0.13
±
HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
INFINEON Technologies 18 2002-07-18
Package Outlines for Raw Card B
Module Package
JEDEC MO-161
Registered DIMM Modules Raw Card B (L-DIM168-37)
128MB, 256MB, 512MB & 1GB modules based on
x4 SDRAM components
note: all outline dimensions and tolerances are in accordance with the JEDEC standard
133.35
10 11
36.35 6.35
4140
42.18
84
127.35
3
1.27
0.1
±
85 94 95 124 125 168
2
17.78
3.125
±0.1
4
4max.
43.18
Detail of Contacts
2.55
1
+0.5
1.27
1
1.27
66.68
0.25
PLLRegister
Register
L-DIM-168-37
Register
0.13
±
0.15
±
HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
INFINEON Technologies 19 2002-07-18
Package Outlines for Raw Card B (with stacked components)
Module Package
JEDEC MO-161
Registered DIMM Modules Raw Card B (L-DIM168-37)
1 GByte and 2 GByte modules
note: all outline dimensions and tolerances are in accordance with the JEDEC standard
133.35
10 11
36.35 6.35
4140
42.18
84
127.35
3
1.27
0.1
±
85 94 95 124 125 168
2
17.78
3.125
±0.1
4
6.8 max.
43.18
Detail of Contacts
2.55
1
+0.5
1.27
1
1.27
66.68
0.25
PLL
Register
L-DIM-168-37-S
Register
Register
0.15
±
0.13
±
HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
INFINEON Technologies 20 2002-07-18
Functional Description
All these PC133 168-pin Registered DIMMs conform to a compatible set of timing and operation
characteristics intended to comply with the 133 MHz standards. The Registered DIMMs achieve
high speed data transfer rate up to 133 MHz, when in “registered mode”. The “registered mode” is
achieved when the REGE input signal is in “high” state or the pin is not connected. Operation in
“buffered mode” (REGE = “low”) needs careful system design to compensate all input signals for the
extra delay time of the register components when in “buffered mode”. “Buffered mode” is limited to
66 Mhz maximum operation frequency.
Registered Mode:
All control and address signals are synchronized with the positive edge of externally supplied clocks
and are registered on-DIMM and hence delayed by one clock cycle in arriving at the SDRAM
devices. The use of the on-board register reduces the capacitive loading of the DIMM on input
control and address signals. The SDRAM device data lines (DQ) are connected directly to the DIMM
tabs through 10 Ohm series resistors. All the following timing diagrams and explanations show
DIMM operation at the tabs, not SDRAM operation.
The picture below depicts an overview of the effect of the Registered Mode on the data outputs
(DQs) for a Read operation. Without the registers, the data is delayed according to the device CAS
latency, in the case two clocks. With the register, the data is delayed according to the device CAS
latency plus an additional clock cycle. This is known as the DIMM CAS latency, and in this example
is four three. The data path can be thought of as a pipeline in which the register effectively lengthens
thepipebyoneclockcycle.
In case of a Burst Write Command the data-in is delayed one clock due the op-DIMM pipeline
register also. Therefore, data for the first Burst Write cycle must be applied on the DQ pins on the
next clock cycle after the Write command is issued. the remaining data inputs must be supplied on
SPT03968
CLK
Read A
T0 T1 T2 T3 T4 T5 T6
Command
DOUT A0 DOUT A1 DOUT A2 DOUT A3
NOP NOP NOP NOP NOP
CAS latency = 2
, DQ’s
CK2
t
Registered DIMM Burst Read Operation (BL = 4)
Device
NOP
DOUT A1DOUT A0 DOUT A2 DOUT A3CAS latency = 3
DIMM
, DQ’s
CK3
t
One Clock Added for on-DIMM pipeline register
Reg-DIMM Latency = 1
HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
INFINEON Technologies 21 2002-07-18
each subsequent rising clock edge until the burst length is completed. When the burst has finished,
any additional data supplied to the DQ pins will be ignored.
Registered DIMM Burst Write Operation (BL = 4)
DQ’s
Thefirst data element and theWrite
areregistered on the next clockedge
Reg-DIMM Latency = 1 CLK
DINA0 DINA1
Extra data isignored after
termination ofaBurst.
don’t care
DINA2 DINA3
SPT03969
T8
NOP
CLK
Command NOP
T0
Write A
T1
NOP
T2
NOP
T3 T6
NOP
T4
NOP
T5 T7
NOP NOP
HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
INFINEON Technologies 22 2002-07-18
