LT1997-3
30
19973f
For more information www.linear.com/LT1997-3
applicaTions inForMaTion
Shutdown
The LT1997-3 has a shutdown pin (SHDN). Under normal
operation this pin should be tied to V+ or allowed to float.
Tying this pin 2.5V or more below V+ will cause the part
to enter a low power state. The supply current is reduced
to less than 25µA and the op amp output becomes high
impedance. The voltages at the input pins can be still be
present even in shutdown mode.
Supply Voltage
The positive supply pin of the LT1997-3 should be bypassed
with a small capacitor (typically 0.1µF) as close to the supply
pins as possible. When driving heavy loads, an additional
4.7µF electrolytic capacitor should be added. When using
split supplies, the same is true for the V– supply pin.
Output
The output of the LT1997-3 can typically swing to within
100mV of either rail with no load and is capable of sourcing
and sinking approximately 25mA at 25°C. The LT1997-3 is
internally compensated to drive at least 1nF of capacitance
under any output loading conditions. For larger capacitive
loads, a 0.22µF capacitor in series with a 150Ω resistor
between the output and ground will compensate the
amplifier to drive capacitive loads greater than 1nF. Ad-
ditionally, the LT1997-3 has more gain and phase margin
as its gain is increased.
Distortion
The LT1997-3 features excellent distortion performance
when the internal op amp is operating in the normal op-
erating region. Operating the LT1997-3 with the internal
op amp in the over the top region will increase distortion
due to the lower loop gain of the op amp. Operating the
LT1997-3 with input common mode voltages that go from
the normal to Over-The-Top operation will significantly
degrade the LT1997-3’s linearity as the op amp must
transition between two different input stages. Driving
resistive loads significantly smaller than the 22.5k internal
feedback resistor will also degrade the amplifier’s linearity
performance.
Power Dissipation Considerations
Because of the ability of the LT1997-3 to operate on power
supplies up to ±25V, to withstand very high input volt-
ages and to drive heavy loads, there is a need to ensure
the die junction temperature does not exceed 150°C. The
LT1997-3 is housed in DF14 (θJA = 45°C/W, θJC = 3°C/W)
and MS16 (θJA = 130°C/W) packages.
In general, the die junction temperature (TJ) can be es-
timated from the ambient temperature (TA), the device’s
power dissipation (PD) and the thermal resistance of the
device and board (θJA).
TJ = TA + PD • θJA
The thermal resistance from the junction to the ambient
environment (θJA) is the sum of the thermal resistance
from the junction to the exposed pad (θJC) and the thermal
resistance from the exposed pad to the ambient environ-
ment (θCA). The θCA value depends on how much PCB
metal is connected to the exposed pad in the board. The
more PCB metal that is used, the lower θCA and θJA will be.
Power is dissipated by the amplifier’s quiescent current, by
the output current driving a resistive load, and by the input
current driving the LT1997-3’s internal resistor network.
P
D=VS+– VS–
( )
•IS
+POD +P
RESD
For a given supply voltage, the worst-case output power
dissipation POD(MAX) occurs with the output voltage at half
of either supply voltage. POD(MAX) is given by:
POD(MAX) =VS2
( )
2
R
The power dissipated in the internal resistors (PRESD)
depends on the manner the input resistors have been
configured as well as the input voltage, the output voltage
and the voltage on the REF pin. The following equations
and Figure18 show the different components of PRESD
corresponding to the different groups of the LT1997-3’s
internal resistors, assuming that the LT1997-3 is used with
a dual supply configuration with +INC, –INC, and REF pins