ANALOG CMOS Low Cost DEVICES 8-Bit Buffered Multiplying DAC AD7524 1.1 Scope. This specification covers the detail requirements for an 8-bit monolithic CMOS multiplying digital-to-analog converter with on-chip latches for direct interface to most microprocessors. The AD7524 can be used with any supply voltage from +5V to +15V. 1.2 Part Number. The complete part number per Tables 1 and 2 of this specification is as follows: Device Part Number! -l AD7524S(XY883B 2 AD7524T(X)/883B 3 AD7524U(X)/883B NOTE See paragraph 1.2.3 for package identifier. 1.2.3 Case Outline. See Appendix 1 of General Specification ADI-M-1000: package outline: (X) Package Description Q Q-16 16-Pin Cerdip E E-20A 20-Contact LCC 1.3 Absolute Maximum Ratings. (T, = 25C unless otherwise noted) Vpp toGND .. 0... ee te es Veres toGND .. 0... ee Vrer toGND .. 0... 0.0. ce ee ee ee ee Digital Input VoltagetoGND ............02.00005 Vout > Vout2 (Pin 1, Pin 2) toGround ....,....,...... Power Dissipation Upto +75C 2... ee ee es Derates above +75 2. ee ee Operating Temperature Range ..........020 00 eee Storage Temperature Range... 2... 2... eee es Lead Temperature (Soldering l0sec) ............0.... Note: Pin numbers refer to DIP package ONLY 1.5 Thermal Characteristics. Thermal Resistance 0j = 35C/W for Q-16and E-20A Oya = 120C/W for Q-16 and E-20A ee ee 0.3V, +17V Ce ee ee ee +25V Se eee +25V a -0.3V to Vpp ewe we ee ae 0.3V to Vop Lee ee ee 6m W/C ce eee 55C to + 125C Lee eee 65C to + 150C Le ee eee + 300C DIGITAL-TO-ANALOG CONVERTERS 8-111 1 DIGITAL-TO-ANALOG CONVERTERS aAD7524 SPECIFICATIONS Table 1. Design Sub |;Sub [Sub Limit Group| Group] Group | Test Condition Test Symbol] Device | TaisTmax| 1 2,3 |4 Vpp= + 15V Units Resolution RES -1,2,3 |8 its Relative Accuracy RA -1 1/2 1/2 1/2 + LSB max -2 1/4 1/2 4 =/1/4 -3 1/8 1/2 1/8 1/8 Gain Error AE -1,2,3 | 0.6 0.5 10.6 +% FSR max Gain Tempco TCag | -1,2,3 | 10 From + 25C to Trex tO Tmin + ppm/C max Power Supply Rejection PSRR | -1,2,3 | 0.04 0.02 | 0.04 AVpp = + 10% + %/% max Output Leakage Current Tour Io. | 1,2,3| 200 50 | 200 DBO-DB7 =0V, WR=CS=0V_ |+nA max lour2 lor -1,2,3] 200 50 200 DBO-DB7 = Vpp, WR = CS = 0V| + nA max Output Current Settling Time | ts. -1,2,3 | 350 To + V/2LSB; Rouri = 1000 ns max Couti = 13pF; WR=CS = 0V; DBO-DB7 = 0V to Vppor Vpp to 0V Feedthrough Error FT -1,2,3 | 50 Vrer= + 10V, 100kHz Sinewave; mV p-p max DBO-DB7 = 0V; WR=CS=0V Input Resistance (Pin 15) Rw -1,2,315 5 5 kO min 20 20 20 kQ max Digital Input High Voltage Vin -1,2,3 | 13.5 13.5 | 13.5 Vmin Digital Input Low Voltage Vin -1,2,3} 1.5 1.5 1.5 V max Digital Input Leakage Current | lin -1,2,3] 10 1 10 Vin = OV or Vop +pA max Digital Input Capacitance DBO-DB7 Gw -1,2,3| 5 pF max WR, CS 20 pF max Output Capacitance __ , Cour: | 1,2,3| 120 DBO-DB7 = Vpp; WR = CS = 0V| pF max Courz | 1,2,3] 30 Coun {| -1,2,3| 30 DBO-DB7 = 0V; WR=CS=0V | pF max Coum | 1,2,3| 120 Supply Current Ipp -1,2,3| 2 2 2 All Digital Inputs = Vy or Vox _ | mA max 500 100 500 All Digital Inputs = OV or Vop pA max Chip Select toWriteSetup Time | tes 1,2,3] 150 ns min Chip Select to Write Hold Time") tox 1,2,3] 0 ns min Write Pulse Width* twr 1,2,3] 150 ns min Data Setup Time* tps -1,2,3] 100 ns min Data Hold Time* ton 1,2,3| 10 ns min NOTES 'Vour: = Vout2=0V; Vrer = + 10V unless otherwise stated. 2Measured using internal Rpg and includes effect of leakage current and gain TC. 2 Feedthrough error can be reduced by connecting the metal lid on the package to ground. Timing per Figure 1. 8-112 DIGITAL-TO-ANALOG CONVERTERS REV. CAD7524 Table 2. Design Sub |Sub j|Sub Limit Group|Group|Group| Test Condition! Test Symbol] Device | Tyain~Tmax| I 2,3 |4 Vpp= +5V Units Resolution RES -1,2,3]8 Bits Relative Accuracy RA -1,2,3) 1/2 1/2 1/2 + LSB max Gain Error AE -1,2,3] 1.4 1.0 1.4 + % FSR max Gain Tempco TCaz | -1,2,3| 40 From + 25C to Tax t0 T min + ppm/C max Power Supply Rejection PSRR | 1,2,3 | 0.16 0.08 | ]0.16 AVpp= + 10% + %/% max Output Leakage Current lous lon. 1,2,3| 400 50 400 DBO-DB7 =0V, WR=CS=0V_ |+nAmax Toutrz Tou. -1,2,3] 400 50 400 DB0O-DB7 = Vpp, WR = CS = 0V| + nA max Output Current Setuling Time [ts 1,2,3 | 500 To + V/2LSB; Royri = 1000 ins max Couri = 13pF; WR =CS = 0V; DBO-DB7 = 0V to Vppor Vpp to0V Feedthrough Error? FT 1,2,3 | 50 Vaer= + 10V, 100kHz Sinewave;imV p-p max DBO-DB7 = 0V; WR =CS=0V Input Resistance (Pin 15) Rw -1,2,3|5 5 5 KN min 20 20 20 KO max Digital Input High Voltage Vin 1,2,3) 2.4 2.4 2.4 'V min Digital Input Low Voltage Vin -1,2,3] 0.8 0.8 0.8 'V max Digital Input Leakage Current |Iiw -1,2,3] 10 1 10 Vin = 0VorVpp +pA max Digital Input Capacitance DBO-DB7 Gn |-1,2,3]5 F max WR,CS 20 pF max Output Capacitance Cour: | 1,2,3 | 120 DBO-DB7 = Vpp; WR = CS = 0V| pF max Courz | 1,2,3] 30 Cour | -1,2,3| 30 DB0-DB7 =0V; WR=CS=0V [pF max Courz | -1,2,3] 120 Supply Current Ipp -1,2,3| 2 2 2 All Digital Inputs= Vitor Vin | mA max 500 100 |500 All Digital Inputs=OVorVpp |pAmax Chip Select to Write SetupTime*} tcs 1,2,3] 240 ns min Chip Select to Write Hold Time*} to -1,2,3| 0 ns min Write Pulse Width* twr -1,2,3] 240 ns min Data Setup Time* tps 1,2,3| 170 ns min Data Hold Time* tpy 1,2,3] 10 ns min NOTES Vout = Vour2 = OV; Ver = + 10V unless otherwise stated. 7M d using i I Rep and includes effect of leak: urrent and gain TC. Feedthrough error can be reduced by connecting the metal lid on the package to ground. Timing per Figure 1. REV. C DIGITAL-TO-ANALOG CONVERTERS 8-113 1 DIGITAL-TO-ANALOG CONVERTERS aAD7524 3.2.1 Functional Block Diagram and Terminal Assignments. Vop - 14 Be o > a a3a8e > 5 10k 10K 10k VAEF pe et 3.2 1 20 19 20 = $20k = $ 20k $20 $20 : 4 16 t 0 Fee ' 18 , st S-2 fy $3 } $8 S10 GND 4 a Vpo ' i i? 0B7(MSB) 5 17 WR \ 1 +O4 5 out! AD7524 Ne ' i ! ! NC 6 TOP VIEW 6 b+ + t } 5 T OUT2 pes 7 (Not to Scale} 15 S CHIP SELECT 12 t : 1+ts 1 u . 14 DBO(LSB) DATA LATCHES 3 ~OGNO bes 8 WATE tL . AD7524 7 a 9 10 19 12 13 5 eone 3 DB? oB6 DBS DBO 22235 g ) (LSB) 5 6 a DATA INPUTS 3.2.4 Microcircuit Technology Group. This microcircuit is covered by technology group (80). 4.2. 1 Life Test/Burn-In Circuit. Steady state life test is per MIL-STD-883 Method 1005. Burn-in is per MIL-STD-883 Method 1015 test condition (B). | Table 3. Mode Selection Table I GND _ | cS | WR MODE DAC RESPONSE | L L Write DAC responds to data bus (DBO DB7) inputs H Xx Hold Data bus (DBO DB7) is locked out; DATA X H Hold DAC holds last data present 100k OAT = GND - STATIC TEST when WR or cs assumed 1 ONE PER BOARD HIGH state. NOTE ALL RES(STOR 5% 1/4 METAL FILM AT 125C USE SAME BURN-IN BOARD AS AD7520/A07521 SERIES tcH L = Low State, H = High State, X = Don't Care. e0 _ tCS_ _____= | <5 | Vop CHIP SELECT Q NOTES: 4. All input signal rise and fall times measured from Voo 10% to 90% of Vop. Von = +5V. tr = ty = 20ns; WR Vop = +15V, 4 = tr = 40ns. WRITE 0 2. Timing Measurement Reference levei is vin Ni je- tps -we| "DH 3. tos + tox is approximately constant at 145ns min Vpo at +25C, Vop = +5V and twr = 170ns min. The Vin DATA IN s AD75264 is specified for a minimum ton of 10ns, DATA IN (DBO 0B7) however, in applications where toy > 10ns, tos Viv TABLE Z 0 may be reduced accordingly up to the limit tps = 65ns, ton = 80ns. Figure 1. Write Cycle Timing Diagram 8-114 DIGITAL-TO-ANALOG CONVERTERS REV. C