eGaN(R) FET DATASHEET EPC2016 EPC2016 - Enhancement Mode Power Transistor VDSS , 100 V RDS(ON) , 16 mW ID , 11 A NEW PRODUCT EFFICIENT POWER CONVERSION HAL Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment leveraging the infrastructure that has been developed over the last 55 years. GaN's exceptionally high electron mobility and low temperature coefficient allows very low RDS(ON), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. EPC2016 eGaN(R) FETs are supplied only in passivated die form with solder bars Maximum Ratings VDS ID VGS TJ TSTG Drain-to-Source Voltage (Continuous) 100 V Drain-to-Source Voltage (up to 10,000 5ms pulses at 125 C) 120 V Continuous (TA = 25C, JA = 32) 11 Pulsed (25C, Tpulse = 300 s) 50 Gate-to-Source Voltage 6 Gate-to-Source Voltage -5 Operating Temperature -40 to 125 Storage Temperature -40 to 150 PARAMETER Applications * High Speed DC-DC conversion * Class D Audio * Hard Switched and High Frequency Circuits A Benefits * Ultra High Efficiency * Ultra Low RDS(on) * Ultra low QG * Ultra small footprint V C TEST CONDITIONS MIN 100 TYP MAX UNIT Static Characteristics (TJ= 25C unless otherwise stated) BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 200 A IDSS Drain Source Leakage VDS = 80 V, VGS = 0 V 25 150 Gate-Source Forward Leakage VGS = 5 V 0.5 3 Gate-Source Reverse Leakage VGS = -5 V 0.1 0.5 VGS(th) Gate Threshold Voltage VDS = VGS, ID = 3 mA 1.4 2.5 V RDS(ON) Drain-Source On Resistance VGS = 5 V, ID = 11 A 12 16 m IGSS 0.7 V A mA Source-Drain Characteristics (TJ= 25C unless otherwise stated) VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V, T = 25C 1.68 IS = 0.5 A, VGS = 0 V, T = 125C 1.73 V All measurements were done with substrate shorted to source. Thermal Characteristics TYP RJC Thermal Resistance, Junction to Case 3.6 C/W RJB Thermal Resistance, Junction to Board 19 C/W RJA Thermal Resistance, Junction to Ambient (Note 1) 69 C/W Note 1: RJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board. See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details. EPC - EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2013 | | PAGE 1 eGaN(R) FET DATASHEET EPC2016 PARAMETER TEST CONDITIONS MIN TYP MAX 433 520 225 280 UNIT Dynamic Characteristics (TJ= 25C unless otherwise stated) CISS Input Capacitance COSS Output Capacitance CRSS Reverse Transfer Capacitance 4.3 6 QG Total Gate Charge (VGS = 5 V) 3.8 5.2 QGD Gate to Drain Charge 0.70 1.4 QGS Gate to Source Charge 0.99 1.5 QOSS Output Charge 20 30 QRR Source-Drain Recovery Charge 0 0 VDS = 50 V, VGS = 0 V VDS = 50 V, ID = 11 A pF nC All measurements were done with substrate shorted to source. Figure 1: Typical Output Characteristics 50 50 VGS = 5 VGS = 4 VGS = 3 VGS = 2 30 20 0 0.5 1 1.5 VDS - Drain to Source Voltage (V) Figure 3: RDS(on) vs VGS for Various Drain Currents 20 50 ID = 8 A ID = 12 A ID = 20 A ID = 40 A 35 30 20 15 10 5 2 2.5 3 3.5 4 VGS - Gate to Source Voltage (V) 4.5 0.5 1 1.5 2 2.5 3 3.5 4 VGS - Gate-to-Source Voltage (V) 5 4.5 Figure 4: RDS(on) vs VGS for Various Temperatures 25C 125C 45 25 0 30 0 2 R DS(ON) - Drain to Source Resistance (m) R DS(ON) - Drain to Source Resistance (m) 40 V DS = 3V 10 10 0 25C 125C 40 ID - Drain Current (A) - Drain Current (A 40 Figure 2: Transfer Characteristics 40 ID = 11 A 35 30 25 20 15 10 5 0 2 2.5 EPC - EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2013 | 3 3.5 4 VGS - Gate-to-Source Voltage (V) 4.5 5 | PAGE 2 eGaN(R) FET DATASHEET EPC2016 Figure 6: Gate Charge Figure 5: Capacitance 0.8 5 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 0.7 4 VG - Gate Voltage (V) C- Capacitance (nF) 0.6 0.5 0.4 0.3 0.2 3.5 3 2.5 2 1.5 1 0.1 0 ID = 11A VD = 50 V 4.5 0.5 0 20 40 60 80 0 100 0 0.5 1 1.5 Figure 7: Reverse Drain-Source Characteristics 1.8 25C 125C 40 30 20 10 0 1.5 0 0.5 1 1.5 2 2.5 3 3.5 VSD - Source to Drain Voltage (V) 3.5 4 ID = 11A VGS = 5 V 1.4 1.2 1 0.8 -20 4 0 20 40 60 80 100 TJ - Junction Temperature ( C ) 120 140 Figure 10: Gate Current 0.015 25C 125C ID = 3 mA 1.3 1.2 IG - Gate Current (A) Normalized Threshold Voltage 3 1.6 Figure 9: Normalized Threshold Voltage vs. Temperature 1.4 2.5 Figure 8: Normalized On Resistance vs. Temperature Normalized On-State Resistance - RDS(ON) ISD - Source to Drain Current (A) 50 2 QG - Gate Charge (nC) VDS - Drain to Source Voltage (V) 1.1 1 0.9 0.8 0.01 0.005 0.7 0.6 0.5 -20 0 20 40 60 80 100 120 140 0 0 1 TJ - Junction Temperature ( C ) 2 3 4 5 6 VGS - Gate-to-Source Voltage (V) All measurements were done with substrate shortened to source. EPC - EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2013 | | PAGE 3 eGaN(R) FET DATASHEET EPC2016 Figure 11: Transient Thermal Response Curves Normalized Maximum Transient Thermal Impedance ZJB, Normalized Thermal Impedance 1 Duty Factors: 0.5 0.1 0.2 0.1 0.05 0.01 0.02 0.01 t1 Single Pulse 0.001 0.0001 PDM 10-5 10-4 t2 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZJB x RJB + TB 10-3 10-2 10-1 1 10 100 tp, Rectangular Pulse Duration, seconds Normalized Maximum Transient Thermal Impedance ZJC, Normalized Thermal Impedance 1 Duty Factors: 0.5 0.1 0.2 0.1 PDM 0.05 t1 0.01 0.02 0.01 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZJC x RJC + TC Single Pulse 0.001 1.0E-06 t2 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+01 tp, Rectangular Pulse Duration, seconds Figure 12: Safe Operating Area I D- Drain Current (A) 100 10 s 10 100 s limited by RDS(ON) 1 ms 1 10 ms 0.1 TJ = Max Rated, TC = +25C, Single Pulse 0.1 1 10 100 ms/DC 100 1000 VDS - Drain-Source Voltage (V) EPC - EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2013 | | PAGE 4 eGaN(R) FET DATASHEET EPC2016 TAPE AND REEL CONFIGURATION 4mm pitch, 8mm wide tape on 7" reel b e d g f Loaded Tape Feed Direction Die orientation dot 7" reel c a Gate solder bar is under this corner Die is placed into pocket solder bar side down (face side down) EPC2016 (note 1) Dimension (mm) target min max a b c (see note) d e f (see note) g 8.00 1.75 3.50 4.00 4.00 2.00 1.5 7.90 1.65 3.45 3.90 3.90 1.95 1.5 8.30 1.85 3.55 4.10 4.10 2.05 1.6 Note 1: MSL1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard. Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. DIE MARKINGS 2016 YYYY Die orientation dot Part Number ZZZZ Gate Pad solder bar is under this corner EPC2016 DIE OUTLINE Laser Markings Part # Marking Line 1 Lot_Date Code Marking line 2 Lot_Date Code Marking Line 3 2016 YYYY ZZZZ A Solder Bar View f f X4 d X2 DIM 3 4 5 A B c d e f g 6 c B 2 1 e g MIN micrometers Nominal MAX 2076 1602 1379 577 235 195 400 2106 1632 1382 580 250 200 400 2136 1662 1385 583 265 205 400 g X3 SEATING PLANE 815 Max 100 +/- 20 (685) Side View EPC - EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2013 | | PAGE 5 eGaN(R) FET DATASHEET EPC2016 RECOMMENDED LAND PATTERN The land pattern is solder mask defined. Pad no. 1 is Gate; (units in m) Pads no. 3, 5 are Drain; Pads no. 4, 6 are Source; Pad no. 2 is Substrate. X3 1362 560 X2 2106 180 X4 180 Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. eGaN(R) is a registered trademark of Efficient Power Conversion Corporation. U.S. Patents 8,350,294; 8,404,508; 8,431,960; 8,436,398 EPC - EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2013 | Information subject to change without notice. Revised September, 2013 | PAGE 6