eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2013 | | PAGE 1
EPC2016
Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment leverag-
ing the infrastructure that has been developed over the last 55 years. GaN’s exceptionally high elec-
tron mobility and low temperature coecient allows very low R
DS(ON)
, while its lateral device structure
and majority carrier diode provide exceptionally low Q
G
and zero Q
RR
. The end result is a device that
can handle tasks where very high switching frequency, and low on-time are benecial as well as
those where on-state losses dominate.
EPC2016 eGaN® FETs are supplied only in
passivated die form with solder bars
Applications
• HighSpeedDC-DCconversion
• ClassDAudio
• HardSwitchedandHighFrequencyCircuits
Benets
• UltraHighEciency
• UltraLowRDS(on)
• UltralowQG
• Ultrasmallfootprint
EFFICIENT POWER CONVERSION
HAL
EPC2016 – Enhancement Mode Power Transistor
VDSS , 100 V
RDS(ON) , 16 mW
ID , 11 A
NEW PRODUCT
Maximum Ratings
V
DS
Drain-to-Source Voltage (up to 10,000 5ms pulses at 125° C) 120 V
Drain-to-Source Voltage (Continuous) 100 V
I
D
Continuous (T
A
= 25˚C, θ
JA
= 32) 11 A
Pulsed (25˚C, Tpulse = 300 µs) 50
V
GS
Gate-to-Source Voltage 6 V
Gate-to-Source Voltage -5
T
J
Operating Temperature -40 to 125 ˚C
T
STG
Storage Temperature -40 to 150
Thermal Characteristics
R
θ
JC
Thermal Resistance, Junction to Case 3.6 ˚C/W
R
θ
JB
Thermal Resistance, Junction to Board 19 ˚C/W
R
θ
JA
Thermal Resistance, Junction to Ambient (Note 1) 69 ˚C/W
TYP
Note 1: R
θ
JA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Static Characteristics (T
J
= 25˚C unless otherwise stated)
BV
DSS
Drain-to-Source Voltage V
GS
= 0 V, I
D
= 200 µA 100 V
I
DSS
Drain Source Leakage V
DS
= 80 V, V
GS
= 0 V 25 150 µA
I
GSS
Gate-Source Forward Leakage V
GS
= 5 V 0.5 3 mA
Gate-Source Reverse Leakage V
GS
= -5 V 0.1 0.5
V
GS(th)
Gate Threshold Voltage V
DS
= V
GS
, I
D
= 3 mA 0.7 1.4 2.5 V
R
DS(ON)
Drain-Source On Resistance V
GS
= 5 V, I
D
= 11 A 12 16 mΩ
Source-Drain Characteristics (T
J
= 25˚C unless otherwise stated)
V
SD
Source-Drain Forward Voltage I
S
= 0.5 A, V
GS
= 0 V, T = 25˚C
1.73 V
I
S
= 0.5 A, V
GS
= 0 V, T = 125˚C
1.68
All measurements were done with substrate shorted to source.
eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2013 | | PAGE 2
EPC2016
40
50
30
20
10
0
VGS – Gate-to-Source Voltage (V)
0.5 1 1.5 2 2.5 3 3.5 4 4.5
ID – Drain Current (A)
Figure 2: Transfer Characteristics
– Drain Current (A
50
40
30
20
10
0
RDS(ON) – Drain to Source Resistance (m)
RDS(ON) – Drain to Source Resistance (m)
VGS – Gate to Source Voltage (V)
35
40
30
25
20
15
10
5
02.5 2 3 3.5 4 4.5 5
VGS – Gate-to-Source Voltage (V)
10
15
20
25
30
35
40
45
50
5
02.5 2 3 3.5 4 4.5 5
ID = 11 A
25˚C
125˚C
Figure 1: Typical Output Characteristics
Figure 3: RDS(on) vs VGS for Various Drain Currents Figure 4: RDS(on) vs VGS for Various Temperatures
ID = 8 A
ID = 12 A
ID = 20 A
ID = 40 A
0 1 1.50.5 2
VDS – Drain to Source Voltage (V)
VGS
GS
GS
GS
= 5
V = 4
V = 3
V = 2
25˚C
125˚C
VDS = 3V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Dynamic Characteristics (T
J
= 25˚C unless otherwise stated)
C
ISS
Input Capacitance
V
DS
= 50 V, V
GS
= 0 V
433
pFC
OSS
Output Capacitance 225
C
RSS
Reverse Transfer Capacitance 4.3
Q
G
Total Gate Charge (V
GS
= 5 V)
V
DS
= 50 V, I
D
= 11 A
3.8
nC
Q
GD
Gate to Drain Charge 0.70
Q
GS
Gate to Source Charge 0.99
5.2
1.4
1.5
Q
OSS
Output Charge 20 30
Q
RR
Source-Drain Recovery Charge 0
520
280
6
0
All measurements were done with substrate shorted to source.
eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2013 | | PAGE 3
EPC2016
10
20
30
40
50
Normalized On-State Resistance – RDS(ON)
TJ – Junction Temperature ( ˚C )
1.6
1.8
1.2
1.4
1
0.8
-20 0 20 40 60 80 100 120 140
ID = 11A
VGS = 5 V
Normalized Threshold Voltage
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
-20 0 20 40 60 80 100 120 140
ID = 3 mA
Figure 8: Normalized On Resistance vs. Temperature
Figure 9: Normalized Threshold Voltage vs. Temperature
TJ – Junction Temperature ( ˚C )
VG – Gate Voltage (V)
QG – Gate Charge (nC)
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
00
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0 0.5 1.51 2 3 4 2.5 3.5
ID = 11A
VD = 50 V
Figure 6: Gate Charge
IG – Gate Current (A)
VGS – Gate-to-Source Voltage (V)
0.015
0.01
0.005
00 1 2 3 4 5 6
25˚C
125˚C
Figure 10: Gate Current
Figure 5: Capacitance
VDS – Drain to Source Voltage (V)
0 20 40 60 80 100
C– Capacitance (nF)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
0
ISD – Source to Drain Current (A)
Figure 7: Reverse Drain-Source Characteristics
0 0.5 1 1.5 2 2.5 3 3.5 4
VSD – Source to Drain Voltage (V)
25˚C
125˚C
All measurements were done with substrate shortened to source.
eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2013 | | PAGE 4
EPC2016
Figure 11: Transient Thermal Response Curves
Figure 12: Safe Operating Area
Duty Factors:
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
PDM
t1
t2
0.5
0.2
0.1
0.05
0.02
0.01
Single Pulse
1
0.1
0.01
0.001
0.0001
10-5 10-4 10-3 10-2 10-1 1 10 100
ZθJB, Normalized Thermal Impedance
tp, Rectangular Pulse Duration, seconds
Normalized Maximum Transient Thermal Impedance
Normalized Maximum Transient Thermal Impedance
tp, Rectangular Pulse Duration, seconds
Duty Factors:
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
PDM
t1
t2
0.5
0.2
0.1
0.05
0.02
0.01
Single Pulse
1
0.1
0.01
0.001
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+01
ZθJC, Normalized Thermal Impedance
0.1
1
10
100
0.1 1 10 100 1000
ID- Drain Current (A)
VDS - Drain-Source Voltage (V)
limited by RDS(ON)
TJ = Max Rated, TC = +25°C, Single Pulse
10 µs
100 µs
1 ms
10 ms
100 ms/DC
eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2013 | | PAGE 5
EPC2016
815 Max
100 +/- 20
SEATING PLANE
(685)
B
A
d
X2
c
e g
3 4 5 6
g
X3
f f
2
1
X4
DIE OUTLINE
Solder Bar View
Side View
DIM MIN Nominal MAX
A2076 2106 2136
B1602 1632 1662
c1379 1382 1385
d577 580 583
e235 250 265
f195 200 205
g400 400 400
MICROMETERS
2016
YYYY
ZZZZ
Die orientation dot
Gate Pad solder bar
is under this corner
Part
Number
Laser Markings
Part #
Marking Line 1
Lot_Date Code
Marking line 2
Lot_Date Code
Marking Line 3
EPC2016 2016 YYYY ZZZZ
DIE MARKINGS
TAPE AND REEL CONFIGURATION
a
d e f g
c
b
Note 1: MSL1 (moisture sensitivity level 1) classied according to IPC/JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,
not the pocket hole.
Die
orientation
dot
Gate
solder bar is
under this
corner
Die is placed into pocket
solder bar side down
(face side down)
7” reel
Loaded Tape Feed Direction
EPC2016 (note 1)
Dimension (mm) target min max
a 8.00 7.90 8.30
b 1.75 1.65 1.85
c (see note) 3.50 3.45 3.55
d 4.00 3.90 4.10
e 4.00 3.90 4.10
f (see note) 2.00 1.95 2.05
g 1.5 1.5 1.6
4mm pitch, 8mm wide tape on 7” reel
eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2013 | | PAGE 6
EPC2016
Information subject to
change without notice.
Revised September, 2013
Ecient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Ecient Power Conversion Corporation.
U.S. Patents 8,350,294; 8,404,508; 8,431,960; 8,436,398
1362
560
180 180
X3
2106
X4
X2
RECOMMENDED
LAND PATTERN
(units in µm)
Pad no. 1 is Gate;
Padsno.3,5areDrain;
Padsno.4,6areSource;
Pad no. 2 is Substrate.
The land pattern is solder mask dened.