W24LH8 32K x 8 CMOS STATIC RAM GENERAL DESCRIPTION The W24LH8 is a normal speed, very low power CMOS static RAM organized as 32768 x 8 bits that operates on a wide voltage range from 2.7V to 5.5V power supply. The W24LH8 family, W24LH8-55LE and W24LH8-55LI, can meet requirement of various operating temperature. This device is manufactured using Winbond's high performance CMOS technology. FEATURES * * * * * Low power consumption Access time: 55 nS (5V 10%), 100 nS (3V 10%) 2.7V to 5.5V supply voltage Fully static operation All inputs and outputs directly TTL compatible * Three-state outputs * Battery back-up operation capability * Data retention voltage: 2V (min.) * Available packages: 330 mil SOP and standard type one TSOP (8 mm x 13.4 mm) BLOCK DIAGRAM PIN CONFIGURATIONS CLK GEN. PRECHARGE CKT. R O W CORE CELL ARRAY A12 A14 A14 1 28 A12 2 27 #WE A7 3 26 A13 VDD A2 A3 A4 A6 4 25 A8 A5 A5 5 24 A9 A6 A4 6 23 A11 A7 A3 7 22 #OE A13 A2 8 21 A10 I/O1 A1 9 20 #CS I/O8 A0 10 19 I/O8 I/O1 11 18 I/O7 I/O2 12 17 I/O6 I/O3 13 16 I/O5 VSS 14 15 I/O4 28-pin SOP D E C O D E R DATA CNTRL. 512 ROWS 64 X 8 COLUMNS I/O CKT. COLUMN DECODER CLK GEN. A11 A10 A1 A0 A8 A9 #WE #CS #OE PIN DESCRIPTION #OE A11 A9 A8 A13 #WE VDD A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28-pin TSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 #CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 SYMBOL A0-A14 I/O1-I/O8 #CS #WE #OE VDD VSS -1- DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Input Write Enable Input Output Enable Input Power Supply Ground Publication Release Date: March 2001 Revision A3 W24LH8 TRUTH TABLE #CS #OE #WE MODE VDD CURRENT H X X Not Selected High Z ISB, ISB1 L H H Output Disable High Z IDD L L H Read Data Out IDD L X L Write Data In IDD I/O1-I/O8 DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER RATING UNIT -0.5 to +7.0 V Input/Output to VSS Potential -0.5 to VDD +0.5 V Allowable Power Dissipation 1.0 W -65 to +150 C LE -20 to 85 C LI -40 to 85 C Supply Voltage to VSS Potential Storage Temperature Operating Temperature Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. Operating Characteristics (VSS = 0V; TA (C) = -20 to 85 for LE; -40 to 85 for LI) PARAMETER SYM. TEST CONDITIONS MIN. MAX. UNIT Input Low Voltage VIL - -0.5 +0.6 V Input High Voltage VIH - +2.0 VDD +0.5 V Input Leakage Current ILI VIN = VSS to VDD -1 +1 A Output Leakage Current ILO VI/O = VSS to VDD, #CS = VIH (min.) or #OE = VIH (min.) or #WE = VIL (max.) -1 +1 A Output Low Voltage VOL IOL = +2.1 mA - 0.4 V Output High Voltage VOH IOH = -1.0 mA 2.2 - V -2- W24LH8 Operating Characteristics, continued PARAMETER SYM. Operating Power Supply IDD Current Standby Power Supply Current TEST CONDITIONS MIN. TYP. MAX. UNIT mA #CS = VIL (max.), I/O = 0 mA, 5V - - 70 Cycle = min. Duty = 100% 3V - - 40 ISB #CS = VIH (min.), Cycle = min. Duty = 100% - - 1 mA ISB1 #CS VDD -0.2V - 0.5 5 A Note: Typical parameter is measured under ambient temperature TA = 25 C and VDD = 5V/ 3V. CAPACITANCE (TA = 25 C, f = 1 MHz) PARAMETER SYM. CONDITIONS MAX. UNIT Input Capacitance CIN VIN = 0V 6 pF Input/Output Capacitance CI/O VOUT = 0V 8 pF Note: These parameters are sampled but not 100% tested. AC CHARACTERISTICS AC Test Conditions PARAMETER CONDITIONS Input Pulse Levels 0V to 2.4V Input Rise and Fall Times 5 nS Input and Output Timing Reference Level 1.5V Output Load See the drawing below AC Test Loads and Waveform 1 TTL 1 TTL OUTPUT OUTPUT 100 pF Including Jig and Scope 5 pF Including Jig and Scope (For TCLZ, TOLZ, TCHZ TOHZ, TWHZ, TOW ) , 2.4V 90% 0V 10% 90% 10% 5 nS 5 nS -3- Publication Release Date: March 2001 Revision A3 W24LH8 AC Characteristics, continued (VSS = 0V; TA (C) = -20 to 85 for LE; -40 to 85 for LI) Read Cycle PARAMETER SYMBOL 3V 10% 5V 10% MIN. MAX. MIN. MAX. UNIT Read Cycle Time TRC 100 - 55 - nS Address Access Time TAA - 100 - 55 nS Chip Select Access Time TACS - 100 - 55 nS Output Enable to Output Valid TAOE - 50 - 30 nS Chip Selection to Output in Low Z TCLZ* 15 - 10 - nS Output Enable to Output in Low Z TOLZ* 5 - 5 - nS Chip Deselection to Output in High Z TCHZ* - 35 - 20 nS Output Disable to Output in High Z TOHZ* - 35 - 20 nS Output Hold from Address Change TOH 15 - 10 - nS These parameters are sampled but not 100% tested Write Cycle PARAMETER SYMBOL 3V 10% 5V 10% MIN. MAX. MIN. MAX. UNIT Write Cycle Time TWC 100 - 55 - nS Chip Selection to End of Write TCW 80 - 40 - nS Address Valid to End of Write TAW 80 - 40 - nS Address Setup Time TAS 0 - 0 - nS Write Pulse Width TWP 70 - 30 - nS TWR 0 - 0 - nS Data Valid to End of Write TDW 40 - 25 - nS Data Hold from End of Write TDH 0 - 0 - nS Write to Output in High Z TWHZ* - 35 - 20 nS Output Disable to Output in High Z TOHZ* - 35 - 20 nS TOW 5 - 5 - nS Write Recovery Time #CS, #WE Output Active from End of Write These parameters are sampled but not 100% tested -4- W24LH8 TIMING WAVEFORMS Read Cycle 1 (Address Controlled) TRC Address TAA TOH TOH DOUT Read Cycle 2 (Chip Select Controlled) #CS TACS TCHZ TCLZ DOUT Read Cycle 3 (Output Enable Controlled) T RC Address T AA #OE TOH T AOE T OLZ #CS T ACS D OUT T CHZ T OHZ TCLZ -5- Publication Release Date: March 2001 Revision A3 W24LH8 Timing Waveforms, continued Write Cycle 1 TWC Address T WR #OE T CW #CS T AW #WE T WP TAS TOHZ (1, 4) D OUT T DW TDH D IN Write Cycle 2 (#OE = VIL Fixed) T WC Address TWR TCW #CS TAW #WE TWP TAS TOH TWHZ (1, 4) D OUT TDW (2) (3) TOW TDH DIN Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from DOUT are the same as the data written to DIN during the write cycle. 3. DOUT provides the read data for the next address. 4. Transition is measured 500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested. -6- W24LH8 DATA RETENTION CHARACTERISTICS (TA (C) = -20 to 85 for LE; -40 to 85 for LI) PARAMETER TEST CONDITIONS SYM. MIN. TYP. MAX. UNIT 2.0 - - V VDD for Data Retention VDR #CS VDD -0.2V Data Retention Current IDDDR #CS VDD -0.2V, VDD = 3V - - 5 A Chip Deselect to Data Retention Time TCDR See data retention waveform 0 - - nS Operation Recovery Time TR TRC* - - nS * Read Cycle Time DATA RETENTION WAVEFORM VDD 0.9 V DD VDR > = 2V TCDR #CS VIH 0.9 V DD TR #CS > = V DD - 0.2V -7- VIH Publication Release Date: March 2001 Revision A3 W24LH8 ORDERING INFORMATION PART NO. W24LH8S-55LE W24LH8Q-55LE W24LH8S-55LI W24LH8Q-55LI ACCESS TIME (nS) OPERATING VOLTAGE (V) OPERATING TEMPERATURE (C) 55 4.5V to 5.5V -20 to 85 100 2.7V to 3.3V -20 to 85 55 4.5V to 5.5V -20 to 85 100 2.7V to 3.3V -20 to 85 55 4.5V to 5.5V -40 to 85 100 2.7V to 3.3V -40 to 85 55 4.5V to 5.5V -40 to 85 100 2.7V to 3.3V -40 to 85 PACKAGE 330 mil SOP Standard type one TSOP 330 mil SOP Standard type one TSOP Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. -8- W24LH8 PACKAGE DIMENSIONS 28-pin SOP Wide Body Dimension in mm Dimension in Inches Symbol 28 A A1 A2 b c D E e HE L LE S y 15 e1 E HE L Detail F 14 1 b e1 c y 0.004 2.85 0.10 0.093 0.098 0.103 2.36 2.49 0.014 0.016 0.020 0.36 0.41 0.51 0.008 0.010 0.014 0.20 0.25 0.36 18.11 18.62 2.62 0.713 0.733 0.326 0.331 0.336 8.28 8.41 8.53 0.044 0.050 0.056 1.12 1.27 1.42 0.453 0.465 0.477 11.51 11.81 12.12 0.028 0.036 0.044 0.71 0.91 1.12 0.059 0.067 0.075 1.50 1.70 1.91 0.047 1.19 0.004 0.10 0 10 0 10 1. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion/intrusion. 3. Dimensions D & E include mold mismatch . and determined at the mold parting line. 4. Controlling dimension: Inches. 5. General appearance spec should be based on final visual inspection spec. A2 A e Min. Nom. Max. 0.112 Notes: D S Min. Nom. Max. LE A1 See Detail F Seating Plane 28-pin Standard Type One TSOP HD Dimension In Inches Dimension In mm Min. Min. Symbol D c A A1 A2 b c D E HD e L L1 Y 1 e E b A2 A A1 L Nom. Max. Nom. 0.006 0.002 Max. 1.20 0.047 0.05 0.15 0.035 0.040 0.041 0.95 1.00 0.007 0.008 0.011 0.17 0.20 0.27 0.004 0.006 0.008 0.10 0.15 0.21 11.90 1.05 0.461 0.465 0.469 11.70 11.80 0.311 0.315 0.319 7.90 8.00 8.10 0.520 0.528 0.536 13.20 13.40 13.60 0.020 0.024 0.028 0.50 0.60 0.022 0.55 0.010 0.000 0 3 0.70 0.25 0.004 0.00 5 0 0.10 3 5 Controlling dimension: Millimeters Y L1 -9- Publication Release Date: March 2001 Revision A3 W24LH8 VERSION HISTORY VERSION DATE PAGE A1 Nov. 1998 - Initial Issued A2 Jan. 1999 1 Change low power consumption active: from 108 to 156 mW (max.) 3 Change operating power supply current (IDD) from 30 to 40 mA (max.) 1 Change operating power supply voltage from (2.7V to 3.6V) to (2.7V to 5.5V), access time from 70 nS to (55 nS (5V 10%), 100 nS (3V 10%)), and remove 28-pin 600 mil DIP package. 3 Change operating power supply current (IDD) from 40 mA to (70 mA/5V, 40 mA/3V)(max.) 4 Add 55 nS (5V 10%) spec. and change 3V 10% spec. from 70 nS to 100 nS. A3 Mar. 2001 DESCRIPTION 2, 4, 7, 8 Delete SL grade 8 Headquarters Correct Ordering Information Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 4, Creation Rd. III, No. 378 Kwun Tong Rd; Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852 -27513100 TEL: 886-3-5770066 FAX: 852 -27552064 FAX: 886 -3-5792766 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886 -2-27197006 Taipei Office 11F, No. 115, Sec. 3, Min -Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886 -2-27197502 Note: All data and specifications are subject to change withou t notice. - 10 - Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798