8-Bit, 210 MSPS TxDAC(R) D/A Converter AD9748 FEATURES APPLICATIONS High performance member of pin-compatible TxDAC product family Linearity 0.1 LSB DNL 0.1 LSB INL Twos complement or straight binary data format Differential current outputs: 2 mA to 20 mA Power dissipation: 135 mW @ 3.3 V Power-down mode: 15 mW @ 3.3 V On-chip 1.20 V reference CMOS-compatible digital interface 32-lead LFCSP Edge-triggered latches Fast settling: 11 ns to 0.1% full-scale Communications Direct digital synthesis (DSS) Instrumentation FUNCTIONAL BLOCK DIAGRAM 3.3V RSET 3.3V AVDD 150pF 1.2V REF REFIO FS ADJ CURRENT SOURCE ARRAY AD9748 DVDD DCOM SEGMENTED SWITCHES CLK+ CLK- ACOM LSB SWITCHES IOUTA IOUTB LATCHES 3.3V MODE CMODE CLKVDD CLKCOM SLEEP DIGITAL DATA INPUTS (DB7-DB0) 03211-001 0.1F Figure 1. GENERAL DESCRIPTION The AD9748 1 is an 8-bit resolution, wideband, third generation member of the TxDAC series of high performance, low power CMOS digital-to-analog converters (DACs). The TxDAC family, consisting of pin-compatible 8-, 10-, 12-, and 14-bit DACs, is specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface options, small outline package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. The AD9748 offers exceptional ac and dc performance while supporting update rates up to 210 MSPS. The AD9748's low power dissipation makes it well suited for portable and low power applications. Its power dissipation can be further reduced to 60 mW with a slight degradation in performance by lowering the full-scale current output. In addition, a power-down mode reduces the standby power dissipation to approximately 15 mW. A segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. Edge-triggered input latches and a 1.2 V temperaturecompensated band gap reference have been integrated to provide a complete monolithic DAC solution. The digital inputs support 3 V CMOS logic families. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 6. 1 32-lead LFCSP. The AD9748 is the 8-bit member of the pin-compatible TxDAC family, which offers excellent INL and DNL performance. Differential or single-ended clock input (LVPECL or CMOS), supports 210 MSPS conversion rate. Data input supports twos complement or straight binary data coding. Low power: Complete CMOS DAC function operates on 135 mW from a 2.7 V to 3.6 V single supply. The DAC fullscale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods. On-chip voltage reference: The AD9748 includes a 1.2 V temperature-compensated band gap voltage reference. Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved. AD9748 TABLE OF CONTENTS Features .............................................................................................. 1 Applying the AD9748 ................................................................ 15 Applications....................................................................................... 1 Differential Coupling Using a Transformer............................... 15 Functional Block Diagram .............................................................. 1 Differential Coupling Using an Op Amp................................ 16 General Description ......................................................................... 1 Single-Ended, Unbuffered Voltage Output............................. 16 Product Highlights ........................................................................... 1 Single-Ended, Buffered Voltage Output Configuration........ 16 Revision History ............................................................................... 2 Power and Grounding Considerations, Power Supply Rejection...................................................................................... 17 Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 Dynamic Specifications ............................................................... 4 Digital Specifications ................................................................... 5 Absolute Maximum Ratings............................................................ 6 Thermal Characteristics .............................................................. 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Terminology ...................................................................................... 8 Typical Performance Characteristics ............................................. 9 Functional Description .................................................................. 11 Reference Operation .................................................................. 11 Reference Control Amplifier .................................................... 11 DAC Transfer Function ............................................................. 12 Analog Outputs........................................................................... 12 Digital Inputs .............................................................................. 13 Clock Input.................................................................................. 13 DAC Timing................................................................................ 14 Evaluation Board ............................................................................ 18 General Description................................................................... 18 Outline Dimensions ....................................................................... 24 Ordering Guide .......................................................................... 24 REVISION HISTORY 12/05--Rev. 0 to Rev. A Updated Format..................................................................Universal Changes to General Description and Product Highlights ...........1 Changes to Table 1.............................................................................3 Changes to Table 2.............................................................................4 Changes to Table 4.............................................................................6 Inserted Figure 7; Renumbered Sequentially.................................9 Changes to Figure 8 and Figure 9....................................................9 Changes to Functional Description, Reference Operation, and Reference Control Amplifier Sections......................................... 11 Inserted Figure 16; Renumbered Sequentially ........................... 11 Changes to DAC Transfer Function Section............................... 12 Changes to Digital Inputs Section................................................ 13 Changes to Figure 22, Figure 23, and Figure 24 ......................... 14 Changes to Figure 25...................................................................... 15 Changes to Figure 26, Figure 27, Figure 28, and Figure 29....... 16 Updated Outline Dimensions....................................................... 24 Changes to Ordering Guide .......................................................... 24 2/03--Revision 0: Initial Version Power Dissipation....................................................................... 14 Rev. A | Page 2 of 24 AD9748 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted. Table 1. Parameter RESOLUTION DC ACCURACY 1 Integral Linearity Error (INL) Differential Nonlinearity (DNL) ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) Full-Scale Output Current 2 Output Compliance Range Output Resistance Output Capacitance REFERENCE OUTPUT Reference Voltage Reference Output Current 3 REFERENCE INPUT Input Compliance Range Reference Input Resistance (External Reference) Small Signal Bandwidth TEMPERATURE COEFFICIENTS Offset Drift Gain Drift (Without Internal Reference) Gain Drift (With Internal Reference) Reference Voltage Drift POWER SUPPLY Supply Voltages AVDD DVDD CLKVDD Analog Supply Current (IAVDD) Digital Supply Current (IDVDD) 4 Clock Supply Current (ICLKVDD) Supply Current Sleep Mode (IAVDD) Power Dissipation4 Power Dissipation 5 Power Supply Rejection Ratio--AVDD 6 Power Supply Rejection Ratio--DVDD6 OPERATING RANGE Min 8 Typ Max Unit Bits 0.25 0.25 0.1 0.1 +0.25 +0.25 LSB LSB +0.02 +0.5 +0.5 20.0 +1.25 % of FSR % of FSR % of FSR mA V k pF 1.26 V nA 1.25 7 0.5 V k MHz 0 50 100 50 ppm of FSR/C ppm of FSR/C ppm of FSR/C ppm/C -0.02 -0.5 -0.5 2.0 -1.0 0.1 0.1 100 5 1.14 1.20 100 0.1 2.7 2.7 2.7 -1 -0.04 -40 1 3.3 3.3 3.3 33 8 5 5 135 145 3.6 3.6 3.6 36 9 7 6 145 +1 +0.04 +85 Measured at IOUTA, driving a virtual ground. Nominal full-scale current, IOUTFS, is 32 times the IREF current. 3 An external buffer amplifier with input bias current <100 nA should be used to drive any external load. 4 Measured at fCLOCK = 100 MSPS and fOUT = 1 MHz. 5 Measured as unbuffered voltage output with IOUTFS = 20 mA, 50 RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS, and fOUT = 40 MHz. 6 5% power supply variation. 2 Rev. A | Page 3 of 24 V V V mA mA mA mA mW mW % of FSR/V % of FSR/V C AD9748 DYNAMIC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, differential transformer coupled output, 50 doubly terminated, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (fCLOCK) Output Settling Time (tST) (to 0.1%) 1 Output Propagation Delay (tPD) Glitch Impulse Output Rise Time (10% to 90%)1 Output Fall Time (10% to 90%)1 Output Noise (IOUTFS = 20 mA) 2 Output Noise (IOUTFS = 2 mA)2 AC LINEARITY Signal-to-Noise and Distortion Ratio fCLOCK = 50 MSPS; fOUT = 5 MHz fCLOCK = 50 MSPS; fOUT = 19 MHz fCLOCK = 100 MSPS; fOUT = 5 MHz fCLOCK = 100 MSPS; fOUT = 39 MHz fCLOCK = 165 MSPS; fOUT = 5 MHz fCLOCK = 165 MSPS; fOUT = 49 MHz fCLOCK = 210 MSPS; fOUT = 9 MHz fCLOCK = 210 MSPS; fOUT = 68 MHz Total Harmonic Distortion fCLOCK = 25 MSPS; fOUT = 1 MHz fCLOCK = 50 MSPS; fOUT = 12.5 MHz fCLOCK = 100 MSPS; fOUT = 25 MHz fCLOCK = 165 MSPS; fOUT = 41.3 MHz fCLOCK = 210 MSPS; fOUT = 68 MHz Spurious-Free Dynamic Range to Nyquist fCLOCK = 25 MSPS; fOUT = 1 MHz 0 dBFS Output fCLOCK = 65 MSPS; fOUT = 5 MHz fCLOCK = 65 MSPS; fOUT = 19 MHz fCLOCK = 100 MSPS; fOUT = 5 MHz fCLOCK = 100 MSPS; fOUT = 39 MHz fCLOCK = 165 MSPS; fOUT = 5 MHz fCLOCK = 165 MSPS; fOUT = 49 MHz fCLOCK = 210 MSPS; fOUT = 5 MHz fCLOCK = 210 MSPS; fOUT = 68 MHz 1 2 Min Typ Max 210 11 1 5 2.5 2.5 50 30 MSPS ns ns pV-s ns ns pA/Hz pA/Hz 50 48 50 46 50 47 50 46 dB dB dB dB dB dB dB dB -72 -65 -60 -58 -65 61 -61 72 69 65 68 62 68 54 67 60 Measured single-ended into 50 load. Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only. Rev. A | Page 4 of 24 Unit dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc AD9748 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted. Table 3. Parameter DIGITAL INPUTS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Input Capacitance Input Setup Time (tS) Input Hold Time (tH) Latch Pulse Width (tLPW) CLK INPUTS 1 Input Voltage Range Common-Mode Voltage Differential Voltage Typ 2.1 3 0 Max 0.9 +10 +10 -10 -10 5 2.0 1.5 1.5 0 0.75 0.5 3 2.25 1.5 1.5 Applicable to CLK+ and CLK- inputs when configured for differential or PECL clock input mode. DB0-DB7 tS tH CLOCK tLPW tPD IOUTA OR IOUTB tST 0.1% Figure 2. Timing Diagram Rev. A | Page 5 of 24 0.1% 03211-002 1 Min Unit V V A A pF ns ns ns V V V AD9748 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter AVDD DVDD CLKVDD ACOM ACOM DCOM AVDD AVDD DVDD CLK+, CLK-, SLEEP Digital Inputs, MODE IOUTA, IOUTB REFIO, FS ADJ CLK+, CLK-, MODE Junction Temperature Storage Temperature Range Lead Temperature (10 sec) THERMAL CHARACTERISTICS 1 With Respect to ACOM DCOM CLKCOM DCOM CLKCOM CLKCOM DVDD CLKVDD CLKVDD DCOM DCOM ACOM ACOM CLKCOM Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -3.9 -3.9 -3.9 -0.3 -0.3 -1.0 -0.3 -0.3 -65 Max +3.9 +3.9 +3.9 +0.3 +0.3 +0.3 +3.9 +3.9 +3.9 DVDD + 0.3 DVDD + 0.3 AVDD + 0.3 AVDD + 0.3 CLKVDD + 0.3 150 +150 Unit V V V V V V V V V V V V V V C C 300 C Thermal Resistance 32-Lead LFCSP JA = 32.5C/W 1 Thermal impedance measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD51-7. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 6 of 24 AD9748 32 31 30 29 28 27 26 25 DB2 DB3 DB4 DB5 DB6 DB7 (MSB) DCOM SLEEP PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 PIN 1 INDICATOR AD9748 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 FS ADJ REFIO ACOM IOUTA IOUTB ACOM AVDD AVDD NC = NO CONNECT 03211-003 NC DCOM CLKVDD CLK+ CLK- CLKCOM CMODE MODE 9 10 11 12 13 14 15 16 DB1 (LSB) DB0 DVDD NC NC NC NC NC Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. 27 28 to 32, 1 2 3 4 to 9 10, 26 11 12 13 14 15 Mnemonic DB7 (MSB) DB6 to DB1 DB0 (LSB) DVDD NC DCOM CLKVDD CLK+ CLK- CLKCOM CMODE 16 17, 18 19, 22 20 21 23 24 25 MODE AVDD ACOM IOUTB IOUTA REFIO FS ADJ SLEEP Description Most Significant Data Bit (MSB). Data Bits 6 to 1. Least Significant Data Bit (LSB). Digital Supply Voltage (3.3 V). No Internal Connection. Digital Common. Clock Supply Voltage (3.3 V). Differential Clock Input. Differential Clock Input. Clock Common. Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+ and float CLK-). Connect to CLKVDD for differential receiver. Float for PECL receiver (terminations on-chip). Selects Input Data Format. Connect to DCOM for straight binary, DVDD for twos complement. Analog Supply Voltage (3.3 V). Analog Common. Complementary DAC Current Output. Full-scale current when all data bits are 0s. DAC Current Output. Full-scale current when all data bits are 1s. Reference Input/Output. Requires 0.1 F capacitor to ACOM. Full-Scale Current Output Adjust. Power-Down Control Input. Active high. Contains active pull-down circuit; it can be left unterminated if not used. Rev. A | Page 7 of 24 AD9748 TERMINOLOGY Linearity Error (Also Called Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Power Supply Rejection The maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. Differential Nonlinearity (or DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Settling Time The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. Monotonicity A DAC is monotonic if the output increases or remains constant as the digital input increases. Glitch Impulse Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-s. Offset Error The deviation of the output current from the ideal of zero is called the offset error. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1s. Spurious-Free Dynamic Range The difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. Gain Error The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. Total Harmonic Distortion (THD) T THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. It is expressed as a percentage or in decibels (dB). Output Compliance Range The range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. Multitone Power Ratio The spurious-free dynamic range containing multiple carrier tones of equal amplitude. It is measured as the difference between the rms amplitude of a carrier tone to the peak spurious signal in the region of a removed tone. Temperature Drift Temperature drift is specified as the maximum change from the ambient (25C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per C. For reference drift, the drift is reported in ppm per C. 3.3V *AWG2021 CLOCK RETIMED SO THAT THE DIGITAL DATA TRANSITIONS ON FALLING EDGE OF 50% DUTY CYCLE CLOCK. RSET 3.3V 1.2V REF AVDD 150pF REFIO FS ADJ CURRENT SOURCE ARRAY AD9748 DVDD DCOM SEGMENTED SWITCHES ACOM LSB SWITCHES MINI-CIRCUITS T1-1T IOUTA IOUTB CLK+ 50 3.3V DVDD DCOM RETIMED CLOCK OUTPUT* LECROY 9210 PULSE GENERATOR MODE LATCHES CLK- 50 CLKVDD CLKCOM SLEEP CLOCK OUTPUT 100 ROHDE & SCHWARZ FSEA30 SPECTRUM ANALYZER CMODE 50 20pF 20pF DIGITAL DATA INPUTS (DB7-DB0) DIGITAL DATA TEKTRONIX AWG-2021 WITH OPTION 4 Figure 4. Basic AC Characterization Test Setup (SOIC/TSSOP Packages) Rev. A | Page 8 of 24 03211-004 0.1F AD9748 TYPICAL PERFORMANCE CHARACTERISTICS 80 55 5mA THD@50MSPS 75 THD@100MSPS 50 70 SINAD (dB) 2.5mA SINAD/THD (dB) THD@165MSPS 10mA 20mA 40 45 65 THD@210MSPS 60 55 SINAD@165MSPS 50 35 1 10 100 fOUT (MHz) 03211-005 30 40 SINAD@100MSPS SINAD@210MSPS 1 10 100 fOUT (MHz) Figure 8. SINAD/THD vs. fOUT (Single-Ended Output) Figure 5. SINAD vs. IOUTFS @ 100 MSPS (Single-Ended Output) 80 55 10mA 20mA THD@165MSPS 75 50 THD@210MSPS SINAD/THD (dB) 70 5mA SINAD (dB) 03211-039 SINAD@50MSPS 45 40 2.5mA 45 THD@50MSPS 65 60 THD@100MSPS 55 SINAD@165MSPS 50 SINAD@50MSPS SINAD@100MSPS 35 45 10 100 fOUT (MHz) 03211-006 1 40 1 Figure 6. SINAD vs. IOUTFS @ 165 MSPS (Single-Ended Output) 100 Figure 9. SINAD/THD vs. fOUT (Differential Output) 55 0 5mA 20mA fCLOCK = 25MSPS fOUT = 7.81MHz -10 10mA 50 SFDR = 65.0dBc AMPLITUDE = 0dBFS -20 40 -30 MAGNITUDE (dBm) 2.5mA 45 -40 -50 -60 -70 35 -80 1 10 fOUT (MHz) Figure 7. SINAD vs. IOUTFS @ 210 MSPS (Single-Ended Output) 100 -100 0 2 4 6 8 FREQUENCY (MHz) 10 12 Figure 10. Single-Tone Spectral Plot @ 25 MSPS (Single-Ended Output) Rev. A | Page 9 of 24 03211-009 -90 30 03211-038 SINAD (dB) 10 fOUT (MHz) 03211-040 SINAD@210MSPS 30 AD9748 0 fCLOCK = 125MSPS fOUT = 27MHz -10 SFDR = 56.2dBc AMPLITUDE = 0dBFS -30 -40 50mV/DIV MAGNITUDE (dBm) -20 -50 -60 -70 -80 10 20 30 40 FREQUENCY (MHz) 50 60 5ns/DIV Figure 11. Single-Tone Spectral Plot @ 125 MSPS (Single-Ended Output) Figure 13. Step Response (Single-Ended Output) 0 0 fCLOCK = 165MSPS fOUT = 49MHz -10 SFDR = 50dBc AMPLITUDE = 0dBFS -20 MAGNITUDE (dBm) -30 -40 -50 -60 -70 -30 -40 -50 -60 -70 03211-043 -80 -80 -90 -90 10 20 30 40 50 FREQUENCY (MHz) 60 70 80 0 10.5 FREQUENCY (MHz) 3.3V 0.1F RSET 3.3V 1.2V REF AVDD 150pF REFIO FS ADJ CURRENT SOURCE ARRAY ACOM AD9748 DVDD DCOM CLK+ CLK- SEGMENTED SWITCHES LSB SWITCHES LATCHES 3.3V VDIFF = VOUTA = VOUTB IOUTA IOUTB MODE CMODE RLOAD 50 RLOAD 50 CLKVDD CLKCOM SLEEP 105 Figure 14. Single-Tone Spectral Plot @ 210 MSPS (Single-Ended Output) Figure 12. Single-Tone Spectral Plot @ 165 MSPS (Single-Ended Output) DIGITAL DATA INPUTS (DB7-DB0) Figure 15. Simplified Block Diagram Rev. A | Page 10 of 24 03211-013 0 -100 03211-011 MAGNITUDE (dBm) fCLOCK = 210MSPS fOUT = 68MHz -10 SFDR = 50.1dBc AMPLITUDE = 0dBFS -20 -100 03211-012 0 03211-010 -90 -100 AD9748 FUNCTIONAL DESCRIPTION The analog and digital sections of the AD9748 have separate power supply inputs (that is, AVDD and DVDD) that can operate independently over a 2.7 V to 3.6 V range. The digital section, which is capable of operating at a rate of up to 210 MSPS, consists of edge-triggered latches and segment decoding logic circuitry. The analog section includes the PMOS current sources, the associated differential switches, a 1.2 V band gap voltage reference, and a reference control amplifier. AVDD 84A REFIO 7k REFLO Figure 16. Equivalent Circuit of Internal Reference 3.3V OPTIONAL EXTERNAL REF BUFFER REFLO REFIO 0.1F 2k CURRENT SOURCE ARRAY FS ADJ AD9748 03211-045 ADDITIONAL LOAD Figure 17. Internal Reference Configuration An external reference can be applied to REFIO, as shown in Figure 18. The external reference can provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. Note that the 0.1 F compensation capacitor is not required because the internal reference is overridden, and the relatively high input impedance of REFIO minimizes any loading of the external reference. 3.3V The DAC full-scale output current is regulated by the reference control amplifier and can be set from 2 mA to 20 mA via an external resistor, RSET, connected to the full-scale adjust (FS ADJ) pin. The external resistor, in combination with both the reference control amplifier and voltage reference, VREFIO, sets the reference current, IREF, which is replicated to the segmented current sources with the proper scaling factor. The full-scale current, IOUTFS, is 32 times IREF. REFLO 150pF AVDD 1.2V REF REFIO FS ADJ AD9748 CURRENT SOURCE ARRAY REFERENCE CONTROL AMPLIFIER REFERENCE OPERATION The AD9748 contains an internal 1.2 V band gap reference. The internal reference cannot be disabled but can be easily overridden by an external reference with no effect on performance. Figure 16 shows an equivalent circuit of the band gap reference. REFIO serves as either an output or an input depending on whether the internal or an external reference is used. To use the internal reference, simply decouple the REFIO pin to ACOM with a 0.1 F capacitor and connect REFLO to ACOM via a resistance less than 5 . The internal reference voltage are present at REFIO. If the voltage at REFIO is to be used anywhere else in the circuit, than an external buffer amplifier with an input bias AVDD 150pF 1.2V REF 03211-046 All of these current sources are switched to one or the other of the two output nodes (that is, IOUTA or IOUTB) via PMOS differential current switches. The switches are based on the architecture that was pioneered in the AD9764 family, with further refinements to reduce distortion contributed by the switching transient. This switch architecture also reduces various timing errors and provides matching complementary drive signals to the inputs of the differential current switches. current of less than 100 nA should be used. An example of the use of the internal reference is shown in Figure 17. 03211-044 Figure 15 shows a simplified block diagram of the AD9748. The AD9748 consists of a DAC, digital control logic, and full-scale output current control. The DAC contains a PMOS current source array capable of providing up to 20 mA of full-scale current (IOUTFS). The array is divided into 31 equal currents that make up the five most significant bits (MSBs). The next three bits consist of seven equal current sources whose value is of an MSB current source. Implementing the lower bits with current sources, instead of an R-2R ladder, enhances its dynamic performance for multitone or low amplitude signals and helps maintain the DAC's high output impedance (that is, >100 k). Figure 18. External Reference Configuration REFERENCE CONTROL AMPLIFIER The AD9748 contains a control amplifier that is used to regulate the full-scale output current, IOUTFS. The control amplifier is configured as a V-I converter, as shown in Figure 17, so that its current output, IREF, is determined by the ratio of the VREFIO and an external resistor, RSET, as stated in Equation 4. IREF is copied to the segmented current sources with the proper scale factor to set IOUTFS, as stated in Equation 3. Rev. A | Page 11 of 24 AD9748 The control amplifier allows a wide (10:1) adjustment span of IOUTFS over a 2 mA to 20 mA range by setting IREF between 62.5 A and 625 A. The wide adjustment span of IOUTFS provides several benefits. The first relates directly to the power dissipation of the AD9748, which is proportional to IOUTFS (see the Power Dissipation section). The second relates to a 20 dB adjustment, which is useful for system gain control purposes. The small signal bandwidth of the reference control amplifier is approximately 500 kHz and can be used for low frequency small signal multiplying applications. DAC TRANSFER FUNCTION The AD9748 provides complementary current outputs, IOUTA and IOUTB. IOUTA provides a near full-scale current output, IOUTFS, when all bits are high (that is, DAC CODE = 255), while IOUTB, the complementary output, provides no current. The current output appearing at IOUTA and IOUTB is a function of both the input code and IOUTFS and can be expressed as: Substituting the values of IOUTA, IOUTB, IREF, and VDIFF can be expressed as: VDIFF = {(2 x DAC CODE - 255)/256} (32 x RLOAD/RSET) x VREFIO (8) Equation 7 and Equation 8 highlight some of the advantages of operating the AD9748 differentially. First, the differential operation helps cancel common-mode error sources associated with IOUTA and IOUTB, such as noise, distortion, and dc offsets. Second, the differential code dependent current and subsequent voltage, VDIFF, is twice the value of the single-ended voltage output (that is, VOUTA or VOUTB), thus providing twice the signal power to the load. Note that the gain drift temperature performance for a singleended (VOUTA and VOUTB) or differential output (VDIFF) of the AD9748 can be enhanced by selecting temperature tracking resistors for RLOAD and RSET due to their ratiometric relationship, as shown in Equation 8. B IOUTA = (DAC CODE/256) x IOUTFS (1) ANALOG OUTPUTS IOUTB = (255 - DAC CODE)/256 x IOUTFS (2) The complementary current outputs in each DAC, IOUTA, and IOUTB can be configured for single-ended or differential operation. IOUTA and IOUTB can be converted into complementary single-ended voltage outputs, VOUTA and VOUTB, via a load resistor, RLOAD, as described in the DAC Transfer Function section by Equation 5 through Equation 8. The differential voltage, VDIFF, existing between VOUTA and VOUTB, can also be converted to a single-ended voltage via a transformer or differential amplifier configuration. The ac performance of the AD9748 is optimum and specified using a differential transformer-coupled output in which the voltage swing at IOUTA and IOUTB is limited to 0.5 V. where DAC CODE = 0 to 255 (that is, decimal representation). As mentioned previously, IOUTFS is a function of the reference current IREF, which is nominally set by a reference voltage, VREFIO, and external resistor, RSET. It can be expressed as: IOUTFS = 32 x IREF (3) where IREF = VREFIO/RSET (4) The two current outputs typically drive a resistive load directly or via a transformer. If dc coupling is required, then IOUTA and IOUTB should be directly connected to matching resistive loads, RLOAD, that are tied to analog common, ACOM. Note that RLOAD can represent the equivalent load resistance seen by IOUTA or IOUTB as would be the case in a doubly terminated 50 or 75 cable. The single-ended voltage output appearing at the IOUTA and IOUTB nodes is simply VOUTA = IOUTA x RLOAD (5) VOUTB = IOUTB x RLOAD (6) Note that the full-scale value of VOUTA and VOUTB should not exceed the specified output compliance range to maintain specified distortion and linearity performance. VDIFF = (IOUTA - IOUTB) x RLOAD (7) The distortion and noise performance of the AD9748 can be enhanced when it is configured for differential operation. The common-mode error sources of both IOUTA and IOUTB can be significantly reduced by the common-mode rejection of a transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise. The enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases and/or its amplitude decreases. This is due to the first-order cancellation of various dynamic commonmode distortion mechanisms, digital feedthrough, and noise. Performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the reconstructed signal power to the load (assuming no source termination). Because the output currents of IOUTA and IOUTB are complementary, they become additive when processed differentially. A properly selected transformer allows the AD9748 to provide the required power and voltage levels to different loads. Rev. A | Page 12 of 24 AD9748 The output impedance of IOUTA and IOUTB is determined by the equivalent parallel combination of the PMOS switches associated with the current sources and is typically 100 k in parallel with 5 pF. It is also slightly dependent on the output voltage (that is, VOUTA and VOUTB) due to the nature of a PMOS device. As a result, maintaining IOUTA and/or IOUTB at a virtual ground via an I-V op amp configuration results in the optimum dc linearity. Note that the INL/DNL specifications for the AD9748 are measured with IOUTA maintained at a virtual ground via an op amp. IOUTA and IOUTB also have a negative and positive voltage compliance range that must be adhered to in order to achieve optimum performance. The negative output compliance range of -1 V is set by the breakdown limits of the CMOS process. Operation beyond this maximum limit can result in a breakdown of the output stage and affect the reliability of the AD9748. The positive output compliance range is slightly dependent on the full-scale output current, IOUTFS. It degrades slightly from its nominal 1.2 V for an IOUTFS = 20 mA to 1 V for an IOUTFS = 2 mA. The optimum distortion performance for a single-ended or differential output is achieved when the maximum full-scale signal at IOUTA and IOUTB does not exceed 0.5 V. DIGITAL INPUTS The AD9748 digital section consists of eight input bit channels and a clock input. The 8-bit parallel data inputs follow standard positive binary coding, where DB7 is the most significant bit (MSB) and DB0 is the least significant bit (LSB). IOUTA produces a full-scale output current when all data bits are at Logic 1. IOUTB produces a complementary output with the full-scale current split between the two outputs as a function of the input code. DVDD CLOCK INPUT A configurable clock input allows for one single-ended and two differential modes. The mode selection is controlled by the CMODE input, as summarized in Table 6. Connecting CMODE to CLKCOM selects the single-ended clock input. In this mode, the CLK+ input is driven with rail-to-rail swings and the CLK- input is left floating. If CMODE is connected to CLKVDD, then the differential receiver mode is selected. In this mode, both inputs are high impedance. The final mode is selected by floating CMODE. This mode is also differential, but internal terminations for positive emitter-coupled logic (PECL) are activated. There is no significant performance difference between any of the three clock input modes. Table 6. Clock Mode Selection CMODE Pin CLKCOM CLKVDD Float Clock Input Mode Single-ended Differential PECL In the single-ended input mode, the CLK+ pin must be driven with rail-to-rail CMOS levels. The quality of the DAC output is directly related to the clock quality, and jitter is a key concern. Any noise or jitter in the clock translates directly into the DAC output. Optimal performance is achieved if the clock input has a sharp rising edge, because the DAC latches are positive edge triggered. In the differential input mode, the clock input functions as a high impedance differential pair. The common-mode level of the CLK+ and CLK- inputs can vary from 0.75 V to 2.25 V, and the differential voltage can be as low as 0.5 V p-p. This mode can be used to drive the clock with a differential sine wave, because the high gain bandwidth of the differential inputs convert the sine wave into a single-ended square wave internally. The final clock mode allows for a reduced external component count when the DAC clock is distributed on the board using PECL logic. The internal termination configuration is shown in Figure 20. These termination resistors are untrimmed and can vary up to 20%. However, matching between the resistors should generally be better than 1%. Figure 19. Equivalent Digital Input The digital interface is implemented using an edge-triggered master/slave latch. The DAC output updates on the rising edge of the clock and is designed to support a clock rate as high as 210 MSPS. The clock can be operated at any duty cycle that meets the specified latch pulse width. The setup and hold times can also be varied within the clock cycle as long as the specified minimum times are met, although the location of these transition edges can affect digital feedthrough and distortion performance. Best performance is typically achieved when the input data transitions on the falling edge of a 50% duty cycle clock. Rev. A | Page 13 of 24 AD9748 CLK+ CLOCK RECEIVER CLK- 50 TO DAC CORE 50 VTT = 1.3V NOM Figure 20. Clock Termination in PECL Mode 03211-017 03211-016 DIGITAL INPUT AD9748 Input Clock and Data Timing Relationship Dynamic performance in a DAC is dependent on the relationship between the position of the clock edges and the time at which the input data changes. The AD9748 is rising edge triggered, and so exhibits dynamic performance sensitivity when the data transition is close to this edge. In general, the goal when applying the AD9748 is to make the data transition close to the falling clock edge. This becomes more important as the sample rate increases. Figure 21 shows the relationship of SFDR to clock placement with different sample rates. Note that at the lower sample rates, more tolerance is allowed in clock placement, while at higher rates, more care must be taken. Conversely, IDVDD is dependent on both the digital input waveform, fCLOCK, and digital supply DVDD. Figure 23 shows IDVDD as a function of full-scale sine wave output ratios (fOUT/fCLOCK) for various update rates with DVDD = 3.3 V. 35 30 25 IAVDD (mA) DAC TIMING 20 15 80 10 75 0 70 2 4 6 SFDR (dB) 65 10 12 IOUTFS (mA) 14 16 18 20 Figure 22. IAVDD vs. IOUTFS 60 55 20 50MHz SFDR 50 18 210MSPS 45 16 40 14 2 4 6 8 CLOCK PLACEMENT (ns) 10 12 03211-018 0 IDVDD (mA) 35 30 8 03211-019 20MHz SFDR Figure 21. SFDR vs. Clock Placement @ fOUT = 20 MHz and 50 MHz (fCLOCK = 165 MSPS) 165MSPS 12 10 125MSPS 8 6 65MSPS 4 Sleep Mode Operation The power dissipation, PD, of the AD9748 is dependent on several factors that include the: 0.1 RATIO (fOUT/fCLOCK) 1 Figure 23. IDVDD vs. Ratio @ DVDD = 3.3 V 11 10 9 DIFF 8 ICLKVDD (mA) POWER DISSIPATION 7 6 PECL 5 SE 4 3 Power supply voltages (AVDD, CLKVDD, and DVDD) Full-scale current output (IOUTFS) Update rate (fCLOCK) Reconstructed digital input waveform 2 1 0 The power dissipation is directly proportional to the analog supply current, IAVDD, and the digital supply current, IDVDD. IAVDD is directly proportional to IOUTFS, as shown in Figure 22, and is insensitive to fCLOCK. Rev. A | Page 14 of 24 0 50 100 150 200 fCLOCK (MSPS) Figure 24. ICLKVDD vs. fCLOCK and Clock Mode 250 03211-042 * * * * 0 0.01 03211-041 2 The AD9748 has a power-down function that turns off the output current and reduces the supply current to less than 6 mA over the specified supply range of 2.7 V to 3.6 V and the temperature range. This mode can be activated by applying a Logic Level 1 to the SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 AVDD. This digital input also contains an active pull-down circuit that ensures that the AD9748 remains enabled if this input is left disconnected. The AD9748 takes less than 50 ns to power down and approximately 5 s to power back up. AD9748 APPLYING THE AD9748 DIFFERENTIAL COUPLING USING A TRANSFORMER Output Configurations An RF transformer can be used to perform a differential-tosingle-ended signal conversion, as shown in Figure 25. A differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformer's pass band. An RF transformer, such as the Mini-Circuits(R) T1-1T, provides excellent rejection of common-mode distortion (that is, even-order harmonics) and noise over a wide frequency range. It also provides electrical isolation and the ability to deliver twice the power to the load. Transformers with different impedance ratios can also be used for impedance matching purposes. Note that the transformer provides ac coupling only. A single-ended output is suitable for applications requiring a unipolar voltage output. A positive unipolar output voltage results if IOUTA and/or IOUTB is connected to an appropriately sized load resistor, RLOAD, referred to ACOM. This configuration can be more suitable for a single-supply system requiring a dccoupled, ground referred output voltage. Alternatively, an amplifier could be configured as an I-V converter, thus converting IOUTA or IOUTB into a negative unipolar voltage. This configuration provides the best dc linearity because IOUTA or IOUTB is maintained at a virtual ground. IOUTA MINI-CIRCUITS T1-1T AD9748 RLOAD IOUTB OPTIONAL RDIFF 03211-022 The following sections illustrate some typical output configurations for the AD9748. Unless otherwise noted, it is assumed that IOUTFS is set to a nominal 20 mA. For applications requiring the optimum dynamic performance, a differential output configuration is suggested. A differential output configuration can consist of either an RF transformer or a differential op amp configuration. The transformer configuration provides the optimum high frequency performance and is recommended for any application that allows ac coupling. The differential op amp configuration is suitable for applications requiring dc coupling, bipolar output, signal gain, and/or level shifting within the bandwidth of the chosen op amp. Figure 25. Differential Output Using a Transformer The center tap on the primary side of the transformer must be connected to ACOM to provide the necessary dc current path for both IOUTA and IOUTB. The complementary voltages appearing at IOUTA and IOUTB (that is, VOUTA and VOUTB) swing symmetrically around ACOM and should be maintained with the specified output compliance range of the AD9748. A differential resistor, RDIFF, can be inserted in applications where the output of the transformer is connected to the load, RLOAD, via a passive reconstruction filter or cable. RDIFF is determined by the transformer's impedance ratio and provides the proper source termination that results in a low VSWR. Note that approximately half the signal power is dissipated across RDIFF. B Rev. A | Page 15 of 24 AD9748 DIFFERENTIAL COUPLING USING AN OP AMP SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT An op amp can also be used to perform a differential-to-singleended conversion, as shown in Figure 26. The AD9748 is configured with two equal load resistors, RLOAD, of 25 . The differential voltage developed across IOUTA and IOUTB is converted to a single-ended signal via the differential op amp configuration. An optional capacitor can be installed across IOUTA and IOUTB, forming a real pole in a low-pass filter. The addition of this capacitor also enhances the op amp's distortion performance by preventing the DAC's high slewing output from overloading the op amp's input. Figure 28 shows the AD9748 configured to provide a unipolar output range of approximately 0 V to 0.5 V for a doubly terminated 50 cable because the nominal full-scale current, IOUTFS, of 20 mA flows through the equivalent RLOAD of 25 . In this case, RLOAD represents the equivalent load resistance seen by IOUTA or IOUTB. The unused output (IOUTA or IOUTB) can be connected to ACOM directly or via a matching RLOAD. Different values of IOUTFS and RLOAD can be selected as long as the positive compliance range is adhered to. One additional consideration in this mode is the integral nonlinearity (INL), discussed in the Analog Outputs section. For optimum INL performance, the single-ended, buffered voltage output configuration is suggested. 500 AD9748 225 IOUTA AD8047 225 AD9748 COPT IOUTFS = 20mA 500 50 25 03211-023 25 VOUTA = 0V TO 0.5V IOUTA 50 IOUTB 03211-025 IOUTB 25 Figure 26. DC Differential Coupling Using an Op Amp Figure 28. 0 V to 0.5 V Unbuffered Voltage Output The common-mode rejection of this configuration is typically determined by the resistor matching. In this circuit, the differential op amp circuit using the AD8047 is configured to provide some additional signal gain. The op amp must operate off a dual supply because its output is approximately 1 V. A high speed amplifier capable of preserving the differential performance of the AD9748 while meeting other system level objectives (that is, cost or power) should be selected. The op amp's differential gain, gain setting resistor values, and full-scale output swing capabilities should all be considered when optimizing this circuit. The differential circuit shown in Figure 27 provides the necessary level shifting required in a single-supply system. In this case, AVDD, which is the positive analog supply for both the AD9748 and the op amp, is also used to level shift the differential output of the AD9748 to midsupply (that is, AVDD/2). The AD8041 is a suitable op amp for this application. 500 Figure 29 shows a buffered single-ended output configuration in which the op amp U1 performs an I-V conversion on the AD9748 output current. U1 maintains IOUTA (or IOUTB) at a virtual ground, minimizing the nonlinear output impedance effect on the DAC's INL performance as described in the Analog Outputs section. Although this single-ended configuration typically provides the best dc linearity performance, its ac distortion performance at higher DAC update rates can be limited by U1's slew rate capabilities. U1 provides a negative unipolar output voltage, and its full-scale output voltage is simply the product of RFB and IOUTFS. The fullscale output should be set within U1's voltage output swing capabilities by scaling IOUTFS and/or RFB. An improvement in ac distortion performance can result with a reduced IOUTFS because U1 is required to sink less signal current. 225 COPT AD8041 225 IOUTB COPT 25 1k 25 1k RFB 200 AD9748 AVDD 03211-024 IOUTA IOUTFS = 10mA IOUTA U1 VOUT = IOUTFS x RFB IOUTB Figure 27. Single-Supply DC Differential Coupled Circuit 200 Figure 29. Unipolar Buffered Voltage Output Rev. A | Page 16 of 24 03211-026 AD9748 SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT CONFIGURATION AD9748 POWER AND GROUNDING CONSIDERATIONS, POWER SUPPLY REJECTION Many applications seek high speed and high performance under less than ideal operating conditions. In these application circuits, the implementation and construction of the printed circuit board is as important as the circuit design. Proper RF techniques must be used for device selection, placement, and routing as well as power supply bypassing and grounding to ensure optimum performance. Figure 35 to Figure 38 illustrate the recommended printed circuit board ground, power, and signal plane layouts implemented on the AD9748 evaluation board. One factor that can measurably affect system performance is the ability of the DAC output to reject dc variations or ac noise superimposed on the analog or digital dc power distribution. This is referred to as the power supply rejection ratio (PSRR). For dc variations of the power supply, the resulting performance of the DAC directly corresponds to a gain error associated with the DAC's full-scale current, IOUTFS. AC noise on the dc supplies is common in applications where the power distribution is generated by a switching power supply. Typically, switching power supply noise occurs over the spectrum from tens of kilohertz to several megahertz. The PSRR vs. frequency of the AD9748 AVDD supply over this frequency range is shown in Figure 30. 85 Note that the ratio in Figure 30 is calculated as amps out/volts in. Noise on the analog power supply has the effect of modulating the internal switches, and therefore the output current. The voltage noise on AVDD, therefore, is added in a nonlinear manner to the desired IOUT. Due to the relative different size of these switches, the PSRR is very code dependent. This can produce a mixing effect that can modulate low frequency power supply noise to higher frequencies. Worst-case PSRR for either one of the differential DAC outputs occurs when the full-scale current is directed toward that output. As a result, the PSRR measurement in Figure 30 represents a worst-case condition in which the digital inputs remain static and the full-scale output current of 20 mA is directed to the DAC output being measured. The following illustrates the effect of supply noise on the analog supply. Suppose a switching regulator with a switching frequency of 250 kHz produces 10 mV of noise and, for simplicity's sake (ignoring harmonics), all of this noise is concentrated at 250 kHz. To calculate how much of this undesired noise appears as current noise superimposed on the DAC's full-scale current, IOUTFS, users must determine the PSRR in dB using Figure 30 at 250 kHz. To calculate the PSRR for a given RLOAD, such that the units of PSRR are converted from A/V to V/V, adjust the curve in Figure 30 by the scaling factor 20 log (RLOAD). For instance, if RLOAD is 50 , then the PSRR is reduced by 34 dB (that is, PSRR of the DAC at 250 kHz, which is 85 dB in Figure 30, becomes 51 dB VOUT/VIN). 80 Proper grounding and decoupling should be a primary objective in any high speed, high resolution system. The AD9748 features separate analog and digital supplies and ground pins to optimize the management of analog and digital ground currents in a system. In general, AVDD, the analog supply, should be decoupled to ACOM, the analog common, as close to the chip as physically possible. Similarly, DVDD, the digital supply, should be decoupled to DCOM as close to the chip as physically possible. 75 65 60 55 50 45 0 2 4 6 8 FREQUENCY (MHz) 10 Figure 30. Power Supply Rejection Ratio (PSRR) 12 For those applications that require a single 3.3 V supply for both the analog and digital supplies, a clean analog supply can be generated using the circuit shown in Figure 31. The circuit consists of a differential LC filter with separate power supply and return lines. Lower noise can be attained by using low ESR type electrolytic and tantalum capacitors. FERRITE BEADS TTL/CMOS LOGIC CIRCUITS AVDD 100F ELECT. 10F-22F TANT. 0.1F CER. ACOM 3.3V POWER SUPPLY Figure 31. Differential LC Filter for Single 3.3 V Applications Rev. A | Page 17 of 24 03211-028 40 03211-027 PSRR (dB) 70 AD9748 EVALUATION BOARD GENERAL DESCRIPTION The AD9748 evaluation boards allow for easy setup and testing of the product in the LFCSP package. Careful attention to layout and circuit design, combined with a prototyping area, allows the user to evaluate the AD9748 easily and effectively in any application where high resolution, high speed conversion is required. This board allows the user the flexibility to operate the AD9748 in various configurations. Possible output configurations include transformer coupled, resistor terminated, and single and differential outputs. The digital inputs are designed to be driven from various word generators, with the on-board option to add a resistor network for proper load termination. Provisions are also made to exercise the power-down feature of the AD9748 and select the clock and data modes. Rev. A | Page 18 of 24 AD9748 RED TP12 TB1 C3 0.1F TB1 CVDD 1 BLK C2 10F 6.3V TP2 2 C10 0.1F 2 4 1 3 6 5 8 7 DB10X 10 9 DB9X 11 DB8X 13 DB7X 15 DB6X 17 DB5X 19 DB4X 21 DB3X 23 DB2X 25 DB1X 27 DB0X 12 L2 BEAD TB3 16 DVDD 1 C7 0.1F TB3 14 RED TP13 18 20 BLK C6 0.1F C4 10F 6.3V TP4 2 22 24 26 28 RED TP5 L3 BEAD C9 0.1F TB4 32 AVDD 1 BLK 36 C8 0.1F C5 10F 6.3V TP6 34 38 40 2 DB13X DB12X DB11X 29 31 33 35 JP3 CKEXTX 37 39 J1 R3 100 R4 100 R15 100 R16 100 R17 100 R18 100 R19 100 DB13X DB12X DB11X DB10X DB9X DB8X DB7X DB6X DB5X DB4X DB3X DB2X DB1X DB0X CKEXTX R21 100 R24 100 R25 100 R26 100 R27 100 R20 100 1 RP3 22 16 2 RP3 22 15 3 RP3 22 14 4 RP3 22 13 5 RP3 22 12 6 RP3 7 RP3 22 11 22 10 8 RP3 22 9 1 RP4 22 16 2 RP4 22 15 3 RP4 22 14 4 RP4 22 13 5 RP4 22 12 6 RP4 7 RP4 22 11 22 10 8 RP4 22 9 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CKEXT R28 100 03211-029 TB4 30 HEADER STRAIGHT UP MALE NO SHROUD L1 BEAD Figure 32. Evaluation Board Schematic--Power Supply and Digital Inputs Rev. A | Page 19 of 24 AD9748 AVDD DVDD CVDD C19 0.1F C17 0.1F C32 0.1F SLEEP TP11 WHT R29 10k DB7 DB6 DVDD DB5 DB4 DB3 DB2 DB1 DB0 CVDD CLK CLKB CMODE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DB7 DB6 DVDD DB5 DB4 DB3 DB2 DB1 DB0 DCOM U1 CVDD CLK CLKB CCOM CMODE MODE DB8 DB9 DB10 DB11 DB12 DB13 DCOM1 SLEEP FS ADJ REFIO ACOM IA IB ACOM1 AVDD AVDD1 32 31 30 29 28 27 26 25 DB8 DB9 DB10 DB11 DB12 DB13 R11 50 DNP C13 24 23 22 TP3 TP1 WHT WHT JP8 IOUT 3 21 20 19 18 17 TP7 R30 10 S3 AGND: 3, 4, 5 5 2 6 1 AVDD T1 - 1T C11 0.1F JP9 AD9748LFCSP WHT 4 T1 DNP C12 R10 50 CVDD R1 2k 0.1% JP1 03211-030 MODE Figure 33. Evaluation Board Schematic--Output Signal Conditioning CVDD 1 7 U4 C20 10F 16V 2 AGND: 5 CVDD: 8 C35 0.1F CVDD R5 120 3 JP2 CKEXT CLK 4 U4 6 AGND: 5 CVDD: 8 R2 120 C34 0.1F S5 AGND: 3, 4, 5 R6 50 03211-031 CLKB Figure 34. Evaluation Board Schematic--Clock Input Rev. A | Page 20 of 24 03211-032 AD9748 03211-033 Figure 35. Evaluation Board Layout--Primary Side Figure 36. Evaluation Board Layout--Secondary Side Rev. A | Page 21 of 24 03211-034 AD9748 03211-035 Figure 37. Evaluation Board Layout--Ground Plane Figure 38. Evaluation Board Layout--Power Plane Rev. A | Page 22 of 24 03211-036 AD9748 03211-037 Figure 39. Evaluation Board Layout Assembly--Primary Side Figure 40. Evaluation Board Layout Assembly--Secondary Side Rev. A | Page 23 of 24 AD9748 OUTLINE DIMENSIONS 0.60 MAX 5.00 BSC SQ 0.60 MAX PIN 1 INDICATOR TOP VIEW 0.50 BSC 4.75 BSC SQ 0.50 0.40 0.30 32 1 3.25 3.10 SQ 2.95 EXPOSED PAD (BOTTOM VIEW) 17 16 9 8 0.25 MIN 3.50 REF 0.80 MAX 0.65 TYP 12 MAX 1.00 0.85 0.80 PIN 1 INDICATOR 25 24 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 41. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm x 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters ORDERING GUIDE Model AD9748ACP AD9748ACPRL7 AD9748ACPZ 1 AD9748ACPZRL71 AD9748ACP-PCB 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 32-Lead LFCSP_VQ 32-Lead LFCSP_VQ 32-Lead LFCSP_VQ 32-Lead LFCSP_VQ Evaluation Board Z = Pb-free part. (c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03211-0-12/05(A) Rev. A | Page 24 of 24 Package Option CP-32-2 CP-32-2 CP-32-2 CP-32-2