8-Bit, 210 MSPS TxDAC® D/A Converter
AD9748
Rev. A
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Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
High performance member of pin-compatible
TxDAC product family
Linearity
0.1 LSB DNL
0.1 LSB INL
Twos complement or straight binary data format
Differential current outputs: 2 mA to 20 mA
Power dissipation: 135 mW @ 3.3 V
Power-down mode: 15 mW @ 3.3 V
On-chip 1.20 V reference
CMOS-compatible digital interface
32-lead LFCSP
Edge-triggered latches
Fast settling: 11 ns to 0.1% full-scale
APPLICATIONS
Communications
Direct digital synthesis (DSS)
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
1.2V REF
3.3V
R
SET
0.1μF
CLK+
SLEEP
REFIO
FS ADJ
DVDD
DCOM
DIGITAL DATA INPUTS (DB7–DB0)
150pF
3.3V
AVDD ACOM
AD9748
CURRENT
SOURCE
ARRAY
IOUTA
IOUTB
MODE
LSB
SWITCHES
SEGMENTED
SWITCHES
3.3V CLKVDD
CLKCOM
CLK– CMODE
LATCHES
03211-001
Figure 1.
GENERAL DESCRIPTION
The AD97481 is an 8-bit resolution, wideband, third generation
member of the TxDAC series of high performance, low power
CMOS digital-to-analog converters (DACs). The TxDAC
family, consisting of pin-compatible 8-, 10-, 12-, and 14-bit
DACs, is specifically optimized for the transmit signal path of
communication systems. All of the devices share the same
interface options, small outline package, and pinout, providing
an upward or downward component selection path based on
performance, resolution, and cost. The AD9748 offers
exceptional ac and dc performance while supporting update
rates up to 210 MSPS.
The AD9748’s low power dissipation makes it well suited for
portable and low power applications. Its power dissipation can
be further reduced to 60 mW with a slight degradation in
performance by lowering the full-scale current output. In
addition, a power-down mode reduces the standby power
dissipation to approximately 15 mW. A segmented current
source architecture is combined with a proprietary switching
technique to reduce spurious components and enhance
dynamic performance.
Edge-triggered input latches and a 1.2 V temperature-
compensated band gap reference have been integrated to
provide a complete monolithic DAC solution. The digital inputs
support 3 V CMOS logic families.
PRODUCT HIGHLIGHTS
1. 32-lead LFCSP.
2. The AD9748 is the 8-bit member of the pin-compatible
TxDAC family, which offers excellent INL and DNL
performance.
3. Differential or single-ended clock input (LVPECL or
CMOS), supports 210 MSPS conversion rate.
4. Data input supports twos complement or straight binary
data coding.
5. Low power: Complete CMOS DAC function operates on
135 mW from a 2.7 V to 3.6 V single supply. The DAC full-
scale current can be reduced for lower power operation,
and a sleep mode is provided for low power idle periods.
6. On-chip voltage reference: The AD9748 includes a 1.2 V
temperature-compensated band gap voltage reference.
1 Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519.
AD9748
Rev. A | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
Dynamic Specifications ............................................................... 4
Digital Specifications ................................................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Characteristics .............................................................. 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Ter mi no lo g y ...................................................................................... 8
Typical Performance Characteristics ............................................. 9
Functional Description .................................................................. 11
Reference Operation .................................................................. 11
Reference Control Amplifier .................................................... 11
DAC Transfer Function ............................................................. 12
Analog Outputs........................................................................... 12
Digital Inputs .............................................................................. 13
Clock Input.................................................................................. 13
DAC Timing ................................................................................ 14
Power Dissipation....................................................................... 14
Applying the AD9748 ................................................................ 15
Differential Coupling Using a Transformer............................... 15
Differential Coupling Using an Op Amp................................ 16
Single-Ended, Unbuffered Voltage Output............................. 16
Single-Ended, Buffered Voltage Output Configuration........ 16
Power and Grounding Considerations, Power Supply
Rejection...................................................................................... 17
Evaluation Board ............................................................................ 18
General Description................................................................... 18
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
12/05—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to General Description and Product Highlights ...........1
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................4
Changes to Table 4.............................................................................6
Inserted Figure 7; Renumbered Sequentially.................................9
Changes to Figure 8 and Figure 9....................................................9
Changes to Functional Description, Reference Operation, and
Reference Control Amplifier Sections......................................... 11
Inserted Figure 16; Renumbered Sequentially ........................... 11
Changes to DAC Transfer Function Section............................... 12
Changes to Digital Inputs Section................................................ 13
Changes to Figure 22, Figure 23, and Figure 24 ......................... 14
Changes to Figure 25...................................................................... 15
Changes to Figure 26, Figure 27, Figure 28, and Figure 29....... 16
Updated Outline Dimensions....................................................... 24
Changes to Ordering Guide.......................................................... 24
2/03—Revision 0: Initial Version
AD9748
Rev. A | Page 3 of 24
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit
RESOLUTION 8 Bits
DC ACCURACY1
Integral Linearity Error (INL) ±0.25 ±0.1 +0.25 LSB
Differential Nonlinearity (DNL) ±0.25 ±0.1 +0.25 LSB
ANALOG OUTPUT
Offset Error −0.02 +0.02 % of FSR
Gain Error (Without Internal Reference) −0.5 ±0.1 +0.5 % of FSR
Gain Error (With Internal Reference) −0.5 ±0.1 +0.5 % of FSR
Full-Scale Output Current2 2.0 20.0 mA
Output Compliance Range −1.0 +1.25 V
Output Resistance 100 kΩ
Output Capacitance 5 pF
REFERENCE OUTPUT
Reference Voltage 1.14 1.20 1.26 V
Reference Output Current3 100 nA
REFERENCE INPUT
Input Compliance Range 0.1 1.25 V
Reference Input Resistance (External Reference) 7 kΩ
Small Signal Bandwidth 0.5 MHz
TEMPERATURE COEFFICIENTS
Offset Drift 0 ppm of FSR/°C
Gain Drift (Without Internal Reference) ±50 ppm of FSR/°C
Gain Drift (With Internal Reference) ±100 ppm of FSR/°C
Reference Voltage Drift ±50 ppm/°C
POWER SUPPLY
Supply Voltages
AVDD 2.7 3.3 3.6 V
DVDD 2.7 3.3 3.6 V
CLKVDD 2.7 3.3 3.6 V
Analog Supply Current (IAVDD) 33 36 mA
Digital Supply Current (IDVDD)4 8 9 mA
Clock Supply Current (ICLKVDD) 5 7 mA
Supply Current Sleep Mode (IAVDD) 5 6 mA
Power Dissipation4 135 145 mW
Power Dissipation5 145 mW
Power Supply Rejection Ratio—AVDD6 −1 +1 % of FSR/V
Power Supply Rejection Ratio—DVDD6−0.04 +0.04 % of FSR/V
OPERATING RANGE −40 +85 °C
1 Measured at IOUTA, driving a virtual ground.
2 Nominal full-scale current, IOUTFS, is 32 times the IREF current.
3 An external buffer amplifier with input bias current <100 nA should be used to drive any external load.
4 Measured at fCLOCK = 100 MSPS and fOUT = 1 MHz.
5 Measured as unbuffered voltage output with IOUTFS = 20 mA, 50 Ω RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS, and fOUT = 40 MHz.
6 ±5% power supply variation.
AD9748
Rev. A | Page 4 of 24
DYNAMIC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly
terminated, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit
DYNAMIC PERFORMANCE
Maximum Output Update Rate (fCLOCK) 210 MSPS
Output Settling Time (tST) (to 0.1%)1 11 ns
Output Propagation Delay (tPD) 1 ns
Glitch Impulse 5 pV-s
Output Rise Time (10% to 90%)1 2.5 ns
Output Fall Time (10% to 90%)1 2.5 ns
Output Noise (IOUTFS = 20 mA)2 50 pA/√Hz
Output Noise (IOUTFS = 2 mA)2 30 pA/√Hz
AC LINEARITY
Signal-to-Noise and Distortion Ratio
fCLOCK = 50 MSPS; fOUT = 5 MHz 50 dB
fCLOCK = 50 MSPS; fOUT = 19 MHz 48 dB
fCLOCK = 100 MSPS; fOUT = 5 MHz 50 dB
fCLOCK = 100 MSPS; fOUT = 39 MHz 46 dB
fCLOCK = 165 MSPS; fOUT = 5 MHz 50 dB
fCLOCK = 165 MSPS; fOUT = 49 MHz 47 dB
fCLOCK = 210 MSPS; fOUT = 9 MHz 50 dB
fCLOCK = 210 MSPS; fOUT = 68 MHz 46 dB
Total Harmonic Distortion
fCLOCK = 25 MSPS; fOUT = 1 MHz −72 −61 dBc
fCLOCK = 50 MSPS; fOUT = 12.5 MHz −65 dBc
fCLOCK = 100 MSPS; fOUT = 25 MHz −60 dBc
fCLOCK = 165 MSPS; fOUT = 41.3 MHz −58 dBc
fCLOCK = 210 MSPS; fOUT = 68 MHz −65 dBc
Spurious-Free Dynamic Range to Nyquist
fCLOCK = 25 MSPS; fOUT = 1 MHz
0 dBFS Output 61 72 dBc
fCLOCK = 65 MSPS; fOUT = 5 MHz 69 dBc
fCLOCK = 65 MSPS; fOUT = 19 MHz 65 dBc
fCLOCK = 100 MSPS; fOUT = 5 MHz 68 dBc
fCLOCK = 100 MSPS; fOUT = 39 MHz 62 dBc
fCLOCK = 165 MSPS; fOUT = 5 MHz 68 dBc
fCLOCK = 165 MSPS; fOUT = 49 MHz 54 dBc
fCLOCK = 210 MSPS; fOUT = 5 MHz 67 dBc
fCLOCK = 210 MSPS; fOUT = 68 MHz 60 dBc
1 Measured single-ended into 50 Ω load.
2 Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only.
AD9748
Rev. A | Page 5 of 24
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.
Table 3.
Parameter Min Typ Max Unit
DIGITAL INPUTS
Logic 1 Voltage 2.1 3 V
Logic 0 Voltage 0 0.9 V
Logic 1 Current −10 +10 μA
Logic 0 Current −10 +10 μA
Input Capacitance 5 pF
Input Setup Time (tS) 2.0 ns
Input Hold Time (tH) 1.5 ns
Latch Pulse Width (tLPW) 1.5 ns
CLK INPUTS1
Input Voltage Range 0 3 V
Common-Mode Voltage 0.75 1.5 2.25 V
Differential Voltage 0.5 1.5 V
1 Applicable to CLK+ and CLK− inputs when configured for differential or PECL clock input mode.
0.1% 0.1%
t
S
t
H
t
PD
DB0–DB7
CLOCK
IOUTA
OR
IOUTB
t
LPW
t
ST
03211-002
Figure 2. Timing Diagram
AD9748
Rev. A | Page 6 of 24
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
With
Respect
to Min Max Unit
AVDD ACOM −0.3 +3.9 V
DVDD DCOM −0.3 +3.9 V
CLKVDD CLKCOM −0.3 +3.9 V
ACOM DCOM −0.3 +0.3 V
ACOM CLKCOM −0.3 +0.3 V
DCOM CLKCOM −0.3 +0.3 V
AVDD DVDD −3.9 +3.9 V
AVDD CLKVDD −3.9 +3.9 V
DVDD CLKVDD −3.9 +3.9 V
CLK+, CLK−, SLEEP DCOM −0.3 DVDD + 0.3 V
Digital Inputs, MODE DCOM −0.3 DVDD + 0.3 V
IOUTA, IOUTB ACOM −1.0 AVDD + 0.3 V
REFIO, FS ADJ ACOM −0.3 AVDD + 0.3 V
CLK+, CLK−, MODE CLKCOM −0.3 CLKVDD + 0.3 V
Junction Temperature 150 °C
Storage Temperature
Range
−65 +150 °C
Lead Temperature
(10 sec)
300 °C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may effect
device reliability.
THERMAL CHARACTERISTICS1
Thermal Resistance
32-Lead LFCSP
θJA = 32.5°C/W
1 Thermal impedance measurements were taken on a 4-layer board in still air,
in accordance with EIA/JESD51-7.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD9748
Rev. A | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
NC = NO CONNECT
1DB1
2(LSB) DB0
3DVDD
4NC
5NC
6NC
7NC
8NC
24 FS ADJ
23 REFIO
22 ACOM
21 IOUTA
20 IOUTB
19 ACOM
18 AVDD
17 AVDD
9
NC
10
DCOM
11
CLKVDD
12
CLK+
13
CLK–
14
CLKCOM
15
CMODE
16
MODE
32 DB2
31 DB3
30 DB4
29 DB5
28 DB6
27 DB7 (MSB)
26 DCOM
25 SLEEP
TOP VIEW
(Not to Scale)
AD9748
03211-003
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
27 DB7 (MSB) Most Significant Data Bit (MSB).
28 to 32, 1 DB6 to DB1 Data Bits 6 to 1.
2 DB0 (LSB) Least Significant Data Bit (LSB).
3 DVDD Digital Supply Voltage (3.3 V).
4 to 9 NC No Internal Connection.
10, 26 DCOM Digital Common.
11 CLKVDD Clock Supply Voltage (3.3 V).
12 CLK+ Differential Clock Input.
13 CLK− Differential Clock Input.
14 CLKCOM Clock Common.
15 CMODE Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+ and float
CLK–). Connect to CLKVDD for differential receiver. Float for PECL receiver (terminations on-chip).
16 MODE Selects Input Data Format. Connect to DCOM for straight binary, DVDD for twos complement.
17, 18 AVDD Analog Supply Voltage (3.3 V).
19, 22 ACOM Analog Common.
20 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s.
21 IOUTA DAC Current Output. Full-scale current when all data bits are 1s.
23 REFIO Reference Input/Output. Requires 0.1 μF capacitor to ACOM.
24 FS ADJ Full-Scale Current Output Adjust.
25 SLEEP Power-Down Control Input. Active high. Contains active pull-down circuit; it can be left unterminated
if not used.
AD9748
Rev. A | Page 8 of 24
TERMINOLOGY
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A DAC is monotonic if the output increases or remains constant
as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called the offset error. For IOUTA, 0 mA output is expected
when the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current output
DAC. Operation beyond the maximum compliance limits can
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Tem p erature D ri ft
Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either TMIN or TMAX. For offset
and gain drift, the drift is reported in ppm of full-scale range (FSR)
per °C. For reference drift, the drift is reported in ppm per °C.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified
bandwidth.
TTotal Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal. It is
expressed as a percentage or in decibels (dB).
Multitone Power Ratio
The spurious-free dynamic range containing multiple carrier
tones of equal amplitude. It is measured as the difference
between the rms amplitude of a carrier tone to the peak
spurious signal in the region of a removed tone.
50Ω
ROHDE & SCHWARZ
FSEA30
SPECTRUM
ANALYZER
MINI-CIRCUITS
T1-1T
*AWG2021 CLOCK
RETIMED SO THAT
THE DIGITAL DATA
TRANSITIONS ON
FALLING EDGE OF
50% DUTY CYCLE
CLOCK.
50Ω
DVDD
DCOM
50Ω
RETIMED
CLOCK
OUTPUT* DIGITAL
DATA
TEKTRONIX AWG-2021
WITH OPTION 4
LECROY 9210
PULSE GENERATOR
CLOCK
OUTPUT
1.2V REF
3.3V
RSET
0.1μF
SLEEP
REFIO
FS ADJ
DVDD
DCOM
DIGITAL DATA INPUTS (DB7–DB0)
150pF
20pF
3.3V
AVDD ACOM
AD9748
CURRENT
SOURCE
ARRAY
IOUTA
IOUTB
MODE
LSB
SWITCHES
SEGMENTED
SWITCHES
3.3V CLKVDD
CLKCOM
CLK–
CLK+
CMODE
LATCHES
100Ω
20pF
03211-004
Figure 4. Basic AC Characterization Test Setup (SOIC/TSSOP Packages)
AD9748
Rev. A | Page 9 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
10mA
5mA
20mA
2.5mA
f
OUT
(MHz)
SINAD (dB)
55
50
45
40
35
30
1 10 100
03211-005
Figure 5. SINAD vs. IOUTFS @ 100 MSPS (Single-Ended Output)
f
OUT
(MHz)
SINAD (dB)
55
50
45
40
35
30
1 10 100
10mA
2.5mA
20mA
5mA
03211-006
Figure 6. SINAD vs. IOUTFS @ 165 MSPS (Single-Ended Output)
5mA
20mA
2.5mA
f
OUT
(MHz)
SINAD (dB)
55
50
45
40
35
30
1 10 100
10mA
03211-038
Figure 7. SINAD vs. IOUTFS @ 210 MSPS (Single-Ended Output)
f
OUT (MHz)
SINAD/THD (dB)
80
75
60
65
70
50
45
55
40
1 10 100
SINAD@210MSPS
03211-039
SINAD@100MSPS
SINAD@50MSPS
SINAD@165MSPS
THD@50MSPS
THD@100MSPS
THD@210MSPS
THD@165MSPS
Figure 8. SINAD/THD vs. fOUT (Single-Ended Output)
f
OUT
(MHz)
SINAD/THD (dB)
80
75
60
65
70
50
45
55
40
1 10 100
SINAD@210MSPS
THD@210MSPS
03211-040
THD@165MSPS
THD@50MSPS
SINAD@165MSPS
SINAD@100MSPS
SINAD@50MSPS
THD@100MSPS
Figure 9. SINAD/THD vs. fOUT (Differential Output)
f
CLOCK
= 25MSPS
f
OUT
= 7.81MHz
SFDR = 65.0dBc
AMPLITUDE = 0dBFS
FREQUENCY (MHz)
MAGNITUDE (dBm)
0
–30
–20
–10
–50
–40
–90
–80
–70
–60
–100
02 4 6 81012
03211-009
Figure 10. Single-Tone Spectral Plot @ 25 MSPS (Single-Ended Output)
AD9748
Rev. A | Page 10 of 24
FREQUENCY (MHz)
MAGNITUDE (dBm)
0
–30
–20
–10
–50
–40
–90
–80
–70
–60
–100
0 102030405060
f
CLOCK
= 125MSPS
f
OUT
= 27MHz
SFDR = 56.2dBc
AMPLITUDE = 0dBFS
03211-010
Figure 11. Single-Tone Spectral Plot @ 125 MSPS (Single-Ended Output)
FREQUENCY (MHz)
MAGNITUDE (dBm)
0
–30
–20
–10
–50
–40
–90
–80
–70
–60
–100
010203040 706050 80
f
CLOCK
= 165MSPS
f
OUT
= 49MHz
SFDR = 50.1dBc
AMPLITUDE = 0dBFS
03211-011
Figure 12. Single-Tone Spectral Plot @ 165 MSPS (Single-Ended Output)
5ns/DIV
50mV/DIV
03211-012
Figure 13. Step Response (Single-Ended Output)
FREQUENCY (MHz)
MAGNITUDE (dBm)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0 10.5 105
03211-043
f
CLOCK
= 210MSPS
f
OUT
= 68MHz
SFDR = 50dBc
AMPLITUDE = 0dBFS
Figure 14. Single-Tone Spectral Plot @ 210 MSPS (Single-Ended Output)
1.2V REF
3.3V
R
SET
R
LOAD
50Ω
V
DIFF
= V
OUTA
= V
OUTB
R
LOAD
50Ω
0.1μF
CLK+
SLEEP
REFIO
FS ADJ
DVDD
DCOM
DIGITAL DATA INPUTS (DB7–DB0)
150pF
3.3V
AVDD ACOM
AD9748
CURRENT
SOURCE
ARRAY
IOUTA
IOUTB
MODE
LSB
SWITCHES
SEGMENTED
SWITCHES
3.3V CLKVDD
CLKCOM
CLK– CMODE
LATCHES
03211-013
Figure 15. Simplified Block Diagram
AD9748
Rev. A | Page 11 of 24
FUNCTIONAL DESCRIPTION
Figure 15 shows a simplified block diagram of the AD9748. The
AD9748 consists of a DAC, digital control logic, and full-scale
output current control. The DAC contains a PMOS current
source array capable of providing up to 20 mA of full-scale
current (IOUTFS). The array is divided into 31 equal currents that
make up the five most significant bits (MSBs). The next three
bits consist of seven equal current sources whose value is ⅛ of
an MSB current source. Implementing the lower bits with
current sources, instead of an R-2R ladder, enhances its
dynamic performance for multitone or low amplitude signals
and helps maintain the DAC’s high output impedance (that is,
>100 kΩ).
All of these current sources are switched to one or the other of
the two output nodes (that is, IOUTA or IOUTB) via PMOS
differential current switches. The switches are based on the
architecture that was pioneered in the AD9764 family, with
further refinements to reduce distortion contributed by the
switching transient. This switch architecture also reduces
various timing errors and provides matching complementary
drive signals to the inputs of the differential current switches.
The analog and digital sections of the AD9748 have separate
power supply inputs (that is, AVDD and DVDD) that can
operate independently over a 2.7 V to 3.6 V range. The digital
section, which is capable of operating at a rate of up to 210 MSPS,
consists of edge-triggered latches and segment decoding logic
circuitry. The analog section includes the PMOS current sources,
the associated differential switches, a 1.2 V band gap voltage
reference, and a reference control amplifier.
The DAC full-scale output current is regulated by the reference
control amplifier and can be set from 2 mA to 20 mA via an
external resistor, RSET, connected to the full-scale adjust (FS ADJ)
pin. The external resistor, in combination with both the reference
control amplifier and voltage reference, VREFIO, sets the reference
current, IREF, which is replicated to the segmented current
sources with the proper scaling factor. The full-scale current,
IOUTFS, is 32 times IREF.
REFERENCE OPERATION
The AD9748 contains an internal 1.2 V band gap reference. The
internal reference cannot be disabled but can be easily overridden
by an external reference with no effect on performance. Figure 16
shows an equivalent circuit of the band gap reference. REFIO
serves as either an output or an input depending on whether the
internal or an external reference is used. To use the internal
reference, simply decouple the REFIO pin to ACOM with a
0.1 μF capacitor and connect REFLO to ACOM via a resistance
less than 5 Ω. The internal reference voltage are present at
REFIO. If the voltage at REFIO is to be used anywhere else in
the circuit, than an external buffer amplifier with an input bias
current of less than 100 nA should be used. An example of the
use of the internal reference is shown in Figure 17.
AVDD
7k
84µA
REFLO
REFIO
03211-044
Figure 16. Equivalent Circuit of Internal Reference
150pF
1.2V REF
AVDD
REFLO
CURRENT
SOURCE
ARRAY
3.3V
REFIO
FS ADJ
AD9748
A
DDITION
A
L
LOAD
OPTIONAL
EXTERNAL
REF BUFFER
03211-045
0.1μF
2kΩ
Figure 17. Internal Reference Configuration
An external reference can be applied to REFIO, as shown in
Figure 18. The external reference can provide either a fixed
reference voltage to enhance accuracy and drift performance or
a varying reference voltage for gain control. Note that the 0.1 μF
compensation capacitor is not required because the internal
reference is overridden, and the relatively high input impedance of
REFIO minimizes any loading of the external reference.
150pF
1.2V REF
AVDD
REFLO
CURRENT
SOURCE
ARRAY
REFIO
FS ADJ
AD9748
REFERENCE
CONTROL
AMPLIFIER
3.3
V
03211-046
Figure 18. External Reference Configuration
REFERENCE CONTROL AMPLIFIER
The AD9748 contains a control amplifier that is used to regulate
the full-scale output current, IOUTFS. The control amplifier is
configured as a V-I converter, as shown in Figure 17, so that its
current output, IREF, is determined by the ratio of the VREFIO and
an external resistor, RSET, as stated in Equation 4. IREF is copied
to the segmented current sources with the proper scale factor to
set IOUTFS, as stated in Equation 3.
AD9748
Rev. A | Page 12 of 24
The control amplifier allows a wide (10:1) adjustment span of
IOUTFS over a 2 mA to 20 mA range by setting IREF between 62.5
μA and 625 μA. The wide adjustment span of IOUTFS provides
several benefits. The first relates directly to the power
dissipation of the AD9748, which is proportional to IOUTFS (see
the Power Dissipation section). The second relates to a 20 dB
adjustment, which is useful for system gain control purposes.
The small signal bandwidth of the reference control amplifier is
approximately 500 kHz and can be used for low frequency small
signal multiplying applications.
DAC TRANSFER FUNCTION
The AD9748 provides complementary current outputs, IOUTA
and IOUTB. IOUTA provides a near full-scale current output,
IOUTFS, when all bits are high (that is, DAC CODE = 255), while
IOUTB, the complementary output, provides no current. The
current output appearing at IOUTA and IOUTB is a function of
both the input code and IOUTFS and can be expressed as:
IOUTA = (DAC CODE/256) × IOUTFS (1)
IOUTB = (255 − DAC CODE)/256 × IOUTFS (2)
where DAC CODE = 0 to 255 (that is, decimal representation).
As mentioned previously, IOUTFS is a function of the reference
current IREF, which is nominally set by a reference voltage,
VREFIO, and external resistor, RSET. It can be expressed as:
IOUTFS = 32 × IREF (3)
where
IREF = VREFIO/RSET (4)
The two current outputs typically drive a resistive load directly
or via a transformer. If dc coupling is required, then IOUTA
and IOUTB should be directly connected to matching resistive
loads, RLOAD, that are tied to analog common, ACOM. Note
that RLOAD can represent the equivalent load resistance seen by
IOUTA or IOUTB as would be the case in a doubly terminated
50 Ω or 75 Ω cable. The single-ended voltage output appearing
at the IOUTA and IOUTB nodes is simply
VOUTA = IOUTA × RLOAD (5)
VOUTB = IOUTB × RLOAD (6)
Note that the full-scale value of VOUTA and VOUTB should not
exceed the specified output compliance range to maintain
specified distortion and linearity performance.
VDIFF = (IOUTA − IOUTB) × RLOAD (7)
Substituting the values of IOUTA, IOUTB, IREF, and VDIFF can be
expressed as:
VDIFF = {(2 × DAC CODE − 255)/256}
(32 × RLOAD/RSET) × VREFIO (8)
Equation 7 and Equation 8 highlight some of the advantages of
operating the AD9748 differentially. First, the differential
operation helps cancel common-mode error sources associated
with IOUTA and IOUTB, such as noise, distortion, and dc
offsets. Second, the differential code dependent current and
subsequent voltage, VDIFF, is twice the value of the single-ended
voltage output (that is, VOUTA or VOUTB), thus providing twice the
signal power to the load.
Note that the gain drift temperature performance for a single-
ended (VOUTA and VOUTB) or differential output (VBDIFF) of the
AD9748 can be enhanced by selecting temperature tracking
resistors for RLOAD and RSET due to their ratiometric relationship,
as shown in Equation 8.
ANALOG OUTPUTS
The complementary current outputs in each DAC, IOUTA,
and IOUTB can be configured for single-ended or differential
operation. IOUTA and IOUTB can be converted into
complementary single-ended voltage outputs, VOUTA and VOUTB,
via a load resistor, RLOAD, as described in the DAC Transfer
Function section by Equation 5 through Equation 8. The
differential voltage, VDIFF, existing between VOUTA and VOUTB, can
also be converted to a single-ended voltage via a transformer or
differential amplifier configuration. The ac performance
of the AD9748 is optimum and specified using a differential
transformer-coupled output in which the voltage swing at
IOUTA and IOUTB is limited to ±0.5 V.
The distortion and noise performance of the AD9748 can be
enhanced when it is configured for differential operation. The
common-mode error sources of both IOUTA and IOUTB can
be significantly reduced by the common-mode rejection of a
transformer or differential amplifier. These common-mode
error sources include even-order distortion products and noise.
The enhancement in distortion performance becomes more
significant as the frequency content of the reconstructed
waveform increases and/or its amplitude decreases. This is due
to the first-order cancellation of various dynamic common-
mode distortion mechanisms, digital feedthrough, and noise.
Performing a differential-to-single-ended conversion via a
transformer also provides the ability to deliver twice the
reconstructed signal power to the load (assuming no source
termination). Because the output currents of IOUTA and
IOUTB are complementary, they become additive when
processed differentially. A properly selected transformer allows
the AD9748 to provide the required power and voltage levels to
different loads.
AD9748
Rev. A | Page 13 of 24
The output impedance of IOUTA and IOUTB is determined
by the equivalent parallel combination of the PMOS switches
associated with the current sources and is typically 100 kΩ in
parallel with 5 pF. It is also slightly dependent on the output
voltage (that is, VOUTA and VOUTB) due to the nature of a PMOS
device. As a result, maintaining IOUTA and/or IOUTB at a
virtual ground via an I-V op amp configuration results in the
optimum dc linearity. Note that the INL/DNL specifications for
the AD9748 are measured with IOUTA maintained at a virtual
ground via an op amp.
IOUTA and IOUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range
of −1 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit can result in a breakdown
of the output stage and affect the reliability of the AD9748.
The positive output compliance range is slightly dependent on
the full-scale output current, IOUTFS. It degrades slightly from its
nominal 1.2 V for an IOUTFS = 20 mA to 1 V for an IOUTFS = 2 mA.
The optimum distortion performance for a single-ended or
differential output is achieved when the maximum full-scale
signal at IOUTA and IOUTB does not exceed 0.5 V.
DIGITAL INPUTS
The AD9748 digital section consists of eight input bit channels
and a clock input. The 8-bit parallel data inputs follow standard
positive binary coding, where DB7 is the most significant bit
(MSB) and DB0 is the least significant bit (LSB). IOUTA
produces a full-scale output current when all data bits are at
Logic 1. IOUTB produces a complementary output with the
full-scale current split between the two outputs as a function of
the input code.
DVDD
DIGITAL
INPUT
03211-016
Figure 19. Equivalent Digital Input
The digital interface is implemented using an edge-triggered
master/slave latch. The DAC output updates on the rising edge
of the clock and is designed to support a clock rate as high as
210 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulse width. The setup and hold times
can also be varied within the clock cycle as long as the specified
minimum times are met, although the location of these
transition edges can affect digital feedthrough and distortion
performance. Best performance is typically achieved when the
input data transitions on the falling edge of a 50% duty cycle clock.
CLOCK INPUT
A configurable clock input allows for one single-ended and two
differential modes. The mode selection is controlled by the
CMODE input, as summarized in Table 6. Connecting CMODE
to CLKCOM selects the single-ended clock input. In this mode,
the CLK+ input is driven with rail-to-rail swings and the CLK−
input is left floating. If CMODE is connected to CLKVDD, then
the differential receiver mode is selected. In this mode, both
inputs are high impedance. The final mode is selected by
floating CMODE. This mode is also differential, but internal
terminations for positive emitter-coupled logic (PECL) are
activated. There is no significant performance difference
between any of the three clock input modes.
Table 6. Clock Mode Selection
CMODE Pin Clock Input Mode
CLKCOM Single-ended
CLKVDD Differential
Float PECL
In the single-ended input mode, the CLK+ pin must be driven
with rail-to-rail CMOS levels. The quality of the DAC output is
directly related to the clock quality, and jitter is a key concern.
Any noise or jitter in the clock translates directly into the DAC
output. Optimal performance is achieved if the clock input has
a sharp rising edge, because the DAC latches are positive edge
triggered.
In the differential input mode, the clock input functions as a
high impedance differential pair. The common-mode level of
the CLK+ and CLK− inputs can vary from 0.75 V to 2.25 V, and
the differential voltage can be as low as 0.5 V p-p. This mode
can be used to drive the clock with a differential sine wave,
because the high gain bandwidth of the differential inputs
convert the sine wave into a single-ended square wave
internally.
The final clock mode allows for a reduced external component
count when the DAC clock is distributed on the board using
PECL logic. The internal termination configuration is shown in
Figure 20. These termination resistors are untrimmed and can
vary up to ±20%. However, matching between the resistors
should generally be better than ±1%.
CLK+
TO DAC CORE
CLK–
V
TT
= 1.3V NOM
50Ω50Ω
AD9748
CLOCK
RECEIVER
03211-017
Figure 20. Clock Termination in PECL Mode
AD9748
Rev. A | Page 14 of 24
DAC TIMING
Input Clock and Data Timing Relationship
Dynamic performance in a DAC is dependent on the
relationship between the position of the clock edges and the
time at which the input data changes. The AD9748 is rising
edge triggered, and so exhibits dynamic performance sensitivity
when the data transition is close to this edge. In general, the
goal when applying the AD9748 is to make the data transition
close to the falling clock edge. This becomes more important as
the sample rate increases. Figure 21 shows the relationship of
SFDR to clock placement with different sample rates. Note that
at the lower sample rates, more tolerance is allowed in clock
placement, while at higher rates, more care must be taken.
50MHz SFDR
20MHz SFDR
CLOCK PLACEMENT (ns)
SFDR (dB)
80
65
70
75
55
60
35
40
45
50
30
02 64 8 10 12
03211-018
Figure 21. SFDR vs. Clock Placement @ fOUT = 20 MHz and 50 MHz
(fCLOCK = 165 MSPS)
Sleep Mode Operation
The AD9748 has a power-down function that turns off the output
current and reduces the supply current to less than 6 mA over the
specified supply range of 2.7 V to 3.6 V and the temperature range.
This mode can be activated by applying a Logic Level 1 to the
SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 Ω
AVDD. This digital input also contains an active pull-down
circuit that ensures that the AD9748 remains enabled if this
input is left disconnected. The AD9748 takes less than 50 ns to
power down and approximately 5 μs to power back up.
POWER DISSIPATION
The power dissipation, PD, of the AD9748 is dependent on
several factors that include the:
• Power supply voltages (AVDD, CLKVDD, and DVDD)
• Full-scale current output (IOUTFS)
• Update rate (fCLOCK)
• Reconstructed digital input waveform
The power dissipation is directly proportional to the analog
supply current, IAVDD, and the digital supply current, IDVDD. IAVDD
is directly proportional to IOUTFS, as shown in Figure 22, and is
insensitive to fCLOCK.
Conversely, IDVDD is dependent on both the digital input
waveform, fCLOCK, and digital supply DVDD. Figure 23 shows IDVDD
as a function of full-scale sine wave output ratios (fOUT/fCLOCK)
for various update rates with DVDD = 3.3 V.
I
OUTFS
(mA)
35
02
I
AVDD
(mA)
30
25
20
15
10
4 6 8 101214161820
03211-019
Figure 22. IAVDD vs. IOUTFS
RATIO (f
OUT
/f
CLOCK
)
20
0.01 10.1
I
DVDD
(mA)
14
16
18
12
10
8
6
4
2
0
165MSPS
210MSPS
65MSPS
03211-041
125MSPS
Figure 23. IDVDD vs. Ratio @ DVDD = 3.3 V
fCLOCK (MSPS)
ICLKVDD (mA)
11
0
0 15010050 200 250
PECL
DIFF
SE
10
9
8
7
6
5
4
3
2
1
03211-042
Figure 24. ICLKVDD vs. fCLOCK and Clock Mode
AD9748
Rev. A | Page 15 of 24
APPLYING THE AD9748
Output Configurations
The following sections illustrate some typical output
configurations for the AD9748. Unless otherwise noted, it is
assumed that IOUTFS is set to a nominal 20 mA. For applications
requiring the optimum dynamic performance, a differential
output configuration is suggested. A differential output
configuration can consist of either an RF transformer or a
differential op amp configuration. The transformer configuration
provides the optimum high frequency performance and is
recommended for any application that allows ac coupling. The
differential op amp configuration is suitable for applications
requiring dc coupling, bipolar output, signal gain, and/or
level shifting within the bandwidth of the chosen op amp.
A single-ended output is suitable for applications requiring a
unipolar voltage output. A positive unipolar output voltage
results if IOUTA and/or IOUTB is connected to an appropriately
sized load resistor, RLOAD, referred to ACOM. This configuration
can be more suitable for a single-supply system requiring a dc-
coupled, ground referred output voltage. Alternatively, an
amplifier could be configured as an I-V converter, thus
converting IOUTA or IOUTB into a negative unipolar voltage.
This configuration provides the best dc linearity because
IOUTA or IOUTB is maintained at a virtual ground.
DIFFERENTIAL COUPLING USING A TRANSFORMER
An RF transformer can be used to perform a differential-to-
single-ended signal conversion, as shown in Figure 25. A
differentially coupled transformer output provides the optimum
distortion performance for output signals whose spectral
content lies within the transformer’s pass band. An RF transformer,
such as the Mini-Circuits® T1–1T, provides excellent rejection of
common-mode distortion (that is, even-order harmonics) and
noise over a wide frequency range. It also provides electrical
isolation and the ability to deliver twice the power to the load.
Transformers with different impedance ratios can also be used
for impedance matching purposes. Note that the transformer
provides ac coupling only.
R
LOAD
AD9748
MINI-CIRCUITS
T1-1T
OPTIONAL R
DIFF
IOUTA
IOUTB
03211-022
Figure 25. Differential Output Using a Transformer
The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
for both IOUTA and IOUTB. The complementary voltages
appearing at IOUTA and IOUTB (that is, VOUTA and VOUTB)
swing symmetrically around ACOM and should be maintained
with the specified output compliance range of the AD9748. A
differential resistor, R
B
DIFF, can be inserted in applications where
the output of the transformer is connected to the load, RLOAD,
via a passive reconstruction filter or cable. RDIFF is determined
by the transformer’s impedance ratio and provides the proper
source termination that results in a low VSWR. Note that
approximately half the signal power is dissipated across RDIFF.
AD9748
Rev. A | Page 16 of 24
DIFFERENTIAL COUPLING USING AN OP AMP
An op amp can also be used to perform a differential-to-single-
ended conversion, as shown in Figure 26. The AD9748 is
configured with two equal load resistors, RLOAD, of 25 Ω. The
differential voltage developed across IOUTA and IOUTB is
converted to a single-ended signal via the differential op amp
configuration. An optional capacitor can be installed across
IOUTA and IOUTB, forming a real pole in a low-pass filter. The
addition of this capacitor also enhances the op amp’s distortion
performance by preventing the DAC’s high slewing output from
overloading the op amp’s input.
AD9748
IOUTA
IOUTB C
OPT
500Ω
225Ω
225Ω
500Ω
25Ω25Ω
AD8047
03211-023
Figure 26. DC Differential Coupling Using an Op Amp
The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the differential
op amp circuit using the AD8047 is configured to provide some
additional signal gain. The op amp must operate off a dual
supply because its output is approximately ±1 V. A high speed
amplifier capable of preserving the differential performance
of the AD9748 while meeting other system level objectives (that
is, cost or power) should be selected. The op amp’s differential
gain, gain setting resistor values, and full-scale output swing
capabilities should all be considered when optimizing this circuit.
The differential circuit shown in Figure 27 provides the
necessary level shifting required in a single-supply system. In
this case, AVDD, which is the positive analog supply for both
the AD9748 and the op amp, is also used to level shift the
differential output of the AD9748 to midsupply (that is,
AVDD/2). The AD8041 is a suitable op amp for this application.
AD9748
IOUTA
IOUTB C
OPT
500
Ω
225Ω
225Ω
1kΩ25Ω25Ω
AD8041
1kΩ
AVDD
03211-024
Figure 27. Single-Supply DC Differential Coupled Circuit
SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT
Figure 28 shows the AD9748 configured to provide a unipolar
output range of approximately 0 V to 0.5 V for a doubly
terminated 50 Ω cable because the nominal full-scale current,
IOUTFS, of 20 mA flows through the equivalent RLOAD of 25 Ω.
In this case, RLOAD represents the equivalent load resistance seen
by IOUTA or IOUTB. The unused output (IOUTA or IOUTB)
can be connected to ACOM directly or via a matching RLOAD.
Different values of IOUTFS and RLOAD can be selected as long as
the positive compliance range is adhered to. One additional
consideration in this mode is the integral nonlinearity (INL),
discussed in the Analog Outputs section. For optimum INL
performance, the single-ended, buffered voltage output
configuration is suggested.
AD9748
IOUTA
IOUTB
50Ω
25Ω
V
OUTA
=0VTO0.5V
I
OUTFS
= 20mA
50Ω
03211-025
Figure 28. 0 V to 0.5 V Unbuffered Voltage Output
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 29 shows a buffered single-ended output configuration
in which the op amp U1 performs an I-V conversion on the
AD9748 output current. U1 maintains IOUTA (or IOUTB) at a
virtual ground, minimizing the nonlinear output impedance
effect on the DAC’s INL performance as described in the
Analog Outputs section. Although this single-ended
configuration typically provides the best dc linearity
performance, its ac distortion performance at higher DAC
update rates can be limited by U1’s slew rate capabilities. U1
provides a negative unipolar output voltage, and its full-scale
output voltage is simply the product of RFB and IOUTFS. The full-
scale output should be set within U1’s voltage output swing
capabilities by scaling IOUTFS and/or RFB. An improvement in ac
distortion performance can result with a reduced IOUTFS because
U1 is required to sink less signal current.
AD9748
IOUTA
IOUTB
C
OPT
200Ω
U1
V
OUT
= I
OUTFS
× R
FB
I
OUTFS
=10mA
R
FB
200Ω
03211-026
Figure 29. Unipolar Buffered Voltage Output
AD9748
Rev. A | Page 17 of 24
POWER AND GROUNDING CONSIDERATIONS,
POWER SUPPLY REJECTION
Many applications seek high speed and high performance under
less than ideal operating conditions. In these application circuits,
the implementation and construction of the printed circuit
board is as important as the circuit design. Proper RF techniques
must be used for device selection, placement, and routing as
well as power supply bypassing and grounding to ensure
optimum performance. Figure 35 to Figure 38 illustrate the
recommended printed circuit board ground, power, and signal
plane layouts implemented on the AD9748 evaluation board.
One factor that can measurably affect system performance is
the ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the power supply rejection ratio (PSRR).
For dc variations of the power supply, the resulting performance
of the DAC directly corresponds to a gain error associated with
the DAC’s full-scale current, IOUTFS. AC noise on the dc supplies
is common in applications where the power distribution is
generated by a switching power supply. Typically, switching
power supply noise occurs over the spectrum from tens of
kilohertz to several megahertz. The PSRR vs. frequency of the
AD9748 AVDD supply over this frequency range is shown in
Figure 30.
FREQUENCY (MHz)
85
40 1268100
PSRR (dB)
80
75
70
65
60
55
50
24
45
03211-027
Figure 30. Power Supply Rejection Ratio (PSRR)
Note that the ratio in Figure 30 is calculated as amps out/volts
in. Noise on the analog power supply has the effect of modulating
the internal switches, and therefore the output current. The
voltage noise on AVDD, therefore, is added in a nonlinear
manner to the desired IOUT. Due to the relative different size of
these switches, the PSRR is very code dependent. This can produce
a mixing effect that can modulate low frequency power supply
noise to higher frequencies. Worst-case PSRR for either one of
the differential DAC outputs occurs when the full-scale current
is directed toward that output. As a result, the PSRR measurement
in Figure 30 represents a worst-case condition in which the
digital inputs remain static and the full-scale output current of
20 mA is directed to the DAC output being measured.
The following illustrates the effect of supply noise on the analog
supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV of noise and, for simplicity’s
sake (ignoring harmonics), all of this noise is concentrated at
250 kHz. To calculate how much of this undesired noise appears as
current noise superimposed on the DAC’s full-scale current,
IOUTFS, users must determine the PSRR in dB using Figure 30 at
250 kHz. To calculate the PSRR for a given RLOAD, such that the
units of PSRR are converted from A/V to V/V, adjust the curve
in Figure 30 by the scaling factor 20 Ω log (RLOAD). For instance,
if RLOAD is 50 Ω, then the PSRR is reduced by 34 dB (that is,
PSRR of the DAC at 250 kHz, which is 85 dB in Figure 30,
becomes 51 dB VOUT/VIN).
Proper grounding and decoupling should be a primary
objective in any high speed, high resolution system. The
AD9748 features separate analog and digital supplies and
ground pins to optimize the management of analog and digital
ground currents in a system. In general, AVDD, the analog
supply, should be decoupled to ACOM, the analog common,
as close to the chip as physically possible. Similarly, DVDD, the
digital supply, should be decoupled to DCOM as close to the
chip as physically possible.
For those applications that require a single 3.3 V supply for both
the analog and digital supplies, a clean analog supply can be
generated using the circuit shown in Figure 31. The circuit
consists of a differential LC filter with separate power supply
and return lines. Lower noise can be attained by using low ESR
type electrolytic and tantalum capacitors.
100μF
ELECT.
0.1μF
CER.
TTL/CMOS
LOGIC
CIRCUITS
3.3V
POWER SUPPLY
FERRITE
BEADS
AVDD
ACOM
10μF–22μF
TANT.
03211-028
Figure 31. Differential LC Filter for Single 3.3 V Applications
AD9748
Rev. A | Page 18 of 24
EVALUATION BOARD
GENERAL DESCRIPTION
The AD9748 evaluation boards allow for easy setup and testing
of the product in the LFCSP package. Careful attention to layout
and circuit design, combined with a prototyping area, allows the
user to evaluate the AD9748 easily and effectively in any
application where high resolution, high speed conversion is
required.
This board allows the user the flexibility to operate the AD9748
in various configurations. Possible output configurations
include transformer coupled, resistor terminated, and single
and differential outputs. The digital inputs are designed to be
driven from various word generators, with the on-board option
to add a resistor network for proper load termination. Provisions
are also made to exercise the power-down feature of the
AD9748 and select the clock and data modes.
AD9748
Rev. A | Page 19 of 24
CVDD
RED
TP12
BEAD
TB1 1
TB1 2
C7
0.1μF
C9
0.1μF
C3
0.1μF
BLK
TP2
TP4
TP6
BLK
BLK
C6
0.1μF
C8
0.1μF
C10
0.1μF
C2
10μF
6.3V
C4
10μF
6.3V
C5
10μF
6.3V
L1
DVDD
RED
TP13
BEAD
TB3 1
TB3 2
L2
AVDD
RED
TP5
BEAD
TB4 1
TB4 2
L3
J1
13
11
9
7
5
3
1
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
39
37
35
33
31
29
27
25
23
21
19
17
15
HEADER STRAIGHT UP MALE NO SHROUD
JP3
CKEXTX
CKEXT
CKEXTX
R21
100Ω
R24
100Ω
R25
100Ω
R26
100Ω
R27
100Ω
R28
100Ω
DB0X
DB1X
DB2X
DB3X
DB4X
DB5X
DB6X
DB7X
DB8X
DB9X
DB10X
DB11X
DB12X
DB13X
DB0X
DB1X
DB2X
DB3X
DB4X
DB5X
DB6X
DB7X
DB8X
DB9X
DB10X
DB11X
DB12X
DB13X
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
22Ω16
22Ω15
22Ω14
22Ω13
22Ω12
22Ω11
22Ω10
22Ω9
22Ω16
22Ω15
22Ω14
22Ω13
22Ω12
22Ω11
22Ω10
22Ω9
R20
100Ω
R19
100Ω
R18
100Ω
R17
100Ω
R16
100Ω
R15
100Ω
R4
100Ω
R3
100Ω
1 RP3
2 RP3
3 RP3
4 RP3
5 RP3
6 RP3
7 RP3
8 RP3
1 RP4
2 RP4
3 RP4
4 RP4
5 RP4
6 RP4
7 RP4
8 RP4
03211-029
Figure 32. Evaluation Board Schematic—Power Supply and Digital Inputs
AD9748
Rev. A | Page 20 of 24
C19
CVDD
CVDD
DB8
DB9
DB10
DB11
CLKB
DB5
DVDD
DB6
DB7
CLK
DB0
DB1
DB2
DB3
DB4
DB13
DB12
IOUT
AVDD
DVDD CVDD
A
V
DD
DB8
DB9
DB10
DB11
IB
FS ADJ
CLKB
DB5
DVDD
DB6
DB7
CLK
CVDD
DCOM
DB0
DB1
DB2
DB3
DB4
DCOM1
DB13
ACOM1
AVDD
ACOM
IA
REFIO
AVDD1
SLEEP
DB12
CCOM
CMODE
MODE
CMODE
MODE
T1 – 1T
T1
JP8
JP9
4
3
2
1
5
6
AGND: 3, 4, 5
S3
R11
C13
28
25
17
23
21
22
18
19
27
26
24
20
29
30
31
32
DNP
DNP
C12
C11
C17 C19 C32
R30
R29
U1
AD9748LFCSP
14
5
6
7
8
9
10
11
12
1
2
3
4
13
15
16
WHT
TP1
WHT
TP11
JP1 0.1%
R1
R10
WHT
TP3
TP7
WHT
SLEEP
03211-030
0.1μF0.1μF0.1μF
50Ω
50Ω
10Ω
10kΩ
0.1μF
2kΩ
Figure 33. Evaluation Board Schematic—Output Signal Conditioning
U4
U4
JP2
AGND: 5
CVDD: 8
4
3
6
CVDD: 8
C35
0.1μF
C20
10μF
16V
S5
AGND: 3, 4, 5
C34
0.1μF
CKEXT
CLK
CLKB
R5
120Ω
R2
120Ω
R6
50Ω
CVDD
AGND: 5
2
1
7
CVDD
03211-031
Figure 34. Evaluation Board Schematic—Clock Input
AD9748
Rev. A | Page 21 of 24
03211-032
Figure 35. Evaluation Board Layout—Primary Side
03211-033
Figure 36. Evaluation Board Layout—Secondary Side
AD9748
Rev. A | Page 22 of 24
03211-034
Figure 37. Evaluation Board Layout—Ground Plane
03211-035
Figure 38. Evaluation Board Layout—Power Plane
AD9748
Rev. A | Page 23 of 24
03211-036
Figure 39. Evaluation Board Layout Assembly—Primary Side
03211-037
Figure 40. Evaluation Board Layout Assembly—Secondary Side
AD9748
Rev. A | Page 24 of 24
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
0.30
0.23
0.18
0.20 REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
12° MAX
1.00
0.85
0.80 SEATING
PLANE
COPLANARITY
0.08
1
32
8
9
25
24
16
17
0.50
0.40
0.30
3.50 REF
0.50
BSC
PIN 1
INDICATOR
TOP
VIEW
5.00
BSC SQ
4.75
BSC SQ
3.25
3.10 SQ
2.95
PIN 1
INDICATOR
0.60 MAX
0.60 MAX
0.25 MIN
EXPOSED
PAD
(BOTTOM VIEW)
Figure 41. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9748ACP −40°C to +85°C 32-Lead LFCSP_VQ CP-32-2
AD9748ACPRL7 −40°C to +85°C 32-Lead LFCSP_VQ CP-32-2
AD9748ACPZ1−40°C to +85°C 32-Lead LFCSP_VQ CP-32-2
AD9748ACPZRL71−40°C to +85°C 32-Lead LFCSP_VQ CP-32-2
AD9748ACP-PCB Evaluation Board
1 Z = Pb-free part.
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03211–0–12/05(A)
