HMCS400 Series Application Note ADE-502-064 Rev. 1.0 3/4/1999 Hitachi, Ltd. Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products. Preface The HMCS43XX family is a family of 4-bit microcomputers built around the HMCS400 CPU and including standard peripheral functions such as A/D converters with a variety of A/D input channels, serial interfaces, and multifunction timers. The architecture of the powerful HMCS400 CPU core is known for its ease of programming. The peripheral functions of the HMCS43XX have been developed as standalone modules and a modular architecture employed in which the respective modules are connected via a standardized interface. The HD404889 Series are also 4-bit microcomputers also built around the powerful HMCS400 CPU core with its excellent ease of programming, and including various peripheral functions such as LCD circuit, A/D converters, and multifunction timers. The microcomputers in this series are ideally suited to display panel control and system control in a wide range of applications, primarily audio-visual equipment such as radiocassette sets with built-in CD players, as well as home appliances such as electronic jars, and telephones and pagers. The peripheral functions of the HM404889 Series have been developed as standalone modules and a modular architecture employed in which the respective modules are connected via a standardized interface. The "Applications" volume of the HMCS400 Series Application Notes is a collection of examples of combinations of the built-in peripherals in the HMCS400 Series of microcomputers. This collection is intended as a reference for software and hardware designers. The operation of the programs and circuits, etc., described in these application notes has been checked. However, please be sure to confirm their operation before actually using them in any application. Rev. 1.0, 03/99, page v of 209 Contents Section 1 1.1 HMCS400 Series Application Notes-- How to Use the Applications Volume ..................................................... Structure of Applications Section ..................................................................................... 1 2 Section 2 2.1 2.2 2.3 Applications ..................................................................................................... 5 Musical Performance ........................................................................................................ 5 Stepping Motor Control .................................................................................................... 82 Key Scan and 7-Segment LED Display............................................................................ 167 Rev. 1.0, 03/99, page vii of 209 Section 1 HMCS400 Series Application Notes-- How to Use the Applications Volume The Application Notes are, as shown in figure 1, divided into two sections. Application Notes HMCS400 Series Application Notes-- How to Use the Applications Volume Applications Figure 1 Structure of Application Notes HMCS400 Series Application Notes--How to Use the Applications Volume This section describes how to use the HMCS400 Series Application Notes--Applications Volume. Applications This section uses simple example tasks to describe how various combinations of the built-in peripherals (timers, serial interface, A/D converters, I/O ports, interrupts, low-power modes, etc.) of the MHCS400 Series of microcomputers are used. Rev. 1.0, 03/99, page 1 of 209 1.1 Structure of Applications Section As shown in figure 2, the Applications section describes how to use the built-in functions of the HMCS400 Series. Applications Specifications Concepts Description of Functions Description of Operation Description of Software Description of Modules Description of Arguments Description of Internal Registers Description of RAM Flowcharts Program Listings Figure 2 Structure of Applications Section Specifications This section describes the system specifications for the example tasks. Concepts This section describes the methods employed to realize the systems in the example tasks. Description of Functions This section describes the features and distribution of the peripheral functions employed in the example tasks. Description of Operation This section uses timing charts to describe the operation of the example tasks. Rev. 1.0, 03/99, page 2 of 209 Description of Software 1. Description of Modules This section describes the software module operating in the example tasks. 2. Description of Arguments This section describes the input arguments required for execution of the respective modules, and the arguments output on completion of module execution. 3. Description of Internal Registers This section describes the internal registers (timer control register and serial mode register, etc.) set by the module. 4. Description of RAM This section describes the RAM labels used by the modules and their functions. Flowcharts This section provides flowcharts of the software run in the example tasks. Program Listings This section provides listings of the software run in the example tasks. Rev. 1.0, 03/99, page 3 of 209 Section 2 Applications 2.1 Musical Performance Musical Performance MCU: H4344/H4318/H4359/ H4369/H4889 Functions Used: R0/R1 Port, Timer B, and Timer C Specifications 1. As shown in figure 1, the Bach minuet is played repeatedly in the H4344/H4318/H4359/ H4369 Series by connecting a speaker with an 8- resistance to the R03 port. In the H4889, this is achieved by connecting to the R12 port. VCC H4344/H4318/H4359/ H4369/H4889 Speaker (8- impedance) R03/R12* Note: * R03: Employed in the H4344/H4318/H4359/H4369 Series R12: Employed in the H4889 Series Figure 1 Speaker Connection in Musical Performance Rev. 1.0, 03/99, page 5 of 209 Concepts 1. The "minuet" is played by outputting a pulse with a frequency corresponding to the notes from the R03/R12 port. 2. The frequencies corresponding to the notes are set using the timer B reload timer function. The data table is referenced using the pattern command and the referenced data set in the timercounter B reload value to achieve the frequency corresponding to the desired note. Moreover, the High/Low output from the R03/R12 port is controlled during timer B interrupt processing. 3. The duration of each note is set using the timer C reload timer function. The data table is referenced using the pattern command and the referenced data set in the timer counter C reload value to set the output duration of each note. 4. Figure 2 shows the settings for the frequencies for the respective notes and the duration of each note. R03/R12 output pin Measurement by timer B reload timer function Measurement by timer C reload timer function Setting of reload values of timer B and timer C Measurement by timer B reload timer function Measurement by timer C reload timer function Setting of reload values of timer B and timer C Figure 2 Method of Setting Frequencies for Notes and Output Durations Rev. 1.0, 03/99, page 6 of 209 Description of Functions 1. In this example task, the R0/R1 port, timer B, and timer C functions are used to play a Bach minuet. Figure 3 is a functional block diagram of this task. H4344/H4318/H4359/H4369/H4889 Functions Output pulse frequency setting Pulse output duration setting Timer B reload timer function Timer C reload timer function Timer B interrupt request Interrupt request flag adjudication TWBL/TWBU setting TWCL/TWCU setting CPU H4344/H4318/H4359/ H4369/H4889 Speaker output pulse I/O port function H4344/H4318/H4359/H4369: R03 output pin H4889: R12 output pin Pulse output Figure 3 Functional Block Diagram * Timer B reload timer function This function sets the output pulse frequency. The frequency of the output pulse is set by the timer counter B reload value. The reload value to be set is referenced from the data table. * Timer C reload timer function This function sets the duration for which a frequency pulse is output. The duration of pulse output is set by the timer counter C reload value. The reload value to be set is referenced from the data table. Rev. 1.0, 03/99, page 7 of 209 * I/O port function This is the output for the pulse to be output to the speaker. 2. The timer B, timer C, and I/O port functions are described below. a. Figure 4 is a block diagram of the timer B function. System clock (4 MHz/4) EVNB pin Edge detection Timer B function (reload timer function) Timer B interrupt cycle setting TCB input clock setting /2048 /512 /128 /8 /32 /4 /2 Prescaler S (PSS) Selector TCB reload value setting Timer mode register B1 (TMB1) Selects division ratio of 4 Clock derived by dividing system clock by 4 ((4MHz/4) / 4 = 250 kHz) Timer counter B (TCBL) Reload timer function selection (TCBU) TCB reload value setting Timer write register B (TWBL) (TWBU) TCB reload value setting TCB overflow Timer B interrupt request flag (IFTB) Interrupt request from TCB overflow Figure 4 Timer B Function Block Diagram Rev. 1.0, 03/99, page 8 of 209 Reload timer function, TCB input clock select b. Timer B is an 8-bit multifunction timer (free running/event counter/reload timer/input *1 capture ). In this example task, timer B is used as a reload timer. Table 1 describes the timer B functions. Table 1 Timer B Functions Timer Mode Register B1 (TMB1) Function TMB1 is a 4-bit write-only register. It selects the timer B function (free-running/reload timer) and operating clock. TMB1 is initialized to $0 when reset and in stop mode. Timer Write Register BL, U (TWBL, TWBU) Function TWBL and TWBU form an 8-bit write-only register, which is made up of the lower digit (TWBL) and upper digit (TWBU). TWBL and TWBU are used for the initial TCB setting (the reload setting when operation as a reload timer). Timer Counter B (TCB) Function TCB is an 8-bit up-counter, which is incremented by the input internal clock. The TCB input clock is selected using bits TMB12 to TMB10 of TMB1. The value written to TWBL and TWBU is also written to TCB. When TCB overflows, the timer B interrupt request flag (IFTB) is set to "1". If, at this point, timer B is set as a reload timer, the value of TWBL and TWBU is written to this counter and the count starts from this value. TCB is initialized to $00 when reset and in stop mode. Prescaler S (PSS) Function PSS is an 11-bit counter to which the system clock is input when in active mode and *2 standby mode, and the subsystem clock is input when in subactive mode PSS is initialized to $000 at a reset, and division of the system clock starts when the reset is *2 canceled. PSS operation is halted when reset, in stop mode, and in watch mode . However, it runs in other operating modes. The PSS output is shared by the internal peripheral modules, the division ratio being set independently for each of the internal peripheral modules. Timer B Interrupt Request Flag (IFTB) Function IFTB reflects the existence of the timer B interrupt request. When timer B overflows, IFTB is set to "1". IFTB can only be read/written to (only "0" can be written) using bit operation commands. Note that IFTB is not automatically cleared even when the interrupt is received, and must be cleared by writing "0" using software. IFTB is cleared at a reset and in stop mode. Timer B Interrupt Mask (IMTB) Function IMTB is the bit that masks IFTB. When IFTB is set to "1" and, additionally, IMTB is "0", a timer B interrupt request is sent to the CPU (when IE = "1"). If IFTB is set to "1" but IMTB is "1", no interrupt request is sent to the CPU and the timer B interrupt is held. IMTB can only be read or written to using bit operation commands. It is set to "1" at a reset and in stop mode. Notes: 1. Applies to H4318/H4359/H4369 Series only. In the H4344/H4889 Series, timer B has no input capture function. 2. Applies only to H4369/H4889 Series. Rev. 1.0, 03/99, page 9 of 209 c. Figure 5 is a block diagram of the timer C function in the H4344/H4318/H4359/H4369 Series. System clock (4 MHz/4) Timer C functions (reload timer function) Timer C interrupt cycle setting TCC input clock setting /2048 /1024 /512 /128 /8 /32 /4 /2 Prescaler S (PSS) Selector TCC reload value setting Selects division ratio of 2048 Reload timer function, TCC input clock select Clock derived by dividing system clock by 2048 ((4MHz/4) / 2048 = 488.28135 Hz) Timer counter C (TCCL) Reload timer function selection (TCCU) TCC reload value setting Timer write register C (TWCL) Timer mode register C (TMC) (TWCU) TCC overflow Timer C interrupt request flag (IFTC) TCC reload value setting Figure 5 H4344/H4318/H4359/H4369 Series Timer C Function Block Diagram Rev. 1.0, 03/99, page 10 of 209 d. Figure 6 is a block diagram of the timer C function in the H4889 Series. Timer B overflow System clock Timer C function (reload timer function) Timer C interrupt cycle setting TCC input clock setting /2048 /512 /128 /8 /32 /4 /2 Prescaler S (PSS) Selector TCC reload value setting Reload timer function selection (TCCU) TCC reload value setting Timer write register C (TWCL) Selects division ratio of 2048 Reload timer function, TCC input clock select Clock derived by dividing system clock by 2048 ((4MHz/4) / 2048 = 488.28135 Hz) Timer counter C (TCCL) Timer mode register C1 (TMC1) (TWCU) TCC overflow Timer C interrupt request flag (IFTC) TCC reload value setting Figure 6 H4889 Series Timer C Function Block Diagram Rev. 1.0, 03/99, page 11 of 209 e. Timer C is an 8-bit multifunction timer (free running/reload timer). In the H4889 Series, timer B overflow can be selected as the clock source, allowing timer B and timer C to be used as a 16-bit counter. In this example task, timer C is used as a reload timer. Table 2 describes the timer C functions. Table 2 Timer C Functions Timer Mode Register C (TMC) Function TMC is a 4-bit write-only register. It selects the timer C function (free-running/reload timer) and operating clock. TMC is initialized to $0 when reset and in stop mode. Timer Mode Register C1 (TMC1) Function Note: Applies to H4344/H4318/H4359/H4369 Series Note: Applies to H4889 Series TMC1 is a 4-bit write-only register. It selects the timer C function (free-running/reload timer) and operating clock. TMC1 is initialized to $0 when reset and in stop mode. Timer Write Register CL, U (TWCL, TWCU) Function TWCL and TWCU form an 8-bit write-only register, which is made up of the lower digit (TWCL) and upper digit (TWCU). TWCL and TWCU are used for the initial TCC setting (the reload setting when operation as a reload timer). Timer Counter C (TCC) Function TCC is an 8-bit up-counter, which is incremented by the input internal clock. The TCC input clock is selected using bits TMC12 to TMC10 of TMC1. The value written to TWCL and TWCU is also written to TCC. When TCC overflows, the timer C interrupt request flag (IFTC) is set to "1". If, at this point, timer C is set as a reload timer, the value of TWCL and TWCU is written to this counter and the count starts from this value. TCC is initialized to $00 when reset and in stop mode. Timer C Interrupt Request Flag (IFTC) Function IFTC reflects the existence of the timer C interrupt request. When timer C overflows, IFTC is set to "1". IFTC can only be read/written to (only "0" can be written) using bit operation commands. Note that IFTC is not automatically cleared even when the interrupt is received, and must be cleared by writing "0" using software. IFTC is cleared at a reset and in stop mode. Timer C Interrupt Mask (IMTC) Function IMTC is the bit that masks IFTC. When IFTC is set to "1" and, additionally, IMTC is "0", a timer C interrupt request is sent to the CPU (when IE = "1"). If IFTC is set to "1" but IMTC is "1", no interrupt request is sent to the CPU and the timer C interrupt is held. IMTC can only be read or written to using bit operation commands. It is set to "1" at a reset and in stop mode. Rev. 1.0, 03/99, page 12 of 209 f. Figure 7 is a block diagram of the R0 port functions in the H4344/H4318/H4359/H4369 Series. Figure 8 is a block diagram of the R1 port functions in the H4889 Series. R0 port functions R00/SCK pin R01/SI pin R02/SO pin R03 output pin R0 port R03 output data R03 output data setting R03 output pin function setting R03 output pin function setting R03 output data Port data register (PDR) R03 I/O pin function setting Data control register (DCR0) R03 I/O pin function switch setting Port mode register A (PMRA) R03/TOC pin function switch setting Pulse output to speaker Figure 7 Function Block Diagram of R0 Port in H4344/H4318/H4359/H4369 Series R1 port functions R10/EVNB pin R11/EVND pin R12 output data R12 output pin R13/T0B pin R1 port R12 output data Port data register (PDR) R12 output data setting R12 output pin function settings R12 output pin function setting R12 I/O pin function setting Data control register (DCR1) R12 I/O pin function switch setting Port mode register 2 (PMR2) R12/BUZZ pin function switch setting Pulse output to speaker Figure 8 Function Block Diagram of R1 Port in H4889 Series Rev. 1.0, 03/99, page 13 of 209 g. The R0 port in the H4344/H4318/H4359/H4369 Series, and the R1 port in the H4889 Series are 4-bit I/O ports. The LAR and LBR commands are used for 4-bit input, and the LRA and LRB commands for 4-bit output of both ports. The output data is stored in the PDR of the respective pin. In this example task, the R03 pin in the H4344/H4318/H4359/ H4369 Series and the R12 pin the H4889 Series are set for output, and output a pulse to a speaker. Table 3 describes the functions of the R0 port in the H4344/H4318/H4359/H4369 Series and the R1 port in the H4889 Series. Table 3 Description of R0 Port Functions in H4344/H4318/H4359/H4369 Series and R1 Port Functions in H4889 Series Data Control Register R0 (DCR0) Function DCR0 switches the I/O pin function of the R0 port. When any bit of DCR0 is cleared to "0", the output buffer (CMOS) of the corresponding pin is turned OFF and the output is set to high impedance. When the respective bit of DCR0 is set to "1", the output buffer of the corresponding pin is set ON and the corresponding PDR value is output. Data Control Register R1 (DCR1) Function Note: Applies to H4344/H4318/H4359/H4369 Series PMRA is a 4-bit write-only register. Bits PMRA2 to PMRA0 switch the dual-function R0 port pins. Port Mode Register 2 (PMR2) Function Note: Applies to H4889 Series DCR1 switches the I/O pin function of the R1 port. When any bit of DCR1 is cleared to "0", the output buffer (CMOS) of the corresponding pin is turned OFF and the output is set to high impedance. When the respective bit of DCR1 is set to "1", the output buffer of the corresponding pin is set ON and the corresponding PDR value is output. Port Mode Register A (PMRA) Function Note: Applies to H4344/H4318/H4359/H4369 Series Note: Applies to H4889 Series PMR2 is a 4-bit write-only register. Bits PMR23 to PMR20 switch the dual-function R1 port pins. Port Data Register (PDR) Function The I/O pins of the R ports have built-in PDRs to store the output data. When the LRA and LRB commands are executed, the contents of the accumulator (A) and B register (B) are transferred to the PDR of the specified R port. When the corresponding bit of the DCR of the R port is "1", the output buffer of the appropriate pin is set ON and the value in the PDR is output via that pin. The PDR is initialized to $F at a reset. Rev. 1.0, 03/99, page 14 of 209 3. Table 4 shows the allocation of functions in the example task. Table 4 Function Allocation Function Function Allocation System clock The system clock is obtained by dividing the clock output from the system clock oscillator by 4. It is used for operating the CPU and internal peripheral modules. In this example task, a 4 MHz system clock oscillator is used, so the clock supplied to the CPU and internal peripheral modules is 1 MHz. The clock used by timer B and timer C is obtained by dividing the 1 MHz clock at PSS. PSS The clock input to timer B and timer C is obtained by dividing the system clock. The clock supplied to timer B is obtained by dividing the system clock by 4. The clock supplied to timer C is obtained by dividing the system clock by 2048. TCB This is an 8-bit up-counter. The count starts from the value set in TWBL and TWBU. When an overflow occurs, IFTB is set to "1". After an overflow, the reload value set in TWBL and TWBU is set in TCB. TWBL, TWBU The TCB reload value is set in TWBL and TWBU. The reload value is determined from the pulse frequency to be output to the speaker. The frequencies corresponding to the various notes are stored in the data table. TMB1 TMB1 selects the reload timer function for timer B and a clock obtained by dividing the system clock by 4 as the TCB input clock. IFTB IFTB reflects the existence of a timer B interrupt request. The pulse output pin output level is set in the timer B interrupt processing. IMTB Enables/disables timer B interrupt requests. TCC This is an 8-bit up-counter. The count starts from the value set in TWCL and TWCU. When an overflow occurs, IFTC is set to "1". After an overflow, the reload value set in TWCL and TWCU is set in TCC. TWCL, TWCU The TCC reload value is set in TWCL and TWCU. The reload value is determined from the duration of pulse output to the speaker. The output duration for each note is stored in the data table. TMC (H4344/H4318/ H4359/H4369) TMC (or TMC1) selects the reload timer function for timer C and a clock obtained by dividing the system clock by 2048 as the TCC input clock. TMC1 (H4889) IFTC Reflects the existence of a timer C interrupt request. IMTC Enables/disables timer C interrupt requests. DCR0 (H4344/H4318/ H4359/H4369) Sets the R03 pins (H4344/H4318/H4359/H4369 Series) and R12 pins (H4889 Series) as output pins. DCR1 (H4889) Rev. 1.0, 03/99, page 15 of 209 Table 4 Function Allocation (cont) Function Function Allocation PMRA (H4344/H4318/ H4359/H4369) PMR2 (H4889) Sets the R03/TOC dual-function pin (H4344/H4318/H4359/H4369 Series) as an R03 I/O pin and the R12/BUZZ dual-function pin (H4889 Series) as an R12 pin. PDR Stores the output data for the R03/R12 pin. R03 pin Output pin for the pulse in the H4344/H4318/H4359/H4369 Series. R12 pin Output pin for the pulse in the H4889 Series. Rev. 1.0, 03/99, page 16 of 209 Description of Operation 1. Figure 9 shows the operating principles of the timer B, timer C, and R03/R12 output pins. Outputs "SO" Outputs "DO" TCB H'FF H'AB H'7F H'00 Time TCC H'FF H'9C H'38 H'00 Time High R03/R12 output pin Low 516 s 2.064 ms 409.6 ms Software processing 1. The data table is referenced and the TCB reload value set in TWBL and TWBU. 2. The data table is reference and the TCC reload value set in TWCL and TWCU. Hardware processing 1. The TCB value is set to the value in TWBL and TWBU and the count up starts. 2. The TCC value is set to the value in TWCL and TWCU and the count up starts. Software processing 1. Timer B interrupt processing starts. 2. IFTB is cleared to "0". 3. Data is set in the PDR of the R03/R12 pin. Hardware processing 1. TCB overflows. 2. The value in TWBL and TWBU is set in TCB. 3. IFTB is set to "1". 4. A "High" or "Low" signal is output from the R03/R12 pin. Software processing 1. The data table is referenced and the TCB reload value set in TWBL and TWBU. 2. The data table is reference and the TCC reload value set in TWCL and TWCU. Hardware processing 1. The TCB value is set to the value in TWBL and TWBU and the count up starts. 2. The TCC value is set to the value in TWCL and TWCU and the count up starts. Figure 9 Operating Principles of Timer C, Timer B, and R03/R12 Output Pins Rev. 1.0, 03/99, page 17 of 209 2. Figure 10 shows the operating principles for the pulse output from the R03/R12 pin. 1st Cycle "So" "Do" "Re" "Mi" "Fa" R03/R12 output pin 1.360 ms 2.064 ms 1.824 ms 1.616 ms 114.67 ms 319.49 ms 319.49 ms 319.49 ms "So" "Do" " " "Do" 1.520 ms 319.49 ms R03/R12 output pin 1.360 ms 2.064 ms 2.064 ms 114.67 ms 217.09 ms 421.89 ms 114.67 ms "La" "Fa" "So" "La" "Ti" R03/R12 output pin 1.216 ms 1.520 ms 1.360 ms 1.216 ms 114.67 ms 319.49 ms 319.49 ms 319.49 ms "Do" "Do" " " "Do" 1.056 ms 319.49 ms R03/R12 output pin 1.008 ms 2.064 ms 2.064 ms 114.67 ms 217.09 ms 421.89 ms 114.67 ms "Fa" "So" "Fa" "Mi" "Re" R03/R12 output pin 1.520 ms 1.360 ms 114.67 ms 319.49 ms 1.520 ms 319.49 ms 1.616 ms 319.49 ms Figure 10 Operating Principles of Output Pulse Rev. 1.0, 03/99, page 18 of 209 1.824 ms 319.49 ms "Mi" "Fa" "Mi" "Re" "Do" R03/R12 output pin 1.616 ms 1.520 ms 114.67 ms "Ti" 319.49 ms "Do" 1.616 ms 319.49 ms "Re" 1.824 ms 319.49 ms "Mi" 2.064 ms 319.49 ms "Fa" R03/R12 output pin 2.144 ms 2.064 ms 1.824 ms 114.67 ms 319.49 ms 319.49 ms "Re" "Re" "Re" 1.616 ms 1.520 ms 319.49 ms 319.49 ms "Mi" "Fa" R03/R12 output pin 1.824 ms 1.824 ms 114.67 ms 114.67 ms 1.824 ms 114.67 ms 2nd Cycle "So" "Do" "Re" R03/R12 output pin 1.360 ms 2.064 ms 1.824 ms 1.616 ms 114.67 ms 319.49 ms 319.49 ms 319.49 ms "So" "Do" " " "Do" 1.520 ms 319.49 ms R03/R12 output pin 1.360 ms 2.064 ms 114.67 ms "La" 217.09 ms "Fa" 2.064 ms 421.89 ms "So" 114.67 ms "La" "Ti" R03/R12 output pin 1.216 ms 1.520 ms 114.67 ms 319.49 ms 1.360 ms 319.49 ms 1.216 ms 319.49 ms 1.056 ms 319.49 ms Figure 10 Operating Principles of Output Pulse (cont) Rev. 1.0, 03/99, page 19 of 209 "Do" "Do" " " "Do" R03/R12 output pin 1.008 ms 2.064 ms 217.09 ms 114.67 ms "Fa" "So" 2.064 ms 421.89 ms 114.67 ms "Fa" "Mi" "Re" R03/R12 output pin 1.520 ms 1.360 ms 114.67 ms 319.49 ms "Mi" "Fa" 1.520 ms 319.49 ms "Mi" 1.616 ms 319.49 ms "Re" 1.824 ms 319.49 ms "Do" R03/R12 output pin 1.616 ms 1.520 ms 319.49 ms 114.67 ms "Re" "Mi" 1.616 ms 319.49 ms "Re" 1.824 ms 319.49 ms "Do" 2.064 ms 319.49 ms "Ti" R03/R12 output pin 1.824 ms 1.616 ms 114.67 ms 319.49 ms "Do" "Do" 1.824 ms 319.49 ms 2.064 ms 319.49 ms " " R03/R12 output pin 2.064 ms 2.064 ms 319.49 ms 319.49 ms 319.49 ms Figure 10 Operating Principles of Output Pulse (cont) Rev. 1.0, 03/99, page 20 of 209 2.144 ms 319.49 ms 3. Table 5 shows the output pulse frequencies for the respective notes. Table 5 Output Pulse Frequencies for Respective Notes TCB Reload Value TCB Overflow Cycle Speaker Pulse Output Frequency Ti $7A 536 s 1 / (536 s x 4) 466.42 Hz Do $7F 516 s 1 / (516 s x 4) 484.50 Hz Re $8E 456 s 1 / (456 s x 4) 548.25 Hz Mi $9B 404 s 1 / (404 s x 4) 618.81 Hz Fa $A1 380 s 1 / (380 s x 4) 657.89 Hz So $AB 340 s 1 / (340 s x 4) 735.29 Hz La $B4 304 s 1 / (304 s x 4) 822.37 Hz Ti $BD 264 s 1 / (264 s x 4) 946.97 Hz Do $C1 252 s 1 / (252 s x 4) 992.06 Hz Note Score Rev. 1.0, 03/99, page 21 of 209 Description of Functions 1. Description of Modules Table 6 describes the modules used in the example task. Table 6 Description of Modules Module Label Function Main routine SPLMN This routine makes the initial stack pointer, timer B, timer C, and I/O port settings, enables the interrupts, and initializes the RAM to be used. It also sets the output pulse cycle created by the timer C overflow and the output duration, and initializes and sets those again each time another play starts. Timer B interrupt processing routine SPLINT Controls the "High/Low" setting of the output pulse. 2. Description of Arguments No arguments are used in this example task. Rev. 1.0, 03/99, page 22 of 209 3. Description of Internal Registers a. Table 7 shows the internal registers of the H4344/H4318/H4359/H4369 used in this example. Table 7 Internal Registers of H4344/H4318/H4359/H4369 Used in Example Register Description RAM Address Setting IE Interrupt Enable Flag 0, $000 1 1, $000 0 0, $002 0 1, $002 0 2, $002 0 3, $002 1 $004 $0 This flag controls reception of all interrupts by the CPU. RSP * When IE = "0", CPU reception of all interrupts is disabled. * When IE = "1", CPU reception is enabled. Reset Stack Pointer Clearing RSP to "0" initializes the stack pointer. IFTB Timer B Interrupt Request Flag Reflects the existence of a timer B interrupt request. IMTB * When IFTB = "0", no timer B interrupt is requested. * When IFTB = "1", a timer B interrupt is requested. Timer B Interrupt Mask This bit masks IFTB. IFTC * When IMTB = "0", IFTB is enabled. * When IMTB = "1", IFTB is masked. Timer C Interrupt Request Flag Reflects the existence of a timer C interrupt request. IMTC * When IFTC = "0", no timer C interrupt is requested. * When IFTC = "1", a timer C interrupt is requested. Timer C Interrupt Mask This bit masks IFTC. PMRA * When IMTC = "0", IFTC is enabled. * When IMTC = "1", IFTC is masked. Port Mode Register A Bit 0 switches R02, SO pin functions, bit 1 switches R01/SI pin functions, bit 2 switches R03/TOC pin functions, and bit 3 switches D3/BUZZ pin functions. * When PMRA = $0, pins R02, R01, R03 and D3 are selected. Note: PMRA bit 3 cannot be used in the H4344 Series. Rev. 1.0, 03/99, page 23 of 209 Table 7 Internal Registers of H4344/H4318/H4359/H4369 Used in Example (cont) Register Description RAM Address Setting TMB1 Timer Mode Register B1 $009 $D $00A $0 $00B $0 $00D $8 $00E $0 $00F $0 $026 $0 TMB13 selects timer B functions, TMB12 to TMB10 select the operating clock * TWBL When TMB13 = "1", TMB12 = "1", TMB11 = "1", and TMB10 = "1", timer B is set for reload timer functions and the operating clock is set for the system clock divided by 4. Timer Write Register BL Sets the lower digit of the TCB reload value. TWBU Timer Write Register BU Sets the upper digit of the TCB reload value. TMC Timer Mode Register C Selects timer C functions and operating clock. * TWCL When TMC3 = "1", TMC2 = "0", TMC1 = "0", and TMC0 = "0", timer C is set for reload timer functions and the operating clock is set for the system clock divided by 2048. Timer Write Register CL Sets the lower digit of the TCC reload value. TWCU Timer Write Register CU Sets the upper digit of the TCC reload value. TMB2 Timer Mode Register B2 Sets the input capture function and selects the detection edge of the EVNB pin input. * When TMB22 = "0", free-running/reload timer B functions are selected. * When TMB22 = "1", input capture timer B functions are selected. Note: The TMB22 bit cannot be used in the H4344. * When TMB21 = "0" and TMB20 = "0", there is no edge detection of the EVNB pin input. Rev. 1.0, 03/99, page 24 of 209 Table 7 Internal Registers of H4344/H4318/H4359/H4369 Used in Example (cont) Register Description RAM Address Setting SSR1 System Clock Selection Register 1 $027 $2 $030 $8 Selects the system clock oscillation frequency, subsystem clock frequency division, and, in stop mode, the subsystem clock oscillation. * When SSR11 = "0", the system clock oscillation frequency is set to 0.4 to 1 MHz. * When SSR11 = "1", the system clock oscillation frequency is set to 1.6 to 5 MHz. Note: Applicable only to H4369 DCR0 Data Control Register R0 Controls the ON/OFF state of the R0 port output buffer. * When DCR03 = "0", the R03 pin output buffer is set OFF and output set to high impedance. * When DCR03 = "1", the R03 pin output buffer is set ON and the value in the corresponding PDR is output. Rev. 1.0, 03/99, page 25 of 209 b. Table 8 describes the internal registers used in the H4889. Table 8 Internal Registers Used in H4889 Register Function RAM Address Setting IE Interrupt Enable Flag 0, $000 1 1, $000 0 2, $002 0 3, $002 0 0, $003 0 1, $003 1 $004 $2 Controls whether interrupts are received by the CPU. RSP * When IE = "0", CPU interrupt reception is disabled. * When IE = "1", CPU interrupt reception is enabled. Reset Stack Pointer Clearing RSP to "0" initializes the stack pointer. IFTB Timer B Interrupt Request Flag Reflects the existence of a timer B interrupt request. IMTB * When IFTB = "0", no timer B interrupt is requested. * When IFTB = "1", a timer B interrupt is requested. Timer B Interrupt Mask This bit masks IFTB. IFTC * When IMTB = "0", IFTB is enabled. * When IMTB = "1", IFTB is masked. Timer C Interrupt Request Flag Reflects the existence of a timer C interrupt request. IMTC * When IFTC = "0", no timer C interrupt is requested. * When IFTC = "1", a timer C interrupt is requested. Timer C Interrupt Mask This bit masks IFTC. SSR * When IMTC = "0", IFTC is enabled. * When IMTC = "1", IFTC is masked. System Clock Selection Register Selects the system clock oscillation frequency, subsystem clock frequency division, the subsystem clock oscillation, and the system clock division ratio for stop mode. * When SSR1 = "0", the system clock oscillation frequency is set to 0.4 to 1.0 MHz. * When SSR1 = "1", the system clock oscillation frequency is set to 1.6 to 4.5 MHz. Rev. 1.0, 03/99, page 26 of 209 Table 8 Internal Registers Used in H4889 (cont) Register Function RAM Address Setting PMR2 Port Mode Register 2 $00A $0 $010 $D $011 $0 $012 $0 $013 $0 $014 $8 $016 $0 $017 $0 Bit 0 switches R10/EVNB pin functions, bit 1 switches R11/EVND pin functions, bit 2 switches R12/BUZZ pin functions, and bit 3 switches R13/TOB pin functions. * TMB1 When PMR2 = $0, R10, R11, R12 and R13 pins are selected. Timer Mode Register B1 TMB13 selects timer B functions, TMB12 to TMB10 select the operating clock. * TMB2 When TMB13 = "1", TMB12 = "1", TMB11 = "0" and TMB10 = "1", timer B has reload timer functions, and the operating clock is set to the system clock divided by 4. Timer Mode Register B2 Selects timer B output mode and EVNB pin input detection edge. TWBL * When TMB22 = "0", timer B output is set to a toggle waveform. * When TMB22 = "1", timer B output is set for PWM output. * When TMB21 = "0" and TMB20 = "0", there is no EVNB pin input edge detection. Timer Write Register BL Sets the lower digit of the TCB reload value. TWBU Timer Write Register BU Sets the upper digit of the TCB reload value. TMC1 Timer Mode Register C1 Selects timer C functions and operating clock. * TWCL When TMC13 = "1", TMC12 = "0", TMC11 = "0", and TMC10 = "0", timer C functions as a reload timer, and the operating clock is set to the system clock divided by 2048. Timer Write Register CL Sets the lower digit of the TCC reload value. TWCU Timer Write Register CU Sets the upper digit of the TCC reload value. Rev. 1.0, 03/99, page 27 of 209 Table 8 Internal Registers Used in H4889 (cont) Register Function RAM Address Setting DCR1 Data Control Register R1 $035 $4 RAM Address Module Controls the ON/OFF state of the R1 port output buffer. * When DCR12 = "0", the R12 pin output buffer is set OFF and the output is set to high impedance. * When DCR12 = "1", the R12 pin output buffer is set ON and the value of the corresponding PDR is output. 4. Description of RAM Table 9 shows the RAM used in this example task. Table 9 Used RAM Label Function AESC Stores the contents of the accumulator during timer B interrupt processing. $040 SPLINT BESC Stores the contents of the B register during timer B interrupt processing. $041 SPLINT PLCNT This counter controls the High/Low output when outputting a pulse from the R03/R12 pin. $090 SPLMN, SPLINT PLONF This flag controls the enabling/disabling of pulse output. 0, $091 SPLMN, SPLINT CNTL Stores the contents of the accumulator used for specifying the address when executing a pattern command. $093 SPLMN CNTU Stores the contents of the B register used for specifying the address when executing a pattern command. $094 SPLMN PCNT This counter controls the number of times a pulse of a given frequency is output. $095 SPLMN AWORK Temporarily stores the contents of the accumulator during processing of the main routine. $097 SPLMN BWORK Temporarily stores the contents of the B register during processing of the main routine. $098 SPLMN Rev. 1.0, 03/99, page 28 of 209 Flow charts 1. H4344/H4318/H4359/H4369 a. Main Routine SPLMN 1 Reset stack pointer Set IE to "1" to enable interrupts Set SSR11 to "1", and set system clock to 1.6 to 5.0 MHz * 4 No Set R0 port PDR to $0, and initialize R0 port Set DCR0 to $8, and set R03 I/O pin to function as R03 output pin Set PMRA to $0 and set R03/TOC dual-function pin to function as R03 I/O pin IFTC = "1"? Yes Clear IFTC to "0" Increment PCNT No PCNT OVF? Initialize PCNT to $F Yes Execute P command from values of CNTL and CNTU, reference the cycle data corresponding to the tone to be output from the data table, store the contents of the accumulator in AWORK and the contents of the B register in BWORK Initialize PLONF to "1" BWORK <= "0"? Set TMC to $8, and set timer C to function as reload timer and TCC input clock to the system clock divided by 2048 Set IMTB to "1" to disable timer B interrupts Initialize PLCNT to $3 Initialize CNTL to $0 Initialize CNTU to $0 No 2 Yes Initialize CNTL to $0 Clear IFTC to "0" Initialize CNTU to $0 Set TMB1 to $D, and set timer B to function as reload timer and TCB input clock to the system clock divided by 4 Set R0 port PDR to $0 and initialize R0 port Clear IMTB to "0" to enable timer B interrupts Set TWCL to $0 and TWCU to $8, setting the TCC reload value to $80 Clear IFTB to "0" Clear IFTC to "0" 1 Note: * Applies only to H4369. Rev. 1.0, 03/99, page 29 of 209 2 BWORK <= $E? No Yes Write the contents of AWORK to TWBL and of BWORK to TWBU to set the TCB reload value Set IMTB to "1" to disable timer B interrupts Clear IFTB to "0" Clear IFTB to "0" Set IMTB to "1" to disable timer B interrupts Execute the P command from the values of CNTL and CNTU, reference the cycle data corresponding to the duration of the note to be output from the data table, store the contents of the accumulator in TWCL and the contents of the B register in TWCU to set the TCC reload value Execute the P command from the values of CNTL and CNTU, reference the PCNT data from the data table, and store the contents of the accumulator in PCNT Increment CNTL Increment CNTU 4 Rev. 1.0, 03/99, page 30 of 209 Set R0 port PDR to $0 b. Timer B Interrupt Processing Routine SPLINT Clear IFTB to "0" Save registers No PLONF = "1"? Yes Output Low from P03 pin PLCNT <= $1? No Yes Output High from P03 pin Output Low from P03 PLCNT = PLCNT + $F PLCNT OVF? Yes No Initialize PLCNT to $3 Restore registers RTNI Rev. 1.0, 03/99, page 31 of 209 2. H4889 a. Main Routine SPLMN 1 Reset stack pointer Set IE to "1" to enable interrupts Set SSR1 to "1", and set system clock to 1.6 to 4.5 MHz 4 No Yes Set R1 port PDR to $0, and initialize R1 port Set DCR1 to $4, and set R12 I/O pin to function as R12 output pin Set PMR2 to $0 and set R12/BUZZ dual-function pin to function as R12 I/O pin IFTC = "1"? Clear IFTC to "0" Increment PCNT No PCNT OVF? Yes Initialize PCNT to $F Execute P command from values of CNTL and CNTU, reference the cycle data corresponding to the tone to be output from the data table, store the contents of the accumulator in AWORK and the contents of the B register in BWORK Initialize PLONF to "1" BWORK <= "0"? Initialize PLCNT to $3 Initialize CNTL to $0 Initialize CNTU to $0 Set TMC1 to $8, and set timer C to function as reload timer and TCC input clock to the system clock divided by 2048 Yes Set IMTB to "1" to disable timer B interrupts Initialize CNTL to $0 Clear IFTC to "0" Initialize CNTU to $0 Set TMB1 to $D, and set timer B to function as reload timer and TCB input clock to the system clock divided by 4 Set R1 port PDR to $0 and initialize R1 port Clear IMTB to "0" to enable timer B interrupts Set TWCL to $0 and TWCU to $8, setting the TCC reload value to $80 Clear IFTB to "0" Clear IFTC to "0" 1 Rev. 1.0, 03/99, page 32 of 209 No 2 2 BWORK <= $E? No Yes Write the contents of AWORK to TWBL and of BWORK to TWBU to set the TCB reload value Set IMTB to "1" to disable timer B interrupts Clear IFTB to "0" Clear IFTB to "0" Set IMTB to "1" to disable timer B interrupts Set R1 port PDR to $0 Execute the P command from the values of CNTL and CNTU, reference the cycle data corresponding to the duration of the note to be output from the data table, store the contents of the accumulator in TWCL and the contents of the B register in TWCU to set the TCC reload value Execute the P command from the values of CNTL and CNTU, reference the PCNT data from the data table, and store the contents of the accumulator in PCNT Increment CNTL Increment CNTU 4 Rev. 1.0, 03/99, page 33 of 209 b. Timer B Interrupt Processing Routine SPLINT Clear IFTB to "0" Save registers No PLONF = "1"? Yes Output Low from P12 pin PLCNT <= $1? No Yes Output High from P12 pin Output Low from P12 PLCNT = PLCNT + $F PLCNT OVF? No Initialize PLCNT to $3 Restore registers RTNI Rev. 1.0, 03/99, page 34 of 209 Yes Program Listing 1. H4344 ************************************************************ * * HMCS400 Series Application Note * * 'Sound Play * - Minuet : J.S.Bach' * * MCU : H4344 * * External Clock : 4MHz * Internal Clock : 1MHz * Sub Clock : 32.768kHz * ************************************************************ * ************************************************************ * Symbol Definition ************************************************************ * IE equ 0,$000 Interrupt Enable Flag RSP equ 1,$000 Reset Stack Pointer IF0 equ 2,$000 INT0 Interrupt Request Flag IM0 equ 3,$000 INT0 Interrupt Mask * IFTB equ 0,$002 Timer B Interrupt Request Flag IMTB equ 1,$002 Timer B Interrupt Mask IFTC equ 2,$002 Timer C Interrupt Request Flag IMTC equ 3,$002 Timer C Interrupt Mask * IFAD equ 0,$003 A/D Converter Interrupt Request Flag IMAD equ 1,$003 A/D Converter Interrupt Mask IFS equ 2,$003 Serial Interrupt Request Flag IMS equ 3,$003 Serial Interrupt Mask * PMRA equ $004 Port Mode Register SMR equ $005 Serial Mode Register SRL equ $006 Serial Data Register L SRU equ $007 Serial Data Register U * TMB1 equ $009 Timer Mode Register B1 TRBL equ $00A Timer Read Register BL TWBL equ $00A Timer Write Register BL TRBU equ $00B Timer Read Register BU TWBU equ $00B Timer Write Register BU MIS equ $00C Miscellaneous Register TMC equ $00D Timer Mode Register C TRCL equ $00E Timer Read Register CL Rev. 1.0, 03/99, page 35 of 209 TWCL equ $00E Timer Write Register CL TRCU equ $00F Timer Read Register CU TWCU equ $00F Timer Write Register CU ACR equ $016 A/D Channel Register ADRL equ $017 A/D Data Register L ADRU equ $018 A/D Data Register U AMR1 equ $019 A/D Mode Register 1 AMR2 equ $01A A/D Mode Register 2 * WDON equ 1,$020 Watchdog on Flag ADSF equ 2,$020 A/D Start Flag * IAOF equ 2,$021 IAD off Flag RAME equ 3,$021 RAM Enable Flag * PMRB equ $024 Port Mode Register B PMRC equ $025 Port Mode Register C TMB2 equ $026 Timer Mode Register B2 * DCD0 equ $02C D Port Data Control Register 0 DCD1 equ $02D D Port Data Control Register 1 * DCR0 equ $030 R Port Data Control Register 0 DCR1 equ $031 R Port Data Control Register 1 DCR2 equ $032 R Port Data Control Register 2 DCR3 equ $033 R Port Data Control Register 3 * ************************************************************ * RAM ALLOCATION ************************************************************ * AESC equ $040 Accumulator Escape BESC equ $041 B Register Escape * PLCNT equ $090 Pulse Counter * PLFLG1 equ $091 Pulse Flag 1 PLONF equ 0,PLFLG1 Pulse Output Enable Flag * CNTL equ $093 Lower Counter CNTU equ $094 Upper Counter PCNT equ $095 Period Counter AWORK equ $096 Accumulator Work RAM Area BWORK equ $097 B Register Work RAM Area * ************************************************************ * Vector Address ************************************************************ * org $0000 * Rev. 1.0, 03/99, page 36 of 209 JMPL JMPL SPLMN SPLMN org $0008 JMPL JMPL JMPL JMPL SPLINT SPLMN SPLMN SPLMN Reset Interrupt INT0 Interrupt * * Timer B Interrupt Timer C Interrupt A/D Converter Interrupt Serial Interrupt * ************************************************************ * Main Program ************************************************************ * org $1000 * SPLMN REMD RSP Reset Stack Pointer * LAI 0 LRA 0 Initialize R0 Port PDR LMID 8,DCR0 Initialize R03 Output Terminal Function LMID 0,PMRA Initialize R03 Input/Output Terminal Function * LMID 3,PLCNT Initialize Pulse Counter LMID 0,CNTL Initialize Lower Counter LMID 0,CNTU Initialize Upper Counter LMID $F,PCNT Initialize Period Counter SEMD PLONF Initialize Pulse Output Enable Flag * LMID 8,TMC Initialize Timer C Function & Input Clock Period REMD IFTC Clear IFTC to 0 * LMID $D,TMB1 Initialize Timer B Function & Input Clock Period LMID 0,TMB2 Initialize Timer B Function * SEMD IMTB Timer B Interrupt Disable REMD IFTB Clear IFTB to 0 * SEMD IE All Interrupt Enable * SPLMN00 TMD IFTC IFTC = "1" ? BRS SPLMN10 Yes. Branch to SPLMN10 BRS SPLMN00 No. Branch to SPLMN00 * REMD IFTC Clear IFTC to 0 LMID 9,TWCL Set TCC Reload Value Lower LMID 0,TWCU Set TCC Reload Value Upper * SPLMN05 TMD IFTC IFTC = "1" ? BRS SPLMN10 Yes. Branch to SPLMN10 SEMD IMTB Timer B Interrupt Disable Rev. 1.0, 03/99, page 37 of 209 * SPLMN10 * SPLMN40 * SPLMN20 * SPLMN30 REMD LAI LRA BRS IFTB 0 0 SPLMN05 Clear IFTB to 0 REMD LAMD AI BRS LMAD BRS IFTC PCNT 1 SPLMN40 PCNT SPLMN00 Clear IFTC to 0 Load PCNT Increment PCNT PCNT Overflow ? Yes. Branch to SPLMN40 No. Save PCNT Branch to SPLMN00 LAMD LBA LAMD P LMAD LAB LMAD ALEI BRS ALEI BRS SEMD REMD LAI LRA BRS CNTU Load CNTL CNTL 2 AWORK Load CNTU Scale Data Pattern Generation Save Scale Lower Data BWORK 0 SPLMN90 $E SPLMN20 IMTB IFTB 0 0 SPLMN30 Save Scale Upper Data Scale Upper Data <= $0 ? End Sound Play ? Yes. Branch to SPLMN90 Scale Upper Data <= $E ? Yes. Branch to SPLMN20 Timer B Interrupt Disable Clear IFTB to 0 LAMD LMAD LAMD LMAD REMD REMD AWORK TWBL BWORK TWBU IFTB IMTB Load AWORK Set TCB Reload Value Lower to Scale Data Load BWORK Set TCB Reload Value Upper to Scale Data Clear IFTB to 0 Timer B Interrupt Enable LAMD LBA LAMD P LMAD LAB LMAD CNTU Load Upper Counter CNTL 3 TWCL Load Lower Counter Time Period Data Pattern Generation Set TCC Reload Value Lower to Time Period Lower Data TWCU Set TCC Reload Value Upper to Time Period Upper Data LAMD LBA LAMD P LMAD CNTU Load Upper Counter CNTL 4 PCNT Load Lower Counter Time Counter Data Pattern Generation Set PCNT to Time Counter Data Sound off Branch to SPLMN05 R03 Output Terminal is "Low" Output Branch to SPLMN30 * * SEC Rev. 1.0, 03/99, page 38 of 209 Set Carry Flag at 1 * SPLMN90 LAI AMCD LMAD LAI AMCD LMAD BR BRS 0 CNTL CNTL 0 CNTU CNTU *+1 SPLMN00 SEMD LMID LMID LAI LRA LMID LMID REMD BRS IMTB 0,CNTL 0,CNTU 0 0 0,TWCL 8,TWCU IFTC SPLMN00 Increment Lower Counter Save Lower Counter If CNTL Overflow, Increment Upper Counter Save Upper Counter Branch to SPLMN00 Timer B Interrupt Disable Initialize Lower Counter Initialize Upper Counter Initialize R0 Port PDR Initialize TCC Reload Value Lower Initialize TCC Reload Value Upper Clear IFTC to 0 Branch to SPLMN00 * ************************************************************ * Timer B Interrupt Process * ---Pulse Output Routine--************************************************************ * SPLINT REMD IFTB Clear IFTB to 0 * LMAD AESC Store Accumulator LAB LMAD BESC Store B Register * TMD PLONF Pulse Enable Flag = "1" ? BRS PLI00 Yes. Branch to PLI00 LAI 0 No. Stop Output Pulse LRA 0 R03 Output Terminal is "Low" Output BRS PLI99 Branch to PLI99 * PLI00 LAMD PLCNT Load Pulse Counter Value LBA Store Pulse Counter Value ALEI 1 PLCNT <= $1 ? Is R03 Output Terminal "High" Output ? BRS PLI10 Yes. Branch to PLI10 LAI 0 No. R03 Output Terminal is "Low" Output BRS PLI20 Branch to PLI20 PLI10 LAI 8 PLI20 LRA 0 R03 Output Terminal is "High" Output LAB Restore Pulse Counter Value AI $F PLCNT + $F <= $F ? Pulse Counter = $0 ? BRS PLI30 No. Branch to PLI30 LAI 3 Yes. Pulse Counter Initialize PLI30 LMAD PLCNT Save Pulse Counter Value * PLI99 LAMD BESC Restore B Register Rev. 1.0, 03/99, page 39 of 209 LBA LAMD AESC Restore Accumulator * RTNI Return from Interrupt * ************************************************************ * Scale Data ************************************************************ * ORG $0200 * *** 1st Cycle * dc $1AB 'G' Data. TCB Reload Value = $AB dc $17F 'C' Data. TCB Reload Value = $7F dc $18E 'D' Data. TCB Reload Value = $8E dc $19B 'E' Data. TCB Reload Value = $9B dc $1A1 'F' Data. TCB Reload Value = $A1 * dc $1AB 'G' Data. TCB Reload Value = $AB dc $17F 'C' Data. TCB Reload Value = $7F dc $1FF ' ' Data. TCB Reload Value = $FF dc $17F 'C' Data. TCB Reload Value = $7F * dc $1B4 'A' Data. TCB Reload Value = $B4 dc $1A1 'F' Data. TCB Reload Value = $A1 dc $1AB 'G' Data. TCB Reload Value = $AB dc $1B4 'A' Data. TCB Reload Value = $B4 dc $1BD 'B' Data. TCB Reload Value = $BD * dc $1C1 'C' Data. TCB Reload Value = $C1 dc $17F 'C' Data. TCB Reload Value = $7F dc $1FF ' ' Data. TCB Reload Value = $FF dc $17F 'C' Data. TCB Reload Value = $7F * dc $1A1 'F' Data. TCB Reload Value = $A1 dc $1AB 'G' Data. TCB Reload Value = $AB dc $1A1 'F' Data. TCB Reload Value = $A1 dc $19B 'E' Data. TCB Reload Value = $9B dc $18E 'D' Data. TCB Reload Value = $8E * dc $19B 'E' Data. TCB Reload Value = $9B dc $1A1 'F' Data. TCB Reload Value = $A1 dc $19B 'E' Data. TCB Reload Value = $9B dc $18E 'D' Data. TCB Reload Value = $8E dc $17F 'C' Data. TCB Reload Value = $7F * dc $17A 'B' Data. TCB Reload Value = $7A dc $17F 'C' Data. TCB Reload Value = $7F dc $18E 'D' Data. TCB Reload Value = $8E dc $19B 'E' Data. TCB Reload Value = $9B Rev. 1.0, 03/99, page 40 of 209 dc $17F 'C' Data. TCB Reload Value = $7F $18E 'D' Data. TCB Reload Value = $8E $1AB $17F $18E $19B $1A1 'G' 'C' 'D' 'E' 'F' Data. Data. Data. Data. Data. TCB TCB TCB TCB TCB Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $AB $7F $8E $9B $A1 $1AB $17F $1FF $17F 'G' 'C' ' ' 'C' Data. Data. Data. Data. TCB TCB TCB TCB Reload Reload Reload Reload Value Value Value Value = = = = $AB $7F $FF $7F $1B4 $1A1 $1AB $1B4 $1BD 'A' 'F' 'G' 'A' 'B' Data. Data. Data. Data. Data. TCB TCB TCB TCB TCB Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $B4 $A1 $AB $B4 $BD $1C1 $17F $1FF $17F 'C' 'C' ' ' 'C' Data. Data. Data. Data. TCB TCB TCB TCB Reload Reload Reload Reload Value Value Value Value = = = = $C1 $7F $FF $7F $1A1 $1AB $1A1 $19B $18E 'F' 'G' 'F' 'E' 'D' Data. Data. Data. Data. Data. TCB TCB TCB TCB TCB Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $A1 $AB $A1 $9B $8E $19B $1A1 $19B $18E $17F 'E' 'F' 'E' 'D' 'C' Data. Data. Data. Data. Data. TCB TCB TCB TCB TCB Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $9B $A1 $9B $8E $7F $18E $19B $18E $17F $17A 'D' 'E' 'D' 'C' 'B' Data. Data. Data. Data. Data. TCB TCB TCB TCB TCB Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $8E $9B $8E $7F $7A $17F $1FF 'C' Data. TCB Reload Value = $7F ' ' Data. TCB Reload Value = $FF $100 ' ' Data. TCB Reload Value = $00 * dc * *** 2nd Cycle * dc dc dc dc dc * dc dc dc dc * dc dc dc dc dc * dc dc dc dc * dc dc dc dc dc * dc dc dc dc dc * dc dc dc dc dc * dc dc * dc * Rev. 1.0, 03/99, page 41 of 209 ************************************************************ * Time Period Data ************************************************************ * org $0300 * *** 1st Cycle * dc $138 'G' Time Period Data. TCC Reload Value dc $19C 'C' Time Period Data. TCC Reload Value dc $19C 'D' Time Period Data. TCC Reload Value dc $19C 'E' Time Period Data. TCC Reload Value dc $19C 'F' Time Period Data. TCC Reload Value * dc $138 'G' Time Period Data. TCC Reload Value dc $16A 'C' Time Period Data. TCC Reload Value dc $1CE ' ' Time Period Data. TCC Reload Value dc $138 'C' Time Period Data. TCC Reload Value * dc $138 'A' Time Period Data. TCC Reload Value dc $19C 'F' Time Period Data. TCC Reload Value dc $19C 'G' Time Period Data. TCC Reload Value dc $19C 'A' Time Period Data. TCC Reload Value dc $19C 'B' Time Period Data. TCC Reload Value * dc $138 'C' Time Period Data. TCC Reload Value dc $16A 'C' Time Period Data. TCC Reload Value dc $1CE ' ' Time Period Data. TCC Reload Value dc $138 'C' Time Period Data. TCC Reload Value * dc $138 'F' Time Period Data. TCC Reload Value dc $19C 'G' Time Period Data. TCC Reload Value dc $19C 'F' Time Period Data. TCC Reload Value dc $19C 'E' Time Period Data. TCC Reload Value dc $19C 'D' Time Period Data. TCC Reload Value * dc $138 'E' Time Period Data. TCC Reload Value dc $19C 'F' Time Period Data. TCC Reload Value dc $19C 'E' Time Period Data. TCC Reload Value dc $19C 'D' Time Period Data. TCC Reload Value dc $19C 'C' Time Period Data. TCC Reload Value * dc $138 'B' Time Period Data. TCC Reload Value dc $19C 'C' Time Period Data. TCC Reload Value dc $19C 'D' Time Period Data. TCC Reload Value dc $19C 'E' Time Period Data. TCC Reload Value dc $19C 'C' Time Period Data. TCC Reload Value * dc $138 'D' Time Period Data. TCC Reload Value * *** 2nd Cycle Rev. 1.0, 03/99, page 42 of 209 = = = = = $38 $9C $9C $9C $9C = = = = $38 $6A $CE $38 = = = = = $38 $9C $9C $9C $9C = = = = $38 $6A $CE $38 = = = = = $38 $9C $9C $9C $9C = = = = = $38 $9C $9C $9C $9C = = = = = $38 $9C $9C $9C $9C = $38 * dc dc dc dc dc $138 $19C $19C $19C $19C 'G' 'C' 'D' 'E' 'F' Time Time Time Time Time Period Period Period Period Period Data. Data. Data. Data. Data. TCC TCC TCC TCC TCC Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $38 $9C $9C $9C $9C dc dc dc dc $138 $16A $1CE $138 'G' 'C' ' ' 'C' Time Time Time Time Period Period Period Period Data. Data. Data. Data. TCC TCC TCC TCC Reload Reload Reload Reload Value Value Value Value = = = = $38 $6A $CE $38 dc dc dc dc dc $138 $19C $19C $19C $19C 'A' 'F' 'G' 'A' 'B' Time Time Time Time Time Period Period Period Period Period Data. Data. Data. Data. Data. TCC TCC TCC TCC TCC Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $38 $9C $9C $9C $9C dc dc dc dc $138 $16A $1CE $138 'C' 'C' ' ' 'C' Time Time Time Time Period Period Period Period Data. Data. Data. Data. TCC TCC TCC TCC Reload Reload Reload Reload Value Value Value Value = = = = $38 $6A $CE $38 dc dc dc dc dc $138 $19C $19C $19C $19C 'F' 'G' 'F' 'E' 'D' Time Time Time Time Time Period Period Period Period Period Data. Data. Data. Data. Data. TCC TCC TCC TCC TCC Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $38 $9C $9C $9C $9C dc dc dc dc dc $138 $19C $19C $19C $19C 'E' 'F' 'E' 'D' 'C' Time Time Time Time Time Period Period Period Period Period Data. Data. Data. Data. Data. TCC TCC TCC TCC TCC Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $38 $9C $9C $9C $9C dc dc dc dc dc $138 $19C $19C $19C $19C 'D' 'E' 'D' 'C' 'B' Time Time Time Time Time Period Period Period Period Period Data. Data. Data. Data. Data. TCC TCC TCC TCC TCC Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $38 $9C $9C $9C $9C dc dc $138 $138 'C' Time Period Data. TCC Reload Value = $38 ' ' Time Period Data. TCC Reload Value = $38 * * * * * * * * ************************************************************ * Times Counter Data ************************************************************ * org $0400 * *** 1st Cycle Rev. 1.0, 03/99, page 43 of 209 * dc dc dc dc dc $10F $10F $10F $10F $10F 'G' 'C' 'D' 'E' 'F' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F dc dc dc dc $10F $10F $10F $10F 'G' 'C' ' ' 'C' Time Time Time Time Counter Counter Counter Counter Data. Data. Data. Data. PCNT PCNT PCNT PCNT = = = = $F $F $F $F dc dc dc dc dc $10F $10F $10F $10F $10F 'A' 'F' 'G' 'A' 'B' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F dc dc dc dc $10F $10F $10F $10F 'C' 'C' ' ' 'C' Time Time Time Time Counter Counter Counter Counter Data. Data. Data. Data. PCNT PCNT PCNT PCNT = = = = $F $F $F $F dc dc dc dc dc $10F $10F $10F $10F $10F 'F' 'G' 'F' 'E' 'D' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F dc dc dc dc dc $10F $10F $10F $10F $10F 'E' 'F' 'E' 'D' 'C' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F dc dc dc dc dc $10F $10F $10F $10F $10F 'B' 'C' 'D' 'E' 'C' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F $10D 'D' Time Counter Data. PCNT = $D $10F $10F $10F $10F $10F 'G' 'C' 'D' 'E' 'F' * * * * * * * dc * *** 2nd Cycle * dc dc dc dc dc * Rev. 1.0, 03/99, page 44 of 209 Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F dc dc dc dc $10F $10F $10F $10F 'G' 'C' ' ' 'C' Time Time Time Time Counter Counter Counter Counter Data. Data. Data. Data. PCNT PCNT PCNT PCNT = = = = $F $F $F $F dc dc dc dc dc $10F $10F $10F $10F $10F 'A' 'F' 'G' 'A' 'B' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F dc dc dc dc $10F $10F $10F $10F 'C' 'C' ' ' 'C' Time Time Time Time Counter Counter Counter Counter Data. Data. Data. Data. PCNT PCNT PCNT PCNT = = = = $F $F $F $F dc dc dc dc dc $10F $10F $10F $10F $10F 'F' 'G' 'F' 'E' 'D' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F dc dc dc dc dc $10F $10F $10F $10F $10F 'E' 'F' 'E' 'D' 'C' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F dc dc dc dc dc $10F $10F $10F $10F $10F 'D' 'E' 'D' 'C' 'B' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F dc dc dc $10F $10F $10F 'F' Time Counter Data. PCNT = $F 'E' Time Counter Data. PCNT = $F 'D' Time Counter Data. PCNT = $F dc dc dc dc dc $10F $10F $10F $10F $10F 'E' 'F' 'E' 'D' 'C' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F dc dc dc dc dc $10F $10F $10F $10F $10F 'B' 'C' 'D' 'E' 'C' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F dc $10D 'D' Time Counter Data. PCNT = $D * * * * * * * * * Rev. 1.0, 03/99, page 45 of 209 *** 2nd Cycle dc dc dc dc dc * dc dc dc dc * dc dc dc dc dc * dc dc dc dc * dc dc dc dc dc * dc dc dc dc dc * dc dc dc dc dc * dc dc end $10F $10F $10F $10F $10F 'G' 'C' 'D' 'E' 'F' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F $10F $10F $10F $10F 'G' 'C' ' ' 'C' Time Time Time Time Counter Counter Counter Counter Data. Data. Data. Data. PCNT PCNT PCNT PCNT = = = = $F $F $F $F $10F $10F $10F $10F $10F 'A' 'F' 'G' 'A' 'B' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F $10F $10F $10F $10F 'C' 'C' ' ' 'C' Time Time Time Time Counter Counter Counter Counter Data. Data. Data. Data. PCNT PCNT PCNT PCNT = = = = $F $F $F $F $10F $10F $10F $10F $10F 'F' 'G' 'F' 'E' 'D' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F $10F $10F $10F $10F $10F 'E' 'F' 'E' 'D' 'C' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F $10F $10F $10F $10F $10F 'D' 'E' 'D' 'C' 'B' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F $10E $10F 'C' Time Counter Data. PCNT = $E ' ' Time Counter Data. PCNT = $F Rev. 1.0, 03/99, page 46 of 209 2. H4318/H4359 ************************************************************ * * HMCS400 Series Application Note * * 'Sound Play * - Minuet : J.S.Bach' * * MCU : H4318/H4359 * * External Clock : 4MHz * Internal Clock : 1MHz * Sub Clock : 32.768kHz * ************************************************************ * ************************************************************ * Symbol Definition ************************************************************ * IE equ 0,$000 Interrupt Enable Flag RSP equ 1,$000 Reset Stack Pointer IF0 equ 2,$000 INT0 Interrupt Request Flag IM0 equ 3,$000 INT0 Interrupt Mask * IF1 equ 0,$001 INT1 Interrupt Request Flag IM1 equ 1,$001 INT1 Interrupt Mask IFTA equ 2,$001 Timer A Interrupt Request Flag IMTA equ 3,$001 Timer A Interrupt Mask * IFTB equ 0,$002 Timer B Interrupt Request Flag IMTB equ 1,$002 Timer B Interrupt Mask IFTC equ 2,$002 Timer C Interrupt Request Flag IMTC equ 3,$002 Timer C Interrupt Mask * IFAD equ 0,$003 A/D Converter Interrupt Request Flag IMAD equ 1,$003 A/D Converter Interrupt Mask IFS equ 2,$003 Serial Interrupt Request Flag IMS equ 3,$003 Serial Interrupt Mask * PMRA equ $004 Port Mode Register SMR equ $005 Serial Mode Register SRL equ $006 Serial Data Register L SRU equ $007 Serial Data Register U TMA equ $008 Timer Mode Register A TMB1 equ $009 Timer Mode Register B1 TRBL equ $00A Timer Read Register BL TWBL equ $00A Timer Write Register BL TRBU equ $00B Timer Read Register BU TWBU equ $00B Timer Write Register BU Rev. 1.0, 03/99, page 47 of 209 MIS equ $00C Miscellaneous Register TMC equ $00D Timer Mode Register C TRCL equ $00E Timer Read Register CL TWCL equ $00E Timer Write Register CL TRCU equ $00F Timer Read Register CU TWCU equ $00F Timer Write Register CU ACR equ $016 A/D Channel Register ADRL equ $017 A/D Data Register L ADRU equ $018 A/D Data Register U AMR1 equ $019 A/D Mode Register 1 AMR2 equ $01A A/D Mode Register 2 * WDON equ 1,$020 Watchdog on Flag ADSF equ 2,$020 A/D Start Flag * ICSF equ 0,$021 Input Capture Status Flag ICEF equ 1,$021 Input Capture Error Flag IAOF equ 2,$021 IAD off Flag RAME equ 3,$021 RAM Enable Flag * PMRB equ $024 Port Mode Register B PMRC equ $025 Port Mode Register C TMB2 equ $026 Timer Mode Register B2 DCD0 equ $02C D Port Data Control Register 0 DCD1 equ $02D D Port Data Control Register 1 DCD2 equ $02E D Port Data Control Register 2 DCR0 equ $030 R Port Data Control Register 0 DCR1 equ $031 R Port Data Control Register 1 DCR2 equ $032 R Port Data Control Register 2 DCR3 equ $033 R Port Data Control Register 3 DCR4 equ $034 R Port Data Control Register 4 DCR8 equ $038 R Port Data Control Register 8 * ************************************************************ * RAM ALLOCATION ************************************************************ * AESC equ $040 Accumulator Escape BESC equ $041 B Register Escape * PLCNT equ $090 Pulse Counter * PLFLG1 equ $091 Pulse Flag 1 PLONF equ 0,PLFLG1 Pulse Output Enable Flag * CNTL equ $093 Lower Counter CNTU equ $094 Upper Counter PCNT equ $095 Period Counter AWORK equ $096 Accumulator Work RAM Area BWORK equ $097 B Register Work RAM Area * Rev. 1.0, 03/99, page 48 of 209 ************************************************************ * Vector Address ************************************************************ * org $0000 * JMPL SPLMN Reset Interrupt JMPL SPLMN INT0 Interrupt JMPL SPLMN INT1 Interrupt JMPL SPLMN Timer A Interrupt JMPL SPLINT Timer B Interrupt JMPL SPLMN Timer C Interrupt JMPL SPLMN A/D Converter Interrupt JMPL SPLMN Serial Interrupt * ************************************************************ * Main Program ************************************************************ * org $1000 * SPLMN REMD RSP Reset Stack Pointer * LAI 0 LRA 0 Initialize R0 Port PDR LMID 8,DCR0 Initialize R03 Output Terminal Function LMID 0,PMRA Initialize R03 Input/Output Terminal Function * LMID 3,PLCNT Initialize Pulse Counter LMID 0,CNTL Initialize Lower Counter LMID 0,CNTU Initialize Upper Counter LMID $F,PCNT Initialize Period Counter SEMD PLONF Initialize Pulse Output Enable Flag * LMID 8,TMC Initialize Timer C Function & Input Clock Period REMD IFTC Clear IFTC to 0 * LMID $D,TMB1 Initialize Timer B Function & Input Clock Period LMID 0,TMB2 Initialize Timer B Function * SEMD IMTB Timer B Interrupt Disable REMD IFTB Clear IFTB to 0 * SEMD IE All Interrupt Enable * SPLMN00 TMD IFTC IFTC = "1" ? BRS SPLMN10 Yes. Branch to SPLMN10 BRS SPLMN00 No. Branch to SPLMN00 * REMD IFTC Clear IFTC to 0 LMID 9,TWCL Set TCC Reload Value Lower Rev. 1.0, 03/99, page 49 of 209 * SPLMN05 * SPLMN10 * SPLMN40 * SPLMN20 * SPLMN30 LMID 0,TWCU Set TCC Reload Value Upper TMD BRS SEMD REMD LAI LRA BRS IFTC SPLMN10 IMTB IFTB 0 0 SPLMN05 IFTC = "1" ? Yes. Branch to SPLMN10 Timer B Interrupt Disable Clear IFTB to 0 REMD LAMD AI BRS LMAD BRS IFTC PCNT 1 SPLMN40 PCNT SPLMN00 Clear IFTC to 0 Load PCNT Increment PCNT PCNT Overflow ? Yes. Branch to SPLMN40 No. Save PCNT Branch to SPLMN00 LAMD LBA LAMD P LMAD LAB LMAD ALEI BRS ALEI BRS SEMD REMD LAI LRA BRS CNTU Load CNTL CNTL 2 AWORK Load CNTU Scale Data Pattern Generation Save Scale Lower Data BWORK 0 SPLMN90 $E SPLMN20 IMTB IFTB 0 0 SPLMN30 Save Scale Upper Data Scale Upper Data <= $0 ? End Sound Play ? Yes. Branch to SPLMN90 Scale Upper Data <= $E ? Yes. Branch to SPLMN20 Timer B Interrupt Disable Clear IFTB to 0 LAMD LMAD LAMD LMAD REMD REMD AWORK TWBL BWORK TWBU IFTB IMTB Load AWORK Set TCB Reload Value Lower to Scale Data Load BWORK Set TCB Reload Value Upper to Scale Data Clear IFTB to 0 Timer B Interrupt Enable LAMD LBA LAMD P LMAD LAB LMAD CNTU Load Upper Counter CNTL 3 TWCL Load Lower Counter Time Period Data Pattern Generation Set TCC Reload Value Lower to Time Period Lower Data TWCU Set TCC Reload Value Upper to Time Period Upper Data LAMD LBA CNTU Load Upper Counter Sound off Branch to SPLMN05 R03 Output Terminal is "Low" Output Branch to SPLMN30 * Rev. 1.0, 03/99, page 50 of 209 LAMD P LMAD CNTL 4 PCNT SEC LAI AMCD LMAD LAI AMCD LMAD BR BRS 0 CNTL CNTL 0 CNTU CNTU *+1 SPLMN00 SEMD LMID LMID LAI LRA LMID LMID REMD BRS IMTB 0,CNTL 0,CNTU 0 0 0,TWCL 8,TWCU IFTC SPLMN00 Load Lower Counter Time Counter Data Pattern Generation Set PCNT to Time Counter Data * * SPLMN90 Set Carry Flag at 1 Increment Lower Counter Save Lower Counter If CNTL Overflow, Increment Upper Counter Save Upper Counter Branch to SPLMN00 Timer B Interrupt Disable Initialize Lower Counter Initialize Upper Counter Initialize R0 Port PDR Initialize TCC Reload Value Lower Initialize TCC Reload Value Upper Clear IFTC to 0 Branch to SPLMN00 * ************************************************************ * Timer B Interrupt Process * ---Pulse Output Routine--************************************************************ * SPLINT REMD IFTB Clear IFTB to 0 * LMAD AESC Store Accumulator LAB LMAD BESC Store B Register * TMD PLONF Pulse Enable Flag = "1" ? BRS PLI00 Yes. Branch to PLI00 LAI 0 No. Stop Output Pulse LRA 0 R03 Output Terminal is "Low" Output BRS PLI99 Branch to PLI99 * PLI00 LAMD PLCNT Load Pulse Counter Value LBA Store Pulse Counter Value ALEI 1 PLCNT <= $1 ? Is R03 Output Terminal "High" Output ? BRS PLI10 Yes. Branch to PLI10 LAI 0 No. R03 Output Terminal is "Low" Output BRS PLI20 Branch to PLI20 PLI10 LAI 8 PLI20 LRA 0 R03 Output Terminal is "High" Output LAB Restore Pulse Counter Value AI $F PLCNT + $F <= $F ? Pulse Counter = $0 ? Rev. 1.0, 03/99, page 51 of 209 PLI30 * PLI99 BRS LAI LMAD PLI30 3 PLCNT No. Branch to PLI30 Yes. Pulse Counter Initialize Save Pulse Counter Value LAMD LBA LAMD BESC Restore B Register AESC Restore Accumulator * RTNI Return from Interrupt * ************************************************************ * Scale Data ************************************************************ * ORG $0200 * *** 1st Cycle * dc $1AB 'G' Data. TCB Reload Value = $AB dc $17F 'C' Data. TCB Reload Value = $7F dc $18E 'D' Data. TCB Reload Value = $8E dc $19B 'E' Data. TCB Reload Value = $9B dc $1A1 'F' Data. TCB Reload Value = $A1 * dc $1AB 'G' Data. TCB Reload Value = $AB dc $17F 'C' Data. TCB Reload Value = $7F dc $1FF ' ' Data. TCB Reload Value = $FF dc $17F 'C' Data. TCB Reload Value = $7F * dc $1B4 'A' Data. TCB Reload Value = $B4 dc $1A1 'F' Data. TCB Reload Value = $A1 dc $1AB 'G' Data. TCB Reload Value = $AB dc $1B4 'A' Data. TCB Reload Value = $B4 dc $1BD 'B' Data. TCB Reload Value = $BD * dc $1C1 'C' Data. TCB Reload Value = $C1 dc $17F 'C' Data. TCB Reload Value = $7F dc $1FF ' ' Data. TCB Reload Value = $FF dc $17F 'C' Data. TCB Reload Value = $7F * dc $1A1 'F' Data. TCB Reload Value = $A1 dc $1AB 'G' Data. TCB Reload Value = $AB dc $1A1 'F' Data. TCB Reload Value = $A1 dc $19B 'E' Data. TCB Reload Value = $9B dc $18E 'D' Data. TCB Reload Value = $8E * dc $19B 'E' Data. TCB Reload Value = $9B dc $1A1 'F' Data. TCB Reload Value = $A1 dc $19B 'E' Data. TCB Reload Value = $9B dc $18E 'D' Data. TCB Reload Value = $8E dc $17F 'C' Data. TCB Reload Value = $7F Rev. 1.0, 03/99, page 52 of 209 * dc dc dc dc dc $17A $17F $18E $19B $17F 'B' 'C' 'D' 'E' 'C' Data. Data. Data. Data. Data. TCB TCB TCB TCB TCB Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $7A $7F $8E $9B $7F $18E 'D' Data. TCB Reload Value = $8E $1AB $17F $18E $19B $1A1 'G' 'C' 'D' 'E' 'F' Data. Data. Data. Data. Data. TCB TCB TCB TCB TCB Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $AB $7F $8E $9B $A1 $1AB $17F $1FF $17F 'G' 'C' ' ' 'C' Data. Data. Data. Data. TCB TCB TCB TCB Reload Reload Reload Reload Value Value Value Value = = = = $AB $7F $FF $7F $1B4 $1A1 $1AB $1B4 $1BD 'A' 'F' 'G' 'A' 'B' Data. Data. Data. Data. Data. TCB TCB TCB TCB TCB Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $B4 $A1 $AB $B4 $BD $1C1 $17F $1FF $17F 'C' 'C' ' ' 'C' Data. Data. Data. Data. TCB TCB TCB TCB Reload Reload Reload Reload Value Value Value Value = = = = $C1 $7F $FF $7F $1A1 $1AB $1A1 $19B $18E 'F' 'G' 'F' 'E' 'D' Data. Data. Data. Data. Data. TCB TCB TCB TCB TCB Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $A1 $AB $A1 $9B $8E $19B $1A1 $19B $18E $17F 'E' 'F' 'E' 'D' 'C' Data. Data. Data. Data. Data. TCB TCB TCB TCB TCB Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $9B $A1 $9B $8E $7F $18E $19B $18E $17F $17A 'D' 'E' 'D' 'C' 'B' Data. Data. Data. Data. Data. TCB TCB TCB TCB TCB Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $8E $9B $8E $7F $7A * dc * *** 2nd Cycle * dc dc dc dc dc * dc dc dc dc * dc dc dc dc dc * dc dc dc dc * dc dc dc dc dc * dc dc dc dc dc * dc dc dc dc dc * Rev. 1.0, 03/99, page 53 of 209 dc dc $17F $1FF 'C' Data. TCB Reload Value = $7F ' ' Data. TCB Reload Value = $FF * dc $100 ' ' Data. TCB Reload Value = $00 * ************************************************************ * Time Period Data ************************************************************ * org $0300 * *** 1st Cycle * dc $138 'G' Time Period Data. TCC Reload Value dc $19C 'C' Time Period Data. TCC Reload Value dc $19C 'D' Time Period Data. TCC Reload Value dc $19C 'E' Time Period Data. TCC Reload Value dc $19C 'F' Time Period Data. TCC Reload Value * dc $138 'G' Time Period Data. TCC Reload Value dc $16A 'C' Time Period Data. TCC Reload Value dc $1CE ' ' Time Period Data. TCC Reload Value dc $138 'C' Time Period Data. TCC Reload Value * dc $138 'A' Time Period Data. TCC Reload Value dc $19C 'F' Time Period Data. TCC Reload Value dc $19C 'G' Time Period Data. TCC Reload Value dc $19C 'A' Time Period Data. TCC Reload Value dc $19C 'B' Time Period Data. TCC Reload Value * dc $138 'C' Time Period Data. TCC Reload Value dc $16A 'C' Time Period Data. TCC Reload Value dc $1CE ' ' Time Period Data. TCC Reload Value dc $138 'C' Time Period Data. TCC Reload Value * dc $138 'F' Time Period Data. TCC Reload Value dc $19C 'G' Time Period Data. TCC Reload Value dc $19C 'F' Time Period Data. TCC Reload Value dc $19C 'E' Time Period Data. TCC Reload Value dc $19C 'D' Time Period Data. TCC Reload Value * dc $138 'E' Time Period Data. TCC Reload Value dc $19C 'F' Time Period Data. TCC Reload Value dc $19C 'E' Time Period Data. TCC Reload Value dc $19C 'D' Time Period Data. TCC Reload Value dc $19C 'C' Time Period Data. TCC Reload Value * dc $138 'B' Time Period Data. TCC Reload Value dc $19C 'C' Time Period Data. TCC Reload Value dc $19C 'D' Time Period Data. TCC Reload Value dc $19C 'E' Time Period Data. TCC Reload Value Rev. 1.0, 03/99, page 54 of 209 = = = = = $38 $9C $9C $9C $9C = = = = $38 $6A $CE $38 = = = = = $38 $9C $9C $9C $9C = = = = $38 $6A $CE $38 = = = = = $38 $9C $9C $9C $9C = = = = = $38 $9C $9C $9C $9C = = = = $38 $9C $9C $9C dc $19C 'C' Time Period Data. TCC Reload Value = $9C * dc $138 'D' Time Period Data. TCC Reload Value * *** 2nd Cycle * dc $138 'G' Time Period Data. TCC Reload Value dc $19C 'C' Time Period Data. TCC Reload Value dc $19C 'D' Time Period Data. TCC Reload Value dc $19C 'E' Time Period Data. TCC Reload Value dc $19C 'F' Time Period Data. TCC Reload Value * dc $138 'G' Time Period Data. TCC Reload Value dc $16A 'C' Time Period Data. TCC Reload Value dc $1CE ' ' Time Period Data. TCC Reload Value dc $138 'C' Time Period Data. TCC Reload Value * dc $138 'A' Time Period Data. TCC Reload Value dc $19C 'F' Time Period Data. TCC Reload Value dc $19C 'G' Time Period Data. TCC Reload Value dc $19C 'A' Time Period Data. TCC Reload Value dc $19C 'B' Time Period Data. TCC Reload Value * dc $138 'C' Time Period Data. TCC Reload Value dc $16A 'C' Time Period Data. TCC Reload Value dc $1CE ' ' Time Period Data. TCC Reload Value dc $138 'C' Time Period Data. TCC Reload Value * dc $138 'F' Time Period Data. TCC Reload Value dc $19C 'G' Time Period Data. TCC Reload Value dc $19C 'F' Time Period Data. TCC Reload Value dc $19C 'E' Time Period Data. TCC Reload Value dc $19C 'D' Time Period Data. TCC Reload Value * dc $138 'E' Time Period Data. TCC Reload Value dc $19C 'F' Time Period Data. TCC Reload Value dc $19C 'E' Time Period Data. TCC Reload Value dc $19C 'D' Time Period Data. TCC Reload Value dc $19C 'C' Time Period Data. TCC Reload Value * dc $138 'D' Time Period Data. TCC Reload Value dc $19C 'E' Time Period Data. TCC Reload Value dc $19C 'D' Time Period Data. TCC Reload Value dc $19C 'C' Time Period Data. TCC Reload Value dc $19C 'B' Time Period Data. TCC Reload Value * dc $138 'C' Time Period Data. TCC Reload Value dc $138 ' ' Time Period Data. TCC Reload Value * ************************************************************ * Time Counter Data = $38 = = = = = $38 $9C $9C $9C $9C = = = = $38 $6A $CE $38 = = = = = $38 $9C $9C $9C $9C = = = = $38 $6A $CE $38 = = = = = $38 $9C $9C $9C $9C = = = = = $38 $9C $9C $9C $9C = = = = = $38 $9C $9C $9C $9C = $38 = $38 Rev. 1.0, 03/99, page 55 of 209 ************************************************************ * org $0400 * *** 1st Cycle * dc $10F 'G' Time Counter Data. PCNT = $F dc $10F 'C' Time Counter Data. PCNT = $F dc $10F 'D' Time Counter Data. PCNT = $F dc $10F 'E' Time Counter Data. PCNT = $F dc $10F 'F' Time Counter Data. PCNT = $F * dc $10F 'G' Time Counter Data. PCNT = $F dc $10F 'C' Time Counter Data. PCNT = $F dc $10F ' ' Time Counter Data. PCNT = $F dc $10F 'C' Time Counter Data. PCNT = $F * dc $10F 'A' Time Counter Data. PCNT = $F dc $10F 'F' Time Counter Data. PCNT = $F dc $10F 'G' Time Counter Data. PCNT = $F dc $10F 'A' Time Counter Data. PCNT = $F dc $10F 'B' Time Counter Data. PCNT = $F * dc $10F 'C' Time Counter Data. PCNT = $F dc $10F 'C' Time Counter Data. PCNT = $F dc $10F ' ' Time Counter Data. PCNT = $F dc $10F 'C' Time Counter Data. PCNT = $F * dc $10F 'F' Time Counter Data. PCNT = $F dc $10F 'G' Time Counter Data. PCNT = $F dc $10F 'F' Time Counter Data. PCNT = $F dc $10F 'E' Time Counter Data. PCNT = $F dc $10F 'D' Time Counter Data. PCNT = $F * dc $10F 'E' Time Counter Data. PCNT = $F dc $10F 'F' Time Counter Data. PCNT = $F dc $10F 'E' Time Counter Data. PCNT = $F dc $10F 'D' Time Counter Data. PCNT = $F dc $10F 'C' Time Counter Data. PCNT = $F * dc $10F 'B' Time Counter Data. PCNT = $F dc $10F 'C' Time Counter Data. PCNT = $F dc $10F 'D' Time Counter Data. PCNT = $F dc $10F 'E' Time Counter Data. PCNT = $F dc $10F 'C' Time Counter Data. PCNT = $F * dc $10D 'D' Time Counter Data. PCNT = $D * *** 2nd Cycle * dc $10F 'G' Time Counter Data. PCNT = $F Rev. 1.0, 03/99, page 56 of 209 dc dc dc dc $10F $10F $10F $10F 'C' 'D' 'E' 'F' Time Time Time Time Counter Counter Counter Counter Data. Data. Data. Data. PCNT PCNT PCNT PCNT = = = = $F $F $F $F dc dc dc dc $10F $10F $10F $10F 'G' 'C' ' ' 'C' Time Time Time Time Counter Counter Counter Counter Data. Data. Data. Data. PCNT PCNT PCNT PCNT = = = = $F $F $F $F dc dc dc dc dc $10F $10F $10F $10F $10F 'A' 'F' 'G' 'A' 'B' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F dc dc dc dc $10F $10F $10F $10F 'C' 'C' ' ' 'C' Time Time Time Time Counter Counter Counter Counter Data. Data. Data. Data. PCNT PCNT PCNT PCNT = = = = $F $F $F $F dc dc dc dc dc $10F $10F $10F $10F $10F 'F' 'G' 'F' 'E' 'D' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F dc dc dc dc dc $10F $10F $10F $10F $10F 'E' 'F' 'E' 'D' 'C' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F dc dc dc dc dc $10F $10F $10F $10F $10F 'D' 'E' 'D' 'C' 'B' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F dc dc $10E $10F 'C' Time Counter Data. PCNT = $E ' ' Time Counter Data. PCNT = $F * * * * * * * * end Rev. 1.0, 03/99, page 57 of 209 3. H4369 ************************************************************ * * HMCS400 Series Application Note * * 'Sound Play * - Minuet : J.S.Bach' * * MCU : H4369 * * External Clock : 4MHz * Internal Clock : 1MHz * Sub Clock : 32.768kHz * ************************************************************ * ************************************************************ * Symbol Definition ************************************************************ * IE equ 0,$000 Interrupt Enable Flag RSP equ 1,$000 Reset Stack Pointer IF0 equ 2,$000 INT0 Interrupt Request Flag IM0 equ 3,$000 INT0 Interrupt Mask * IF1 equ 0,$001 INT1 Interrupt Request Flag IM1 equ 1,$001 INT1 Interrupt Mask IFTA equ 2,$001 Timer A Interrupt Request Flag IMTA equ 3,$001 Timer A Interrupt Mask * IFTB equ 0,$002 Timer B Interrupt Request Flag IMTB equ 1,$002 Timer B Interrupt Mask IFTC equ 2,$002 Timer C Interrupt Request Flag IMTC equ 3,$002 Timer C Interrupt Mask * IFAD equ 0,$003 A/D Converter Interrupt Request Flag IMAD equ 1,$003 A/D Converter Interrupt Mask IFS equ 2,$003 Serial Interrupt Request Flag IMS equ 3,$003 Serial Interrupt Mask * PMRA equ $004 Port Mode Register SMR equ $005 Serial Mode Register SRL equ $006 Serial Data Register L SRU equ $007 Serial Data Register U TMA equ $008 Timer Mode Register A TMB1 equ $009 Timer Mode Register B1 TRBL equ $00A Timer Read Register BL TWBL equ $00A Timer Write Register BL TRBU equ $00B Timer Read Register BU TWBU equ $00B Timer Write Register BU Rev. 1.0, 03/99, page 58 of 209 MIS equ $00C Miscellaneous Register TMC equ $00D Timer Mode Register C TRCL equ $00E Timer Read Register CL TWCL equ $00E Timer Write Register CL TRCU equ $00F Timer Read Register CU TWCU equ $00F Timer Write Register CU * ACR equ $016 A/D Channel Register ADRL equ $017 A/D Data Register L ADRU equ $018 A/D Data Register U AMR1 equ $019 A/D Mode Register 1 AMR2 equ $01A A/D Mode Register 2 * LSON equ 0,$020 Low Speed on Flag WDON equ 1,$020 Watchdog on Flag ADSF equ 2,$020 A/D Start Flag DTON equ 3,$020 Direct Transfer on Flag * ICSF equ 0,$021 Input Capture Status Flag ICEF equ 1,$021 Input Capture Error Flag IAOF equ 2,$021 IAD off Flag RAME equ 3,$021 RAM Enable Flag * PMRB equ $024 Port Mode Register B PMRC equ $025 Port Mode Register C TMB2 equ $026 Timer Mode Register B2 SSR1 equ $027 System Clock Selection Register 1 SSR2 equ $028 System Clock Selection Register 2 * DCD0 equ $02C D Port Data Control Register 0 DCD1 equ $02D D Port Data Control Register 1 DCD2 equ $02E D Port Data Control Register 2 DCD3 equ $02F D Port Data Control Register 3 DCR0 equ $030 R Port Data Control Register 0 DCR1 equ $031 R Port Data Control Register 1 DCR2 equ $032 R Port Data Control Register 2 DCR3 equ $033 R Port Data Control Register 3 DCR4 equ $034 R Port Data Control Register 4 DCR5 equ $035 R Port Data Control Register 5 DCR6 equ $036 R Port Data Control Register 6 SCR7 equ $037 R Port Data Control Register 7 DCR8 equ $038 R Port Data Control Register 8 * ************************************************************ * RAM ALLOCATION ************************************************************ * AESC equ $040 Accumulator Escape BESC equ $041 B Register Escape * PLCNT equ $090 Pulse Counter Rev. 1.0, 03/99, page 59 of 209 * PLFLG1 equ $091 Pulse Flag 1 PLONF equ 0,PLFLG1 Pulse Output Enable Flag * CNTL equ $093 Lower Counter CNTU equ $094 Upper Counter PCNT equ $095 Period Counter AWORK equ $096 Accumulator Work RAM Area BWORK equ $097 B Register Work RAM Area * ************************************************************ * Vector Address ************************************************************ * org $0000 * JMPL SPLMN Reset Interrupt JMPL SPLMN INT0 Interrupt JMPL SPLMN INT1 Interrupt JMPL SPLMN Timer A Interrupt JMPL SPLINT Timer B Interrupt JMPL SPLMN Timer C Interrupt JMPL SPLMN A/D Converter Interrupt JMPL SPLMN Serial Interrupt * ************************************************************ * Main Program ************************************************************ * org $1000 * SPLMN REMD RSP Reset Stack Pointer LMID $2,SSR1 Set System Clock to 1.6 - 5.0MHz * LAI 0 LRA 0 Initialize R0 Port PDR LMID 8,DCR0 Initialize R03 Output Terminal Function LMID 0,PMRA Initialize R03 Input/Output Terminal Function * LMID 3,PLCNT Initialize Pulse Counter LMID 0,CNTL Initialize Lower Counter LMID 0,CNTU Initialize Upper Counter LMID $F,PCNT Initialize Period Counter SEMD PLONF Initialize Pulse Output Enable Flag * LMID 8,TMC Initialize Timer C Function & Input Clock Period REMD IFTC Clear IFTC to 0 * LMID $D,TMB1 Initialize Timer B Function & Input Clock Period LMID 0,TMB2 Initialize Timer B Function * Rev. 1.0, 03/99, page 60 of 209 SEMD REMD IMTB IFTB Timer B Interrupt Disable Clear IFTB to 0 SEMD IE All Interrupt Enable TMD BRS BRS IFTC SPLMN10 SPLMN00 IFTC = "1" ? Yes. Branch to SPLMN10 No. Branch to SPLMN00 REMD LMID LMID IFTC 9,TWCL 0,TWCU Clear IFTC to 0 Set TCC Reload Value Lower Set TCC Reload Value Upper TMD BRS SEMD REMD LAI LRA BRS IFTC SPLMN10 IMTB IFTB 0 0 SPLMN05 IFTC = "1" ? Yes. Branch to SPLMN10 Timer B Interrupt Disable Clear IFTB to 0 REMD LAMD AI BRS LMAD BRS IFTC PCNT 1 SPLMN40 PCNT SPLMN00 Clear IFTC to 0 Load PCNT Increment PCNT PCNT Overflow ? Yes. Branch to SPLMN40 No. Save PCNT Branch to SPLMN00 LAMD LBA LAMD P LMAD LAB LMAD ALEI BRS ALEI BRS SEMD REMD LAI LRA BRS CNTU Load CNTL CNTL 2 AWORK Load CNTU Scale Data Pattern Generation Save Scale Lower Data BWORK 0 SPLMN90 $E SPLMN20 IMTB IFTB 0 0 SPLMN30 Save Scale Upper Data Scale Upper Data <= $0 ? End Sound Play ? Yes. Branch to SPLMN90 Scale Upper Data <= $E ? Yes. Branch to SPLMN20 Timer B Interrupt Disable Clear IFTB to 0 LAMD LMAD LAMD LMAD REMD REMD AWORK TWBL BWORK TWBU IFTB IMTB Load AWORK Set TCB Reload Value Lower to Scale Data Load BWORK Set TCB Reload Value Upper to Scale Data Clear IFTB to 0 Timer B Interrupt Enable * * SPLMN00 * * SPLMN05 * SPLMN10 * SPLMN40 * SPLMN20 Sound off Branch to SPLMN05 R03 Output Terminal is "Low" Output Branch to SPLMN30 Rev. 1.0, 03/99, page 61 of 209 * SPLMN30 LAMD LBA LAMD P LMAD LAB LMAD CNTU Load Upper Counter CNTL 3 TWCL Load Lower Counter Time Period Data Pattern Generation Set TCC Reload Value Lower to Time Period Lower Data TWCU Set TCC Reload Value Upper to Time Period Upper Data LAMD LBA LAMD P LMAD CNTU Load Upper Counter CNTL 4 PCNT Load Lower Counter Time Counter Data Pattern Generation Set PCNT to Time Counter Data * * * SPLMN90 SEC LAI AMCD LMAD LAI AMCD LMAD BR BRS 0 CNTL CNTL 0 CNTU CNTU *+1 SPLMN00 Set Carry Flag at 1 SEMD LMID LMID LAI LRA LMID LMID REMD BRS IMTB 0,CNTL 0,CNTU 0 0 0,TWCL 8,TWCU IFTC SPLMN00 Increment Lower Counter Save Lower Counter If CNTL Overflow, Increment Upper Counter Save Upper Counter Branch to SPLMN00 Timer B Interrupt Disable Initialize Lower Counter Initialize Upper Counter Initialize R0 Port PDR Initialize TCC Reload Value Lower Initialize TCC Reload Value Upper Clear IFTC to 0 Branch to SPLMN00 * ************************************************************ * Timer B Interrupt Process * ---Pulse Output Routine--************************************************************ * SPLINT REMD IFTB Clear IFTB to 0 * LMAD AESC Store Accumulator LAB LMAD BESC Store B Register * TMD PLONF Pulse Enable Flag = "1" ? BRS PLI00 Yes. Branch to PLI00 LAI 0 No. Stop Output Pulse LRA 0 R03 Output Terminal is "Low" Output BRS PLI99 Branch to PLI99 Rev. 1.0, 03/99, page 62 of 209 * PLI00 PLI10 PLI20 PLI30 * PLI99 LAMD LBA ALEI BRS LAI BRS LAI LRA LAB AI BRS LAI LMAD LAMD LBA LAMD PLCNT 1 PLI10 0 PLI20 8 0 Load Pulse Counter Value Store Pulse Counter Value PLCNT <= $1 ? Is R03 Output Terminal "High" Output ? Yes. Branch to PLI10 No. R03 Output Terminal is "Low" Output Branch to PLI20 $F PLI30 3 PLCNT R03 Output Terminal is "High" Output Restore Pulse Counter Value PLCNT + $F <= $F ? Pulse Counter = $0 ? No. Branch to PLI30 Yes. Pulse Counter Initialize Save Pulse Counter Value BESC Restore B Register AESC Restore Accumulator * RTNI Return from Interrupt * ************************************************************ * Scale Data ************************************************************ * ORG $0200 * *** 1st Cycle * dc $1AB 'G' Data. TCB Reload Value = $AB dc $17F 'C' Data. TCB Reload Value = $7F dc $18E 'D' Data. TCB Reload Value = $8E dc $19B 'E' Data. TCB Reload Value = $9B dc $1A1 'F' Data. TCB Reload Value = $A1 * dc $1AB 'G' Data. TCB Reload Value = $AB dc $17F 'C' Data. TCB Reload Value = $7F dc $1FF ' ' Data. TCB Reload Value = $FF dc $17F 'C' Data. TCB Reload Value = $7F * dc $1B4 'A' Data. TCB Reload Value = $B4 dc $1A1 'F' Data. TCB Reload Value = $A1 dc $1AB 'G' Data. TCB Reload Value = $AB dc $1B4 'A' Data. TCB Reload Value = $B4 dc $1BD 'B' Data. TCB Reload Value = $BD * dc $1C1 'C' Data. TCB Reload Value = $C1 dc $17F 'C' Data. TCB Reload Value = $7F dc $1FF ' ' Data. TCB Reload Value = $FF dc $17F 'C' Data. TCB Reload Value = $7F * Rev. 1.0, 03/99, page 63 of 209 dc dc dc dc dc $1A1 $1AB $1A1 $19B $18E 'F' 'G' 'F' 'E' 'D' Data. Data. Data. Data. Data. TCB TCB TCB TCB TCB Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $A1 $AB $A1 $9B $8E dc dc dc dc dc $19B $1A1 $19B $18E $17F 'E' 'F' 'E' 'D' 'C' Data. Data. Data. Data. Data. TCB TCB TCB TCB TCB Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $9B $A1 $9B $8E $7F dc dc dc dc dc $17A $17F $18E $19B $17F 'B' 'C' 'D' 'E' 'C' Data. Data. Data. Data. Data. TCB TCB TCB TCB TCB Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $7A $7F $8E $9B $7F $18E 'D' Data. TCB Reload Value = $8E $1AB $17F $18E $19B $1A1 'G' 'C' 'D' 'E' 'F' Data. Data. Data. Data. Data. TCB TCB TCB TCB TCB Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $AB $7F $8E $9B $A1 $1AB $17F $1FF $17F 'G' 'C' ' ' 'C' Data. Data. Data. Data. TCB TCB TCB TCB Reload Reload Reload Reload Value Value Value Value = = = = $AB $7F $FF $7F $1B4 $1A1 $1AB $1B4 $1BD 'A' 'F' 'G' 'A' 'B' Data. Data. Data. Data. Data. TCB TCB TCB TCB TCB Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $B4 $A1 $AB $B4 $BD $1C1 $17F $1FF $17F 'C' 'C' ' ' 'C' Data. Data. Data. Data. TCB TCB TCB TCB Reload Reload Reload Reload Value Value Value Value = = = = $C1 $7F $FF $7F $1A1 $1AB $1A1 $19B $18E 'F' 'G' 'F' 'E' 'D' Data. Data. Data. Data. Data. TCB TCB TCB TCB TCB Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $A1 $AB $A1 $9B $8E $19B 'E' Data. TCB Reload Value = $9B * * * dc * *** 2nd Cycle * dc dc dc dc dc * dc dc dc dc * dc dc dc dc dc * dc dc dc dc * dc dc dc dc dc * dc Rev. 1.0, 03/99, page 64 of 209 dc dc dc dc $1A1 $19B $18E $17F 'F' 'E' 'D' 'C' Data. Data. Data. Data. TCB TCB TCB TCB Reload Reload Reload Reload Value Value Value Value = = = = $A1 $9B $8E $7F dc dc dc dc dc $18E $19B $18E $17F $17A 'D' 'E' 'D' 'C' 'B' Data. Data. Data. Data. Data. TCB TCB TCB TCB TCB Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $8E $9B $8E $7F $7A dc dc $17F $1FF 'C' Data. TCB Reload Value = $7F ' ' Data. TCB Reload Value = $FF * * * dc $100 ' ' Data. TCB Reload Value = $00 * ************************************************************ * Time Period Data ************************************************************ * org $0300 * *** 1st Cycle * dc $138 'G' Time Period Data. TCC Reload Value dc $19C 'C' Time Period Data. TCC Reload Value dc $19C 'D' Time Period Data. TCC Reload Value dc $19C 'E' Time Period Data. TCC Reload Value dc $19C 'F' Time Period Data. TCC Reload Value * dc $138 'G' Time Period Data. TCC Reload Value dc $16A 'C' Time Period Data. TCC Reload Value dc $1CE ' ' Time Period Data. TCC Reload Value dc $138 'C' Time Period Data. TCC Reload Value * dc $138 'A' Time Period Data. TCC Reload Value dc $19C 'F' Time Period Data. TCC Reload Value dc $19C 'G' Time Period Data. TCC Reload Value dc $19C 'A' Time Period Data. TCC Reload Value dc $19C 'B' Time Period Data. TCC Reload Value * dc $138 'C' Time Period Data. TCC Reload Value dc $16A 'C' Time Period Data. TCC Reload Value dc $1CE ' ' Time Period Data. TCC Reload Value dc $138 'C' Time Period Data. TCC Reload Value * dc $138 'F' Time Period Data. TCC Reload Value dc $19C 'G' Time Period Data. TCC Reload Value dc $19C 'F' Time Period Data. TCC Reload Value dc $19C 'E' Time Period Data. TCC Reload Value dc $19C 'D' Time Period Data. TCC Reload Value = = = = = $38 $9C $9C $9C $9C = = = = $38 $6A $CE $38 = = = = = $38 $9C $9C $9C $9C = = = = $38 $6A $CE $38 = = = = = $38 $9C $9C $9C $9C Rev. 1.0, 03/99, page 65 of 209 * dc dc dc dc dc $138 $19C $19C $19C $19C 'E' 'F' 'E' 'D' 'C' Time Time Time Time Time Period Period Period Period Period Data. Data. Data. Data. Data. TCC TCC TCC TCC TCC Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $38 $9C $9C $9C $9C dc dc dc dc dc $138 $19C $19C $19C $19C 'B' 'C' 'D' 'E' 'C' Time Time Time Time Time Period Period Period Period Period Data. Data. Data. Data. Data. TCC TCC TCC TCC TCC Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $38 $9C $9C $9C $9C $138 'D' Time Period Data. TCC Reload Value = $38 $138 $19C $19C $19C $19C 'G' 'C' 'D' 'E' 'F' Time Time Time Time Time Period Period Period Period Period Data. Data. Data. Data. Data. TCC TCC TCC TCC TCC Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $38 $9C $9C $9C $9C $138 $16A $1CE $138 'G' 'C' ' ' 'C' Time Time Time Time Period Period Period Period Data. Data. Data. Data. TCC TCC TCC TCC Reload Reload Reload Reload Value Value Value Value = = = = $38 $6A $CE $38 $138 $19C $19C $19C $19C 'A' 'F' 'G' 'A' 'B' Time Time Time Time Time Period Period Period Period Period Data. Data. Data. Data. Data. TCC TCC TCC TCC TCC Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $38 $9C $9C $9C $9C $138 $16A $1CE $138 'C' 'C' ' ' 'C' Time Time Time Time Period Period Period Period Data. Data. Data. Data. TCC TCC TCC TCC Reload Reload Reload Reload Value Value Value Value = = = = $38 $6A $CE $38 $138 $19C $19C $19C $19C 'F' 'G' 'F' 'E' 'D' Time Time Time Time Time Period Period Period Period Period Data. Data. Data. Data. Data. TCC TCC TCC TCC TCC Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $38 $9C $9C $9C $9C $138 $19C $19C $19C $19C 'E' 'F' 'E' 'D' 'C' Time Time Time Time Time Period Period Period Period Period Data. Data. Data. Data. Data. TCC TCC TCC TCC TCC Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $38 $9C $9C $9C $9C * * dc * *** 2nd Cycle * dc dc dc dc dc * dc dc dc dc * dc dc dc dc dc * dc dc dc dc * dc dc dc dc dc * dc dc dc dc dc * Rev. 1.0, 03/99, page 66 of 209 dc dc dc dc dc $138 $19C $19C $19C $19C 'D' 'E' 'D' 'C' 'B' Time Time Time Time Time Period Period Period Period Period Data. Data. Data. Data. Data. TCC TCC TCC TCC TCC Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $38 $9C $9C $9C $9C dc dc $138 $138 'C' Time Period Data. TCC Reload Value = $38 ' ' Time Period Data. TCC Reload Value = $38 * * ************************************************************ * Time Counter Data ************************************************************ * org $0400 * *** 1st Cycle * dc $10F 'G' Time Counter Data. PCNT = $F dc $10F 'C' Time Counter Data. PCNT = $F dc $10F 'D' Time Counter Data. PCNT = $F dc $10F 'E' Time Counter Data. PCNT = $F dc $10F 'F' Time Counter Data. PCNT = $F * dc $10F 'G' Time Counter Data. PCNT = $F dc $10F 'C' Time Counter Data. PCNT = $F dc $10F ' ' Time Counter Data. PCNT = $F dc $10F 'C' Time Counter Data. PCNT = $F * dc $10F 'A' Time Counter Data. PCNT = $F dc $10F 'F' Time Counter Data. PCNT = $F dc $10F 'G' Time Counter Data. PCNT = $F dc $10F 'A' Time Counter Data. PCNT = $F dc $10F 'B' Time Counter Data. PCNT = $F * dc $10F 'C' Time Counter Data. PCNT = $F dc $10F 'C' Time Counter Data. PCNT = $F dc $10F ' ' Time Counter Data. PCNT = $F dc $10F 'C' Time Counter Data. PCNT = $F * dc $10F 'F' Time Counter Data. PCNT = $F dc $10F 'G' Time Counter Data. PCNT = $F dc $10F 'F' Time Counter Data. PCNT = $F dc $10F 'E' Time Counter Data. PCNT = $F dc $10F 'D' Time Counter Data. PCNT = $F * dc $10F 'E' Time Counter Data. PCNT = $F dc $10F 'F' Time Counter Data. PCNT = $F dc $10F 'E' Time Counter Data. PCNT = $F dc $10F 'D' Time Counter Data. PCNT = $F dc $10F 'C' Time Counter Data. PCNT = $F * Rev. 1.0, 03/99, page 67 of 209 dc dc dc dc dc $10F $10F $10F $10F $10F 'B' 'C' 'D' 'E' 'C' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F $10D 'D' Time Counter Data. PCNT = $D $10F $10F $10F $10F $10F 'G' 'C' 'D' 'E' 'F' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F $10F $10F $10F $10F 'G' 'C' ' ' 'C' Time Time Time Time Counter Counter Counter Counter Data. Data. Data. Data. PCNT PCNT PCNT PCNT = = = = $F $F $F $F $10F $10F $10F $10F $10F 'A' 'F' 'G' 'A' 'B' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F $10F $10F $10F $10F 'C' 'C' ' ' 'C' Time Time Time Time Counter Counter Counter Counter Data. Data. Data. Data. PCNT PCNT PCNT PCNT = = = = $F $F $F $F $10F $10F $10F $10F $10F 'F' 'G' 'F' 'E' 'D' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F $10F $10F $10F $10F $10F 'E' 'F' 'E' 'D' 'C' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F $10F $10F $10F $10F $10F 'D' 'E' 'D' 'C' 'B' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F $10E 'C' Time Counter Data. PCNT = $E * dc * *** 2nd Cycle * dc dc dc dc dc * dc dc dc dc * dc dc dc dc dc * dc dc dc dc * dc dc dc dc dc * dc dc dc dc dc * dc dc dc dc dc * dc Rev. 1.0, 03/99, page 68 of 209 dc $10F ' ' Time Counter Data. PCNT = $F * end Rev. 1.0, 03/99, page 69 of 209 4. H4889 ************************************************************ * * HMCS400 Series Application Note * * 'Sound Play * - Minuet : J.S.Bach' * * MCU : H4889 * * External Clock : 4MHz * Internal Clock : 1MHz * Sub Clock : 32.768kHz * ************************************************************ * ************************************************************ * Symbol Definition ************************************************************ * IE equ 0,$000 Interrupt Enable Flag RSP equ 1,$000 Reset Stack Pointer IFWU equ 2,$000 WU0-WU3 Interrupt Request Flag IMWU equ 3,$000 WU0-WU3 Interrupt Mask * IF0 equ 0,$001 INT0 Interrupt Request Flag IM0 equ 1,$001 INT0 Interrupt Mask IF1 equ 2,$001 INT1 Interrupt Request Flag IM1 equ 3,$001 INT1 Interrupt Mask * IFTA equ 0,$002 Timer A Interrupt Request Flag IMTA equ 1,$002 Timer A Interrupt Mask IFTB equ 2,$002 Timer B Interrupt Request Flag IMTB equ 3,$002 Timer B Interrupt Mask * IFTC equ 0,$003 Timer C Interrupt Request Flag IMTC equ 1,$003 Timer C Interrupt Mask IFAD equ 2,$003 A/D Converter Interrupt Request Flag IMAD equ 3,$003 A/D Converter Interrupt Mask * SSR equ $004 System Clock selection Register MIS equ $005 Miscellaneous Register ESR equ $006 Edge Detect Selection Register * PMR0 equ $008 Port Mode Register 0 PMR1 equ $009 Port Mode Register 1 PMR2 equ $00A Port Mode Register 2 PMR3 equ $00B Port Mode Register 3 PMR4 equ $00C Port Mode Register 4 MSR1 equ $00D Module Standby Register 1 Rev. 1.0, 03/99, page 70 of 209 MSR2 TMA TMB1 TMB2 TRBL TWBL TRBU TWBU TMC1 TMC2 TRCL TWCL TRCU TWCU TMD1 TMD2 TRDL TWDL TRDU TWDU * LSON WDON ADSF DTON * ICSF ICEF GEF * IFTD IMTD * IFS IMS * SMR1 SMR2 SRL SRU AMR * ADRL ADRU LCR LMR BMR * DCD0 DCD1 DCD2 equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ eqU equ equ equ equ $00E $00F $010 $011 $012 $012 $013 $013 $014 $015 $016 $016 $017 $017 $018 $019 $01A $01A $01B $01B Module Standby register 2 Timer Mode Register A Timer Mode Register B1 Timer Mode register B2 Timer Read Register BL Timer Write Register BL Timer Read Register BU Timer Write Register BU Timer Mode Register C1 Timer Mode Register C2 Timer Read Register CL Timer Write Register CL Timer Read Register CU Timer Write Register CU Timer Mode Register D1 Timer Mode Register D2 Timer Read Register DL Timer Write Register DL Timer Read Register DU Timer Write Register DU equ equ equ equ 0,$020 1,$020 2,$020 3,$020 Low Speed on Flag Watchdog on Flag A/D Start Flag Direct Transfer on Flag equ equ equ 0,$021 1,$021 3,$021 Input Capture Status Flag Input Capture Error Flag Gear Enable Flag equ equ 2,$022 3,$022 Timer D Interrupt Request Flag Timer D Interrupt Mask equ equ 2,$023 3,$023 Serial Interrupt Request Flag Serial Interrupt Mask equ equ equ equ equ $024 $025 $026 $027 $028 Serial Mode Register Serial Mode Register Serial Data Register Serial Data Register A/D Mode Register equ equ equ equ equ $02A $02B $02C $02D $02E A/D Data Register L A/D Data Register U LCD Control Register LCD Mode Register Buzzer Mode Register equ equ equ $030 $031 $032 D Port Data Control Register 0 D Port Data Control Register 1 D Port Data Control Register 2 1 2 L U Rev. 1.0, 03/99, page 71 of 209 * DCR0 equ $034 R Port Data Control Register 0 DCR1 equ $035 R Port Data Control Register 1 DCR2 equ $036 R Port Data Control Register 2 DCR3 equ $037 R Port Data Control Register 3 DCR4 equ $038 R Port Data Control Register 4 DCR5 equ $039 R Port Data Control Register 5 DCR6 equ $03A R Port Data Control Register 6 DCR7 equ $03B R Port Data Control Register 7 DCR8 equ $03C R port Data Control Register 8 * V equ $03F Bank Register * ************************************************************ * RAM ALLOCATION ************************************************************ * AESC equ $040 Accumulator Escape BESC equ $041 B Register Escape * PLCNT equ $090 Pulse Counter * PLFLG1 equ $091 Pulse Flag 1 PLONF equ 0,PLFLG1 Pulse Output Enable Flag * CNTL equ $093 Lower Counter CNTU equ $094 Upper Counter PCNT equ $095 Period Counter AWORK equ $096 Accumulator Work RAM Area BWORK equ $097 B Register Work RAM Area * ************************************************************ * Vector Address ************************************************************ * org $0000 * JMPL SPLMN Reset Interrupt JMPL SPLMN WU0-WU3 Interrupt JMPL SPLMN INT0 Interrupt JMPL SPLMN INT1 Interrupt JMPL SPLMN Timer A Interrupt JMPL SPLINT Timer B/D Interrupt JMPL SPLMN Timer C Interrupt JMPL SPLMN A/D Converter/Serial Interrupt * ************************************************************ * Main Program ************************************************************ * org $1000 Rev. 1.0, 03/99, page 72 of 209 * SPLMN REMD LMID RSP $2,SSR Reset Stack Pointer Set System Clock to 1.6 - 4.5MHz LAI LRA LMID LMID $0 $1 $4,DCR1 $0,PMR2 Initialize R1 Port PDR Initialize R12 Output Terminal Function Initialize R12 Input/Output Terminal Function LMID LMID LMID LMID SEMD $3,PLCNT $0,CNTL $0,CNTU $F,PCNT PLONF Initialize Initialize Initialize Initialize Initialize LMID REMD $8,TMC1 IFTC Initialize Timer C Function & Input Clock Period Clear IFTC to 0 LMID LMID $D,TMB1 $0,TMB2 Initialize Timer B Function & Input Clock Period Initialize Timer B Function SEMD REMD IMTB IFTB Timer B Interrupt Disable Clear IFTB to 0 SEMD IE All Interrupt Enable TMD BRS BRS IFTC SPLMN10 SPLMN00 IFTC = "1" ? Yes. Branch to SPLMN10 No. Branch to SPLMN00 REMD LMID LMID IFTC $9,TWCL $0,TWCU Clear IFTC to 0 Set TCC Reload Value Lower Set TCC Reload Value Upper TMD BRS SEMD REMD LAI LRA BRS IFTC SPLMN10 IMTB IFTB $0 $1 SPLMN05 IFTC = "1" ? Yes. Branch to SPLMN10 Timer B Interrupt Disable Clear IFTB to 0 REMD LAMD AI BRS LMAD BRS IFTC PCNT $1 SPLMN40 PCNT SPLMN00 Clear IFTC to 0 Load PCNT Increment PCNT PCNT Overflow ? Yes. Branch to SPLMN40 No. Save PCNT Branch to SPLMN00 LAMD LBA CNTU Load CNTL * * Pulse Counter Lower Counter Upper Counter Period Counter Pulse Output Enable Flag * * * * * SPLMN00 * * SPLMN05 * SPLMN10 * SPLMN40 Sound off Branch to SPLMN05 Rev. 1.0, 03/99, page 73 of 209 * SPLMN20 * SPLMN30 LAMD P LMAD LAB LMAD ALEI BRS ALEI BRS SEMD REMD LAI LRA BRS CNTL $2 AWORK Load CNTU Scale Data Pattern Generation Save Scale Lower Data BWORK $0 SPLMN90 $E SPLMN20 IMTB IFTB $0 $1 SPLMN30 Save Scale Upper Data Scale Upper Data <= $0 ? End Sound Play ? Yes. Branch to SPLMN90 Scale Upper Data <= $E ? Yes. Branch to SPLMN20 Timer B Interrupt Disable Clear IFTB to 0 LAMD LMAD LAMD LMAD REMD REMD AWORK TWBL BWORK TWBU IFTB IMTB Load AWORK Set TCB Reload Value Lower to Scale Data Load BWORK Set TCB Reload Value Upper to Scale Data Clear IFTB to 0 Timer B Interrupt Enable LAMD LBA LAMD P LMAD LAB LMAD CNTU Load Upper Counter CNTL $3 TWCL Load Lower Counter Time Period Data Pattern Generation Set TCC Reload Value Lower to Time Period Lower Data TWCU Set TCC Reload Value Upper to Time Period Upper Data LAMD LBA LAMD P LMAD CNTU Load Upper Counter CNTL $4 PCNT Load Lower Counter Time Counter Data Pattern Generation Set PCNT to Time Counter Data R12 Output Terminal is "Low" Output Branch to SPLMN30 * * * SPLMN90 SEC LAI AMCD LMAD LAI AMCD LMAD BR BRS $0 CNTL CNTL $0 CNTU CNTU *+1 SPLMN00 Set Carry Flag at 1 SEMD LMID LMID LAI LRA IMTB $0,CNTL $0,CNTU $0 $1 Rev. 1.0, 03/99, page 74 of 209 Increment Lower Counter Save Lower Counter If CNTL Overflow, Increment Upper Counter Save Upper Counter Branch to SPLMN00 Timer B Interrupt Disable Initialize Lower Counter Initialize Upper Counter Initialize R1 Port PDR LMID LMID REMD BRS $0,TWCL $8,TWCU IFTC SPLMN00 Initialize TCC Reload Value Lower Initialize TCC Reload Value Upper Clear IFTC to 0 Branch to SPLMN00 * ************************************************************ * Timer B Interrupt Process * ---Pulse Output Routine--************************************************************ * SPLINT REMD IFTB Clear IFTB to 0 * LMAD AESC Store Accumulator LAB LMAD BESC Store B Register * TMD PLONF Pulse Enable Flag = "1" ? BRS PLI00 Yes. Branch to PLI00 LAI $0 No. Stop Output Pulse LRA $1 R12 Output Terminal is "Low" Output BRS PLI99 Branch to PLI99 * PLI00 LAMD PLCNT Load Pulse Counter Value LBA Store Pulse Counter Value ALEI $1 PLCNT <= $1 ? Is R12 Output Terminal "High" Output ? BRS PLI10 Yes. Branch to PLI10 LAI $0 No. R12 Output Terminal is "Low" Output BRS PLI20 Branch to PLI20 PLI10 LAI $4 PLI20 LRA $1 R03 Output Terminal is "High" Output LAB Restore Pulse Counter Value AI $F PLCNT + $F <= $F ? Pulse Counter = $0 ? BRS PLI30 No. Branch to PLI30 LAI $3 Yes. Pulse Counter Initialize PLI30 LMAD PLCNT Save Pulse Counter Value * PLI99 LAMD BESC Restore B Register LBA LAMD AESC Restore Accumulator * RTNI Return from Interrupt * ************************************************************ * Scale Data ************************************************************ * ORG $0200 * *** 1st Cycle * dc $1AB 'G' Data. TCB Reload Value = $AB Rev. 1.0, 03/99, page 75 of 209 dc dc dc dc $17F $18E $19B $1A1 'C' 'D' 'E' 'F' Data. Data. Data. Data. TCB TCB TCB TCB Reload Reload Reload Reload Value Value Value Value = = = = $7F $8E $9B $A1 dc dc dc dc $1AB $17F $1FF $17F 'G' 'C' ' ' 'C' Data. Data. Data. Data. TCB TCB TCB TCB Reload Reload Reload Reload Value Value Value Value = = = = $AB $7F $FF $7F dc dc dc dc dc $1B4 $1A1 $1AB $1B4 $1BD 'A' 'F' 'G' 'A' 'B' Data. Data. Data. Data. Data. TCB TCB TCB TCB TCB Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $B4 $A1 $AB $B4 $BD dc dc dc dc $1C1 $17F $1FF $17F 'C' 'C' ' ' 'C' Data. Data. Data. Data. TCB TCB TCB TCB Reload Reload Reload Reload Value Value Value Value = = = = $C1 $7F $FF $7F dc dc dc dc dc $1A1 $1AB $1A1 $19B $18E 'F' 'G' 'F' 'E' 'D' Data. Data. Data. Data. Data. TCB TCB TCB TCB TCB Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $A1 $AB $A1 $9B $8E dc dc dc dc dc $19B $1A1 $19B $18E $17F 'E' 'F' 'E' 'D' 'C' Data. Data. Data. Data. Data. TCB TCB TCB TCB TCB Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $9B $A1 $9B $8E $7F dc dc dc dc dc $17A $17F $18E $19B $17F 'B' 'C' 'D' 'E' 'C' Data. Data. Data. Data. Data. TCB TCB TCB TCB TCB Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $7A $7F $8E $9B $7F $18E 'D' Data. TCB Reload Value = $8E $1AB $17F $18E $19B $1A1 'G' 'C' 'D' 'E' 'F' $1AB $17F 'G' Data. TCB Reload Value = $AB 'C' Data. TCB Reload Value = $7F * * * * * * * dc * *** 2nd Cycle * dc dc dc dc dc * dc dc Rev. 1.0, 03/99, page 76 of 209 Data. Data. Data. Data. Data. TCB TCB TCB TCB TCB Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $AB $7F $8E $9B $A1 dc dc $1FF $17F ' ' Data. TCB Reload Value = $FF 'C' Data. TCB Reload Value = $7F dc dc dc dc dc $1B4 $1A1 $1AB $1B4 $1BD 'A' 'F' 'G' 'A' 'B' Data. Data. Data. Data. Data. TCB TCB TCB TCB TCB Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $B4 $A1 $AB $B4 $BD dc dc dc dc $1C1 $17F $1FF $17F 'C' 'C' ' ' 'C' Data. Data. Data. Data. TCB TCB TCB TCB Reload Reload Reload Reload Value Value Value Value = = = = $C1 $7F $FF $7F dc dc dc dc dc $1A1 $1AB $1A1 $19B $18E 'F' 'G' 'F' 'E' 'D' Data. Data. Data. Data. Data. TCB TCB TCB TCB TCB Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $A1 $AB $A1 $9B $8E dc dc dc dc dc $19B $1A1 $19B $18E $17F 'E' 'F' 'E' 'D' 'C' Data. Data. Data. Data. Data. TCB TCB TCB TCB TCB Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $9B $A1 $9B $8E $7F dc dc dc dc dc $18E $19B $18E $17F $17A 'D' 'E' 'D' 'C' 'B' Data. Data. Data. Data. Data. TCB TCB TCB TCB TCB Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $8E $9B $8E $7F $7A dc dc $17F $1FF 'C' Data. TCB Reload Value = $7F ' ' Data. TCB Reload Value = $FF * * * * * * * dc $100 ' ' Data. TCB Reload Value = $00 * ************************************************************ * Time Period Data ************************************************************ * org $0300 * *** 1st Cycle * dc $138 'G' Time Period Data. TCC Reload Value dc $19C 'C' Time Period Data. TCC Reload Value dc $19C 'D' Time Period Data. TCC Reload Value dc $19C 'E' Time Period Data. TCC Reload Value dc $19C 'F' Time Period Data. TCC Reload Value * = = = = = $38 $9C $9C $9C $9C Rev. 1.0, 03/99, page 77 of 209 dc dc dc dc $138 $16A $1CE $138 'G' 'C' ' ' 'C' Time Time Time Time Period Period Period Period Data. Data. Data. Data. TCC TCC TCC TCC Reload Reload Reload Reload Value Value Value Value = = = = $38 $6A $CE $38 dc dc dc dc dc $138 $19C $19C $19C $19C 'A' 'F' 'G' 'A' 'B' Time Time Time Time Time Period Period Period Period Period Data. Data. Data. Data. Data. TCC TCC TCC TCC TCC Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $38 $9C $9C $9C $9C dc dc dc dc $138 $16A $1CE $138 'C' 'C' ' ' 'C' Time Time Time Time Period Period Period Period Data. Data. Data. Data. TCC TCC TCC TCC Reload Reload Reload Reload Value Value Value Value = = = = $38 $6A $CE $38 dc dc dc dc dc $138 $19C $19C $19C $19C 'F' 'G' 'F' 'E' 'D' Time Time Time Time Time Period Period Period Period Period Data. Data. Data. Data. Data. TCC TCC TCC TCC TCC Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $38 $9C $9C $9C $9C dc dc dc dc dc $138 $19C $19C $19C $19C 'E' 'F' 'E' 'D' 'C' Time Time Time Time Time Period Period Period Period Period Data. Data. Data. Data. Data. TCC TCC TCC TCC TCC Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $38 $9C $9C $9C $9C dc dc dc dc dc $138 $19C $19C $19C $19C 'B' 'C' 'D' 'E' 'C' Time Time Time Time Time Period Period Period Period Period Data. Data. Data. Data. Data. TCC TCC TCC TCC TCC Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $38 $9C $9C $9C $9C $138 'D' Time Period Data. TCC Reload Value = $38 $138 $19C $19C $19C $19C 'G' 'C' 'D' 'E' 'F' Time Time Time Time Time Period Period Period Period Period Data. Data. Data. Data. Data. TCC TCC TCC TCC TCC Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $38 $9C $9C $9C $9C $138 $16A $1CE $138 'G' 'C' ' ' 'C' Time Time Time Time Period Period Period Period Data. Data. Data. Data. TCC TCC TCC TCC Reload Reload Reload Reload Value Value Value Value = = = = $38 $6A $CE $38 $138 $19C 'A' Time Period Data. TCC Reload Value = $38 'F' Time Period Data. TCC Reload Value = $9C * * * * * * dc * *** 2nd Cycle * dc dc dc dc dc * dc dc dc dc * dc dc Rev. 1.0, 03/99, page 78 of 209 dc dc dc $19C $19C $19C 'G' Time Period Data. TCC Reload Value = $9C 'A' Time Period Data. TCC Reload Value = $9C 'B' Time Period Data. TCC Reload Value = $9C dc dc dc dc $138 $16A $1CE $138 'C' 'C' ' ' 'C' Time Time Time Time Period Period Period Period Data. Data. Data. Data. TCC TCC TCC TCC Reload Reload Reload Reload Value Value Value Value = = = = $38 $6A $CE $38 dc dc dc dc dc $138 $19C $19C $19C $19C 'F' 'G' 'F' 'E' 'D' Time Time Time Time Time Period Period Period Period Period Data. Data. Data. Data. Data. TCC TCC TCC TCC TCC Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $38 $9C $9C $9C $9C dc dc dc dc dc $138 $19C $19C $19C $19C 'E' 'F' 'E' 'D' 'C' Time Time Time Time Time Period Period Period Period Period Data. Data. Data. Data. Data. TCC TCC TCC TCC TCC Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $38 $9C $9C $9C $9C dc dc dc dc dc $138 $19C $19C $19C $19C 'D' 'E' 'D' 'C' 'B' Time Time Time Time Time Period Period Period Period Period Data. Data. Data. Data. Data. TCC TCC TCC TCC TCC Reload Reload Reload Reload Reload Value Value Value Value Value = = = = = $38 $9C $9C $9C $9C dc dc $138 $138 'C' Time Period Data. TCC Reload Value = $38 ' ' Time Period Data. TCC Reload Value = $38 * * * * * * ************************************************************ * Time Counter Data ************************************************************ * org $0400 * *** 1st Cycle * dc $10F 'G' Time Counter Data. PCNT = $F dc $10F 'C' Time Counter Data. PCNT = $F dc $10F 'D' Time Counter Data. PCNT = $F dc $10F 'E' Time Counter Data. PCNT = $F dc $10F 'F' Time Counter Data. PCNT = $F * dc $10F 'G' Time Counter Data. PCNT = $F dc $10F 'C' Time Counter Data. PCNT = $F dc $10F ' ' Time Counter Data. PCNT = $F dc $10F 'C' Time Counter Data. PCNT = $F * dc $10F 'A' Time Counter Data. PCNT = $F dc $10F 'F' Time Counter Data. PCNT = $F Rev. 1.0, 03/99, page 79 of 209 dc dc dc $10F $10F $10F 'G' Time Counter Data. PCNT = $F 'A' Time Counter Data. PCNT = $F 'B' Time Counter Data. PCNT = $F dc dc dc dc $10F $10F $10F $10F 'C' 'C' ' ' 'C' Time Time Time Time Counter Counter Counter Counter Data. Data. Data. Data. PCNT PCNT PCNT PCNT = = = = $F $F $F $F dc dc dc dc dc $10F $10F $10F $10F $10F 'F' 'G' 'F' 'E' 'D' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F dc dc dc dc dc $10F $10F $10F $10F $10F 'E' 'F' 'E' 'D' 'C' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F dc dc dc dc dc $10F $10F $10F $10F $10F 'B' 'C' 'D' 'E' 'C' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F $10D 'D' Time Counter Data. PCNT = $D $10F $10F $10F $10F $10F 'G' 'C' 'D' 'E' 'F' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F $10F $10F $10F $10F 'G' 'C' ' ' 'C' Time Time Time Time Counter Counter Counter Counter Data. Data. Data. Data. PCNT PCNT PCNT PCNT = = = = $F $F $F $F $10F $10F $10F $10F $10F 'A' 'F' 'G' 'A' 'B' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F $10F $10F $10F 'C' Time Counter Data. PCNT = $F 'C' Time Counter Data. PCNT = $F ' ' Time Counter Data. PCNT = $F * * * * * dc * *** 2nd Cycle * dc dc dc dc dc * dc dc dc dc * dc dc dc dc dc * dc dc dc Rev. 1.0, 03/99, page 80 of 209 dc $10F 'C' Time Counter Data. PCNT = $F dc dc dc dc dc $10F $10F $10F $10F $10F 'F' 'G' 'F' 'E' 'D' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F dc dc dc dc dc $10F $10F $10F $10F $10F 'E' 'F' 'E' 'D' 'C' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F dc dc dc dc dc $10F $10F $10F $10F $10F 'D' 'E' 'D' 'C' 'B' Time Time Time Time Time Counter Counter Counter Counter Counter Data. Data. Data. Data. Data. PCNT PCNT PCNT PCNT PCNT = = = = = $F $F $F $F $F dc dc $10E $10F 'C' Time Counter Data. PCNT = $E ' ' Time Counter Data. PCNT = $F * * * * * end Rev. 1.0, 03/99, page 81 of 209 2.2 Stepping Motor Control Stepping Motor Control MCU: H4344/H4318/H4359/ H4369/H4889 Functions Used: R2/R8 Port and Timer B Specifications 1. The H4344/H4318/H4359/H4369/H4889 Series are used for stepping motor control. The stepping motor is of the permanent magnet type. 2. The stepping motor repeats a forward run, stop, and reverse run cycle. 3. The stepping motor is run for approximately 4 seconds in forward, in stop, and in reverse. 4. Figure 1 shows the example stepping motor control circuit used in this example task. Rev. 1.0, 03/99, page 82 of 209 12 V H4344/H4318/H4359/ H4369/H4889 B R2 /R8 * 3 3 A R2 /R8 2 B R2 /R82 1 1 A R20/R80 oB oB oA 5V oA Permanent magnet type stepping motor Stepping motor driver A B A B Note: * R20 to R23 pins are used in the H4344/H4889 Series. R80 to R83 pins are used in the H4318/H4359/H4369 Series. Figure 1 Example Stepping Motor Control Circuit Rev. 1.0, 03/99, page 83 of 209 Concepts 1. Stepping motors have superb starting, stopping, and positional control characteristics. 2. Stepping motors are synchronous motors that run in sync with the pulse signals output from a pulse oscillator. The motor is run in sync with the pulse signals, so, because there is no speed fluctuation due to load fluctuations, it will stop exactly at the intended position. 3. Stepping motors have the following features: a. The rotational angle of stepping motors is proportional to the number of input pulses. b. There is minimal angle error per step, and no cumulative error. c. Stepping motors have superb starting and stopping response. d. By direct connection to the motor shaft, it's possible to achieve synchronous rotation at extremely low speeds. e. The self holding capacity of stepping motors means that the stop position can be maintained. f. Superb control characteristics can be achieved using open-loop control. 4. The following shows the method of excitation (the method of turning on the current to the windings of the stepping motor in order) of a 2-phase stepping motor. * Single-phase excitation In this method, only one phase excitation is performed at all times. This results in lower power dissipation, but because of the small amount of damping, vibration is more likely. Figure 2 shows the excitation sequence in single-phase excitation. 1 2 3 4 5 6 7 8 9 A B A B CW* CCW Note: * CW: Clockwise (as seen from axis) CCW: Counterclockwise Figure 2 Excitation Sequence in Single-Phase Excitation Rev. 1.0, 03/99, page 84 of 209 * Two-phase excitation In this method, two-phase excitation is performed at all times. Twice the input is required over single-phase excitation, but the output torque is greater and damping is superior. Figure 3 shows the excitation sequence in two-phase excitation. 1 2 3 4 5 6 7 8 9 A B A B CW CCW Figure 3 Excitation Sequence in Two-Phase Excitation * 1-2-phase excitation In this method, single-phase excitation and two-phase excitation are alternated. When a stepping motor is driven using this method, the motor's step angle is halved. Because the step angle is halved, running is smoother and there is minimal vibration. Figure 4 shows the excitation sequence in 1-2-phase excitation. 1 2 3 4 5 6 7 8 9 A B A B CW CCW Figure 4 Excitation Sequence in 1-2-Phase Excitation Rev. 1.0, 03/99, page 85 of 209 5. In this example task, the stepping motor is controlled using two-phase excitation. Figure 5 shows an example of port output when the motor is run in the forward direction in this task. P20/P80 phase A P21/P81 phase B P22/P82 phase A P23/P83 phase B Timer B overflow cycle Figure 5 Example Port Output With Motor Running in Forward Direction Rev. 1.0, 03/99, page 86 of 209 Description of Functions 1. In this example task, we use a permanent magnet type of stepping motor (KP6P8-701 from Japan Servo Co., Ltd.) Table 1 shows the standard specifications of the KP6P8-701. Figure 6 shows the wiring. Table 1 KP6P8-701 Standard Specifications Item Unit Value Model No. -- KP6P8-701 No. of phases -- 2 Step angle deg./step 7.5 Voltage V 12 Current A/PHASE 0.33 Winding resistance /PHASE 36 Inductance mH/PHASE 28 Maximum holding torque gf*cm 800 Detente torque gf*cm 160 2 Rotor inertia gf*cm 23.7 Weight kg 0.25 Insulation class -- Type E or equivalent Insulation resistance -- 500 V DC 100 M 1 min. Dielectric strength -- 500 V AC 50 Hz 1 min. Operating temperature range C -10 to +45 Temperature rise deg 70 Lead specifications -- AWG #22 UL3266 Rev. 1.0, 03/99, page 87 of 209 Brown oA Red oA Black oB oB Orange Red Yellow Figure 6 KP6P8-701 Wiring Rev. 1.0, 03/99, page 88 of 209 2. This section describes the functions of the H4344/H4318/H4359/H4369/H4889 used in stepping motor control. Figure 7 is a block diagram of the functions used in this example task. H4344/H4318/H4359/H4369/H4889 functions Output pulse cycle setting Timer B reload timer Interrupt request by timer B overflow CPU Setting of output pulse cycle by writing reload value for timer counter B Pulse output Pulse output to motor (phases A, B, A, B) A B A P23/P83 P22/P82 P21/P81 P20/P80 R2 port/R8 port B Figure 7 Block Diagram of Functions H4344/H4318/H4359/H4369/H4889 Used in Stepping Motor Control * Timer B reload timer functions Sets the output pulse cycle. The output pulse cycle is determined from the timer counter B reload value. The reload value to be set is referenced from the data table. * R2 port/R8 port functions These are the output pins for the pulses (phases A, B, A, B) output to the stepping motor. Rev. 1.0, 03/99, page 89 of 209 3. The following describes the functions of timer B and the R2/R8 port. a. Figure 8 is a block diagram of timer B functions. System clock (4 MHz/4) EVNB pin edge detection Timer B functions (reload timer functions) Timer B interrupt cycle setting TCB input clock setting Timer mode register B1 (TMB1) /2048 /512 /128 /32 /8 /4 /2 Prescaler S (PSS) Selector TCB reload value setting Clock obtained by dividing system clock by 128 ((4 MHz/4) / 128 = 7.8125 kHz) Timer counter B (TCBL) Selection of reload timer function (TCBU) TCB reload value setting Timer write register B (TWBL) Selects division ratio of 128 (TWBU) TCB reload value setting TCB overflow Timer B interrupt request flag (IFTB) Interrupt request due to TCB overflow Figure 8 Block Diagram of Timer B Functions Rev. 1.0, 03/99, page 90 of 209 Selection of reload timer function and TCB input clock b. Timer B is an 8-bit multifunction timer (free running/event counter/reload timer/input *1 capture ). In this example task, timer B is used as a reload timer. Table 2 describes the timer B functions. Table 2 Timer B Functions Timer Mode Register B1 (TMB1) Function TMB1 is a 4-bit write-only register. It selects the timer B function (free-running/reload timer) and operating clock. TMB1 is initialized to $0 when reset and in stop mode. Timer Write Register BL, U (TWBL, TWBU) Function TWBL and TWBU form an 8-bit write-only register, which is made up of the lower digit (TWBL) and upper digit (TWBU). TWBL and TWBU are used for the initial TCB setting (the reload setting when operation as a reload timer). Timer Counter B (TCB) Function TCB is an 8-bit up-counter, which is incremented by the input internal clock. The TCB input clock is selected using bits TMB12 to TMB10 of TMB1. The value written to TWBL and TWBU is also written to TCB. When TCB overflows, the timer B interrupt request flag (IFTB) is set to "1". If, at this point, timer B is set as a reload timer, the value of TWBL and TWBU is written to this counter and the count starts from this value. TCB is initialized to $00 when reset and in stop mode. Prescaler S (PSS) Function PSS is an 11-bit counter to which the system clock is input when in active mode and *2 standby mode, and the subsystem clock is input when in subactive mode . PSS is initialized to $000 at a reset, and starts to count the system clock when the reset is *2 canceled. PSS operation is halted when reset, in stop mode, and in watch mode . However, it runs in other operating modes. The PSS output is shared by the internal peripheral modules, the division ratio being set independently for each of the internal peripheral modules. Timer B Interrupt Request Flag (IFTB) Function IFTB reflects the existence of the timer B interrupt request. When timer B overflows, IFTB is set to "1". IFTB can only be read/written to (only "0" can be written) using bit operation commands. Note that IFTB is not automatically cleared even when the interrupt is received, and must be cleared by writing "0" using software. IFTB is cleared at a reset and in stop mode. Timer B Interrupt Mask (IMTB) Function IMTB is the bit that masks IFTB. When IFTB is set to "1" and, additionally, IMTB is "0", a timer B interrupt request is sent to the CPU (when IE = "1"). If IFTB is set to "1" but IMTB is "1", no interrupt request is sent to the CPU and the timer B interrupt is held. IMTB can only be read or written to using bit operation commands. It is set to "1" at a reset and in stop mode. Notes: 1. Applies to H4318/H4359/H4369 Series only. In the H4344/H4889 Series, timer B has no input capture function. 2. Applies only to H4369/H4889 Series. Rev. 1.0, 03/99, page 91 of 209 c. Figure 9 is a block diagram of the R2 port functions used in the H4344; figure 10 is a block diagram of the R2 port functions used in the H4889; figure 11 is a block diagram of the R8 port functions used in the H4318/H4359/H4369. R2 port functions A phase output R20 pin B phase output R21 pin A phase output B phase output R22 pin R20 to R23 pin output data R2 port Port data register (PDR) R20 to R23 output pin function setting R23 pin Data control register (DCR2) R20 to R23 pin output data settings R20 to R23 I/O pin function switching Figure 9 Block Diagram of Port R2 Functions in H4344 Series R2 port functions R20/TOC pin A phase output R21/SCK pin B phase output R22/SI/SO pin A phase output B phase output R20 to R23 pin output data R2 R2 to R2 0 3 port output pin function setting R23 pin R20 to R22 I/O pin function setting Port data register (PDR) R20 to R23 output pin function setting Data control register (DCR2) Port mode register 3 (PMR3) R20 to R23 pin output data setting R20 to R23 I/O pin function switching R20/TOC, R21/SCK, R22/SI/SO pin function switching Figure 10 Block Diagram of Port R2 Functions in H4889 Series R8 port functions A phase output R80 pin B phase output R81 pin A phase output B phase output R82 pin R80 to R83 pin output data R8 port R83 pin R80 to R83 output pin function setting Port data register (PDR) Data control register (DCR8) Setting R80 to R83 pin output data Switching of R80 to R83 I/O pin functions Figure 11 Block Diagram of Port R8 Functions in H4318/H4359/H4369 Series Rev. 1.0, 03/99, page 92 of 209 d. The R2 port in the H4344/H4889 and the R8 port in the H4318/H4359/H4369 are 4-bit I/O ports. Both R2 and R8 are capable of 4-bit input using the LAR and LBR commands, and 4-bit output using the LRA and LRB commands. The output data is stored in the PDR of the respective pins. In this example task, the R20 to R23 pins in the H4344/H4889 Series and the R80 to R83 pins in the H4318/H4359/H4369 Series are set for output and used to output pulses to the stepping motor. Table 3 describes the functions of the R2 port in the H4344/H4889 and the R8 port in the H4318/H4359/H4369. Table 3 R2 Port Functions in H4344/H4889 and R8 Port Functions in H4318/H4359/H4369 Data Control Register R2 (DCR2) Function DCR2 switches the I/O pin function of the R2 port. When any bit of DCR2 is cleared to "0", the output buffer (CMOS) of the corresponding pin is turned OFF and the output is set to high impedance. When the respective bit of DCR2 is set to "1", the output buffer of the corresponding pin is set ON and the corresponding PDR value is output. Data Control Register R8 (DCR8) Function Note: Applies to H4318/H4359/H4369 Series DCR8 switches the I/O pin function of the R8 port. When any bit of DCR8 is cleared to "0", the output buffer (CMOS) of the corresponding pin is turned OFF and the output is set to high impedance. When the respective bit of DCR8 is set to "1", the output buffer of the corresponding pin is set ON and the corresponding PDR value is output. Port Mode Register 3 (PMR3) Function Note: Applies to H4344/H4889 Series Note: Applies to H4889 Series PMR3 is a 4-bit write-only register. Bits PMR33 to PMR30 switch the functions of the R2 port's dual-function pins. Port Data Register (PDR) Function The I/O pins of the R ports have built-in PDRs to store the output data. When the LRA and LRB commands are executed, the contents of the accumulator (A) and B register (B) are transferred to the PDR of the specified R port. When the corresponding bit of the DCR of the R port is "1", the output buffer of the appropriate pin is set ON and the value in the PDR is output via that pin. The PDR is initialized to $F at a reset. Rev. 1.0, 03/99, page 93 of 209 3. Table 4 shows the allocation of functions in this example task. Table 4 Function Allocation Function Function Allocation System clock The system clock is obtained by dividing the clock output from the system clock oscillator by 4. It is used for operating the CPU and internal peripheral modules. In this example task, a 4 MHz system clock oscillator is used, so the clock supplied to the CPU and internal peripheral modules is 1 MHz. The clock used by timer B is obtained by dividing the 1 MHz clock at PSS. PSS The clock input to timer B is obtained by dividing the system clock. The clock supplied to timer B is obtained by dividing the system clock by 128. TCB This is an 8-bit up-counter. The count starts from the value set in TWBL and TWBU. When an overflow occurs, IFTB is set to "1". After an overflow, the reload value set in TWBL and TWBU is set in TCB. TWBL, TWBU The TCB reload value is set in TWBL and TWBU. The reload value is determined from the pulse cycle to be output to the stepping motor. TMB1 TMB1 selects the reload timer function for timer B and a clock obtained by dividing the system clock by 128 as the TCB input clock. IFTB IFTB reflects the existence of a timer B interrupt request. The pulse output pin output level is set in the timer B interrupt processing. IMTB Enables/disables timer B interrupt requests. DCR2 (H4344/H4889) Sets the R20 to R23 pins (H4344/H4889) and R80 to R83 pins (H4318/H4359/H4369 Series) as output pins. DCR8 (H4318/H4359/ H4369) PMR3 (H4889) Sets the R20/TOC dual-function pin as an R20 I/O pin and the R21/SCK dual-function pin as an R21 pin. PDR Stores the output data for the R20 to R23/R80 to R83 pins. R20 to R23 pins Output pins for the pulse output to the stepping motor in the H4344/H4889 Series. R80 to R83 pins Output pins for the pulse output to the stepping motor in H4318/H4359/ H4369 Series. Rev. 1.0, 03/99, page 94 of 209 Description of Operation 1. Figure 12 is a flowchart of the stepping motor control. START Initial control Slue up control Constant control Clockwise (CW) Slue down control Stop control Stop Slue up control Constant control Counterclockwise (CCW) Slue down control Stop control Stop Figure 12 Flowchart of Stepping Motor Control Rev. 1.0, 03/99, page 95 of 209 2. Figure 13 shows the operating principle of initial control. 475.136 ms 29.696 ms TCB $FF $18 $00 Time R20/R80 phase A R21/R81 phase B R22/R82 phase A R23/R83 phase B R2/R8 port PDR $6 $C $9 $3 $6 $C $9 $3 $6 $C $9 $3 $6 $C Hardware processing Hardware processing 1. TCB overflow. 2. IFTB set to "1". 3. Value of TWCL and TWCU written to TCB. 1. TCB overflow. 2. IFTB set to "1". 3. Value of TWCL and TWCU written to TCB. Software processing 1. IFTB cleared to "0". 2. COUNT0 decremented. 3. Corresponding data stored in PDRs of P20 to P23/P80 to P83. Software processing 1. IFTB cleared to "0". 2. "1" set in IMTB to enable timer B interrupt requests. 3. "1" set in IE to enable interrupts. Figure 13 Operating Principle of Initial Control Rev. 1.0, 03/99, page 96 of 209 $9 $3 3. Figure 14 shows the operating principle of Slue up control when the motor is running clockwise. 30.592 ms TCB $FF 11.008 ms 8.832 ms 6.656 ms 4.480 ms $DD $CC $BB $AA $11 $00 Time R20/R80 phase A R21/R81 phase B R22/R82 phase A R23/R83 phase B Hardware processing 1. TCB overflow. 2. IFTB set to "1". 3. Value of TWCL and TWCU written to TCB. Hardware processing 1. TCB overflow. 2. IFTB set to "1". 3. Value of TWCL and TWCU written to TCB. Software processing Software processing 1. IFTB cleared to "0". 2. Corresponding data stored in PDRs of P20 to P23/P80 to P83. 3. Pattern command reads TCB reload value from data table and sets TWBL/TWBU. 1. IFTB cleared to "0". 2. Corresponding data stored in PDRs of P20 to P23/P80 to P83. 3. CNTADR set to $2, and COUNT2 to 0 set to $3E8. Figure 14 Operating Principle of Slue up Control When Motor Running Clockwise Rev. 1.0, 03/99, page 97 of 209 4. Figure 15 shows the operating principle of Constant control when the motor is running clockwise. 4.48 sec TCB $FF 4.480 ms $DD $00 Time R20/R80 phase A R21/R81 phase B R22/R82 phase A R23/R83 phase B Counter values of COUNT2, $3E8 $3E7 $3E6 $3E5 $3E4 $3E3 $3E2 . . . . . . $007 $006 $005 $004 $003 $002 $001 $000 COUNT1, COUNT0 Hardware processing 1. TCB overflow. 2. IFTB set to "1". 3. Value of TWCL and TWCU written to TCB. Software processing 1. IFTB cleared to "0". 2. Corresponding data stored in PDRs of P20 to P23/P80 to P83. 3. COUNT2 to COUNT0 decremented. Hardware processing 1. TCB overflow. 2. IFTB set to "1". 3. Value of TWCL and TWCU written to TCB. Software processing 1. IFTB cleared to "0". 2. Corresponding data stored in PDRs of P20 to P23/P80 to P83. 3. CNTADR set to $4, and PLPADR set to $D. Figure 15 Operating Principle of Constant Control When Motor Running Clockwise Rev. 1.0, 03/99, page 98 of 209 5. Figure 16 shows the operating principle of Slue down control when the motor is running clockwise. 4.480 ms 6.656 ms 8.832 ms 11.008 ms TCB $FF 30.592 ms $DD $CC $BB $AA $11 $00 Time R20/R80 phase A R21/R81 phase B R22/R82 phase A R23/R83 phase B Hardware processing 1. TCB overflow. 2. IFTB set to "1". 3. Value of TWCL and TWCU written to TCB. Software processing 1. IFTB cleared to "0". 2. Corresponding data stored in PDRs of P20 to P23/P80 to P83. 3. Pattern command reads TCB reload value from data table and sets TWBL/TWBU. Hardware processing 1. TCB overflow. 2. IFTB set to "1". 3. Value of TWCL and TWCU written to TCB. Software processing 1. IFTB cleared to "0". 2. Corresponding data stored in PDRs of P20 to P23/P80 to P83. 3. CNTADR set to $6, and COUNT2 to 0 set to $08D. Figure 16 Operating Principle of Slue down Control When Motor Running Clockwise Rev. 1.0, 03/99, page 99 of 209 6. Figure 17 shows the operating principle of Stop control when the motor is running clockwise. 4.14744 sec TCB $FF 29.696 ms $18 $00 Time R20/R80 phase A R21/R81 phase B R22/R82 phase A R23/R83 phase B Counter values of COUNT2, $08D $08C $08B $08A $089 $088 $087 . . . . . . $007 $006 $005 $004 $003 $002 $001 $000 COUNT1, COUNT0 Hardware processing Hardware processing 1. TCB overflow. 2. IFTB set to "1". 3. Value of TWCL and TWCU written to TCB. 1. TCB overflow. 2. IFTB set to "1". 3. Value of TWCL and TWCU written to TCB. Software processing 1. IFTB cleared to "0". 2. COUNT2 to COUNT0 decremented. Software processing 1. IFTB cleared to "0". 2. CNTADR set to $0, and PLPADR set to $1. 3. FOWRDF set to "0". Figure 17 Operating Principle of Stop Control When Motor Running Clockwise Rev. 1.0, 03/99, page 100 of 209 7. Figure 18 shows the operating principle of Slue up control when the motor is running counterclockwise. TCB $FF 30.592 ms 11.008 ms 8.832 ms 6.656 ms 4.480 ms $DD $CC $BB $AA $11 $00 Time R20/R80 phase A R21/R81 phase B R22/R82 phase A R23/R83 phase B Hardware processing 1. TCB overflow. 2. IFTB set to "1". 3. Value of TWCL and TWCU written to TCB. Software processing 1. IFTB cleared to "0". 2. Corresponding data stored in PDRs of P20 to P23/P80 to P83. 3. Pattern command reads TCB reload value from data table and sets TWBL/TWBU. Hardware processing 1. TCB overflow. 2. IFTB set to "1". 3. Value of TWCL and TWCU written to TCB. Software processing 1. IFTB cleared to "0". 2. Corresponding data stored in PDRs of P20 to P23/P80 to P83. 3. CNTADR set to $2, and COUNT2 to 0 set to $3E8. Figure 18 Operating Principle of Slue up Control When Motor Running Counterclockwise Rev. 1.0, 03/99, page 101 of 209 8. Figure 19 shows the operating principle of Constant control when the motor is running counterclockwise. 4.224 sec TCB $FF 4.224 ms $DF $00 Time R20/R80 phase A R21/R81 phase B R22/R82 phase A R23/R83 phase B Counter values of COUNT2, $3E8 $3E7 $3E6 $3E5 $3E4 $3E3 $3E2 . . . . . . $007 $006 $005 $004 $003 $002 $001 $000 COUNT1, COUNT0 Hardware processing 1. TCB overflow. 2. IFTB set to "1". 3. Value of TWCL and TWCU written to TCB. Software processing 1. IFTB cleared to "0". 2. Corresponding data stored in PDRs of P20 to P23/P80 to P83. 3. COUNT2 to COUNT0 decremented. Hardware processing 1. TCB overflow. 2. IFTB set to "1". 3. Value of TWCL and TWCU written to TCB. Software processing 1. IFTB cleared to "0". 2. Corresponding data stored in PDRs of P20 to P23/P80 to P83. 3. CNTADR set to $4, and PLPADR set to $D. Figure 19 Operating Principle of Constant Control When Motor Running Counterclockwise Rev. 1.0, 03/99, page 102 of 209 9. Figure 20 shows the operating principle of Slue down control when the motor is running counterclockwise. 4.480 ms 6.656 ms 8.832 ms 11.008 ms TCB $FF 30.592 ms $DD $CC $BB $AA $11 $00 Time R20/R80 phase A R21/R81 phase B R22/R82 phase A R23/R83 phase B Hardware processing 1. TCB overflow. 2. IFTB set to "1". 3. Value of TWCL and TWCU written to TCB. Software processing 1. IFTB cleared to "0". 2. Corresponding data stored in PDRs of P20 to P23/P80 to P83. 3. Pattern command reads TCB reload value from data table and sets TWBL/TWBU. Hardware processing 1. TCB overflow. 2. IFTB set to "1". 3. Value of TWCL and TWCU written to TCB. Software processing 1. IFTB cleared to "0". 2. Corresponding data stored in PDRs of P20 to P23/P80 to P83. 3. CNTADR set to $6, and COUNT2 to 0 set to $08D. Figure 20 Operating Principle of Slue down Control When Motor Running Counterclockwise Rev. 1.0, 03/99, page 103 of 209 10. Figure 21 shows the operating principle of Stop control when the motor is running counterclockwise. 4.14744 sec TCB $FF 29.696 ms $18 $00 Time R20/R80 phase A R21/R81 phase B R22/R82 phase A R23/R83 phase B Counter values of COUNT2, $08D $08C $08B $08A $089 $088 $087 . . . . . . $007 $006 $005 $004 $003 $002 $001 $000 COUNT1, COUNT0 Hardware processing Hardware processing 1. TCB overflow. 2. IFTB set to "1". 3. Value of TWCL and TWCU written to TCB. 1. TCB overflow. 2. IFTB set to "1". 3. Value of TWCL and TWCU written to TCB. Software processing Software processing 1. IFTB cleared to "0". 2. COUNT2 to COUNT0 decremented. 1. IFTB cleared to "0". 2. CNTADR set to $0, and PLPADR set to $1. 3. FOWRDF set to "0". Figure 21 Operating Principle of Stop Control When Motor Running Counterclockwise Rev. 1.0, 03/99, page 104 of 209 Description of Functions 1. Description of Modules Table 5 describes the modules used in this example task. Table 5 Description of Modules Module Label Function Main routine STEPMN This routine makes the initial stack pointer, RAM, I/O port, and timer B settings, performs initial stepping motor control, and enables interrupts. Timer B interrupt processing routine STEPCNT This routine saves the contents of the registers, makes table branch settings, and restores the registers. Pulse output subroutine table PLOUT Branches to the subroutine for pulse output (POUT). Decrement subroutine table DEC Branches to the subroutine for decrementing the count (DECR). Pulse output POUT Rotates the output pulse data and stores it in the PDR of the output port. Decrement DECR Decrements the 12-bit counter made up of COUNT2, COUNT1, and COUNT0. Slue up control SLUP Reads the timer B reload value data using the pattern command and, by increasing the output pulse cycle, performs Slue up control of the stepping motor. Constant control CNST Performs Constant control of the stepping motor by maintaining the output pulse cycle at a constant rate. Slue down control SLDOWN Reads the timer B reload value data using the pattern command and, by decreasing the output pulse cycle, performs Slue down control of the stepping motor. Stop control STOP Performs Stop control by stopping the pulse output. 2. Description of Arguments No arguments are used in this example task. Rev. 1.0, 03/99, page 105 of 209 3. Description of Internal Registers a. Table 6 describes the internal registers used in the H4344. Table 6 Internal Registers Used in H4344/H4318/H4359/H4369 Register Description RAM Address Setting IE Interrupt Enable Flag 0, $000 1 1, $000 0 0, $002 0 1, $001 1 $009 $A $00A $8 $00B $1 This flag controls reception of all interrupts by the CPU. RSP * When IE = "0", CPU reception of all interrupts is disabled. * When IE = "1", CPU reception is enabled. Reset Stack Pointer Clearing RSP to "0" initializes the stack pointer. IFTB Timer B Interrupt Request Flag Reflects the existence of a timer B interrupt request. IMTB * When IFTB = "0", no timer B interrupt is requested. * When IFTB = "1", a timer B interrupt is requested. Timer B Interrupt Mask This bit masks IFTB. TMB1 * When IMTB = "0", IFTB is enabled. * When IMTB = "1", IFTB is masked. Timer Mode Register B1 TMB13 selects the timer B functions. TMB12 to TMB10 select the operating clock. * TWBL When TMB13 = "1", TMB12 = "0", TMB11 = "1", and TMB10 = "0", timer B functions as a reload timer, and the operating clock for timer B is set to the system clock divided by 128. Timer Write Register BL Sets the lower digit of the TCB reload value. TWBU Timer Write Register BU Sets the upper digit of the TCB reload value. Rev. 1.0, 03/99, page 106 of 209 Table 6 Internal Registers Used in H4344/H4318/H4359/H4369 (cont) Register Description RAM Address Setting TMB2 Timer Mode Register B2 $026 $0 $027 $2 $032 $F $038 $F Sets the input capture function and selects the detection edge for EVNB pin input. * When TMB22 = "0", timer B functions as a freerunning/reload timer. * When TMB22 = "1", timer B functions as an input capture timer. Note: TMB22 is not used in the H4344. * SSR1 When TMB21 = "0" and TMB20 = "0", no edge detection is performed on EVNB pin input. System Clock Selection Register 1 Sets the oscillation frequency of the system clock, sets the division for the subsystem clock frequency, and sets the subsystem clock oscillation in stop mode. * When SSR11 = "0", the system clock oscillation frequency is set to 0.4 to 1MHz. * When SSR11 = "1", the system clock oscillation frequency is set to 1.6 to 5 MHz. Note: Applies only to H4369. DCR2 Data Control Register R2 Controls the ON/OFF switching of the R2 port output buffer. * When DCR23 to DCR20 = "0", the output buffers of R23 to R20 are OFF and R23 to R20 pins are set to high impedance. * When DCR23 to DCR20 = "1", the output buffers of R23 to R20 are ON and the values of the corresponding PDRs are output. Note: Applies to H4344 only. DCR8 Data Control Register R8 Controls the ON/OFF switching of the R8 port output buffer. * When DCR83 to DCR80 = "0", the output buffers of R83 to R80 are OFF, and R83 to R80 pins are set to high impedance. * When DCR83 to DCR80 = "1", the output buffers of R83 to R80 are ON and the values of the corresponding PDRs are output. Note: Applies to H4318/H4359/H4369 only. Rev. 1.0, 03/99, page 107 of 209 b. Table 7 describes the internal registers used in the H4889. Table 7 Internal Registers Used in H4889 Register Description RAM Address Setting IE Interrupt Enable Flag 0, $000 1 1, $000 0 2, $002 0 3, $002 1 $004 $2 $00B $0 This flag controls reception of all interrupts by the CPU. RSP * When IE = "0", CPU reception of all interrupts is disabled. * When IE = "1", CPU reception is enabled. Reset Stack Pointer Clearing RSP to "0" initializes the stack pointer. IFTB Timer B Interrupt Request Flag Reflects the existence of a timer B interrupt request. IMTB * When IFTB = "0", no timer B interrupt is requested. * When IFTB = "1", a timer B interrupt is requested. Timer B Interrupt Mask This bit masks IFTB. SSR * When IMTB = "0", IFTB is enabled. * When IMTB = "1", IFTB is masked. System Clock Selection Register Selects the system clock oscillation frequency, subsystem clock frequency division, and, in stop mode, the subsystem clock oscillation and system clock frequency division ratio. PMR3 * When SSR1 = "0", the system clock oscillation frequency is set to 0.4 to 1 MHz. * When SSR1 = "1", the system clock oscillation frequency is set to 1.6 to 4.5 MHz. Port Mode Register 3 Sets the functions of the R22/SI/SO pin, R21/SCK pin, and R20/TOC pin. * When PMR33 = "0", PMR32 = "0", PRM31 = "0" and PRM30 = "0", the R22/SI/SO pin functions as R22 I/O pin, R21/SCK functions as R21 I/O pin, and R20/TOC functions as R20 I/O pin. Rev. 1.0, 03/99, page 108 of 209 Table 7 Internal Registers Used in H4889 (cont) Register Description RAM Address Setting TMB1 Timer Mode Register B1 $010 $A $011 $0 $012 $8 $013 $1 $03C $F TMB13 selects the timer B function, TMB12 to TMB10 select the operating clock. * TMB2 When TMB13 = "1", TMB12 = "0", TMB11 = "1", and TMB10 = "0", timer B functions as a reload timer, and the timer B clock is the system clock divided by 128. Timer Mode Register B2 Sets the timer B output mode and selects the detection edge for EVNB pin input. TWBL * When TMB22 = "0", timer B output is set to toggle waveform. * When TMB22 = "1", timer B output is set to PWM. * When TMB21 = "0" and TMB20 = "0", no edge detection is performed on EVNB pin input. Timer Write Register BL Sets the lower digit of the TCB reload value. TWBU Timer Write Register BU Sets the upper digit of the TCB reload value. DCR8 Data Control Register 8 Controls the ON/OFF switching of the R8 port output buffer. * When DCR83 to DCR80 = "0", the output buffers of R83 to R80 are OFF, and the output pins are set to high impedance. * When DCR83 to DCR80 = "1", the output buffers of R83 to R80 are ON and the values of the corresponding PDRs are output. Rev. 1.0, 03/99, page 109 of 209 4. Description of RAM Table 8 describes the RAM used in this example task. Table 8 RAM Label Function AESC RAM Address Module Stores the contents of the accumulator during timer B interrupt processing. $040 STEPCNT BESC Stores the contents of the B register during timer B interrupt processing. $041 STEPCNT XESC Stores the contents of the X register during timer B interrupt processing. $043 STEPCNT YESC Stores the contents of the Y register during timer B interrupt processing. $044 STEPCNT PLDATA Stores the data for the pulse output from the port. $050 STEPMN, POUT CNTADR Stores the contents of the accumulator used for specifying the address when executing a table branch command. $051 STEPMN, SLUP, CNST, SLDOWN, STOP, STEPCNT PLPADR Stores the contents of the accumulator used for specifying the address when executing a pattern command. $052 STEPMN, SLUP, CNST, SLDOWN, STOP COUNT0 Stores bits 3 to 0 of the 12-bit counter made up of COUNT0, COUNT1, COUNT2. $053 STEPMN, SLUP, SLDOWN, DECR COUNT1 Stores bits 7 to 4 of the 12-bit counter made up of COUNT0, COUNT1, COUNT2. $054 SLUP, SLDOWN, DECR COUNT2 Stores bits 11 to 8 of the 12-bit counter made up of COUNT0, COUNT1, COUNT2. $055 SLUP, SLDOWN, DECR FOWRDF This flag is used to identify the direction (CW or CCW) of the stepping motor. 0, $05F STEPMN, STOP, POUT Rev. 1.0, 03/99, page 110 of 209 Flow charts 1. H4344 a. Main Routine 1 STEPMN Set COUNT0 to $F Reset stack pointer PLOUT Initialize PLDATA to $3 Initialize CNTADR to $0 IFTB = "1"? No Initialize FOWRDF to "1" Yes Initialize PLPADR to $1 Clear IFTB to "0" Set R2 port PDR to $0 and initialize R2 port Add $F to COUNT0 to decrement COUNT0 Set DCR2 to $F and set R20 to R23 I/O pins to function as output pins No COUNT0 = 0? Yes Set TMB1 to $A, timer B to function as reload timer, and TCB input clock to system clock divided by 128 Set TWBL to $8 and TWBU to $1 to set the TCB reload value to $18 Clear IFTB to "0" Clear IMTB to "0" to enable timer B interrupts Set IE to "1" to enable interrupts Clear IFTB to "0" Use BR command to set ST to "1" 1 Rev. 1.0, 03/99, page 111 of 209 b. Timer B Interrupt Processing Routine STEPCNT Clear IFTB to "0" Save registers Make table branch using value of CNTADR 2 Restore registers RTNI c. Pulse Output PLOUT POUT d. Decrement DEC DECR Rev. 1.0, 03/99, page 112 of 209 e. Pulse Output POUT Store content of PLDATA in accumulator FOWRDF = "1"? Yes No No Store $8 in B register Store $1 in B register Clear CA to "0" Clear CA to "0" Link accumulator and CA and shift 1 bit right Link accumulator and CA and rotate 1 bit left CA = "1"? Yes No CA = "1"? Yes Take the logical OR of the contents of accumulator and B register and store result in accumulator Take the logical OR of the contents of the accumulator and B register and store result in accumulator Set content of accumulator in PDR of R2 port Set content of accumulator in PDR of R2 port Store content of accumulator in PLDATA Store content of accumulator in PLDATA RTN Rev. 1.0, 03/99, page 113 of 209 f. Decrement DECR Clear CA to "0" Set $0 in accumulator Subtract content of accumulator and CA from COUNT0, store the result in the accumulator, and store NB in CA Store content of accumulator in COUNT0 Set $0 in accumulator Subtract content of accumulator and CA from COUNT1, store the result in the accumulator, and store NB in CA Store content of accumulator in COUNT1 Set $0 in accumulator Subtract content of accumulator and CA from COUNT2, store the result in the accumulator, and store NB in CA Store content of accumulator in COUNT2 RTN Rev. 1.0, 03/99, page 114 of 209 g. Slue Up Control SLUP Use BR command to set ST to "1" PLOUT Store content of PLPADR in accumulator Set $0 in B register Use P command to read output pulse cycle data from data table and store in accumulator and B register Store content of B register in accumulator A <= $0? Yes No Set content of accumulator in TWBL Set CNTADR to $2 Set COUNT0 to $8 Store content of B register in accumulator Set COUNT1 to $E Set content of B register in TWBU Store content of PLPADR in accumulator Set COUNT2 to $3 2 Increment content of accumulator Store content of accumulator in PLPADR 2 Rev. 1.0, 03/99, page 115 of 209 h. Constant Control CNST Use BR command to set ST to "1" PLOUT DEC ST = "1"? No Set CNTADR to $4 Set PLPADR to $D 2 Rev. 1.0, 03/99, page 116 of 209 Yes 2 i. Slow Down Control SLDOWN Use BR command to set ST to "1" PLOUT Store content of PLPADR in accumulator Set B register to $0 Use the P command to read the output pulse cycle data from the data table, and store in accumulator and B register Store contents of B register in accumulator A <= $0? Yes No Set contents of accumulator in TWBL Set CNTADR to $6 Set COUNT0 to $D Store contents of B register in accumulator Set contents of B register in TWBU Store contents of PLPADR in accumulator Set COUNT1 to $8 Set COUNT2 to $0 2 Decrement contents of accumulator Store contents of accumulator in PLPADR 2 Rev. 1.0, 03/99, page 117 of 209 j. Stop Control STOP DEC ST = "1"? Yes 2 No Set CNTADR to $0 Set PLPADR to $1 FOWRDF = "1"? Yes No Set FOWRDF to "1" Clear FOWRDF to "0" 2 2 Rev. 1.0, 03/99, page 118 of 209 2. H4318/H4359/H4369 a. Main Routine 1 STEPMN Set COUNT0 to $F Reset stack pointer Set SSR11 to "1" to set the system clock to 1.6 to 5.0MHz PLOUT * Initialize PLDATA to $3 IFTB = "1"? No Yes Initialize CNTADR to $0 Clear IFTB to "0" Initialize FOWRDF to "1" Add $F to COUNT0 to decrement COUNT0 Initialize PLPADR to $1 No Set R8 port PDR to $0 and initialize R8 port COUNT0 = 0? Yes Set DCR8 to $F and set R80 to R83 I/O pins to function as output pins Clear IFTB to "0" Clear IMTB to "0" to enable timer B interrupts Set TMB1 to $A, timer B to function as reload timer, and TCB input clock to system clock divided by 128 Set IE to "1" to enable interrupts Set TWBL to $8 and TWBU to $1 to set the TCB reload value to $18 Clear IFTB to "0" Use BR command to set ST to "1" 1 Note: * Applies to H4369 only Rev. 1.0, 03/99, page 119 of 209 b. Timer B Interrupt Processing Routine STEPCNT Clear IFTB to "0" Save registers Make table branch using value of CNTADR 2 Restore registers RTNI c. Pulse Output PLOUT POUT d. Decrement DEC DECR Rev. 1.0, 03/99, page 120 of 209 e. Pulse Output POUT Store content of PLDATA in accumulator FOWRDF = "1"? Yes No No Store $8 in B register Store $1 in B register Clear CA to "0" Clear CA to "0" Link accumulator and CA and shift 1 bit right Link accumulator and CA and rotate 1 bit left CA = "1"? Yes No CA = "1"? Yes Take the logical OR of the contents of accumulator and B register and store result in accumulator Take the logical OR of the contents of the accumulator and B register and store result in accumulator Set content of accumulator in PDR of R8 port Set content of accumulator in PDR of R8 port Store content of accumulator in PLDATA Store content of accumulator in PLDATA RTN Rev. 1.0, 03/99, page 121 of 209 f. Decrement DECR Clear CA to "0" Set $0 in accumulator Subtract content of accumulator and CA from COUNT0, store the result in the accumulator, and store NB in CA Store content of accumulator in COUNT0 Set $0 in accumulator Subtract content of accumulator and CA from COUNT1, store the result in the accumulator, and store NB in CA Store content of accumulator in COUNT1 Set $0 in accumulator Subtract content of accumulator and CA from COUNT2, store the result in the accumulator, and store NB in CA Store content of accumulator in COUNT2 RTN Rev. 1.0, 03/99, page 122 of 209 g. Slue Up Control SLUP Use BR command to set ST to "1" PLOUT Store content of PLPADR in accumulator Set $0 in B register Use P command to read output pulse cycle data from data table and store in accumulator and B register Store content of B register in accumulator A <= $0? Yes No Set content of accumulator in TWBL Set CNTADR to $2 Set COUNT0 to $8 Store content of B register in accumulator Set COUNT1 to $E Set content of B register in TWBU Store content of PLPADR in accumulator Set COUNT2 to $3 2 Increment content of accumulator Store content of accumulator in PLPADR 2 Rev. 1.0, 03/99, page 123 of 209 h. Constant Control CNST Use BR command to set ST to "1" PLOUT DEC ST = "1"? No Set CNTADR to $4 Set PLPADR to $D 2 Rev. 1.0, 03/99, page 124 of 209 Yes 2 i. Slue Down Control SLDOWN Use BR command to set ST to "1" PLOUT Store content of PLPADR in accumulator Set B register to $0 Use the P command to read the output pulse cycle data from the data table, and store in accumulator and B register Store contents of B register in accumulator A <= $0? Yes No Set contents of accumulator in TWBL Set CNTADR to $6 Set COUNT0 to $D Store contents of B register in accumulator Set contents of B register in TWBU Store contents of PLPADR in accumulator Set COUNT1 to $8 Set COUNT2 to $0 2 Decrement contents of accumulator Store contents of accumulator in PLPADR 2 Rev. 1.0, 03/99, page 125 of 209 j. Stop Control STOP DEC ST = "1"? Yes 2 No Set CNTADR to $0 Set PLPADR to $1 FOWRDF = "1"? Yes No Set FOWRDF to "1" Clear FOWRDF to "0" 2 2 Rev. 1.0, 03/99, page 126 of 209 3. H4889 a. Main Routine 1 STEPMN Set COUNT0 to $F Reset stack pointer PLOUT Set SSR1 to "1" to set the system clock to 1.6 to 4.5 MHz Initialize PLDATA to $3 IFTB = "1"? No Yes Initialize CNTADR to $0 Clear IFTB to "0" Initialize FOWRDF to "1" Add $F to COUNT0 to decrement COUNT0 Initialize PLPADR to $1 No Set R2 port PDR to $0 and initialize R2 port COUNT0 = 0? Yes Set DCR2 to $F and set R20 to R23 I/O pins to function as output pins Clear IFTB to "0" Clear IMTB to "0" to enable timer B interrupts Set TMB1 to $A, timer B to function as reload timer, and TCB input clock to system clock divided by 128 Set IE to "1" to enable interrupts Set TWBL to $8 and TWBU to $1 to set the TCB reload value to $18 Clear IFTB to "0" Use BR command to set ST to "1" 1 Rev. 1.0, 03/99, page 127 of 209 b. Timer B Interrupt Processing Routine STEPCNT Clear IFTB to "0" Save registers Make table branch using value of CNTADR 2 Restore registers RTNI c. Pulse Output PLOUT POUT d. Decrement DEC DECR Rev. 1.0, 03/99, page 128 of 209 e. Pulse Output POUT Store content of PLDATA in accumulator FOWRDF = "1"? Yes No No Store $8 in B register Store $1 in B register Clear CA to "0" Clear CA to "0" Link accumulator and CA and rotate 1 bit right Link accumulator and CA and rotate 1 bit left CA = "1"? Yes No CA = "1"? Yes Take the logical OR of the contents of accumulator and B register and store result in accumulator Take the logical OR of the contents of the accumulator and B register and store result in accumulator Set content of accumulator in PDR of R2 port Set content of accumulator in PDR of R2 port Store content of accumulator in PLDATA Store content of accumulator in PLDATA RTN Rev. 1.0, 03/99, page 129 of 209 f. Decrement DECR Clear CA to "0" Set $0 in accumulator Subtract content of accumulator and CA from COUNT0, store the result in the accumulator, and store NB in CA Store content of accumulator in COUNT0 Set $0 in accumulator Subtract content of accumulator and CA from COUNT1, store the result in the accumulator, and store NB in CA Store content of accumulator in COUNT1 Set $0 in accumulator Subtract content of accumulator and CA from COUNT2, store the result in the accumulator, and store NB in CA Store content of accumulator in COUNT2 RTN Rev. 1.0, 03/99, page 130 of 209 g. Slue Up Control SLUP Use BR command to set ST to "1" PLOUT Store content of PLPADR in accumulator Set $0 in B register Use P command to read output pulse cycle data from data table and store in accumulator and B register Store content of B register in accumulator A <= $0? Yes No Set content of accumulator in TWBL Set CNTADR to $2 Set COUNT0 to $8 Store content of B register in accumulator Set COUNT1 to $E Set content of B register in TWBU Store content of PLPADR in accumulator Set COUNT2 to $3 2 Increment content of accumulator Store content of accumulator in PLPADR 2 Rev. 1.0, 03/99, page 131 of 209 h. Constant Control CNST Use BR command to set ST to "1" PLOUT DEC ST = "1"? No Set CNTADR to $4 Set PLPADR to $D 2 Rev. 1.0, 03/99, page 132 of 209 Yes 2 i. Slow Down Control SLDOWN Use BR command to set ST to "1" PLOUT Store content of PLPADR in accumulator Set B register to $0 Use the P command to read the output pulse cycle data from the data table, and store in accumulator and B register Store contents of B register in accumulator A <= $0? Yes No Set contents of accumulator in TWBL Set CNTADR to $6 Set COUNT0 to $D Store contents of B register in accumulator Set contents of B register in TWBU Store contents of PLPADR in accumulator Set COUNT1 to $8 Set COUNT2 to $0 2 Decrement contents of accumulator Store contents of accumulator in PLPADR 2 Rev. 1.0, 03/99, page 133 of 209 j. Stop Control STOP DEC ST = "1"? Yes 2 No Set CNTADR to $0 Set PLPADR to $1 FOWRDF = "1"? Yes No Set FOWRDF to "1" Clear FOWRDF to "0" 2 2 Rev. 1.0, 03/99, page 134 of 209 Program Listing 1. H4344 ************************************************************ * * H400 Series Application Note * - Application Chapter * * 'Stepping Motor Control' * * Function * : Timer B Reload Timer * : I/O Port * * MCU : H4344 * * External Clock : 4MHz * Internal Clock : 1MHz * ************************************************************ * ************************************************************ * Symbol Definition ************************************************************ * IE equ 0,$000 Interrupt Enable Flag RSP equ 1,$000 Reset Stack Pointer IF0 equ 2,$000 INT0 Interrupt Request Flag IM0 equ 3,$000 INT0 Interrupt Mask * IFTB equ 0,$002 TIMER B Interrupt Request Flag IMTB equ 1,$002 TIMER B Interrupt Mask IFTC equ 2,$002 TIMER C Interrupt Request Flag IMTC equ 3,$002 TIMER C Interrupt Mask * IFAD equ 0,$003 A/D Interrupt Request Flag IMAD equ 1,$003 A/D Interrupt Mask IFS equ 2,$003 SCI Interrupt Request Flag IMS equ 3,$003 SCI Interrupt Mask * PMRA equ $004 Port Mode Register A SMR equ $005 Serial Mode Register SRL equ $006 Serial Data Register L SRU equ $007 Serial Data Register U * TMB1 equ $009 Timer Mode Register B1 TRBL equ $00A Timer Read Register BL TWBL equ $00A Timer Write register BL TRBU equ $00B Timer Read Register BU TWBU equ $00B Timer Write Register BU Rev. 1.0, 03/99, page 135 of 209 MIS equ $00C Miscellaneous Register TMC equ $00D Timer Mode Register C TRCL equ $00E Timer Read Register CL TWCL equ $00E Timer Write Register CL TRCU equ $00F Timer Read Register CU TWCU equ $00F Timer Write Register CU * ACR equ $016 A/D Control Register ADRL equ $017 A/D Data Register L ADRU equ $018 A/D Data Register U AMR1 equ $019 A/D Mode Register 1 AMR2 equ $01A A/D Mode Register 2 * WDON equ 1,$020 Watchdog on Flag ADSF equ 2,$020 A/D Start Flag * IAOF equ 2,$021 IAD off Flag RAME equ 3,$021 RAM Enable Flag * PMRB equ $024 Port Mode register B PMRC equ $025 Port Mode Register C TMB2 equ $026 Timer Mode Register B2 DCD0 equ $02C Data Control Register D0 DCD1 equ $02D Data Control Register D1 * DCR0 equ $030 Data Control Register R0 DCR1 equ $031 Data Control Register R1 DCR2 equ $032 Data Control Register R2 DCR3 equ $033 Data Control Register R3 * ************************************************************ * RAM Allocation ************************************************************ * AESC equ $040 A Escape RAM Area BESC equ $041 B Escape RAM Area WESC equ $042 W Escape RAM Area XESC equ $043 X Escape RAM Area YESC equ $044 Y Escape RAM Area SXESC equ $045 SPX Escape RAM Area SYESC equ $046 SPY Escape RAM Area * PLDATA equ $050 Pulse Data ($3 <-> $6 <-> $C <-> $9) CNTADR equ $051 Control Process Address PLPADR equ $052 Pulse Period Address COUNT0 equ $053 Counter 0 COUNT1 equ $054 Counter 1 COUNT2 equ $055 Counter 2 * FOWRDF equ 0,$05F Forward Flag( 1:Forward, 0:Reverce ) * Rev. 1.0, 03/99, page 136 of 209 ************************************************************ * Vector Address ************************************************************ * org $0000 * JMPL STEPMN Reset Interrupt JMPL STEPMN INT0 Interrupt * org $0008 * JMPL STEPCNT Timer B Interrupt JMPL STEPMN Timer C Interrupt JMPL STEPMN A/D Interrupt JMPL STEPMN SCI Interrupt * ************************************************************ * STEPMN : Main Program ************************************************************ * org $1000 * STEPMN REMD RSP Stack Pointer Reset * LMID $3,PLDATA Initialize Pulse Data LMID $0,CNTADR Initialize Control Process Address SEMD FOWRDF Set Forward Mode LMID $1,PLPADR Initialize Pulse Period Address * LAI $0 Initialize R2 Port Data Register LRA $2 LMID $F,DCR2 Initialize R2 Port Output Terminal Function * LMID $A,TMB1 Initialize Timer B (128tcyc,Reload Timer ON) LMID $8,TWBL Initialize Period 29.696ms LMID $1,TWBU REMD IFTB Clear Timer B Interrupt Request Flag * BR *+1 Set Status Flag LMID $F,COUNT0 Initialize Counter 0 STMN10 CAL PLOUT Subroutine Call 'PLOUT' * STMN11 TMD IFTB 29.696ms Pass ? BRS STMN12 Yes. Branch to STMN12 BRS STMN11 No. Branch to STMN11 * STMN12 REMD IFTB Clear IFTB LAMD COUNT0 Load Counter 0 AI $F Decrement Counter 0 LMAD COUNT0 Save Counter 0 BRS STMN10 16 times End ? No. Branch to STMN10 Rev. 1.0, 03/99, page 137 of 209 * REMD REMD SEMD IFTB IMTB IE Clear Timer B Interrupt Request Flag Timer B Interrupt Enable Interrupt Enable * STMN99 BRS STMN99 Infinite Loop * ************************************************************ * STEPCNT : Stepping Motor Control ************************************************************ * STEPCNT REMD IFTB Clear Timer B Interrupt Request Flag * LMAD AESC Store Accumulator LAB LMAD BESC Store B Register XSPX LASPX LMAD XESC Store X Register XSPX LAY LMAD YESC Store Y Register * LAMD CNTADR Load Control Process Address LBI $0 TBR $2 Table Branch (CNTADR=0:SLUP, 2:CNST, 4:SLDOWN, 6:STOP) * STCNT90 LAMD YESC Restore Y Register LYA LAMD XESC Restore X Register LXA LAMD BESC Restore B Register LBA LAMD AESC Restore Accumulator * RTNI Return from Interrupt * ************************************************************ * SLUP : Slue up Control ************************************************************ * SLUP BR *+1 Set Status Flag CAL PLOUT Subroutine Jump to 'PLOUT' LAMD PLPADR Load Pulse Period Address LBI $0 P $1 Pattern Generation 'Output Pulse Period' LAB ALEI $0 A <= $0 ? BRS SLUP10 Yes. Branch to SLUP10 LMAD TWBL Set Pulse Period Data Lower LAB Rev. 1.0, 03/99, page 138 of 209 * SLUP10 LMAD LAMD AI LMAD BR BRS TWBU PLPADR $1 PLPADR *+1 STCNT90 Set Pulse Period Data Upper Load Pulse Period Address Increment Pulse Period Address Save Pulse Period Address LMID LMID LMID LMID BRS $2,CNTADR $8,COUNT0 $E,COUNT1 $3,COUNT2 STCNT90 Set Constant Control Mode Initialize Counter0 to COUNT0 12-bit Counter = H'3E8 = D'1000 Branch to STCNT90 Branch to STCNT90 * ************************************************************ * CNST : Constant Control ************************************************************ * CNST BR *+1 Set Status Flag CAL PLOUT Subroutine Jump to 'PLOUT' * CAL DEC Subroutine Jump to 'DEC' BRS STCNT90 Counter = H'000 ? Yes. Branch to STCNT90 * LMID $4,CNTADR Set Slue down Control Mode LMID $D,PLPADR Set Pulse Period Address BRS STCNT90 Branch to STCNT90 * ************************************************************ * STDOWN : Slue down Control ************************************************************ * SLDOWN BR *+1 Set Status Flag CAL PLOUT Subroutine Jump to 'PLOUT' LAMD PLPADR Load Pulse Period Address LBI $0 P $1 Pattern Generation 'Output Pulse Period' LAB ALEI $0 A <= $0 ? BRS SLDW10 Yes. Branch to SLDW10 LMAD TWBL Set Pulse Period Data Lower LAB LMAD TWBU Set Pulse Period Data Upper LAMD PLPADR Load Pulse Period Address AI $F Decrement Pulse Period Address LMAD PLPADR Save Pulse Period Address BR *+1 BRS STCNT90 Branch to STCNT90 * SLDW10 LMID $6,CNTADR Set Stop Control Mode LMID $D,COUNT0 Initialize COUNT0 to COUNT2 LMID $8,COUNT1 12-bit Counter = H'08D = D'141 Rev. 1.0, 03/99, page 139 of 209 LMID BRS $0,COUNT2 STCNT90 Branch to STCNT90 * ************************************************************ * STOP : Stop Control ************************************************************ * STOP CAL DEC Subroutine Jump to 'DEC' BRS STCNT90 ST = "1"? Yes. Branch to STCNT9 * LMID $0,CNTADR No. Set Slue up Control Mode LMID $1,PLPADR Set Pulse period Address TMD FOWRDF FOWRDF = "1" ? BRS STOP10 Yes. Branch to STOP10 SEMD FOWRDF Set FOWRDF BRS STCNT90 Branch to STCNT90 STOP10 REMD FOWRDF Reset FOWRDF BRS STCNT90 Branch to STCNT90 * ************************************************************ * POUT : Output Pulse ************************************************************ * POUT LAMD PLDATA Load Pulse Data TMD FOWRDF FOWRDF = 1 ? BRS POT20 Yes. Branch to POT20 * LBI $8 No. REC Reset CA ROTR Rotate Right A with Carry TC CA = 1 ? BRS POT10 Yes. Branch to POT10 BRS POT11 No. Branch to POT11 POT10 OR A = A OR B POT11 LRA $2 Set R2 Port PDR LMAD PLDATA Save Pulse Data BRS POT99 Branch to POT99 * POT20 LBI $1 REC Reset CA ROTL Rotate Left A with Carry TC CA = 1 ? BRS POT21 Yes. Branch to POT21 BRS POT22 No. Branch to POT22 POT21 OR A = A OR B POT22 LRA $2 Set R2 Port PDR LMAD PLDATA Save Pulse Data * POT99 RTN Return from Subroutine * ************************************************************ Rev. 1.0, 03/99, page 140 of 209 * DECR : Decrement Counter ************************************************************ * DECR REC Reset Carry LAI $0 SMCD COUNT0 A = COUNT0 - A - _CA LMAD COUNT0 Save COUNT0 LAI $0 SMCD COUNT1 A = COUNT1 - A - _CA LMAD COUNT1 Save COUNT1 LAI $0 SMCD COUNT2 A = COUNT2 - A - _CA LMAD COUNT2 Save COUNT2 RTN Return from Subroutine * ************************************************************ * Subroutine Table ************************************************************ * org $20 * PLOUT BRL POUT Branch to POUT DEC BRL DECR Branch to DECR * ************************************************************ * Timer Period Data Table ************************************************************ * org $100 * dc $100 Start dc $111 30.592ms dc $1AA 11.008ms dc $1BB 8.832ms dc $1CC 6.656ms dc $1CC 6.656ms dc $1CC 6.656ms dc $1DD 4.480ms dc $1DD 4.480ms dc $1DD 4.480ms dc $1DD 4.480ms dc $1DD 4.480ms dc $1DD 4.480ms dc $1DD 4.480ms dc $100 End * ************************************************************ * Pulse Motor Control Address ************************************************************ * org $200 Rev. 1.0, 03/99, page 141 of 209 * JMPL JMPL JMPL JMPL SLUP CNST SLDOWN STOP * end Rev. 1.0, 03/99, page 142 of 209 Jump Jump Jump Jump to to to to Slue up Control Routine Constant Control Routine Slue down Control Routine Stop Control Routine 2. H4318/H4359 ************************************************************ * * H400 Series Application Note * - Application Chapter * * 'Stepping Motor Control' * * Function * : Timer B Reload Timer * : I/O Port * * MCU : H4318/H4359 * * External Clock : 4MHz * Internal Clock : 1MHz * ************************************************************ * ************************************************************ * Symbol Definition ************************************************************ * IE equ 0,$000 Interrupt Enable Flag RSP equ 1,$000 Reset Stack Pointer IF0 equ 2,$000 INT0 Interrupt Request Flag IM0 equ 3,$000 INT0 Interrupt Mask * IF1 equ 0,$001 INT1 Interrupt Request Flag IM1 equ 1,$001 INT1 Interrupt Mask IFTA equ 2,$001 TIMER A Interrupt Request Flag IMTA equ 3,$001 TIMER A Interrupt Mask * IFTB equ 0,$002 TIMER B Interrupt Request Flag IMTB equ 1,$002 TIMER B Interrupt Mask IFTC equ 2,$002 TIMER C Interrupt Request Flag IMTC equ 3,$002 TIMER C Interrupt Mask * IFAD equ 0,$003 A/D Interrupt Request Flag IMAD equ 1,$003 A/D Interrupt Mask IFS equ 2,$003 SCI Interrupt Request Flag IMS equ 3,$003 SCI Interrupt Mask * PMRA equ $004 Port Mode Register A SMR equ $005 Serial Mode Register SRL equ $006 Serial Data Register L SRU equ $007 Serial Data Register U TMA equ $008 Timer Mode Register A TMB1 equ $009 Timer Mode Register B1 TRBL equ $00A Timer Read Register BL Rev. 1.0, 03/99, page 143 of 209 TWBL equ $00A Timer Write register BL TRBU equ $00B Timer Read Register BU TWBU equ $00B Timer Write Register BU MIS equ $00C Miscellaneous Register TMC equ $00D Timer Mode Register C TRCL equ $00E Timer Read Register CL TWCL equ $00E Timer Write Register CL TRCU equ $00F Timer Read Register CU TWCU equ $00F Timer Write Register CU ACR equ $016 A/D Control Register ADRL equ $017 A/D Data Register L ADRU equ $018 A/D Data Register U AMR1 equ $019 A/D Mode Register 1 AMR2 equ $01A A/D Mode Register 2 * WDON equ 1,$020 Watchdog on Flag ADSF equ 2,$020 A/D Start Flag * ICSF equ 0,$021 Input Capture Status Flag ICEF equ 1,$021 Input Capture Error Flag IAOF equ 2,$021 IAD off Flag RAME equ 3,$021 RAM Enable Flag * PMRB equ $024 Port Mode register B PMRC equ $025 Port Mode Register C TMB2 equ $026 Timer Mode Register B2 DCD0 equ $02C Data Control Register D0 DCD1 equ $02D Data Control Register D1 DCD2 equ $02E Data Control Register D2 DCR0 equ $030 Data Control Register R0 DCR1 equ $031 Data Control Register R1 DCR2 equ $032 Data Control Register R2 DCR3 equ $033 Data Control Register R3 DCR4 equ $034 Data Control Register R4 DCR8 equ $038 Data Control Register R8 * ************************************************************ * RAM Allocation ************************************************************ * AESC equ $040 A Escape RAM Area BESC equ $041 B Escape RAM Area WESC equ $042 W Escape RAM Area XESC equ $043 X Escape RAM Area YESC equ $044 Y Escape RAM Area SXESC equ $045 SPX Escape RAM Area SYESC equ $046 SPY Escape RAM Area * PLDATA equ $050 Pulse Data ($3 <-> $6 <-> $C <-> $9) CNTADR equ $051 Control Process Address PLPADR equ $052 Pulse Period Address Rev. 1.0, 03/99, page 144 of 209 COUNT0 equ $053 Counter 0 COUNT1 equ $054 Counter 1 COUNT2 equ $055 Counter 2 * FOWRDF equ 0,$05F Forward Flag( 1:Forward, 0:Reverce ) * ************************************************************ * Vector Address ************************************************************ * org $0000 * JMPL STEPMN Reset Interrupt JMPL STEPMN INT0 Interrupt JMPL STEPMN INT1 Interrupt JMPL STEPMN Timer A Interrupt JMPL STEPCNT Timer B Interrupt JMPL STEPMN Timer C Interrupt JMPL STEPMN A/D Interrupt JMPL STEPMN SCI Interrupt * ************************************************************ * STEPMN : Main Program ************************************************************ * org $1000 * STEPMN REMD RSP Stack Pointer Reset * LMID $3,PLDATA Initialize Pulse Data LMID $0,CNTADR Initialize Control Process Address SEMD FOWRDF Set Forward Mode LMID $1,PLPADR Initialize Pulse Period Address * LAI $0 Initialize R8 Port Data Register LRA $8 LMID $F,DCR8 Initialize R8 Port Output Terminal Function * LMID $A,TMB1 Initialize Timer B (128tcyc,Reload Timer ON) LMID $8,TWBL Initialize Period 29.696ms LMID $1,TWBU REMD IFTB Clear Timer B Interrupt Request Flag * BR *+1 Set Status Flag LMID $F,COUNT0 Initialize Counter 0 STMN10 CAL PLOUT Subroutine Call 'PLOUT' * STMN11 TMD IFTB 29.696ms Pass ? BRS STMN12 Yes. Branch to STMN12 BRS STMN11 No. Branch to STMN11 * Rev. 1.0, 03/99, page 145 of 209 STMN12 REMD LAMD AI LMAD BRS IFTB COUNT0 $F COUNT0 STMN10 Clear IFTB Load Counter 0 Decrement Counter 0 Save Counter 0 16 times End ? No. Branch to STMN10 REMD REMD SEMD IFTB IMTB IE Clear Timer B Interrupt Request Flag Timer B Interrupt Enable Interrupt Enable * * STMN99 BRS STMN99 Infinite Loop * ************************************************************ * STEPCNT : Stepping Motor Control ************************************************************ * STEPCNT REMD IFTB Clear Timer B Interrupt Request Flag * LMAD AESC Store Accumulator LAB LMAD BESC Store B Register XSPX LASPX LMAD XESC Store X Register XSPX LAY LMAD YESC Store Y Register * LAMD CNTADR Load Control Process Address LBI $0 TBR $2 Table Branch (CNTADR=0:SLUP, 2:CNST, 4:SLDOWN, 6:STOP) * STCNT90 LAMD YESC Restore Y Register LYA LAMD XESC Restore X Register LXA LAMD BESC Restore B Register LBA LAMD AESC Restore Accumulator * RTNI Return from Interrupt * ************************************************************ * SLUP : Slue up Control ************************************************************ * SLUP BR *+1 Set Status Flag CAL PLOUT Subroutine Jump to 'PLOUT' LAMD PLPADR Load Pulse Period Address LBI $0 P $1 Paturn Generation 'Output Pulse Period' Rev. 1.0, 03/99, page 146 of 209 LAB ALEI BRS LMAD LAB LMAD LAMD AI LMAD BR BRS * SLUP10 LMID LMID LMID LMID BRS $0 SLUP10 TWBL A <= $0 ? Yes. Branch to SLUP10 Set Pulse Period Data Lower TWBU PLPADR $1 PLPADR *+1 STCNT90 Set Pulse Period Data Upper Load Pulse Period Address Increment Pulse Period Address Save Pulse Period Address $2,CNTADR $8,COUNT0 $E,COUNT1 $3,COUNT2 STCNT90 Set Constant Control Mode Initialize Counter0 to COUNT0 12-bit Counter = H'3E8 = D'1000 Branch to STCNT90 Branch to STCNT90 * ************************************************************ * CNST : Constant Control ************************************************************ * CNST BR *+1 Set Status Flag CAL PLOUT Subroutine Jump to 'PLOUT' * CAL DEC Subroutine Jump to 'DEC' BRS STCNT90 Counter = H'000 ? Yes. Branch to STCNT90 * LMID $4,CNTADR Set Slue down Control Mode LMID $D,PLPADR Set Pulse Period Address BRS STCNT90 Branch to STCNT90 * ************************************************************ * STDOWN : Slue down Control ************************************************************ * SLDOWN BR *+1 Set Status Flag CAL PLOUT Subroutine Jump to 'PLOUT' LAMD PLPADR Load Pulse Period Address LBI $0 P $1 Pattern Generation 'Output Pulse Period' LAB ALEI $0 A <= $0 ? BRS SLDW10 Yes. Branch to SLDW10 LMAD TWBL Set Pulse Period Data Lower LAB LMAD TWBU Set Pulse Period Data Upper LAMD PLPADR Load Pulse Period Address AI $F Decrement Pulse Period Address LMAD PLPADR Save Pulse Period Address BR *+1 Rev. 1.0, 03/99, page 147 of 209 * SLDW10 BRS STCNT90 Branch to STCNT90 LMID LMID LMID LMID BRS $6,CNTADR $D,COUNT0 $8,COUNT1 $0,COUNT2 STCNT90 Set Stop Control Mode Initialize COUNT0 to COUNT2 12-bit Counter = H'08D = D'141 Branch to STCNT90 * ************************************************************ * STOP : Stop Control ************************************************************ * STOP CAL DEC Subroutine Jump to 'DEC' BRS STCNT90 ST = "1"? Yes. Branch to STCNT9 * LMID $0,CNTADR No. Set Slue up Control Mode LMID $1,PLPADR Set Pulse period Address TMD FOWRDF FOWRDF = "1" ? BRS STOP10 Yes. Branch to STOP10 SEMD FOWRDF Set FOWRDF BRS STCNT90 Branch to STCNT90 STOP10 REMD FOWRDF Reset FOWRDF BRS STCNT90 Branch to STCNT90 * ************************************************************ * POUT : Output Pulse ************************************************************ * POUT LAMD PLDATA Load Pulse Data TMD FOWRDF FOWRDF = 1 ? BRS POT20 Yes. Branch to POT20 * LBI $8 No. REC Reset CA ROTR Rotate Right A with Carry TC CA = 1 ? BRS POT10 Yes. Branch to POT10 BRS POT11 No. Branch to POT11 POT10 OR A = A OR B POT11 LRA $8 Set R8 Port PDR LMAD PLDATA Save Pulse Data BRS POT99 Branch to POT99 * POT20 LBI $1 REC Reset CA ROTL Rotate Left A with Carry TC CA = 1 ? BRS POT21 Yes. Branch to POT21 BRS POT22 No. Branch to POT22 POT21 OR A = A OR B POT22 LRA $8 Set R8 Port PDR Rev. 1.0, 03/99, page 148 of 209 LMAD PLDATA Save Pulse Data * POT99 RTN Return from Subroutine * ************************************************************ * DECR : Decrement Counter ************************************************************ * DECR REC Reset Carry LAI $0 SMCD COUNT0 A = COUNT0 - A - _CA LMAD COUNT0 Save COUNT0 LAI $0 SMCD COUNT1 A = COUNT1 - A - _CA LMAD COUNT1 Save COUNT1 LAI $0 SMCD COUNT2 A = COUNT2 - A - _CA LMAD COUNT2 Save COUNT2 RTN Return from Subroutine * ************************************************************ * Subroutine Table ************************************************************ * org $20 * PLOUT BRL POUT Branch to POUT DEC BRL DECR Branch to DECR * ************************************************************ * Timer Period Data Table ************************************************************ * org $100 * dc $100 Start dc $111 30.592ms dc $1AA 11.008ms dc $1BB 8.832ms dc $1CC 6.656ms dc $1CC 6.656ms dc $1CC 6.656ms dc $1DD 4.480ms dc $1DD 4.480ms dc $1DD 4.480ms dc $1DD 4.480ms dc $1DD 4.480ms dc $1DD 4.480ms dc $1DD 4.480ms dc $100 End * Rev. 1.0, 03/99, page 149 of 209 ************************************************************ * Pulse Motor Control Address ************************************************************ * org $200 * JMPL SLUP Jump to Slue up Control Routine JMPL CNST Jump to Constant Control Routine JMPL SLDOWN Jump to Slue down Control Routine JMPL STOP Jump to Stop Control Routine * end Rev. 1.0, 03/99, page 150 of 209 3. H4369 ************************************************************ * * H400 Series Application Note * - Application Chapter * * 'Stepping Motor Control' * * Function * : Timer B Reload Timer * : I/O Port * * MCU : H4369 * * External Clock : 4MHz * Internal Clock : 1MHz * Sub Clock : 32.768kHz * ************************************************************ * ************************************************************ * Symbol Definition ************************************************************ * IE equ 0,$000 Interrupt Enable Flag RSP equ 1,$000 Reset Stack Pointer IF0 equ 2,$000 INT0 Interrupt Request Flag IM0 equ 3,$000 INT0 Interrupt Mask * IF1 equ 0,$001 INT1 Interrupt Request Flag IM1 equ 1,$001 INT1 Interrupt Mask IFTA equ 2,$001 TIMER A Interrupt Request Flag IMTA equ 3,$001 TIMER A Interrupt Mask * IFTB equ 0,$002 TIMER B Interrupt Request Flag IMTB equ 1,$002 TIMER B Interrupt Mask IFTC equ 2,$002 TIMER C Interrupt Request Flag IMTC equ 3,$002 TIMER C Interrupt Mask * IFAD equ 0,$003 A/D Interrupt Request Flag IMAD equ 1,$003 A/D Interrupt Mask IFS equ 2,$003 SCI Interrupt Request Flag IMS equ 3,$003 SCI Interrupt Mask * PMRA equ $004 Port Mode Register A SMR equ $005 Serial Mode Register SRL equ $006 Serial Data Register L SRU equ $007 Serial Data Register U TMA equ $008 Timer Mode Register A TMB1 equ $009 Timer Mode Register B1 Rev. 1.0, 03/99, page 151 of 209 TRBL equ $00A Timer Read Register BL TWBL equ $00A Timer Write register BL TRBU equ $00B Timer Read Register BU TWBU equ $00B Timer Write Register BU MIS equ $00C Miscellaneous Register TMC equ $00D Timer Mode Register C TRCL equ $00E Timer Read Register CL TWCL equ $00E Timer Write Register CL TRCU equ $00F Timer Read Register CU TWCU equ $00F Timer Write Register CU * ACR equ $016 A/D Control Register ADRL equ $017 A/D Data Register L ADRU equ $018 A/D Data Register U AMR1 equ $019 A/D Mode Register 1 AMR2 equ $01A A/D Mode Register 2 * LSON equ 0,$020 LSON Flag WDON equ 1,$020 Watchdog on Flag ADSF equ 2,$020 A/D Start Flag DTON equ 3,$020 DTON Flag * ICSF equ 0,$021 Input Capture Status Flag ICEF equ 1,$021 Input Capture Error Flag IAOF equ 2,$021 IAD off Flag RAME equ 3,$021 RAM Enable Flag * PMRB equ $024 Port Mode register B PMRC equ $025 Port Mode Register C TMB2 equ $026 Timer Mode Register B2 SSR1 equ $027 System Clock Selection Register 1 SSR2 equ $028 System Clock Selection Register 2 * DCD0 equ $02C Data Control Register D0 DCD1 equ $02D Data Control Register D1 DCD2 equ $02E Data Control Register D2 DCD3 equ $02F Data Control Register D3 DCR0 equ $030 Data Control Register R0 DCR1 equ $031 Data Control Register R1 DCR2 equ $032 Data Control Register R2 DCR3 equ $033 Data Control Register R3 DCR4 equ $034 Data Control Register R4 DCR5 equ $035 Data Control Register R5 DCR6 equ $036 Data Control Register R6 DCR7 equ $037 Data Control Register R7 DCR8 equ $038 Data Control Register R8 DCR9 equ $039 Data Control Register R9 * ************************************************************ * RAM Allocation ************************************************************ Rev. 1.0, 03/99, page 152 of 209 * AESC equ $040 A Escape RAM Area BESC equ $041 B Escape RAM Area WESC equ $042 W Escape RAM Area XESC equ $043 X Escape RAM Area YESC equ $044 Y Escape RAM Area SXESC equ $045 SPX Escape RAM Area SYESC equ $046 SPY Escape RAM Area * PLDATA equ $050 Pulse Data ($3 <-> $6 <-> $C <-> $9) CNTADR equ $051 Control Process Address PLPADR equ $052 Pulse Period Address COUNT0 equ $053 Counter 0 COUNT1 equ $054 Counter 1 COUNT2 equ $055 Counter 2 * FOWRDF equ 0,$05F Forward Flag( 1:Forward, 0:Reverce ) * ************************************************************ * Vector Address ************************************************************ * org $0000 * JMPL STEPMN Reset Interrupt JMPL STEPMN INT0 Interrupt JMPL STEPMN INT1 Interrupt JMPL STEPMN Timer A Interrupt JMPL STEPCNT Timer B Interrupt JMPL STEPMN Timer C Interrupt JMPL STEPMN A/D Interrupt JMPL STEPMN SCI Interrupt * ************************************************************ * STEPMN : Main Program ************************************************************ * org $1000 * STEPMN REMD RSP Stack Pointer Reset LMID $2,SSR1 Initialize System Clock * LMID $3,PLDATA Initialize Pulse Data LMID $0,CNTADR Initialize Control Process Address SEMD FOWRDF Set Forward Mode LMID $1,PLPADR Initialize Pulse Period Address * LAI $0 Initialize R8 Port Data Register LRA $8 LMID $F,DCR8 Initialize R8 Port Output Terminal Function * Rev. 1.0, 03/99, page 153 of 209 LMID LMID LMID REMD $A,TMB1 $8,TWBL $1,TWBU IFTB Initialize Timer B (128tcyc,Reload Timer ON) Initialize Period 29.696ms BR LMID CAL *+1 $F,COUNT0 PLOUT Set Status Flag Initialize Counter 0 Subroutine Call 'PLOUT' TMD BRS BRS IFTB STMN12 STMN11 29.696ms Pass ? Yes. Branch to STMN12 No. Branch to STMN11 REMD LAMD AI LMAD BRS IFTB COUNT0 $F COUNT0 STMN10 Clear IFTB Load Counter 0 Decrement Counter 0 Save Counter 0 16 times End ? No. Branch to STMN10 REMD REMD SEMD IFTB IMTB IE Clear Timer B Interrupt Request Flag Timer B Interrupt Enable Interrupt Enable Clear Timer B Interrupt Request Flag * STMN10 * STMN11 * STMN12 * * STMN99 BRS STMN99 Infinite Loop * ************************************************************ * STEPCNT : Stepping Motor Control ************************************************************ * STEPCNT REMD IFTB Clear Timer B Interrupt Request Flag * LMAD AESC Store Accumulator LAB LMAD BESC Store B Register XSPX LASPX LMAD XESC Store X Register XSPX LAY LMAD YESC Store Y Register * LAMD CNTADR Load Control Process Address LBI $0 TBR $2 Table Branch (CNTADR=0:SLUP, 2:CNST, 4:SLDOWN, 6:STOP) * STCNT90 LAMD YESC Restore Y Register LYA LAMD XESC Restore X Register LXA LAMD BESC Restore B Register LBA Rev. 1.0, 03/99, page 154 of 209 LAMD AESC Restore Accumulator * RTNI Return from Interrupt * ************************************************************ * SLUP : Slue up Control ************************************************************ * SLUP BR *+1 Set Status Flag CAL PLOUT Subroutine Jump to 'PLOUT' LAMD PLPADR Load Pulse Period Address LBI $0 P $1 Pattern Generation 'Output Pulse Period' LAB ALEI $0 A <= $0 ? BRS SLUP10 Yes. Branch to SLUP10 LMAD TWBL Set Pulse Period Data Lower LAB LMAD TWBU Set Pulse Period Data Upper LAMD PLPADR Load Pulse Period Address AI $1 Increment Pulse Period Address LMAD PLPADR Save Pulse Period Address BR *+1 BRS STCNT90 Branch to STCNT90 * SLUP10 LMID $2,CNTADR Set Constant Control Mode LMID $8,COUNT0 Initialize Counter0 to COUNT0 LMID $E,COUNT1 12-bit Counter = H'3E8 = D'1000 LMID $3,COUNT2 BRS STCNT90 Branch to STCNT90 * ************************************************************ * CNST : Constant Control ************************************************************ * CNST BR *+1 Set Status Flag CAL PLOUT Subroutine Jump to 'PLOUT' * CAL DEC Subroutine Jump to 'DEC' BRS STCNT90 Counter = H'000 ? Yes. Branch to STCNT90 * LMID $4,CNTADR Set Slue down Control Mode LMID $D,PLPADR Set Pulse Period Address BRS STCNT90 Branch to STCNT90 * ************************************************************ * STDOWN : Slue down Control ************************************************************ * SLDOWN BR *+1 Set Status Flag CAL PLOUT Subroutine Jump to 'PLOUT' Rev. 1.0, 03/99, page 155 of 209 * SLDW10 LAMD LBI P LAB ALEI BRS LMAD LAB LMAD LAMD AI LMAD BR BRS PLPADR $0 $1 Load Pulse Period Address $0 SLDW10 TWBL A <= $0 ? Yes. Branch to SLDW10 Set Pulse Period Data Lower TWBU PLPADR $F PLPADR *+1 STCNT90 Set Pulse Period Data Upper Load Pulse Period Address Decrement Pulse Period Address Save Pulse Period Address LMID LMID LMID LMID BRS $6,CNTADR $D,COUNT0 $8,COUNT1 $0,COUNT2 STCNT90 Set Stop Control Mode Initialize COUNT0 to COUNT2 12-bit Counter = H'08D = D'141 Pattern Generation 'Output Pulse Period' Branch to STCNT90 Branch to STCNT90 * ************************************************************ * STOP : Stop Control ************************************************************ * STOP CAL DEC Subroutine Jump to 'DEC' BRS STCNT90 ST = "1"? Yes. Branch to STCNT9 * LMID $0,CNTADR No. Set Slue up Control Mode LMID $1,PLPADR Set Pulse period Address TMD FOWRDF FOWRDF = "1" ? BRS STOP10 Yes. Branch to STOP10 SEMD FOWRDF Set FOWRDF BRS STCNT90 Branch to STCNT90 STOP10 REMD FOWRDF Reset FOWRDF BRS STCNT90 Branch to STCNT90 * ************************************************************ * POUT : Output Pulse ************************************************************ * POUT LAMD PLDATA Load Pulse Data TMD FOWRDF FOWRDF = 1 ? BRS POT20 Yes. Branch to POT20 * LBI $8 No. REC Reset CA ROTR Rotate Right A with Carry TC CA = 1 ? BRS POT10 Yes. Branch to POT10 BRS POT11 No. Branch to POT11 Rev. 1.0, 03/99, page 156 of 209 POT10 POT11 * POT20 POT21 POT22 OR LRA LMAD BRS LBI REC ROTL TC BRS BRS OR LRA LMAD $8 PLDATA POT99 A = A OR B Set R8 Port PDR Save Pulse Data Branch to POT99 $1 POT21 POT22 $8 PLDATA Reset CA Rotate Left A with Carry CA = 1 ? Yes. Branch to POT21 No. Branch to POT22 A = A OR B Set R8 Port PDR Save Pulse Data * POT99 RTN Return from Subroutine * ************************************************************ * DECR : Decrement Counter ************************************************************ * DECR REC Reset Carry LAI $0 SMCD COUNT0 A = COUNT0 - A - _CA LMAD COUNT0 Save COUNT0 LAI $0 SMCD COUNT1 A = COUNT1 - A - _CA LMAD COUNT1 Save COUNT1 LAI $0 SMCD COUNT2 A = COUNT2 - A - _CA LMAD COUNT2 Save COUNT2 RTN Return from Subroutine * ************************************************************ * Subroutine Table ************************************************************ * org $20 * PLOUT BRL POUT Branch to POUT DEC BRL DECR Branch to DECR * ************************************************************ * Timer Period Data Table ************************************************************ * org $100 * dc $100 Start dc $111 30.592ms dc $1AA 11.008ms Rev. 1.0, 03/99, page 157 of 209 dc dc dc dc dc dc dc dc dc dc dc dc $1BB $1CC $1CC $1CC $1DD $1DD $1DD $1DD $1DD $1DD $1DD $100 8.832ms 6.656ms 6.656ms 6.656ms 4.480ms 4.480ms 4.480ms 4.480ms 4.480ms 4.480ms 4.480ms End * ************************************************************ * Pulse Motor Control Address ************************************************************ * org $200 * JMPL SLUP Jump to Slue up Control Routine JMPL CNST Jump to Constant Control Routine JMPL SLDOWN Jump to Slue down Control Routine JMPL STOP Jump to Stop Control Routine * end Rev. 1.0, 03/99, page 158 of 209 4. H4889 ************************************************************ * * H400 Series Application Note * - Application Chapter * * 'Stepping Motor Control' * * Function * : Timer B Reload Timer * : I/O Port * * MCU : H4889 * * External Clock : 4MHz * Internal Clock : 1MHz * Sub Clock : 32.768kHz * ************************************************************ * ************************************************************ * Symbol Definition ************************************************************ * IE equ 0,$000 Interrupt Enable Flag RSP equ 1,$000 Reset Stack Pointer IFWU equ 2,$000 _WU0-_WU3 Interrupt Request Flag IMWU equ 3,$000 _WU0-_WU3 Interrupt Mask * IF0 equ 0,$001 _INT0 Interrupt Request Flag IM0 equ 1,$001 _INT0 Interrupt Mask IF1 equ 2,$001 _INT1 Interrupt request Flag IM1 equ 3,$001 _INT1 Interrupt Mask * IFTA equ 0,$002 Timer A Interrupt Request Flag IMTA equ 1,$002 Timer A Interrupt Mask IFTB equ 2,$002 Timer B Interrupt Request Flag IMTB equ 3,$002 Timer B Interrupt Mask * IFTC equ 0,$003 Timer C Interrupt Request Flag IMTC equ 1,$003 Timer C Interrupt Mask IFAD equ 2,$003 A/D Converter Interrupt Request Flag IMAD equ 3,$003 A/D Converter Interrupt Mask * SSR equ $004 System Clock Selection Register MIS equ $005 Miscellaneous Register ESR equ $006 Edge Detection Selection Register * PMR0 equ $008 Port Mode Register 0 PMR1 equ $009 Port Mode Register 1 Rev. 1.0, 03/99, page 159 of 209 PMR2 PMR3 PMR4 MSR1 MSR2 TMA TMB1 TMB2 TRBL TWBL TRBU TWBU TMC1 TMC2 TRCL TWCL TRCU TWCU TMD1 TMD2 TRDL TWDL TRDU TWDU * LSON WDON ADSF DTON * ICSF ICEF GEF * IFTD IMTD * IFS IMS * SMR1 SMR2 SRL SRU AMR * ADRL ADRU LCR LMR BMR equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ $00A $00B $00C $00D $00E $00F $010 $011 $012 $012 $013 $013 $014 $015 $016 $016 $017 $017 $018 $019 $01A $01A $01B $01B Port Mode Register 2 Port Mode Register 3 Port Mode Register 4 Module Standby Register 1 Module Standby Register 2 Timer Mode Register A Timer Mode Register B1 Timer Mode Register B2 Timer Read Register BL Timer Write Register BL Timer Read Register BU Timer Write Register BU Timer Mode Register C1 Timer Mode Register C2 Timer Read Register CL Timer Write Register CL Timer Read Register CU Timer Write Register CU Timer Mode Register D1 Timer Mode Register D2 Timer Read Register DL Timer Write Register DL Timer read Register DU Timer Write register DU equ equ equ equ 0,$020 1,$020 2,$020 3,$020 Low Speed on Flag Watchdog on Flag A/D Start Flag DTON Flag equ equ equ 0,$021 1,$021 3,$021 Input Capture Status Flag Input Capture Error Flag Gear Enable Flag equ equ 2,$022 3,$022 Timer D Interrupt Request Flag Timer D Interrupt Mask equ equ 2,$023 3,$023 Serial Interrupt Request Flag Serial Interrupt Mask equ equ equ equ equ $024 $025 $026 $027 $028 Serial Mode Register Serial Mode Register Serial Data Register Serial Data Register A/D Mode Register equ equ equ equ equ $02A $02B $02C $02D $02E A/D Data Register L A/D Data Register U LCD Control Register LCD Mode Register Buzzer Mode Register Rev. 1.0, 03/99, page 160 of 209 1 2 L U * DCD0 equ $030 Data Control Register D0 DCD1 equ $031 Data Control Register D1 DCD2 equ $032 Data Control Register D2 * DCR0 equ $034 Data Control Register R0 DCR1 equ $035 Data Control Register R1 DCR2 equ $036 Data Control Register R2 DCR3 equ $037 Data Control Register R3 DCR4 equ $038 Data Control Register R4 DCR5 equ $039 Data Control Register R5 DCR6 equ $03A Data Control Register R6 DCR7 equ $03B Data Control Register R7 DCR8 equ $03C Data Control Register R8 * V equ $03F Bank Register * ************************************************************ * RAM Allocation ************************************************************ * AESC equ $040 A Escape RAM Area BESC equ $041 B Escape RAM Area WESC equ $042 W Escape RAM Area XESC equ $043 X Escape RAM Area YESC equ $044 Y Escape RAM Area SXESC equ $045 SPX Escape RAM Area SYESC equ $046 SPY Escape RAM Area * PLDATA equ $090 Pulse Data ($3 <-> $6 <-> $C <-> $9) CNTADR equ $091 Control Process Address PLPADR equ $092 Pulse Period Address COUNT0 equ $093 Counter 0 COUNT1 equ $094 Counter 1 COUNT2 equ $095 Counter 2 * FOWRDF equ 0,$09F Forward Flag( 1:Forward, 0:Reverce ) * ************************************************************ * Vector Address ************************************************************ * org $0000 * JMPL STEPMN Reset Interrupt JMPL STEPMN _WU0-_WU3 Interrupt JMPL STEPMN _INT0 Interrupt JMPL STEPMN _INT1 Interrupt JMPL STEPMN Timer A Interrupt JMPL STEPCNT Timer B/D Interrupt JMPL STEPMN Timer C Interrupt Rev. 1.0, 03/99, page 161 of 209 JMPL STEPMN A/D Converter / Serial Interrupt * ************************************************************ * STEPMN : Main Program ************************************************************ * org $1000 * STEPMN REMD RSP Stack Pointer Reset LMID $2,SSR Initialize System Clock * LMID $3,PLDATA Initialize Pulse Data LMID $0,CNTADR Initialize Control Process Address SEMD FOWRDF Set Forward Mode LMID $1,PLPADR Initialize Pulse Period Address * LAI $0 Initialize R2 Port Data Register LRA $2 LMID $F,DCR2 Initialize R2 Port Output Terminal Function * LMID $A,TMB1 Initialize Timer B (128tcyc,Reload Timer ON) LMID $8,TWBL Initialize Period 29.696ms LMID $1,TWBU REMD IFTB Clear Timer B Interrupt Request Flag * BR *+1 Set Status Flag LMID $F,COUNT0 Initialize Counter 0 STMN10 CAL PLOUT Subroutine Call 'PLOUT' * STMN11 TMD IFTB 29.696ms Pass ? BRS STMN12 Yes. Branch to STMN12 BRS STMN11 No. Branch to STMN11 * STMN12 REMD IFTB Clear IFTB LAMD COUNT0 Load Counter 0 AI $F Decrement Counter 0 LMAD COUNT0 Save Counter 0 BRS STMN10 16 times End ? No. Branch to STMN10 * REMD IFTB Clear Timer B Interrupt Request Flag REMD IMTB Timer B Interrupt Enable SEMD IE Interrupt Enable * STMN99 BRS STMN99 Infinite Loop * ************************************************************ * STEPCNT : Stepping Motor Control ************************************************************ * STEPCNT REMD IFTB Clear Timer B Interrupt Request Flag * Rev. 1.0, 03/99, page 162 of 209 LMAD LAB LMAD XSPX LASPX LMAD XSPX LAY LMAD AESC Store Accumulator BESC Store B Register XESC Store X Register YESC Store Y Register LAMD LBI TBR CNTADR $0 $2 Load Control Process Address LAMD LYA LAMD LXA LAMD LBA LAMD YESC Restore Y Register XESC Restore X Register BESC Restore B Register AESC Restore Accumulator * * STCNT90 Table Branch (CNTADR=0:SLUP, 2:CNST, 4:SLDOWN, 6:STOP) * RTNI Return from Interrupt * ************************************************************ * SLUP : Slue up Control ************************************************************ * SLUP BR *+1 Set Status Flag CAL PLOUT Subroutine Jump to 'PLOUT' LAMD PLPADR Load Pulse Period Address LBI $0 P $1 Pattern Generation 'Output Pulse Period' LAB ALEI $0 A <= $0 ? BRS SLUP10 Yes. Branch to SLUP10 LMAD TWBL Set Pulse Period Data Lower LAB LMAD TWBU Set Pulse Period Data Upper LAMD PLPADR Load Pulse Period Address AI $1 Increment Pulse Period Address LMAD PLPADR Save Pulse Period Address BR *+1 BRS STCNT90 Branch to STCNT90 * SLUP10 LMID $2,CNTADR Set Constant Control Mode LMID $8,COUNT0 Initialize Counter0 to COUNT0 LMID $E,COUNT1 12-bit Counter = H'3E8 = D'1000 LMID $3,COUNT2 BRS STCNT90 Branch to STCNT90 * Rev. 1.0, 03/99, page 163 of 209 ************************************************************ * CNST : Constant Control ************************************************************ * CNST BR *+1 Set Status Flag CAL PLOUT Subroutine Jump to 'PLOUT' * CAL DEC Subroutine Jump to 'DEC' BRS STCNT90 Counter = H'000 ? Yes. Branch to STCNT90 * LMID $4,CNTADR Set Slue down Control Mode LMID $D,PLPADR Set Pulse Period Address BRS STCNT90 Branch to STCNT90 * ************************************************************ * STDOWN : Slue down Control ************************************************************ * SLDOWN BR *+1 Set Status Flag CAL PLOUT Subroutine Jump to 'PLOUT' LAMD PLPADR Load Pulse Period Address LBI $0 P $1 Pattern Generation 'Output Pulse Period' LAB ALEI $0 A <= $0 ? BRS SLDW10 Yes. Branch to SLDW10 LMAD TWBL Set Pulse Period Data Lower LAB LMAD TWBU Set Pulse Period Data Upper LAMD PLPADR Load Pulse Period Address AI $F Decrement Pulse Period Address LMAD PLPADR Save Pulse Period Address BR *+1 BRS STCNT90 Branch to STCNT90 * SLDW10 LMID $6,CNTADR Set Stop Control Mode LMID $D,COUNT0 Initialize COUNT0 to COUNT2 LMID $8,COUNT1 12-bit Counter = H'08D = D'141 LMID $0,COUNT2 BRS STCNT90 Branch to STCNT90 * ************************************************************ * STOP : Stop Control ************************************************************ * STOP CAL DEC Subroutine Jump to 'DEC' BRS STCNT90 ST = "1"? Yes. Branch to STCNT9 * LMID $0,CNTADR No. Set Slue up Control Mode LMID $1,PLPADR Set Pulse period Address TMD FOWRDF FOWRDF = "1" ? Rev. 1.0, 03/99, page 164 of 209 STOP10 BRS SEMD BRS REMD BRS STOP10 FOWRDF STCNT90 FOWRDF STCNT90 Yes. Branch to STOP10 Set FOWRDF Branch to STCNT90 Reset FOWRDF Branch to STCNT90 * ************************************************************ * POUT : Output Pulse ************************************************************ * POUT LAMD PLDATA Load Pulse Data TMD FOWRDF FOWRDF = 1 ? BRS POT20 Yes. Branch to POT20 * LBI $8 No. REC Reset CA ROTR Rotate Right A with Carry TC CA = 1 ? BRS POT10 Yes. Branch to POT10 BRS POT11 No. Branch to POT11 POT10 OR A = A OR B POT11 LRA $2 Set R2 Port PDR LMAD PLDATA Save Pulse Data BRS POT99 Branch to POT99 * POT20 LBI $1 REC Reset CA ROTL Rotate Left A with Carry TC CA = 1 ? BRS POT21 Yes. Branch to POT21 BRS POT22 No. Branch to POT22 POT21 OR A = A OR B POT22 LRA $2 Set R2 Port PDR LMAD PLDATA Save Pulse Data * POT99 RTN Return from Subroutine * ************************************************************ * DECR : Decrement Counter ************************************************************ * DECR REC Reset Carry LAI $0 SMCD COUNT0 A = COUNT0 - A - _CA LMAD COUNT0 Save COUNT0 LAI $0 SMCD COUNT1 A = COUNT1 - A - _CA LMAD COUNT1 Save COUNT1 LAI $0 SMCD COUNT2 A = COUNT2 - A - _CA LMAD COUNT2 Save COUNT2 Rev. 1.0, 03/99, page 165 of 209 RTN Return from Subroutine * ************************************************************ * Subroutine Table ************************************************************ * org $20 * PLOUT BRL POUT Branch to POUT DEC BRL DECR Branch to DECR * ************************************************************ * Timer Period Data Table ************************************************************ * org $100 * dc $100 Start dc $111 30.592ms dc $1AA 11.008ms dc $1BB 8.832ms dc $1CC 6.656ms dc $1CC 6.656ms dc $1CC 6.656ms dc $1DD 4.480ms dc $1DD 4.480ms dc $1DD 4.480ms dc $1DD 4.480ms dc $1DD 4.480ms dc $1DD 4.480ms dc $1DD 4.480ms dc $100 End * ************************************************************ * Pulse Motor Control Address ************************************************************ * org $200 * JMPL SLUP Jump to Slue up Control Routine JMPL CNST Jump to Constant Control Routine JMPL SLDOWN Jump to Slue down Control Routine JMPL STOP Jump to Stop Control Routine * end Rev. 1.0, 03/99, page 166 of 209 2.3 Key Scan and 7-Segment LED Display Key Scan and 7-Segment LED Display MCU: H4318/H4359/H4369 Functions Used: R1, R2, R3 Ports, D Port, and Timer A Specifications 1. As shown in figure 1, the H4318/H4359/H4369 Series are used to construct a key matrix keyscanning function and 7-segment LED display. 2. Numbers 0 to F are assigned to the 16 keys and the number (0 to F of the pressed key) is displayed on LED0, which is one of four 7-segment LEDs (LED0 to LED3). 3. Two keys cannot be pressed simultaneously (the result is invalid). 4. Key chattering is suppressed in software. 5. Figure 2 shows the key configuration and number allocation. Figure 3 shows an example 7segment LED display. LED3 LED2 LED1 Strb7 Strb6 B D F 8 A C E LED h Strb5 9 6 LED g Strb4 7 4 LED f Strb3 5 2 LED e Strb2 3 0 LED d D3 D2 D1 D0 Strb0/LED a Strb1/LED b Strb2/LED c Strb3/LED d Strb4/LED e Strb5/LED f Strb6/LED g Strb7/LED h 1 LED a LED deg3 LED deg2 LED deg1 LED deg0 R10 R11 R12 R13 R20 R21 R22 R23 Ret0 Strb1 R30 Ret1 LED c R31 LED b H4318/H4359/H4369 Strb0 6. Figure 4 shows the connection of H4318/H4359/H4369 and keys and 7-segment LED. LED0 Figure 1 Key Scan and 7-Segment LED Display Rev. 1.0, 03/99, page 167 of 209 9 B D F 1 3 5 7 8 A C E 0 2 4 6 LED a LED b LED c LED d LED e LED f LED g LED h Figure 2 Key Configuration and Assigned Numbers a f g e b c d h LED deg0 Figure 3 Example 7-Segment LED Display Rev. 1.0, 03/99, page 168 of 209 VCC Key matrix 1 3 5 7 9 B D F 0 2 4 6 8 A C E H4318/H4359/H4369 R10 R11 R12 R13 R20 R21 R22 R23 R30 R31 D0 D1 D2 D3 a b c d e f g h a b c d e f g h a f g b f c e d a b c d e f g h a g LED3 b f c e h d a b c d e f g h a g LED2 b f c e h a d g c e h b d LED1 h LED0 Figure 4 Connection of H4318/H4359/H4369 and keys and 7-Segment LED Rev. 1.0, 03/99, page 169 of 209 Concepts 1. Key Scan Figure 5 is a timing chart of the key scanning operation. a. A "Low" signal is output from P10 pin, and a strobe signal output to the STrb0 row of the key matrix. b. The key data for the Ret0 row of the key matrix is read from R30 and R31 pins when the strobe signal is output. c. Key depression is detected from the data read from the pins. d. The strobe signal is shifted and steps a to c repeated. 2.048 ms Strobe signal P10 pin P11 pin P12 pin P13 pin P20 pin P21 pin P22 pin P23 pin P30 and P31 pins Key data Key data Key data Key data for Strb0 row for Strb2 row for Strb4 row for Strb6 row Key data for Strb1 row Key data for Strb3 row Key data for Strb5 row Key data for Strb7 row Figure 5 Timing Chart for Key Scanning Operation Rev. 1.0, 03/99, page 170 of 209 2. Chattering Suppression Figure 6 is a timing chart for chattering suppression. a. Key data is sampled at intervals of 10.24 ms. b. The data is checked to see if the same data is obtained 3 times in succession. c. If the key data is not the same for all 3 times, key depression is ignored. d. If the key data is the same for all 3 times, the key is assumed to be depressed and the key data is taken to be valid. Chattering Key depression signal OFF ON 10.24 ms Timing for reading key data 1 2 1 Timing for validating key data 2 3 ON OFF ON Notes: 1 : Key data for time before last. 2 : Key data for last time. 3 : Present key data. Figure 6 Timing Chart for Chattering Suppression Rev. 1.0, 03/99, page 171 of 209 2. LED Display Table 1 shows the relationship between 7-segment LED display, port output and segment data. Table 1 Relationship Between LED Display, Port Output, and Segment Data R1 and R2 Port Output LED Display Segment Data R10 R11 R12 R13 R20 R21 R22 R23 SEG0L SEG0U 0 0 0 0 0 0 1 1 $0 $C 1 0 0 1 1 1 1 1 $9 $F 0 0 1 0 0 1 0 1 $4 $A 0 0 0 0 1 1 0 1 $0 $B 1 0 0 1 1 0 0 1 $9 $9 0 1 0 0 1 0 0 1 $2 $9 0 1 0 0 0 0 0 1 $2 $8 0 0 0 1 1 0 1 1 $8 $D Rev. 1.0, 03/99, page 172 of 209 Table 1 Relationship Between LED Display, Port Output, and Segment Data (cont) R1 and R2 Port Output LED Display Segment Data R10 R11 R12 R13 R20 R21 R22 R23 SEG0L SEG0U 0 0 0 0 0 0 0 1 $0 $8 0 0 0 0 1 0 0 1 $0 $9 0 0 0 1 0 0 0 1 $8 $8 1 1 0 0 0 0 0 1 $3 $8 0 1 1 0 0 0 1 1 $6 $C 1 0 0 0 0 1 0 1 $1 $A 0 1 1 0 0 0 0 1 $6 $8 0 1 1 1 0 0 0 1 $E $8 Rev. 1.0, 03/99, page 173 of 209 Description of Functions 1. This section describes the functions of the H4318/H4359/H4369 used in key scanning and 7segment LED display. Figure 7 is a block diagram of the functions used in this example task. H4318/H4359/H4369 functions Timer A interrupt request Interrupt cycle setting Timer A (free-running timer) H4318/H4359/ H4369 LED deg0 D3 LED deg1 D2 LED deg2 D1 LED deg3 D0 CPU LED control signal D port 7-segment LED display control Key Strobe signal/LED output signal Key return data Key scan control R32 Ret0 R33 Ret1 R20 R3 port Strb4/LED e R21 Strb5/LED f R22 Strb6/LED g R23 Strb7/LED h R10 R2 port Strb0/LED a R11 Strb1/LED b R12 Strb2/LED c Strb3/LED d R13 R1 port Figure 7 Block Diagram of H4318/H4359/H4369 Functions Used in Key Scanning and 7-Segment LED Display Rev. 1.0, 03/99, page 174 of 209 2. Descriptions of Functions of Timer A, R1/R2/R3 Ports, and D Port. a. Figure 8 is a block diagram of the timer A functions. System clock (4 MHz/4) Timer A functions TCA input clock setting Interrupt cycle setting Timer mode register A (TCA) /2048 /1024 /512 /128 /32 /8 /4 /2 Prescaler S (PSS) Selector TCA input clock selection System clock division setting (division by 8) (4 MHz/4) / 8 = 125 kHz Timer counter A (TCA) TCA overflow 256/125 kHz = 2.048 ms Timer A interrupt request flag (IFTA) Interrupt request due to TCA overflow Figure 8 Block Diagram of Timer A Functions Rev. 1.0, 03/99, page 175 of 209 b. Timer A is an 8-bit free-running timer. However, in the H4369, it can also be used as a time based real-time clock using the system clock oscillator (32.768 kHz). Table 2 describes the timer A functions. Table 2 Timer A Functions Timer Mode Register A (TMA) Function TMA is a 4-bit write-only register. It selects the division ratio of the prescaler S, which is the clock source for timer A. TMA is initialized to $0 when reset and in stop mode. In the H4318/H4359 TMA bit 3 (TMA3) cannot be used. In the H4369, TMA3 selects the prescaler (PSS or PSW), which is the clock source of timer A. Timer Counter A (TCA) Function TCA is an 8-bit up-counter, which is incremented by the input internal clock. The TCA input clock is selected by TMA. TCA cannot be read or written to. When TCA overflows, the timer A interrupt request flag (IFTA) is set to "1". TCA is initialized to $00 when reset and in stop mode. Prescaler S (PSS) Function PSS is an 11-bit counter to which the system clock is in put when in active mode and standby mode, and the subsystem clock is input when in subactive mode*. PSS is initialized to $000 at a reset, and the system clock count starts when the reset is canceled. PSS operation is halted when reset, in stop mode, and in watch mode*. However, it runs in other operating modes. The PSS output is shared by the internal peripheral modules, the division ratio being set independently for each of the internal peripheral modules. Timer A Interrupt Request Flag (IFTA) Function IFTA reflects the existence of the timer A interrupt request. When timer A overflows, IFTA is set to "1". IFTA can only be read/written to (only "0" can be written) using bit operation commands. Note that IFTA is not automatically cleared even when the interrupt is received, and must be cleared by writing "0" using software. IFTA is cleared at a reset and in stop mode. Timer A Interrupt Mask (IMTA) Function IMTA is the bit that masks IFTA. When IFTA is set to "1" and, additionally, IMTA is "0", a timer A interrupt request is sent to the CPU (when IE = "1"). If IFTA is set to "1" but IMTA is "1", no interrupt request is sent to the CPU and the timer A interrupt is held. IMTA can only be read or written to using bit operation commands. It is set to "1" at a reset and in stop mode. Note: * Applies to H4369 only. Rev. 1.0, 03/99, page 176 of 209 c. Ports R1, R2, and R3 are 4-bit I/O ports, accessed in units of 4 bits. Each of ports R1 to R3 are accessed in 4-bit units using the output commands (LRA and LRB) to control the output level High/Low. The output data is stored in the port data registers (PDR) of the respective pins. The input commands (LAR and LBR) are used for 4-bit access to read the pin levels. d. Table 3 describes the functions of the R1, R2, and R3 ports. Table 3 Functions of R1, R2, and R3 Ports Data Control Register R1 (DCR1) Function DCR1 switches the I/O pin function of the R1 port. When any bit of DCR1 is cleared to "0", the output buffer (CMOS) of the corresponding pin is turned OFF and the output is set to high impedance. When the respective bit of DCR1 is set to "1", the output buffer of the corresponding pin is set ON and the corresponding PDR value is output. Data Control Register R2 (DCR2) Function DCR2 switches the I/O pin function of the R2 port. When any bit of DCR2 is cleared to "0", the output buffer (CMOS) of the corresponding pin is turned OFF and the output is set to high impedance. When the respective bit of DCR2 is set to "1", the output buffer of the corresponding pin is set ON and the corresponding PDR value is output. Data Control Register R3 (DCR3) Function DCR3 switches the I/O pin function of the R3 port. When any bit of DCR3 is cleared to "0", the output buffer (CMOS) of the corresponding pin is turned OFF and the output is set to high impedance. When the respective bit of DCR3 is set to "1", the output buffer of the corresponding pin is set ON and the corresponding PDR value is output. Port Data Register (PDR) Function The I/O pins of the R ports have built-in PDRs to store the output data. When the LRA and LRB commands are executed, the contents of the accumulator (A) and B register (B) are transferred to the PDR of the specified R port. When the corresponding DCR of the R port is "1", the output buffer of the appropriate pin is set ON and the value in the PDR is output via that pin. The PDR is initialized to $F at a reset. A/D Mode Register 1 (AMR1) Function AMR1 is a 4-bit write-only register. Bits AMR13 to AMR10 switch the functions of the ports dual-function pins. Rev. 1.0, 03/99, page 177 of 209 e. The D ports are 1-bit input output ports, accessed in 1-bit units. Pins D0 to D3 are accessed in 1-bit units using the output commands (SED, SEDD, RED, and REDD) to control the High/Low output level. The output data is stored in the PDR of the respective pin. Pins D0 to D3 are also accessed in 1-bit units using the input commands (TD and TDD) to test the pin level. f. Table 4 describes the functions of the D ports. Table 4 D Port Functions Data Control Register D0 (DCD0) Function DCD0 switches the I/O pin function of pins D0 to D3. When any bit of DCD0 is cleared to "0", the output buffer (CMOS) of the corresponding pin is turned OFF and the output is set to high impedance. When the respective bit of DCD0 is set to "1", the output buffer of the corresponding pin is set ON and the corresponding PDR value is output. Port Data Register (PDR) Function The I/O pins D0 to D8 have built-in PDRs to store the output data. When the SED or SEDD commands are executed for pins D0 to D8, the corresponding PDR is set to "1". When the RED or REDD commands are executed, the corresponding PDR is cleared to "0". When a corresponding bit to DCD0 to DCD2 is "1", the output buffer of that pin is turned ON and the value in the PDR is output via that pin. The PDR is set to "1" at a reset an in stop mode. Port Mode Register A (PMRA) Function PMRA is a 4-bit write-only register. PMRA3 switches the function of the D3/BUZZ pin. Port Mode Register B (PMRB) Function PMRB is a 4-bit write-only register. PMRB0 switches the functions of the D0/INT0 pin, PMRB1 switches D1/INT1, and PMRB2 switches D2/EVNB. Rev. 1.0, 03/99, page 178 of 209 3. Table 5 describes the allocation of functions in this example task. Table 5 Allocation of Functions Function Function Allocation System clock The system clock is obtained by dividing the clock output from the system clock oscillator by 4. It is used for operating the CPU and internal peripheral modules. In this example task, a 4 MHz system clock oscillator is used, so the clock supplied to the CPU and internal peripheral modules is 1 MHz. The clock used by timer B and timer C is obtained by dividing the 1 MHz clock at PSS. PSS Generates the clock input to timer A by dividing the system clock. The clock input to timer A is obtained by dividing the system clock by 8. TCA This 8-bit up-counter counts on the input internal clock ((4 MHz/4) / 8 = 125 kHz). IFTA is set to "1" when TCA overflows. TMA Selects the system clock divided by 8 as the TCA input clock. IFTA Reflects the existence of timer A interrupt requests. IMTA Enables/disables timer A interrupt requests. DCD0 Sets D0 to D3 to function as output pins. DCR1 Sets R10 to R13 of the R1 port to function as output pins. DCR2 Sets R20 to R23 of the R2 port to function as output pins. DCR3 Sets R30 and R31 of the R3 port to function as output pins. PDR Stores the data output from the respective pins. AMR1 Sets the R30/AN0 to R33/AN3 pins to function as R30 to R33 I/O pins. PMRA Sets the D3/BUZZ pin to function as a D3 I/O pin. PMRB Sets the D0/INT0 pin to function as D0 I/O pin, D1/INT1 pin to function as D1 I/O pin, and D2/EVNB pin to function as D2 I/O pin. Pins R10 to R13 Output pins for Strb0/LED a to Strb3/LED d signals. Pins R20 to R23 Output pins for Strb4/LED e to Strb7/LED h signals. Pins R30 and R31 Input pins for Ret0 and Ret1 signals. Pins D0 to D3 Output pins for LED deg1 to LED deg3 signals. Rev. 1.0, 03/99, page 179 of 209 Description of Operation 1. Figure 9 shows the operating principles of key scanning and the 7-segment LED display. 2.048 ms 2.048 ms 2.048 ms 2.048 ms 2.048 ms LED3 on "No display" LED2 on "No display" LED1 on "No display" LED0 on "0" display Key scan TCA $FF $00 R10 pin R11 pin R12 pin R13 pin R20 pin R21 pin R22 pin R23 pin Hardware processing 1. TCA overflows. 2. IFTA set to "1". Software processing 1. Clear IFTA to "0". 2. Output LED display data for LED3 to 0 from pins R10 to R13 and R20 to R23. Hardware processing 1. TCA overflows. 2. IFTA set to "1". Software processing 1. Clear IFTA to "0". 2. Output strobe signal from pins R10 to R13 and R20 to R23 and store input data for pins R30 and R31 in RAM. Figure 9 Operating Principles of Key Scanning and 7-Segment LED Display Rev. 1.0, 03/99, page 180 of 209 Description of Software 1. Description of Modules Table 6 shows the modules used in this example task. Table 6 Modules Module Label Functions Main routine LDKYMN This routine makes the initial stack pointer, RAM, I/O port, and timer A settings, enables interrupts, and calls the KEYDEC and LEDDSP subroutines. Key decoder KEYDEC Converts to key data on completion of key scanning, judges if the key data is the same three times in succession, and suppresses chattering. LED display LEDDSP When the key data is the same three times in succession and is therefore taken to be valid, this routine converts the key data to LED display data and displays the number of the depressed key on the 7-segment LED. Timer A interrupt processing routine LDKYINT Saves the registers, calls the LED and KEY subroutines, and restores registers. LED control LED Controls the lighting of LED0 to LED3. Key scan KEY Performs key scanning by outputting a strobe signal and storing the data input to pins R30 and R31 in RAM. 2. Description of Arguments No arguments are used in this example task. Rev. 1.0, 03/99, page 181 of 209 3. Description of Internal Registers Table 7 describes the internal registers used in this example task. Table 7 Internal Registers Used in Example Task Register Description RAM Address Setting IE Interrupt Enable Flag 0, $000 1 1, $000 0 2, $001 0 3, $001 0 $004 $0 $008 $5 Controls the CPU can receive any interrupts. RSP * When IE = "0", CPU reception of all interrupts is disabled. * When IE = "1", CPU reception is enabled. Reset Stack Pointer The stack pointer is initialized by clearing RSP to "0". IFTA Timer A Interrupt Request Flag Reflects the existence of a timer A interrupt request. IMTA * When IFTA = "0", there is no timer A interrupt request. * When IFTA = "1", there is a timer A interrupt request. Timer A Interrupt Mask This bit masks IFTA. PMRA * When IMTA = "0", IFTA is enabled. * When IMTA = "1", IFTA is masked. Port Mode Register A Switches the function of the D3/BUZZ pin. TMA * When PMRA = "0", the D3/BUZZ pin functions as the D3 I/O pin. * When PMRA = "1", the D3/BUZZ pin functions as the BUZZ output pin. Timer Mode Register A Selects the timer A clock source and the input clock cycle. * When TMA3 = "0", the timer A clock source is the PSS. However, this applies only to the H4369. In the H4318/H4359, TMA3 cannot be used. * When TMA2 = "1" and TMA1 = "0", and TMA0 = "1", the timer A input clock cycle is set to 8 s. Rev. 1.0, 03/99, page 182 of 209 Table 7 Internal Registers Used in Example Task (cont) Register Description RAM Address Setting AMR1 A/D mode register (AMR1) $019 $0 $024 $0 Switches the function of the R3 port's dual-function pins. PMRB * When AMR13 = "0", the R33/AN3 pin functions as the R33 I/O pin. * When AMR13 = "1", the R33/AN3 pin functions as the AN3 input pin. * When AMR12 = "0", the R32/AN2 pin functions as the R32 I/O pin. * When AMR12 = "1", the R32/AN2 pin functions as the AN2 input pin. * When AMR11 = "0", the R31/AN1 pin functions as the R31 I/O pin. * When AMR11 = "1", the R31/AN1 pin functions as the AN1 input pin. * When AMR10 = "0", the R30/AN0 pin functions as the R30 I/O pin. * When AMR10 = "1", the R30/AN0 pin functions as the AN0 input pin. Port Mode Register B (PMRB) Switches the function of the D port's dual-function pins. * When PMRB2 = "0", the D2/EVNB pin functions as the D2 I/O pin. * When PMRB2 = "1", the D2/EVNB pin functions as the EVNB input pin. * When PMRB1 = "0", the D1/INT1 pin functions as the D1 I/O pin. * When PMRB1 = "1", the D1/INT1 pin functions as the INT1 input pin. * When PMRB0 = "0", the D0/INT0 pin functions as the D0 I/O pin. * When PMRB0 = "1", the D0/INT0 pin functions as the INT0 input pin. Rev. 1.0, 03/99, page 183 of 209 Table 7 Internal Registers Used in Example Task (cont) Register Description RAM Address Setting SSR1 System Clock Selection Register 1 $027 $2 $02C $F $030 $F $031 $F Selects the system clock oscillation frequency, subsystem clock frequency division, and, in stop mode, the subsystem clock oscillation. * When SSR11 = "0", the system clock oscillation frequency is set to 0.4 to 1 MHz. * When SSR11 = "1", the system clock oscillation frequency is set to 1.6 to 5 MHz. Note: Applicable only to H4369. DCD0 Data Control Register D0 Controls the ON/OFF state of the D port output buffer. DCR1 * When DCD03 to DCD00 = "0", the output buffers of the D3 to D0 pins are OFF and output set to high impedance. * When DCD03 to DCD00 = "1", the output buffers of the D3 to D0 pins are ON and the values of the corresponding PDRs are output. Data Control Register R1 Controls the ON/OFF state of the R1 port output buffer. DCR2 * When DCR13 to DCR10 = "0", the output buffers of the R13 to R10 pins are OFF and output set to high impedance. * When DCR13 to DCR10 = "1", the output buffers of the R13 to R10 pins are ON and the values of the corresponding PDRs are output. Data Control Register R2 DCR2 switches the output buffer of the R2 port ON/OFF. * When DCR23 to DCR20 = "0", the output buffers of pins R23 to R20 are OFF and the pins are in the high impedance state. * When DCR23 to DCR20 = "1", The output buffers of pins R23 to R20 are ON and the values in the corresponding PDRs are output. Rev. 1.0, 03/99, page 184 of 209 Table 7 Internal Registers Used in Example Task (cont) Register Description RAM Address Setting DCR3 Data Control Register R3 $032 $0 DCR3 switches the output buffer of the R3 port ON/OFF. * When DCR33 to DCR30 = "0", the output buffers of pins R33 to R30 are OFF and the pins are in the high impedance state. * When DCR33 to DCR30 = "1", The output buffers of pins R33 to R30 are ON and the values in the corresponding PDRs are output. 4. Description of RAM Table 8 describes the RAM used in this example task. Table 8 RAM RAM Address Module Stores content of accumulator when processing timer A interrupt. $040 LDKYINT BESC Stores content of B register when processing timer A interrupt. $041 LDKYINT XESC Stores content of X register when processing timer A interrupt. $043 LDKYINT YESC Stores content of Y register when processing timer A interrupt. $044 LDKYINT DIGCNT Counter to control output to 7-segment LED. $054 LDKYMN, LED, KEY SEG0L Stores lower 4 bits of display data output to LED0. $050 LDKYMN, LEDDSP, LED SEG1L Stores lower 4 bits of display data output to LED1. $051 LDKYMN, LEDDSP, LED SEG2L Stores lower 4 bits of display data output to LED2. $052 LDKYMN, LEDDSP, LED SEG3L Stores lower 4 bits of display data output to LED3. $053 LDKYMN, LEDDSP, LED SEG0U Stores upper 4 bits of display data output to LED0. $060 LDKYMN, LEDDSP, LED Label Description AESC Rev. 1.0, 03/99, page 185 of 209 Table 8 RAM (cont) Label Description RAM Address SEG1U Stores upper 4 bits of display data output to LED1. $061 LDKYMN, LEDDSP, LED SEG2U Stores upper 4 bits of display data output to LED2. $062 LDKYMN, LEDDSP, LED SEG3U Stores upper 4 bits of display data output to LED3. $063 LDKYMN, LEDDSP, LED KEYFLG Stores KEYONF and KDECONF. $080 -- KEYONF Flag showing end of key scanning. 0, $080 LDKYMN, KEYDEC, KEY KDECONF Flag confirming key data. 1, $080 LDKYMN, KEYDEC, LEDDSP KONNEW Stores new key data $07F KEYDEC, LEDDSP KONOLD Stores old key data $07E KEYDEC CHATCNT Counter to suppress chattering $07D LDKYMN, KEYDEC STRBU Stores upper 4 bits of output strobe signal $079 KEY STRBL Stores lower 4 bits of output strobe signal $078 KEY Rev. 1.0, 03/99, page 186 of 209 Module Flowcharts 1. Main Routine LDKYMN 1 Reset stack pointer Clear IMTA to "0" to enable timer A interrupts Set SSR11 to "1" to set system clock to 1.6 to 5.0 MHz * Clear IFTA to "0" Initialize R1 port PDR to $F Initialize DIGCNT to $0 Initialize R2 port PDR to $F Initialize KEYFLG to $0 Initialize D0 port PDR to 0 Initialize CHATCNT to $0 Initialize D1 port PDR to 0 Initialize SEG0U to SEG3U and SEG0L to SEG3L to $F Initialize D2 port PDR to 0 Set IE to "1" to enable interrupts Initialize D3 port PDR to 0 KEYDEC Set DCR1 to $F to set the R13 to R10 I/O pins to function as output pins LEDDSP Set DCR2 to $F to set the R23 to R20 I/O pins to function as output pins Set DCD0 to $F to set the D3 to D0 I/O pins to function as output pins Set TMA to $5 to select the system clock divided by 8 as the timer A input clock 1 Note: * Applies to H4369 only Rev. 1.0, 03/99, page 187 of 209 2. Key Decoder KEYDEC KEYONF = "1"? No 3 Yes Set B register $F Set X register to $7 Set Y register to $0 Store the contents of RAM at address indicated by X and Y registers in accumulator Link contents of accumulator with CA and rotate 1 bit left Stores contents of accumulator in address indicated by X and Y registers Decrement content of Y register Y != $4? Yes No CA = "1"? Yes No Store content of B register in accumulator Decrement content of B register Store content of accumulator in KONNEW B >= $1? No 3 2 Rev. 1.0, 03/99, page 188 of 209 Yes 2 Store content of accumulator in KONNEW A != KONOLD? Yes No Increment CHATCNT Yes CHATCNT <=$2? No Initialize CHATCNT to $0 Store content of accumulator in KONOLD Set KDECONF to "1" 3 Clear KEYONF to "0" RTN Rev. 1.0, 03/99, page 189 of 209 3. LED Display LEDDSP KDECONF = "1"? Yes Clear KDECONF to "0" Initialize SEG0U to SEG3U and SEG0L to SEG3L to $F Use the pattern commands to read corresponding segment data from data table according to content of KONNEW Store read segment data in SEG0L and SEG0U RTN Rev. 1.0, 03/99, page 190 of 209 No 4. Timer A Interrupt Processing Routine LDKYINT Clear IFTA to "0" Save registers Use BR command to set ST to "1" LED KEY Restore registers RTNI Rev. 1.0, 03/99, page 191 of 209 5. LED Control LED DIGCNT != $4? Yes No Store content of DIGCNT in accumulator Store $3 in Y register Store content of accumulator in Y register Clear PDR of D port at address indicated by Y register to "0" Decrement content of Y register No Y >= 1? Yes Set CA to "1" Store lower digit of segment data at address indicated by Y register in PDR of R1 port 4 Store upper digit of segment data at address indicated by Y register in PDR of R2 port CA = "1"? Yes No Set PDR of D port at address indicated by Y register to "1" Clear ST to "0" Store content of Y register in DIGCNT RTN Clear CA to "0" 4 Rev. 1.0, 03/99, page 192 of 209 Set ST to "1" 6. Key Scan KEY 5 6 Set STRBU to $F Link content of accumulator with CA and rotate 1 bit right Store content of accumulator in STRBU Set STRBL to $E Set X register to $7 9 Yes 9 Store content of accumulator in RAM at address indicated by X and Y registers CA = 1? No Set KEYONF to "1" Set Y register to $4 Decrement content of Y register Set content of STRBU in PDR of R2 port Y >= 1? Set content of STRBL in PDR of R1 port Initialize DIGCNT to $4 Yes 7 RTN No Decrement content of B register NOP NOP B >= 1? Yes 8 No NOP Set CA to "1" Store contents of R3 port PDR in RAM indicated by X and Y registers Store content of STRBL in accumulator 8 Link content of accumulator with CA and rotate 1 bit left 7 Store content of accumulator in STRBL Set B register to $1 Set Y register to $4 Store contents of RAM at address specified by X and Y registers in accumulator 5 Store content of STRBU in accumulator Link content of accumulator with CA and rotate 1 bit left 6 Rev. 1.0, 03/99, page 193 of 209 Program Listing 1. H4318/H4359 ************************************************************ * * H400 Series Application Note * - Application Chapter * * 'Keyscan & 8-segment LED Display' * * Function * : Timer A Free Running Timer * : I/O Port (D0-D3, R1-R3 Port) * * MCU : H4318/H4359 * * External Clock : 4MHz * Internal Clock : 1MHz * ************************************************************ * ************************************************************ * Symbol Definition ************************************************************ * IE equ 0,$000 Interrupt Request Flag RSP equ 1,$000 Reset Stack Pointer IF0 equ 2,$000 _INT0 Interrupt Request Flag IM0 equ 3,$000 _INT0 Interrupt Mask * IF1 equ 0,$001 _INT1 Interrupt Request Flag IM1 equ 1,$001 _INT1 Interrupt Mask IFTA equ 2,$001 Timer A Interrupt Request Flag IMTA equ 3,$001 Timer A Interrupt Mask * IFTB equ 0,$002 Timer B Interrupt Request Flag IMTB equ 1,$002 Timer B Interrupt Mask IFTC equ 2,$002 Timer C Interrupt Request Flag IMTC equ 3,$002 Timer C Interrupt Mask * IFAD equ 0,$003 A/D Converter Interrupt Request Flag IMAD equ 1,$003 A/D Converter Interrupt Mask IFS equ 2,$003 Serial Interrupt Request Flag IMS equ 3,$003 Serial Interrupt Mask * PMRA equ $004 Port Mode Register A SMR equ $005 Serial Mode Register SRL equ $006 Serial Data Register L SRU equ $007 Serial Data Register U TMA equ $008 Timer Mode Register A Rev. 1.0, 03/99, page 194 of 209 TMB1 equ $009 Timer Mode Register B1 TRBL equ $00A Timer Read Register BL TWBL equ $00A Timer Write Register BL TRBU equ $00B Timer Read Register BU TWBU equ $00B Timer Write Register BU MIS equ $00C Miscellaneous register TMC equ $00D Timer Mode Register C TRCL equ $00E Timer Read Register CL TWCL equ $00E Timer Write Register CL TRCU equ $00F Timer Read Register CU TWCU equ $00F Timer Write Register CU ACR equ $016 A/D Control Register ADRL equ $017 A/D Data Register L ADRU equ $018 A/D Data Register U AMR1 equ $019 A/D Mode Register 1 AMR2 equ $01A A/D Mode Register 2 * WDON equ 1,$020 Watchdog on Flag ADSF equ 2,$020 A/D Start Flag * ICSF equ 0,$021 Input Capture Status Flag ICEF equ 1,$021 Input Capture Error Flag IAOF equ 2,$021 I_AD off Flag RAME equ 3,$021 RAM Enable Flag * PMRB equ $024 Port Mode Register B PMRC equ $025 Port Mode Register C TMB2 equ $026 Timer Mode Register B2 DCD0 equ $02C Data Control Register D0 DCD1 equ $02D Data Control Register D1 DCD2 equ $02E Data Control Register D2 DCR0 equ $030 Data Control Register R0 DCR1 equ $031 Data Control Register R1 DCR2 equ $032 Data Control register R2 DCR3 equ $033 Data Control Register R3 DCR4 equ $034 Data Control Register R4 DCR8 equ $038 Data Control Register R8 * ************************************************************ * Ram Allocation ************************************************************ * AESC equ $040 A Escape RAM Area BESC equ $041 B Escape RAM Area WESC equ $042 W Escape RAM Area XESC equ $043 X Escape RAM Area YESC equ $044 Y Escape RAM Area SXESC equ $045 SPX Escape RAM Area SYESC equ $046 SPY Escape RAM Area * DIGCNT equ $054 LED Digit Counter Rev. 1.0, 03/99, page 195 of 209 * SEG0U equ $060 LED Display Data 0 Upper SEG1U equ $061 LED Display Data 1 Upper SEG2U equ $062 LED Display Data 2 Upper SEG3U equ $063 LED Display Data 3 Upper * SEG0L equ $050 LED Display Data 0 Lower SEG1L equ $051 LED Display Data 1 Lower SEG2L equ $052 LED Display Data 2 Lower SEG3L equ $053 LED Display Data 3 Lower * KEYFLG equ $080 Key Flag Area KEYONF equ 0,KEYFLG Key on Flag KDECONF equ 1,KEYFLG Key Decode on Flag * KONNEW equ $07F Key New Data KONOLD equ $07E Key Old Data CHATCNT equ $07D Chattering Counter KEYYADR equ $07A STRBU equ $079 Key Strobe Data UpperPPER STRBL equ $078 Key Strobe Data Lower * ************************************************************ * Vector Address ************************************************************ * org $0000 * JMPL LDKYMN Reset Interrupt JMPL LDKYMN _INT0 Interrupt JMPL LDKYMN _INT1 Interrupt JMPL LDKYINT Timer A Interrupt JMPL LDKYMN Timer B Interrupt JMPL LDKYMN Timer C Interrupt JMPL LDKYMN A/D Converter Interrupt JMPL LDKYMN SCI Interrupt * ************************************************************ * LDKYMN : Main Program ************************************************************ * org $1000 * LDKYMN REMD RSP Reset Stack Pointer * LAI $F LRA $1 Initialize R1 Port PDR LRA $2 Initialize R2 Port PDR REDD $0 Initialize D0 Port PDR REDD $1 Initialize D1 Port PDR REDD $2 Initialize D2 Port PDR Rev. 1.0, 03/99, page 196 of 209 REDD LMID LMID LMID $3 $F,DCR1 $F,DCR2 $F,DCD0 Initialize Initialize Initialize Initialize D3 Port PDR R1 Port Terminal Function R2 Port Terminal Function D0-D3 Port Terminal Function LMID REMD REMD $5,TMA IMTA IFTA Initialize Timer A Input Clock Period Timer A Interrupt Enable Clear IFTA LMID LMID LMID $0,DIGCNT Initialize LED Digit Counter $0,KEYFLG Initialize Key on Flag & Key Decode on Flag $0,CHATCNT Initialize Chattering Counter LXI XSPX LXI LYI LAI LMAX LMADYX BRS $6 SEMD IE Interrupt Enable CALL CALL BRS KEYDEC LEDDSP LKMN90 Subroutine Jump to KEYDEC Subroutine Jump to LEDDSP Branch to LKMN90 * * * LKMN10 Initialize LED Display Data $5 $3 $F LKMN10 * * LKMN90 * ************************************************************ * KEYDEC : Key Decoder ************************************************************ * KEYDEC TMD KEYONF KEYONF = "1" ? Keyscan End ? BRS KD10 Yes. Branch to KD10 BRS KD90 NO. Branch to KD90 * KD10 LBI $F LXI $7 KD12 LYI $0 KD15 LAM Load Key Data ROTL Rotate Left with Carry LMAIY Save Key Data. Increment Y Register YNEI $4 Y+1 != 0 BRS KD15 Yes. Branch to KD15 TC No. CA = 1 ? BRS KD16 Yes. Branch to KD16 LAB LMAD KONNEW Save Key on New Data BRS KD20 KD16 DB Decrement B Register. B >= 1 ? BRS KD12 Yes. Branch to KD12 Rev. 1.0, 03/99, page 197 of 209 * KD20 KD21 * KD90 BRS KD90 No. Branch to KD90 LMAD ANEMD BRS LAMD AI LMAD ALEI BRS SEMD BRS LMID LMAD KONNEW KONOLD KD21 CHATCNT $1 CHATCNT $2 KD90 KDECONF KD90 $0,CHATCNT KONOLD Load Key on New Data Key on New Data != Key on Old Data ? Yes. Branch to KD21 Load Chattering Counter Increment Chattering Counter Save Chattering Counter A <= $2 ? Yes. Branch to KD90 Set Key Decode on Flag Branch to KD90 Initialize Chattering Counter Save Key on Old Data REMD RTN KEYONF Clear Key on Flag Return * ************************************************************ * LEDDSP : LED Display ************************************************************ * LEDDSP TMD KDECONF KDECONF = 1 ? BRS LDSP10 Yes. Branch to LDSP10 BRS LDSP90 No. Branch to LDSP90 * LDSP10 REMD KDECONF Clear Key Decode on Flag * LXI $6 Initialize LED Display Data XSPX LXI $5 LYI $3 LAI $F LDSP20 LMAX LMADYX End ? BRS LDSP20 No. Branch to LDSP20 * LAMD KONNEW Load Key Data LBI $0 P $F Pattern Generation LMAD SEG0L Save LED Display Data Lower LAB LMAD SEG0U Save LED Display Data Upper * LDSP90 RTN Return from Subroutine * ************************************************************ * LDKYINT : Timer A Interrupt Routine ************************************************************ * LDKYINT REMD IFTA Clear Timer A Interrupt Request Flag Rev. 1.0, 03/99, page 198 of 209 * LMAD LAB LMAD XSPX LASPX LMAD XSPX LAY LMAD AESC Store Accumulator BESC Store B Register XESC Store X Register YESC Store Y Register BR CALL CALL *+1 LED KEY Set Status Flag Subroutine Jump to 'LED' Subroutine Jump to 'KEY' LAMD LYA LAMD LXA LAMD LBA LAMD YESC Restore Y Register XESC Restore X Register BESC Restore B Register AESC Restore Accumulator * * * RTNI Return from Interrupt * ************************************************************ * LED : LED Control ************************************************************ * LED INEMD $4,DIGCNT DIGCNT = 4 ? BRS LED00 No. Branch to LED00 LYI $3 Yes. Initialize DIGCNT BRS LED10 Branch to LED10 LED00 LAMD DIGCNT Load DIGCNT LYA RED Turn off Now Digit DY D >= 1 ? BRS LED10 Yes. Branch to LED10 SEC No. Set CA BRS LED20 Branch to LED20 LED10 LXI $5 Load LED Display Data LAM LRA $1 Output Display Data Lower to R1 Port LXI $6 LAM LRA $2 Output Display Data Upper to R2 Port SED Turn on Next Digit LAY LMAD DIGCNT Save DIGCNT REC Reset CA LED20 TC Test CA Rev. 1.0, 03/99, page 199 of 209 * RTN Return from Subroutine * ************************************************************ * KEY : Key Scan ************************************************************ * KEY LMID $F,STRBU Initialize Strobe Data Upper LMID $E,STRBL Initialize Strobe Data Lower LXI $7 * KEY00 LYI $4 LAMD STRBU Load Strobe Data Upper LRA $2 Output Strobe Data Upper to R2 Port LAMD STRBL Load Strobe Data Lower LRA $1 Output Strobe Data Lower to R1 Port NOP Wait NOP Wait NOP Wait LAR $3 Input Key Return Data LMA Save Key Return Data * LBI $1 KEY10 LYI $4 KEY20 LAM Load Key Return Data ROTR Rotate Right with Carry LMADY Save Key Return Data. Y >= 1 ? BRS KEY20 Yes. Branch to KEY20 DB Decrement B Register. B >= 1 ? BRS KEY10 Yes. Branch to KEY10 * SEC Set CA LAMD STRBL Load Strobe Data ROTL Rotate Left with Carry LMAD STRBL Save Strobe Data LAMD STRBU Load Strobe Data ROTL Rotate Left with Carry LMAD STRBU Save Strobe Data TC CA = 1 ? BRS KEY00 Yes. Branch to KEY20 * SEMD KEYONF Set KEYONF * KEY90 LMID $4,DIGCNT Initialize DIGCNT * RTN * ************************************************************ * LED Display Data Table ************************************************************ * Rev. 1.0, 03/99, page 200 of 209 org $F00 dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc $1C0 $1F9 $1A4 $1B0 $199 $192 $182 $1D8 $180 $190 $188 $183 $1C6 $1A1 $186 $18E * LED LED LED LED LED LED LED LED LED LED LED LED LED LED LED LED Display Display Display Display Display Display Display Display Display Display Display Display Display Display Display Display Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "A" "B" "C" "D" "E" "F" * end Rev. 1.0, 03/99, page 201 of 209 2. H4369 ************************************************************ * * H400 Series Application Note * - Application Chapter * * 'Keyscan & 8-segment LED Display' * * Function * : Timer A Free Running Timer * : I/O Port (D0-D3, R1-R3 Port) * * MCU : H4369 * * External Clock : 4MHz * Internal Clock : 1MHz * Sub Clock : 32.768kHz * ************************************************************ * ************************************************************ * Symbol Definition ************************************************************ * IE equ 0,$000 Interrupt Request Flag RSP equ 1,$000 Reset Stack Pointer IF0 equ 2,$000 _INT0 Interrupt Request Flag IM0 equ 3,$000 _INT0 Interrupt Mask * IF1 equ 0,$001 _INT1 Interrupt Request Flag IM1 equ 1,$001 _INT1 Interrupt Mask IFTA equ 2,$001 Timer A Interrupt Request Flag IMTA equ 3,$001 Timer A Interrupt Mask * IFTB equ 0,$002 Timer B Interrupt Request Flag IMTB equ 1,$002 Timer B Interrupt Mask IFTC equ 2,$002 Timer C Interrupt Request Flag IMTC equ 3,$002 Timer C Interrupt Mask * IFAD equ 0,$003 A/D Converter Interrupt Request Flag IMAD equ 1,$003 A/D Converter Interrupt Mask IFS equ 2,$003 Serial Interrupt Request Flag IMS equ 3,$003 Serial Interrupt Mask * PMRA equ $004 Port Mode Register A SMR equ $005 Serial Mode Register SRL equ $006 Serial Data Register L SRU equ $007 Serial Data Register U TMA equ $008 Timer Mode Register A TMB1 equ $009 Timer Mode Register B1 Rev. 1.0, 03/99, page 202 of 209 TRBL equ $00A Timer Read Register BL TWBL equ $00A Timer Write Register BL TRBU equ $00B Timer Read Register BU TWBU equ $00B Timer Write Register BU MIS equ $00C Miscellaneous register TMC equ $00D Timer Mode Register C TRCL equ $00E Timer Read Register CL TWCL equ $00E Timer Write Register CL TRCU equ $00F Timer Read Register CU TWCU equ $00F Timer Write Register CU ACR equ $016 A/D Control Register ADRL equ $017 A/D Data Register L ADRU equ $018 A/D Data Register U AMR1 equ $019 A/D Mode Register 1 AMR2 equ $01A A/D Mode Register 2 * LSON equ 0,$020 LSON Flag WDON equ 1,$020 Watchdog on Flag ADSF equ 2,$020 A/D Start Flag DTON equ 3,$020 DTON Flag * ICSF equ 0,$021 Input Capture Status Flag ICEF equ 1,$021 Input Capture Error Flag IAOF equ 2,$021 I_AD off Flag RAME equ 3,$021 RAM Enable Flag * PMRB equ $024 Port Mode Register B PMRC equ $025 Port Mode Register C TMB2 equ $026 Timer Mode Register B2 SSR1 equ $027 System Clock Selection Register 1 SSR2 equ $028 System Clock Selection register 2 * DCD0 equ $02C Data Control Register D0 DCD1 equ $02D Data Control Register D1 DCD2 equ $02E Data Control Register D2 DCD3 equ $02F Data Control Register D3 * DCR0 equ $030 Data Control Register R0 DCR1 equ $031 Data Control Register R1 DCR2 equ $032 Data Control register R2 DCR3 equ $033 Data Control Register R3 DCR4 equ $034 Data Control Register R4 DCR5 equ $035 Data Control Register R5 DCR6 equ $036 Data Control Register R6 DCR7 equ $037 Data Control Register R7 DCR8 equ $038 Data Control Register R8 DCR9 equ $039 Data Control Register R9 * ************************************************************ * Ram Allocation ************************************************************ Rev. 1.0, 03/99, page 203 of 209 * AESC equ $040 A Escape RAM Area BESC equ $041 B Escape RAM Area WESC equ $042 W Escape RAM Area XESC equ $043 X Escape RAM Area YESC equ $044 Y Escape RAM Area SXESC equ $045 SPX Escape RAM Area SYESC equ $046 SPY Escape RAM Area * DIGCNT equ $054 LED Digit Counter * SEG0U equ $060 LED Display Data 0 Upper SEG1U equ $061 LED Display Data 1 Upper SEG2U equ $062 LED Display Data 2 Upper SEG3U equ $063 LED Display Data 3 Upper * SEG0L equ $050 LED Display Data 0 Lower SEG1L equ $051 LED Display Data 1 Lower SEG2L equ $052 LED Display Data 2 Lower SEG3L equ $053 LED Display Data 3 Lower * KEYFLG equ $080 Key Flag Area KEYONF equ 0,KEYFLG Key on Flag KDECONF equ 1,KEYFLG Key Decode on Flag * KONNEW equ $07F Key New Data KONOLD equ $07E Key Old Data CHATCNT equ $07D Chattering Counter KEYYADR equ $07A STRBU equ $079 Key Strobe Data UpperPPER STRBL equ $078 Key Strobe Data Lower * ************************************************************ * Vector Address ************************************************************ * org $0000 * JMPL LDKYMN Reset Interrupt JMPL LDKYMN _INT0 Interrupt JMPL LDKYMN _INT1 Interrupt JMPL LDKYINT Timer A Interrupt JMPL LDKYMN Timer B Interrupt JMPL LDKYMN Timer C Interrupt JMPL LDKYMN A/D Converter Interrupt JMPL LDKYMN SCI Interrupt * ************************************************************ * LDKYMN : Main Program ************************************************************ * Rev. 1.0, 03/99, page 204 of 209 * LDKYMN org $1000 REMD LMID RSP $2,SSR1 Reset Stack Pointer Initialize System Clock LAI LRA LRA REDD REDD REDD REDD LMID LMID LMID $F $1 $2 $0 $1 $2 $3 $F,DCR1 $F,DCR2 $F,DCD0 Initialize Initialize Initialize Initialize Initialize Initialize Initialize Initialize Initialize LMID REMD REMD $5,TMA IMTA IFTA Initialize Timer A Input Clock Period Timer A Interrupt Enable Clear IFTA LMID LMID LMID $0,DIGCNT Initialize LED Digit Counter $0,KEYFLG Initialize Key on Flag & Key Decode on Flag $0,CHATCNT Initialize Chattering Counter LXI XSPX LXI LYI LAI LMAX LMADYX BRS $6 SEMD IE Interrupt Enable CALL CALL BRS KEYDEC LEDDSP LKMN90 Subroutine Jump to KEYDEC Subroutine Jump to LEDDSP Branch to LKMN90 * R1 Port PDR R2 Port PDR D0 Port PDR D1 Port PDR D2 Port PDR D3 Port PDR R1 Port Terminal Function R2 Port Terminal Function D0-D3 Port Terminal Function * * * LKMN10 Initialize LED Display Data $5 $3 $F LKMN10 * * LKMN90 * ************************************************************ * KEYDEC : Key Decoder ************************************************************ * KEYDEC TMD KEYONF KEYONF = "1" ? Keyscan End ? BRS KD10 Yes. Branch to KD10 BRS KD90 NO. Branch to KD90 * KD10 LBI $F LXI $7 KD12 LYI $0 KD15 LAM Load Key Data Rev. 1.0, 03/99, page 205 of 209 KD16 * KD20 KD21 * KD90 ROTL LMAIY YNEI BRS TC BRS LAB LMAD BRS DB BRS BRS $4 KD15 KD16 KONNEW KD20 Rotate Left with Carry Save Key Data. Increment Y Register Y+1 != 0 Yes. Branch to KD15 No. CA = 1 ? Yes. Branch to KD16 Save Key on New Data KD12 KD90 Decrement B Register. B >= 1 ? Yes. Branch to KD12 No. Branch to KD90 LMAD ANEMD BRS LAMD AI LMAD ALEI BRS SEMD BRS LMID LMAD KONNEW KONOLD KD21 CHATCNT $1 CHATCNT $2 KD90 KDECONF KD90 $0,CHATCNT KONOLD Load Key on New Data Key on New Data != Key on Old Data ? Yes. Branch to KD21 Load Chattering Counter Increment Chattering Counter Save Chattering Counter A <= $2 ? Yes. Branch to KD90 Set Key Decode on Flag Branch to KD90 Initialize Chattering Counter Save Key on Old Data REMD RTN KEYONF Clear Key on Flag Return * ************************************************************ * LEDDSP : LED Display ************************************************************ * LEDDSP TMD KDECONF KDECONF = 1 ? BRS LDSP10 Yes. Branch to LDSP10 BRS LDSP90 No. Branch to LDSP90 * LDSP10 REMD KDECONF Clear Key Decode on Flag * LXI $6 Initialize LED Display Data XSPX LXI $5 LYI $3 LAI $F LDSP20 LMAX LMADYX End ? BRS LDSP20 No. Branch to LDSP20 * LAMD KONNEW Load Key Data LBI $0 P $F Pattern Generation Rev. 1.0, 03/99, page 206 of 209 LMAD LAB LMAD SEG0L Save LED Display Data Lower SEG0U Save LED Display Data Upper * LDSP90 RTN Return from Subroutine * ************************************************************ * LDKYINT : Timer A Interrupt Routine ************************************************************ * LDKYINT REMD IFTA Clear Timer A Interrupt Request Flag * LMAD AESC Store Accumulator LAB LMAD BESC Store B Register XSPX LASPX LMAD XESC Store X Register XSPX LAY LMAD YESC Store Y Register * BR *+1 Set Status Flag CALL LED Subroutine Jump to 'LED' CALL KEY Subroutine Jump to 'KEY' * LAMD YESC Restore Y Register LYA LAMD XESC Restore X Register LXA LAMD BESC Restore B Register LBA LAMD AESC Restore Accumulator * RTNI Return from Interrupt * ************************************************************ * LED : LED Control ************************************************************ * LED INEMD $4,DIGCNT DIGCNT = 4 ? BRS LED00 No. Branch to LED00 LYI $3 Yes. Initialize DIGCNT BRS LED10 Branch to LED10 LED00 LAMD DIGCNT Load DIGCNT LYA RED Turn off Now Digit DY D >= 1 ? BRS LED10 Yes. Branch to LED10 SEC No. Set CA BRS LED20 Branch to LED20 Rev. 1.0, 03/99, page 207 of 209 LED10 LED20 * LXI LAM LRA LXI LAM LRA SED LAY LMAD REC TC $5 Load LED Display Data $1 $6 Output Display Data Lower to R1 Port $2 Output Display Data Upper to R2 Port Turn on Next Digit DIGCNT Save DIGCNT Reset CA Test CA RTN Return from Subroutine * ************************************************************ * KEY : Key Scan ************************************************************ * KEY LMID $F,STRBU Initialize Strobe Data Upper LMID $E,STRBL Initialize Strobe Data Lower LXI $7 * KEY00 LYI $4 LAMD STRBU Load Strobe Data Upper LRA $2 Output Strobe Data Upper to R2 Port LAMD STRBL Load Strobe Data Lower LRA $1 Output Strobe Data Lower to R1 Port NOP Wait NOP Wait NOP Wait LAR $3 Input Key Return Data LMA Save Key Return Data * LBI $1 KEY10 LYI $4 KEY20 LAM Load Key Return Data ROTR Rotate Right with Carry LMADY Save Key Return Data. Y >= 1 ? BRS KEY20 Yes. Branch to KEY20 DB Decrement B Register. B >= 1 ? BRS KEY10 Yes. Branch to KEY10 * SEC Set CA LAMD STRBL Load Strobe Data ROTL Rotate Left with Carry LMAD STRBL Save Strobe Data LAMD STRBU Load Strobe Data ROTL Rotate Left with Carry LMAD STRBU Save Strobe Data TC CA = 1 ? BRS KEY00 Yes. Branch to KEY20 Rev. 1.0, 03/99, page 208 of 209 * * KEY90 * SEMD KEYONF Set KEYONF LMID $4,DIGCNT Initialize DIGCNT RTN * ************************************************************ * LED Display Data Table ************************************************************ * org $F00 * dc $1C0 LED Display Data "0" dc $1F9 LED Display Data "1" dc $1A4 LED Display Data "2" dc $1B0 LED Display Data "3" dc $199 LED Display Data "4" dc $192 LED Display Data "5" dc $182 LED Display Data "6" dc $1D8 LED Display Data "7" dc $180 LED Display Data "8" dc $190 LED Display Data "9" dc $188 LED Display Data "A" dc $183 LED Display Data "B" dc $1C6 LED Display Data "C" dc $1A1 LED Display Data "D" dc $186 LED Display Data "E" dc $18E LED Display Data "F" * end Rev. 1.0, 03/99, page 209 of 209