HMCS400 Series
Application Note
ADE-502-064
Rev. 1.0
3/4/1999
Hitachi, Ltd.
Cautions
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life support.
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particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
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consider normally foreseeable failure rates or failure modes in semiconductor devices and
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semiconductor pro duct s .
Rev. 1.0, 03/99, page v of 209
Preface
The HMCS43XX family is a family of 4-bit microcomputers built around the HMCS400 CPU and
including standard peripheral functions such as A/D converters with a variety of A/D input
channels, serial interfaces, an d multifunction timers. Th e architectur e of the powerful HMCS400
CPU core is known for its ease of programming.
The peripheral functions of the HMCS43XX have been developed as standalone modules and a
modular architecture employed in which the respective modules are connected via a standardized
interface.
The HD404889 Series are also 4-bit microcomputers also built around the powerful HMCS400
CPU core with its excellent ease of programming, and including various peripheral functions such
as LCD circuit, A/D converters, and multifunction timers. The microcomputers in this series are
ideally suited to display panel control and system control in a wide range of applications,
primarily aud io-visual equipment such as radiocassette sets with built-in CD players, as well as
home appliances such as electronic jars, and telephones and pagers.
The peripheral functions of the HM404889 Series have been developed as standalone modules and
a modular architecture employed in which the respective modules are connected via a standardized
interface.
The “Applications” volume of the HMCS400 Series Application Notes is a collection of examples
of combinations of the built-in peripherals in the HMCS400 Series of microcomputers. This
collection is intended as a reference for software and hardware designers.
The operation of the programs and circuits, etc., described in these application notes has
been checked. However, please be sure to confirm their operation before actually using them
in any application.
Rev. 1.0, 03/99, page vii of 209
Contents
Section 1 HMCS400 Series Application Notes—
How to Use the Applications Volume..................................................... 1
1.1 Structure of Applications Section..................................................................................... 2
Section 2 Applications..................................................................................................... 5
2.1 Musical Performance........................................................................................................ 5
2.2 Stepping Motor Control.................................................................................................... 82
2.3 Key Scan and 7-Segment LED Display............................................................................ 167
Rev. 1.0, 03/99, page 1 of 209
Section 1 HMCS400 Series Application Notes—
How to Use the Applications Volume
The Application Notes are, as shown in figure 1, divided into two sections.
HMCS400 Series Application Notes—
How to Use the Applications Volume
Applications
Application Notes
Figure 1 Structure of Application Notes
HMCS400 Series Application Notes—How to Use the Applications Volume
This section describes how to use the HMCS400 Series Application Notes—Applications Volume.
Applications
This section uses sim ple example tasks to describe how various combinations of the built-in
peripherals (timers, serial interface, A/D converters, I/O ports, interrupts, low-power modes, etc.)
of the MHCS400 Series of microcomputers are used.
Rev. 1.0, 03/99, page 2 of 209
1.1 Structure of Applications Section
As shown in figure 2, the Applications section describes how to use the built-in fun c tions of the
HMCS400 Series.
Specifications
Concepts
Description of Functions
Description of Operation
Description of Software
Flowcharts
Program Listings
Applications
Description of Modules
Description of Arguments
Description of Internal
Registers
Description of RAM
Figure 2 Structure of Applications Section
Specifications
This section describes the system specifications for the example tasks.
Concepts
This section describes the methods employed to realize the systems in the example tasks.
Description of Functions
This section describes the features and distribution of the peripheral functions employed in the
example tasks.
Description of Operation
This section uses timing charts to describe the operation of the example tasks.
Rev. 1.0, 03/99, page 3 of 209
Description of Software
1. Description of Modules
This section describes the software module operating in the example tasks.
2. Description of Argu ments
This section describes the input arguments required for execution of the respective modules,
and the arguments output on completion of module execution.
3. Description of Internal Registers
This section describes the internal registers (timer control register and serial mode register,
etc.) set by the module.
4. Description of RAM
This section describes the RAM labels used by the modules and their functions.
Flowcharts
This section provides flowcharts of th e software run in the example tasks.
Program Listings
This section provides listings of the software run in the example tasks.
Rev. 1.0, 03/99, page 5 of 209
Section 2 Applications
2.1 Musical Performance
Musical Performance MCU:
H4344/H4318/H4359/
H4369/H4889
Functions Use d:
R0/R1 Port, Timer B, and Timer C
Specifications
1. As shown in figure 1, the Bach minuet is played repeatedly in the H4344/H4318/H4359/
H4369 Series by connecting a speaker with an 8-Ω resistance to the R03 port. In the H4889,
this is achieved by connecting to the R12 port.
H4344/H4318/H4359/
H4369/H4889
V
CC
R0
3
/R1
2
*
Note: *R0
3
: Employed in the H4344/H4318/H4359/H4369 Series
R1
2
: Employed in the H4889 Series
Speaker
(8-Ω impedance)
Figure 1 Speaker Connection in Musical Performance
Rev. 1.0, 03/99, page 6 of 209
Concepts
1. The “minuet” is played by outputting a pulse with a frequency corresponding to the notes from
the R03/R12 port.
2. The frequencies corresponding to the notes are set using the timer B reload timer function. The
data table is referenced using the pattern command and the referenced data set in the timer-
counter B reload value to achieve the frequency corresponding to the desired note. Moreover,
the High/Low output from the R03/R12 port is controlled during timer B interrupt processing.
3. The duration of each note is set using the timer C reload timer function. The data table is
referenced using the pattern command and the referenced data set in the timer counter C reload
value to set the output duration of each note.
4. Figure 2 shows the settings for the frequencies for the respective notes and the duration of each
note.
R0
3
/R1
2
output pin
Measurement by timer B
reload timer function Measurement by timer B
reload timer function
Setting of reload values
of timer B and timer C
Setting of reload values
of timer B and timer C
Measurement by timer C
reload timer function Measurement by timer C
reload timer function
Figure 2 Method of Set t ing Frequencies for Notes a nd Output Durations
Rev. 1.0, 03/99, page 7 of 209
Description of Functions
1. In this example task, the R0/R1 port, timer B, and timer C functions are used to play a Bach
minuet. Figure 3 is a functional block diagram of this task.
H4344/H4318/H4359/H4369/H4889 Functions
Output pulse frequency setting Pulse output duration setting
Pulse output
I/O port function
H4344/H4318/H4359/H4369: R0
3
output pin
H4889: R1
2
output pin
CPU
H4344/H4318/H4359/
H4369/H4889
Timer C
reload timer function
Timer B
reload timer function
Timer B interrupt
request Interrupt request
flag adjudication
TWCL/TWCU
setting
TWBL/TWBU
setting
Speaker output
pulse
Figure 3 Functional Block Diagram
• Timer B reload timer functio n
This function sets the output pulse frequency. Th e frequency of the output pulse is set by
the timer counter B reload value. The reload value to be set is referenced from the data
table.
• Timer C reload timer functio n
This function sets the duration for which a frequency pulse is output. The duration of pulse
output is set by th e timer counter C reload value. The reload value to be set is referenced
from the data table.
Rev. 1.0, 03/99, page 8 of 209
• I/O port func tion
This is the output for the pulse to be outpu t to the speaker.
2. The timer B, timer C, and I/O port functions are described below.
a. Figure 4 is a block diagram of the timer B function.
Timer B function (reload timer function)
Timer B interrupt cycle setting
TCB input clock setting
Prescaler S (PSS)
/2
/4
/8
/32
/128
/512
/2048
Selector
Selects division
ratio of 4
Clock derived by dividing system clock
by 4 ((4MHz/4) / 4 = 250 kHz)
Timer counter B Reload timer
function selection
TCB
overflow
TCB reload
value setting
(TCBL) (TCBU)
Timer write register B
(TWBL) (TWBU)
Timer mode
register B1
(TMB1)
Timer B interrupt
request flag
(IFTB)
Interrupt request
from TCB overflow
TCB reload value
setting
System
clock
(4 MHz/4)
EVNB pin
Edge detection
TCB reload
value setting
Reload timer
function,
TCB input
clock select
Figure 4 Timer B Function Block Diagram
Rev. 1.0, 03/99, page 9 of 209
b. Timer B is an 8-bit multifunction timer (free running/even t counter/reload timer/input
capture *1). In this example task, timer B is used as a reload timer. Table 1 describes the
timer B functions.
Table 1 Timer B Functions
Timer Mode Register B1 (TMB1)
Function TMB1 is a 4-bit write-only register. It selects the timer B function (free-running/reload
timer) and operating clock. TMB1 is initialized to $0 when reset and in stop mode.
Timer Write Register BL, U (TWBL, TWBU)
Function TWBL and TWBU form an 8-bit write-only register, which is made up of the lower digit
(TWBL) and upper digit (TWBU). TWBL and TWBU are used for the initial TCB
setting (the reload setting when operation as a reload timer).
Timer Counter B (TCB)
Function TCB is an 8-bit up-counter, which is incremented by the input internal clock. The TCB
input clock is selected using bits TMB12 to TMB10 of TMB1. The value written to
TWBL and TWBU is also written to TCB. When TCB overflows, the timer B interrupt
request flag (IFTB) is set to “1”. If, at this point, timer B is set as a reload timer, the
value of TWBL and TWBU is written to this counter and the count starts from this
value. TCB is initialized to $00 when reset and in stop mode.
Prescaler S (PSS)
Function PSS is an 11-bit counter to which the system clock is input when in active mode and
standby mode, and the subsystem clock is input when in subactive mode*2 PSS is
initialized to $000 at a reset, and division of the system clock starts when the reset is
canceled. PSS operation is halted when reset, in stop mode, and in watch mode*2.
However, it runs in other operating modes. The PSS output is shared by the internal
peripheral modules, the division ratio being set independently for each of the internal
peripheral modules.
Timer B Interrupt Request Flag (IFTB)
Function IFTB reflects the existence of the timer B interrupt request. When timer B overflows,
IFTB is set to “1 ”. IFTB can only be read/written to (only “0” can be written) using bit
operation commands. Note that IFTB is not automatically cleared even when the
interrupt is received, and must be cleared by writing “0” using software. IFTB is
cleared at a reset and in stop mode.
Timer B Interrupt Mask (IMTB)
Function IMTB is the bit that masks IFTB. When IFTB is set to “1” and, additionally, IMTB is
“0”, a timer B interrupt request is sent to the CPU (when IE = “1”). If IFTB is set to “1”
but IMTB is “1”, no interrupt request is sent to the CPU and the timer B interrupt is
held. IMTB can only be read or written to using bit operation commands. It is set to
“1” at a reset and in stop mode.
Notes: 1. Applies to H4318/H4359/H4369 Series only. In the H4344/H4889 Series, timer B has
no input capture fun ctio n.
2. Applies only to H4369/H4889 Series.
Rev. 1.0, 03/99, page 10 of 209
c. Figure 5 is a block diagram of the timer C function in the H4344/H4318/H4359/H4369
Series.
Timer C functions (reload timer function)
Timer C interrupt cycle setting
TCC input clock setting
Prescaler S (PSS)
/2
/4
/8
/32
/128
/512
/1024
/2048
Selector
Selects division
ratio of 2048
Clock derived by dividing
system clock by 2048
((4MHz/4) / 2048 = 488.28135 Hz)
Timer counter C Reload timer
function selection
TCC
overflow
TCC reload
value setting
(TCCL) (TCCU)
Timer write register C
(TWCL) (TWCU)
Timer mode
register C
(TMC)
Timer C interrupt
request flag
(IFTC)
TCC reload value
setting
System
clock
(4 MHz/4)
TCC reload
value setting
Reload timer
function,
TCC input
clock select
Figure 5 H4344/H4318/H4359/H4369 Series Timer C Function Block Diagram
Rev. 1.0, 03/99, page 11 of 209
d. Figure 6 is a block diagram of the timer C function in the H4889 Series.
Timer C function (reload timer function)
Timer C interrupt cycle setting
TCC input clock setting
Prescaler S (PSS)
/2
/4
/8
/32
/128
/512
/2048
Selector
Selects division
ratio of 2048
Clock derived by dividing
system clock by 2048
((4MHz/4) / 2048 = 488.28135 Hz)
Timer counter C Reload timer
function selection
TCC
overflow
TCC reload
value setting
(TCCL) (TCCU)
Timer write register C
(TWCL) (TWCU)
Timer mode
register C1
(TMC1)
Timer C interrupt
request flag
(IFTC)
TCC reload value
setting
System
clock
Timer B
overflow
TCC reload
value setting
Reload timer
function,
TCC input
clock select
Figure 6 H4889 Series Timer C Function Block Diagram
Rev. 1.0, 03/99, page 12 of 209
e. Timer C is an 8-bit multifunction timer (free running/reload timer). In the H4889 Series,
timer B overflow can be selected as the clock source, allowing timer B and timer C to be
used as a 16-bit counter. In this example task, timer C is used as a reload timer. Table 2
describes the timer C functions.
Table 2 Timer C Functions
Timer Mode Register C (TMC) Note: Applies to H4344/H4318/H4359/H4369 Series
Function TMC is a 4-bit write-only register. It selects the timer C function (free-running/reload
timer) and operating clock. TMC is initialized to $0 when reset and in stop mode.
Timer Mode Register C1 (TMC1) Note: Applies to H4889 Series
Function TMC1 is a 4-bit write-only register. It selects the timer C function (free-running/reload
timer) and operating clock. TMC1 is initialized to $0 when reset and in stop mode.
Timer Write Register CL, U (TWCL, TWCU)
Function TWCL and TWCU form an 8-bit write-only register, which is made up of the lower
digit (TWCL) and upper digit (TWCU). TWCL and TWCU are used for the initial TCC
setting (the reload setting when operation as a reload timer).
Timer Counter C (TCC)
Function TCC is an 8-bit up -counter, wh ich is increme nted by the input internal clock. The TCC
input clock is selected using bits TMC12 to TMC10 of TMC1. The value written to
TWCL and TWCU is also written to TCC. When TCC overflows, the timer C interrupt
request flag (IFTC) is set to “1”. If, at this point, timer C is set as a reload timer, the
value of TWCL and TWCU is written to this counter and the count starts from this
value. TCC is initialized to $00 when reset and in stop mode.
Timer C Interrupt Request Flag (IFTC)
Function IFTC reflects the existence of the timer C interrupt request. When timer C overflows,
IFTC is set to “1”. IFTC can only be read/written to (only “0” can be written) using bit
operation commands. Note that IFTC is not automatically cleared even when the
interrupt is received, and must be cleared by writing “0” using software. IFTC is
cleared at a reset and in stop mode.
Timer C Interrupt Mask (IMTC)
Function IMTC is the bit that masks IFTC. When IFTC is set to “1” and, additionally, IMTC is
“0”, a timer C interrupt request is sent to the CPU (when IE = “1”). If IFTC is set to “1”
but IMTC is “1”, no in terrupt request is sent to the CPU and the timer C interrupt is
held. IMTC can only be read or written to using bit operation commands. It is set to
“1” at a reset and in stop mode.
Rev. 1.0, 03/99, page 13 of 209
f. Figure 7 is a block diagram of the R0 port functions in the H4344/H4318/H4359/H4369
Series. Figure 8 is a block diagram of the R1 port functions in the H4889 Series.
R0 port functions
Port data register
(PDR)
R0
3
output pin function setting
Data control register
(DCR0)
Port mode register A
(PMRA)
R0
3
output
data
R0
3
output
pin function
setting
R0
3
I/O pin
function setting
R0
3
output pin
R0
port
R0
3
output
data setting
R0
3
I/O pin
function
switch setting
R0
3
/TOC
pin function
switch setting
R0
0
/SCK pin
R0
1
/SI pin
R0
2
/SO pin
R0
3
output
data
Pulse output to speaker
Figure 7 Function Block Diagram of R0 Port in H4344/H4318/H4359/H4369 Series
R1 port functions
Port data register
(PDR)
R1
2
output pin function settings
Data control register
(DCR1)
Port mode register 2
(PMR2)
R1
2
output
data
R1
2
output
pin function
setting
R1
2
I/O pin
function setting
R1
2
output pin
R1
port
R1
2
output
data setting
R1
2
I/O pin
function
switch setting
R1
2
/BUZZ
pin function
switch setting
R1
0
/EVNB pin
R1
1
/EVND pin
R1
3
/T0B pin
Pulse output to speaker
R1
2
output
data
Figure 8 Function Block Diagram of R1 Port in H4889 Series
Rev. 1.0, 03/99, page 14 of 209
g. The R0 port in the H4344/H4318/H4359/H4369 Series, and the R1 port in the H4889
Series are 4-bit I/O ports. The LAR and LBR commands are used for 4-bit input, and the
LRA and LRB commands for 4-bit output of both ports. The output data is stored in the
PDR of the respective pin. In this example task, the R03 pin in the H4344/H4318/H4359/
H4369 Series and the R12 pin the H4889 Series are set for output, and output a pulse to a
speaker. Table 3 describes the functions of the R0 port in the H4344/H4318/H4359/H4369
Series and the R1 port in the H4889 Series.
Table 3 Description of R0 Port Functions in H4344/H4318/H4359/H4369 Series and
R1 Port Functions in H4889 Series
Data Control Register R0 (DCR0) Note: Applies to H4344/H4318/H4359/H4369 Series
Function DCR0 switches the I/O pin function of the R0 port. When any bit of DCR0 is cleared
to “0”, the output buffer (CMOS) of the corresponding pin is turned OFF and the
output is set to high impedance. When the res pective bit of DCR0 is set to “1”, the
output buffer of the corresponding pin is set ON and the corresponding PDR value is
output.
Data Control Register R1 (DCR1) Note: Applies to H4889 Series
Function DCR1 switches the I/O pin function of the R1 port. When any bit of DCR1 is cleared
to “0”, the output buffer (CMOS) of the corresponding pin is turned OFF and the
output is set to high impedance. When the res pective bit of DCR1 is set to “1”, the
output buffer of the corresponding pin is set ON and the corresponding PDR value is
output.
Port Mode Register A (PMRA) Note: Applies to H4344/H4318/H4359/H4369 Series
Function PMRA is a 4-bit write-only register. Bits PMRA2 to PMRA0 switch the dual-function
R0 port pins.
Port Mode Register 2 (PMR2) Note: Applies to H4889 Series
Function PMR2 is a 4-bit write-only register. Bits PMR23 to PMR20 switch the dual-functi on R1
port pins.
Port Data Register (PDR)
Function The I/O pins of the R ports have bu ilt-in PDRs to store the output da ta. When the LRA
and LRB commands are execut ed, the con tents of the accumula tor (A) and B register
(B) are transferred to the PDR of the specified R port. When the corresponding bit of
the DCR of the R port is “1”, the output buffer of the appropriate pin is set ON and the
value in the PDR is output via that pin. The PDR is initialized to $F at a reset.
Rev. 1.0, 03/99, page 15 of 209
3. Table 4 shows the allocation of functions in the example task.
Table 4 Function Allocation
Function Function Allocation
System clock The system clock is obtained by dividing the clock output from the system
clock oscillator by 4. It is used for operating the CPU and internal
peripheral modules. In this example task, a 4 MHz system clock oscillator
is used, so the clock supplied to the CPU and internal peripheral modules
is 1 MHz. The clock used by timer B and timer C is obtained by dividing
the 1 MHz clock at PSS.
PSS The clock input to timer B and timer C is obtained by dividing the system
clock. The clock supplied to timer B is obtained by dividing the system
clock by 4. The clock supplied to timer C is obtained by dividing the
system clock by 2048.
TCB This is an 8-bit up-counter. The count starts from the value set in TWBL
and TWBU. When an overflow occurs, IFTB is set to “1”. After an
overflow, the reload value set in TWBL and TWBU is set in TCB.
TWBL, TWBU The TCB reload value is set in TWBL and TWBU. The reload value is
determined from the pulse frequency to be output to the speaker. The
frequencies corresponding to the various notes are stored in the data
table.
TMB1 TMB1 selects the reload timer function for timer B and a clock obtained by
dividing the system clock by 4 as the TCB input clock.
IFTB IFTB reflects the existence of a ti mer B interrupt request. The pulse output
pin output level is set in the timer B interrupt processing.
IMTB Enables/disables timer B interrupt requests.
TCC This is an 8-bit up-counter. The count starts from the value set in TWCL
and TWCU. When an overflow occurs, IFTC is set to “1”. After an
overflow, the reload value set in TWCL and TWCU is set in TCC.
TWCL, TWCU The TCC reload value is set in TWCL and TWCU. The reload value is
determined from the duration of pulse output to the speaker. The output
duration for each note is stored in the data table.
TMC (H4344/H4318/
H4359/H4369)
TMC1 (H4889)
TMC (or TMC1) selects the reload timer function for timer C and a c l ock
obtained by dividing the system clock by 2048 as the TCC input clock.
IFTC Reflects the existence of a timer C interrupt request.
IMTC Enables/disables timer C interrupt requests.
DCR0 (H4344/H4318/
H4359/H4369)
DCR1 (H4889)
Sets the R03 pins (H4344/H4318/H4359/H4369 Series) and R12 pins
(H4889 Series) as output pins.
Rev. 1.0, 03/99, page 16 of 209
Table 4 Function Allocation (cont)
Function Function Allocation
PMRA (H4344/H4318/
H4359/H4369)
PMR2 (H4889)
Sets the R03/TOC dual-function pin (H4344/H4318/H4359/H4369 Series)
as an R03 I/O pin and the R12/BUZZ dual-function pin (H4889 Series) as
an R12 pin.
PDR Stores the output data for the R03/R12 pin.
R03 pin Output pin for the pulse in the H4344/H4318/H4359/H4369 Series.
R12 pin Output pin for the pulse in the H4889 Series.
Rev. 1.0, 03/99, page 17 of 209
Description of Operation
1. Figure 9 shows the operating principles of the timer B, timer C, and R03/R12 output pins.
H'FF
H'7F
H'00
TCB
Time
H'FF
H'38
H'00
TCC
Time
R0
3
/R1
2
output pin
H'AB
H'9C
High
Low
409.6 ms
516 µs
Outputs
“DO”
Outputs “SO”
Software processing
Hardware processing
1.
2.
The TCB value is set to the
value in TWBL and TWBU
and the count up starts.
The TCC value is set to the
value in TWCL and TWCU
and the count up starts.
1.
2.
The data table is referenced
and the TCB reload value
set in TWBL and TWBU.
The data table is reference
and the TCC reload value
set in TWCL and TWCU.
Software processing
Hardware processing
1.
2.
3.
4.
TCB overflows.
The value in TWBL and
TWBU is set in TCB.
IFTB is set to “1”.
A “High” or “Low” signal is
output from the R0
3
/R1
2
pin.
1.
2.
3.
Timer B interrupt processing
starts.
IFTB is cleared to “0”.
Data is set in the PDR of the
R0
3
/R1
2
pin.
Software processing
Hardware processing
1.
2.
The TCB value is set to the
value in TWBL and TWBU
and the count up starts.
The TCC value is set to the
value in TWCL and TWCU
and the count up starts.
1.
2.
The data table is referenced
and the TCB reload value
set in TWBL and TWBU.
The data table is reference
and the TCC reload value
set in TWCL and TWCU.
2.064 ms
Figure 9 Operating Principles of Timer C, Timer B, and R03/R12 Output Pins
Rev. 1.0, 03/99, page 18 of 209
2. Figure 10 shows the operating principles for the pulse output from the R03/R12 pin.
1.360 ms
114.67 ms
“So” “Do” “Re” “Mi” “Fa”
319.49 ms
2.064 ms
319.49 ms 319.49 ms 319.49 ms
1.824 ms 1.616 ms 1.520 ms
1.360 ms
114.67 ms
“So” “Do”
217.09 ms
2.064 ms
421.89 ms 114.67 ms
2.064 ms
“Do”
1.216 ms
114.67 ms
“La” “Ti”
319.49 ms
1.056 ms
“Do”
217.09 ms
2.064 ms
421.89 ms 114.67 ms
2.064 ms
“Do”
“Fa”
319.49 ms
1.520 ms 1.360 ms
“So”
319.49 ms
1.216 ms
“La”
319.49 ms
R0
3
/R1
2
output pin
1.008 ms
114.67 ms
“Do”
“Fa”
1.520 ms
114.67 ms
1.360 ms
“So”
319.49 ms
“Fa”
1.520 ms
“Mi”
319.49 ms
1.616 ms
“Re”
319.49 ms
1.824 ms
319.49 ms
“ ”
“ ”
R0
3
/R1
2
output pin
R0
3
/R1
2
output pin
R0
3
/R1
2
output pin
R0
3
/R1
2
output pin
1st Cycle
Figure 10 Operating Principles of Output Pulse
Rev. 1.0, 03/99, page 19 of 209
1.360 ms
114.67 ms 319.49 ms
2.064 ms
319.49 ms 319.49 ms 319.49 ms
1.824 ms 1.616 ms 1.520 ms
1.360 ms
114.67 ms
“So” “Do”
217.09 ms
2.064 ms
421.89 ms 114.67 ms
2.064 ms
“Do”
R0
3
/R1
2
output pin
“Mi”
1.616 ms
“Fa”
319.49 ms
1.520 ms
114.67 ms
“Mi”
319.49 ms
1.616 ms
“Re”
319.49 ms
1.824 ms
“Do”
319.49 ms
2.064 ms
“Do” “Re” “Mi” “Fa”
319.49 ms
2.064 ms
319.49 ms 319.49 ms 319.49 ms
1.824 ms 1.616 ms 1.520 ms
“Ti”
2.144 ms
114.67 ms
“Re”
1.824 ms
114.67 ms
1.216 ms
114.67 ms
“La” “Ti”
319.49 ms
1.056 ms
“Fa”
319.49 ms
1.520 ms 1.360 ms
“So”
319.49 ms
1.216 ms
“La”
319.49 ms
“So” “Do” “Re” “Mi” “Fa”
“Re”
1.824 ms
114.67 ms
“Re”
1.824 ms
114.67 ms
“ ”
R0
3
/R1
2
output pin
R0
3
/R1
2
output pin
R0
3
/R1
2
output pin
R0
3
/R1
2
output pin
R0
3
/R1
2
output pin
2nd Cycle
Figure 10 Operating Principles of Output Pulse (cont)
Rev. 1.0, 03/99, page 20 of 209
“Do”
217.09 ms
2.064 ms
421.89 ms 114.67 ms
2.064 ms
“Do”
R0
3
/R1
2
output pin
1.008 ms
114.67 ms
“Do”
“Fa”
1.520 ms
114.67 ms
1.360 ms
“So”
319.49 ms
“Fa”
1.520 ms
“Mi”
319.49 ms
1.616 ms
“Re”
319.49 ms
1.824 ms
319.49 ms
“Mi”
1.616 ms
“Fa”
319.49 ms
1.520 ms
114.67 ms
“Mi”
319.49 ms
1.616 ms
“Re”
319.49 ms
1.824 ms
“Do”
319.49 ms
2.064 ms
“Re”
319.49 ms
1.824 ms
“Re”
1.824 ms
114.67 ms
“Mi”
319.49 ms
1.616 ms
“Do”
319.49 ms
2.064 ms
“Ti”
2.144 ms
319.49 ms
“Do”
319.49 ms
2.064 ms
319.49 ms
“Do”
319.49 ms
2.064 ms
“ ”
“ ”
R0
3
/R1
2
output pin
R0
3
/R1
2
output pin
R0
3
/R1
2
output pin
R0
3
/R1
2
output pin
Figure 10 Operating Principles of Output Pulse (cont)
Rev. 1.0, 03/99, page 21 of 209
3. Table 5 shows the output pulse frequencies for the respective notes.
Table 5 Output Pulse Frequencies for Respective Notes
Note Score TCB Reload
Value TCB Overflow
Cycle Speaker Pulse Output
Frequency
Ti $7A 536 µs 1 / (536 µs × 4) ≈ 466.42 Hz
Do $7F 516 µs 1 / (516 µs × 4) ≈ 484.50 Hz
Re $8E 456 µs 1 / (456 µs × 4) ≈ 548.25 Hz
Mi $9B 404 µs 1 / (404 µs × 4) ≈ 618.81 Hz
Fa $A1 380 µs 1 / (380 µs × 4) ≈ 657.89 Hz
So $AB 340 µs 1 / (340 µs × 4) ≈ 735.29 Hz
La $B4 304 µs 1 / (304 µs × 4) ≈ 822.37 Hz
Ti $BD 264 µs 1 / (264 µs × 4) ≈ 946.97 Hz
Do $C1 252 µs 1 / (252 µs × 4) ≈ 992.06 Hz
Rev. 1.0, 03/99, page 22 of 209
Description of Functions
1. Description of Modules
Table 6 describes the modules used in the example task.
Table 6 Description of Module s
Module Label Function
Main routine SPLMN This routine makes the initial stack pointer, timer B, timer C,
and I/O port settings, enables the interrupts, and initializes
the RAM to be used. It also sets the output pulse cycle
created by the timer C overflow and the output duration, and
initializes and sets those again each time another play starts.
Timer B interrupt
processing routine SPLINT Controls the “High/Low” setting of the output pulse.
2. Description of Argu ments
No arguments are used in this example task.
Rev. 1.0, 03/99, page 23 of 209
3. Description of Internal Registers
a. Table 7 shows the internal registers of the H4344/H4318/H4359/H4369 used in this
example.
Table 7 Internal Registers of H4344/H4318/H4359/H4369 Used in Example
Register Description RAM
Address Setting
IE Interrupt Enable Flag
This flag controls reception of all interrupts by the CPU.
• When IE = “0”, CPU reception of all interrupts is disabled.
• When IE = “1”, CPU reception is enabled.
0, $000 1
RSP Reset Stack Pointer
Clearing RSP to “0” initializes the stack pointer. 1, $000 0
IFTB Timer B Interrupt Request Flag
Reflects the existence of a timer B interrupt request.
• When IFTB = “0”, no timer B interrupt is requested.
• When IFTB = “1”, a timer B interrupt is requested.
0, $002 0
IMTB Timer B Interrupt Mask
This bit masks IFTB.
• When IMTB = “0”, IFTB is enabled.
• When IMTB = “1”, IFTB is masked.
1, $002 0
IFTC Timer C Interrupt Request Flag
Reflects the existence of a timer C interrupt request.
• When IFTC = “0”, no timer C interrupt is requested.
• When IFTC = “1”, a timer C interrupt is requested.
2, $002 0
IMTC Timer C Interrupt Mask
This bit masks IFTC.
• When IMTC = “0”, IFTC is enabled.
• When IMTC = “1”, IFTC is masked.
3, $002 1
PMRA Port Mode Register A
Bit 0 switches R02, SO pin functions, bit 1 switches R01/SI pin
functions, bit 2 switches R03/TOC pin functions, and bit 3
switches D3/BUZZ pin functions.
• When PMRA = $0, pins R02, R01, R03 and D3 are selecte d.
Note: PMRA bit 3 cannot be used in the H4344 Series.
$004 $0
Rev. 1.0, 03/99, page 24 of 209
Table 7 Internal Registers of H4344/H4318/H4359/H4369 Used in Example (cont)
Register Description RAM
Address Setting
TMB1 Timer Mode Register B1
TMB13 selects timer B functions, TMB12 to TMB10 select the
operating cl oc k
• When TMB13 = “1”, TMB12 = “1”, TMB11 = “1”, and TMB10
= “1”, timer B is set for reload timer functions and the
operating clock is set for the system clock divided by 4.
$009 $D
TWBL Timer Write Register BL
Sets the lower digit of the TCB reload value. $00A $0
TWBU Timer Write Register BU
Sets the upper digit of the TCB reload value. $00B $0
TMC Timer Mode Register C
Selects timer C functions and operating clock.
• When TMC3 = “1”, TMC2 = “0”, TMC1 = “0”, and TMC0 =
“0”, timer C is set for reload timer functions and the
operating clock is set for the system clock divided by 2048.
$00D $8
TWCL Timer Write Register CL
Sets the lower digit of the TCC reload value. $00E $0
TWCU Timer Write Register CU
Sets the upper digit of the TCC reload value. $00F $0
TMB2 Timer Mode Register B2
Sets the input capture function and selects the detection edge of
the EVNB pin input.
• When TMB22 = “0”, free-running/reload timer B functions
are selected.
• When TMB22 = “1”, input capture timer B functions are
selected.
Note: The TMB22 bit cannot be used in the H4344.
• When TMB21 = “0” and TMB20 = “0”, there is no edge
detection of the EVNB pin input.
$026 $0
Rev. 1.0, 03/99, page 25 of 209
Table 7 Internal Registers of H4344/H4318/H4359/H4369 Used in Example (cont)
Register Description RAM
Address Setting
SSR1 System Clock Selection Register 1
Selects the system clock os cillation frequency, subsystem clock
frequency division, and, in stop mode, the subsystem clock
oscillation.
• When SSR11 = “0”, the system clock oscillation frequency is
set to 0.4 to 1 MHz.
• When SSR11 = “1”, the system clock oscillation frequency is
set to 1.6 to 5 MHz.
Note: Applicable only to H4369
$027 $2
DCR0 Data Control Register R0
Controls the ON/OFF state of the R0 port output buffer.
• When DCR03 = “0”, the R03 pin output buffer is set OFF and
output set to high impedance.
• When DCR03 = “1”, the R03 pin output buffer is set ON and
the value in the corresponding PDR is output.
$030 $8
Rev. 1.0, 03/99, page 26 of 209
b. Table 8 describes the internal registers used in the H4889.
Table 8 Internal Registers Used in H4889
Register Function RAM
Address Setting
IE Interrupt Enable Flag
Controls whether interrupts are rece ived by the CPU.
• When IE = “0”, CPU interrupt reception is disabled.
• When IE = “1”, CPU interrupt reception is enabled.
0, $000 1
RSP Reset Stack Pointer
Clearing RSP to “0” initializes the stack pointer. 1, $000 0
IFTB Timer B Interrupt Request Flag
Reflects the existence of a timer B interrupt request.
• When IFTB = “0”, no timer B interrupt is requested.
• When IFTB = “1”, a timer B interrupt is requested.
2, $002 0
IMTB Timer B Interrupt Mask
This bit masks IFTB.
• When IMTB = “0”, IFTB is enabled.
• When IMTB = “1”, IFTB is masked.
3, $002 0
IFTC Timer C Interrupt Request Flag
Reflects the existence of a timer C interrupt request.
• When IFTC = “0”, no timer C interrupt is requested.
• When IFTC = “1”, a timer C interrupt is requested.
0, $003 0
IMTC Timer C Interrupt Mask
This bit masks IFTC.
• When IMTC = “0”, IFTC is enabled.
• When IMTC = “1”, IFTC is masked.
1, $003 1
SSR System Clock Selection Register
Selects the system clock os cillation frequency, subsystem clock
frequency division, the subsystem clock oscillation, and the
system clock division ratio for stop mode.
• When SSR1 = “0”, the system clock oscillation frequency is
set to 0.4 to 1.0 MHz.
• When SSR1 = “1”, the system clock oscillation frequency is
set to 1.6 to 4.5 MHz.
$004 $2
Rev. 1.0, 03/99, page 27 of 209
Table 8 Internal Registers Used in H4889 (cont)
Register Function RAM
Address Setting
PMR2 Port Mode Register 2
Bit 0 switches R10/EVNB pin functions, bit 1 switches R11/EVND
pin functions, bit 2 switches R12/BUZZ pin functions, and bit 3
switches R13/TOB pin functions.
• When PMR2 = $0, R10, R11, R12 an d R13 pins are selected.
$00A $0
TMB1 Timer Mode Register B1
TMB13 selects timer B functions, TMB12 to TMB10 select the
operating cl oc k.
• When TMB13 = “1”, TMB12 = “1”, TMB11 = “0” and TMB10
= “1”, timer B has reload timer functions, and the operating
clock is set to the system cl ock divi ded by 4.
$010 $D
TMB2 Timer Mode Register B2
Selects timer B output mode and EVNB pin input detection
edge.
• When TMB22 = “0”, timer B output is set to a toggle
waveform.
• When TMB22 = “1”, timer B output is set for PWM output.
• When TMB21 = “0” and TMB20 = “0”, there is no EVNB pin
input edge detection.
$011 $0
TWBL Timer Write Register BL
Sets the lower digit of the TCB reload value. $012 $0
TWBU Timer Write Register BU
Sets the upper digit of the TCB reload value. $013 $0
TMC1 Timer Mode Register C1
Selects timer C functions and operating clock.
• When TMC13 = “1”, TMC12 = “0”, TMC11 = “0”, and TMC10
= “0”, timer C functions as a reload timer, and the operating
clock is set to the system cl ock divi ded by 2048 .
$014 $8
TWCL Timer Write Register CL
Sets the lower digit of the TCC reload value. $016 $0
TWCU Timer Write Register CU
Sets the upper digit of the TCC reload value. $017 $0
Rev. 1.0, 03/99, page 28 of 209
Table 8 Internal Registers Used in H4889 (cont)
Register Function RAM
Address Setting
DCR1 Data Control Register R1
Controls the ON/OFF state of the R1 port output buffer.
• When DCR12 = “0”, the R12 pin output buffer is set OFF and
the output is set to high impedance.
• When DCR12 = “1”, the R12 pin output buffer is set ON and
the value of the corresponding PDR is output.
$035 $4
4. Description of RAM
Table 9 shows the RAM used in this example task.
Table 9 Used RAM
Label Function RAM
Address Module
AESC Stores the contents of the accumulator during timer B interrupt
processing. $040 SPLINT
BESC Stores the contents of the B register during timer B interrupt
processing. $041 SPLINT
PLCNT This counter controls the High/Low output when outputting a
pulse from the R03/R12 pin. $090 SPLMN,
SPLINT
PLONF This flag controls the enabling/disabling of pulse output. 0, $091 SPLMN,
SPLINT
CNTL Stores the contents of the accumulator used for specifying the
address when exe cut ing a pattern com m and. $093 SPLMN
CNTU Stores the contents of the B register used for specifying the
address when exe cut ing a pattern com m and. $094 SPLMN
PCNT This counter controls the number of times a pulse of a given
frequency is output. $095 SPLMN
AWORK Temporarily stores the contents of the accumulator during
processing of the main routine. $097 SPLMN
BWORK Temporarily stores the contents of the B register during
processing of the main routine. $098 SPLMN
Rev. 1.0, 03/99, page 29 of 209
Flow charts
1. H4344/H4318/H4359/H4369
a. Main Routine
SPLMN
Reset stack pointer
Set SSR11 to “1”,
and set system clock
to 1.6 to 5.0 MHz
Set R0 port PDR to $0,
and initialize R0 port
Set DCR0 to $8, and set
R0
3
I/O pin to function
as R0
3
output pin
Set PMRA to $0 and set
R0
3
/TOC dual-function
pin to function as R0
3
I/O pin
Initialize PLCNT to $3
Initialize CNTL to $0
Initialize CNTU to $0
Initialize PCNT to $F
Initialize PLONF to “1”
Set TMC to $8, and set
timer C to function as
reload timer and TCC
input clock to the system
clock divided by 2048
Clear IFTC to “0”
Set TMB1 to $D, and set
timer B to function as
reload timer and TCB
input clock to the system
clock divided by 4
Clear IMTB to “0” to
enable timer B interrupts
Clear IFTB to “0”
1
Set IE to “1” to enable
interrupts
1
IFTC = “1”?
Clear IFTC to “0”
Increment PCNT
PCNT OVF?
Execute P command
from values of CNTL
and CNTU, reference the
cycle data corresponding
to the tone to be output
from the data table, store
the contents of the
accumulator in AWORK
and the contents of the
B register in BWORK
BWORK <= “0”?
Set IMTB to “1” to
disable timer B interrupts
Initialize CNTL to $0
Initialize CNTU to $0
Set R0 port PDR to $0
and initialize R0 port
Set TWCL to $0 and
TWCU to $8, setting the
TCC reload value to $80
Clear IFTC to “0”
4
2
No
Yes
No
Yes
Yes
No
Note: * Applies only to H4369.
*
Rev. 1.0, 03/99, page 30 of 209
2
BWORK <= $E?
Write the contents of
AWORK to TWBL and
of BWORK to TWBU
to set the TCB reload
value
Clear IFTB to “0”
Yes
No
Set IMTB to “1” to
disable timer B
interrupts
Execute the P command
from the values of CNTL
and CNTU, reference the
cycle data corresponding
to the duration of the
note to be output from
the data table, store the
contents of the
accumulator in TWCL
and the contents of the B
register in TWCU to set
the TCC reload value
Execute the P command
from the values of CNTL
and CNTU, reference
the PCNT data from the
data table, and store
the contents of the
accumulator in PCNT
Increment CNTL
Increment CNTU
4
Set IMTB to “1”
to disable timer B
interrupts
Clear IFTB to “0”
Set R0 port PDR to $0
Rev. 1.0, 03/99, page 31 of 209
b. Timer B Interrupt Processing Routine
SPLINT
Clear IFTB to “0”
Save registers
PLONF = “1”?
PLCNT <= $1?
Output High from
P03 pin
PLCNT = PLCNT + $F
PLCNT OVF?
Initialize PLCNT to $3
Restore registers
RTNI
Output Low from P03
Output Low from
P03 pin
Yes
Yes
No
No
Yes
No
Rev. 1.0, 03/99, page 32 of 209
2. H4889
a. Main Routine
SPLMN
Reset stack pointer
Set SSR1 to “1”,
and set system clock
to 1.6 to 4.5 MHz
Set R1 port PDR to $0,
and initialize R1 port
Set DCR1 to $4, and set
R1
2
I/O pin to function
as R1
2
output pin
Set PMR2 to $0 and set
R1
2
/BUZZ dual-function
pin to function as R1
2
I/O pin
Initialize PLCNT to $3
Initialize CNTL to $0
Initialize CNTU to $0
Initialize PCNT to $F
Initialize PLONF to “1”
Set TMC1 to $8, and set
timer C to function as
reload timer and TCC
input clock to the system
clock divided by 2048
Clear IFTC to “0”
Set TMB1 to $D, and set
timer B to function as
reload timer and TCB
input clock to the system
clock divided by 4
Clear IMTB to “0” to
enable timer B interrupts
Clear IFTB to “0”
1
Set IE to “1” to enable
interrupts
1
IFTC = “1”?
Clear IFTC to “0”
Increment PCNT
PCNT OVF?
Execute P command
from values of CNTL
and CNTU, reference the
cycle data corresponding
to the tone to be output
from the data table, store
the contents of the
accumulator in AWORK
and the contents of the
B register in BWORK
BWORK <= “0”?
Set IMTB to “1” to
disable timer B interrupts
Initialize CNTL to $0
Initialize CNTU to $0
Set R1 port PDR to $0
and initialize R1 port
Set TWCL to $0 and
TWCU to $8, setting the
TCC reload value to $80
Clear IFTC to “0”
4
2
No
Yes
No
Yes
Yes
No
Rev. 1.0, 03/99, page 33 of 209
2
BWORK <= $E?
Write the contents of
AWORK to TWBL and
of BWORK to TWBU
to set the TCB reload
value
Clear IFTB to “0”
Yes
No
Set IMTB to “1” to
disable timer B
interrupts
Execute the P command
from the values of CNTL
and CNTU, reference the
cycle data corresponding
to the duration of the
note to be output from
the data table, store the
contents of the
accumulator in TWCL
and the contents of the B
register in TWCU to set
the TCC reload value
Execute the P command
from the values of CNTL
and CNTU, reference
the PCNT data from the
data table, and store
the contents of the
accumulator in PCNT
Increment CNTL
Increment CNTU
4
Set IMTB to “1” to
disable timer B
interrupts
Clear IFTB to “0”
Set R1 port PDR to $0
Rev. 1.0, 03/99, page 34 of 209
b. Timer B Interrupt Processing Routine
SPLINT
Clear IFTB to “0”
Save registers
PLONF = “1”?
PLCNT <= $1?
Output High from
P12 pin
PLCNT = PLCNT + $F
PLCNT OVF?
Initialize PLCNT to $3
Restore registers
RTNI
Output Low from P12
Output Low from
P12 pin
Yes
Yes
No
No
Yes
No
Rev. 1.0, 03/99, page 35 of 209
Program Listing
1. H4344
************************************************************
*
* HMCS400 Series Application Note
*
* 'Sound Play
* - Minuet : J.S.Bach'
*
* MCU : H4344
*
* External Clock : 4MHz
* Internal Clock : 1MHz
* Sub Clock : 32.768kHz
*
************************************************************
*
************************************************************
* Symbol Definition
************************************************************
*
IE equ 0,$000 Interrupt Enable Flag
RSP equ 1,$000 Reset Stack Pointer
IF0 equ 2,$000 INT0 Interrupt Request Flag
IM0 equ 3,$000 INT0 Interrupt Mask
*
IFTB equ 0,$002 Timer B Interrupt Request Flag
IMTB equ 1,$002 Timer B Interrupt Mask
IFTC equ 2,$002 Timer C Interrupt Request Flag
IMTC equ 3,$002 Timer C Interrupt Mask
*
IFAD equ 0,$003 A/D Converter Interrupt Request Flag
IMAD equ 1,$003 A/D Converter Interrupt Mask
IFS equ 2,$003 Serial Interrupt Request Flag
IMS equ 3,$003 Serial Interrupt Mask
*
PMRA equ $004 Port Mode Register
SMR equ $005 Serial Mode Register
SRL equ $006 Serial Data Register L
SRU equ $007 Serial Data Register U
*
TMB1 equ $009 Timer Mode Register B1
TRBL equ $00A Timer Read Register BL
TWBL equ $00A Timer Write Register BL
TRBU equ $00B Timer Read Register BU
TWBU equ $00B Timer Write Register BU
MIS equ $00C Miscellaneous Register
TMC equ $00D Timer Mode Register C
TRCL equ $00E Timer Read Register CL
Rev. 1.0, 03/99, page 36 of 209
TWCL equ $00E Timer Write Register CL
TRCU equ $00F Timer Read Register CU
TWCU equ $00F Timer Write Register CU
ACR equ $016 A/D Channel Register
ADRL equ $017 A/D Data Register L
ADRU equ $018 A/D Data Register U
AMR1 equ $019 A/D Mode Register 1
AMR2 equ $01A A/D Mode Register 2
*
WDON equ 1,$020 Watchdog on Flag
ADSF equ 2,$020 A/D Start Flag
*
IAOF equ 2,$021 IAD off Flag
RAME equ 3,$021 RAM Enable Flag
*
PMRB equ $024 Port Mode Register B
PMRC equ $025 Port Mode Register C
TMB2 equ $026 Timer Mode Register B2
*
DCD0 equ $02C D Port Data Control Register 0
DCD1 equ $02D D Port Data Control Register 1
*
DCR0 equ $030 R Port Data Control Register 0
DCR1 equ $031 R Port Data Control Register 1
DCR2 equ $032 R Port Data Control Register 2
DCR3 equ $033 R Port Data Control Register 3
*
************************************************************
* RAM ALLOCATION
************************************************************
*
AESC equ $040 Accumulator Escape
BESC equ $041 B Register Escape
*
PLCNT equ $090 Pulse Counter
*
PLFLG1 equ $091 Pulse Flag 1
PLONF equ 0,PLFLG1 Pulse Output Enable Flag
*
CNTL equ $093 Lower Counter
CNTU equ $094 Upper Counter
PCNT equ $095 Period Counter
AWORK equ $096 Accumulator Work RAM Area
BWORK equ $097 B Register Work RAM Area
*
************************************************************
* Vector Address
************************************************************
*org $0000
*
Rev. 1.0, 03/99, page 37 of 209
JMPL SPLMN Reset Interrupt
JMPL SPLMN INT0 Interrupt
*org $0008
*JMPL SPLINT Timer B Interrupt
JMPL SPLMN Timer C Interrupt
JMPL SPLMN A/D Converter Interrupt
JMPL SPLMN Serial Interrupt
*
************************************************************
* Main Program
************************************************************
*org $1000
*
SPLMN REMD RSP Reset Stack Pointer
*LAI 0
LRA 0 Initialize R0 Port PDR
LMID 8,DCR0 Initialize R03 Output Terminal Function
LMID 0,PMRA Initialize R03 Input/Output Terminal Function
*LMID 3,PLCNT Initialize Pulse Counter
LMID 0,CNTL Initialize Lower Counter
LMID 0,CNTU Initialize Upper Counter
LMID $F,PCNT Initialize Period Counter
SEMD PLONF Initialize Pulse Output Enable Flag
*LMID 8,TMC Initialize Timer C Function & Input Clock Period
REMD IFTC Clear IFTC to 0
*LMID $D,TMB1 Initialize Timer B Function & Input Clock Period
LMID 0,TMB2 Initialize Timer B Function
*SEMD IMTB Timer B Interrupt Disable
REMD IFTB Clear IFTB to 0
*SEMD IE All Interrupt Enable
*
SPLMN00 TMD IFTC IFTC = "1" ?
BRS SPLMN10 Yes. Branch to SPLMN10
BRS SPLMN00 No. Branch to SPLMN00
*REMD IFTC Clear IFTC to 0
LMID 9,TWCL Set TCC Reload Value Lower
LMID 0,TWCU Set TCC Reload Value Upper
*
SPLMN05 TMD IFTC IFTC = "1" ?
BRS SPLMN10 Yes. Branch to SPLMN10
SEMD IMTB Timer B Interrupt Disable
Rev. 1.0, 03/99, page 38 of 209
REMD IFTB Clear IFTB to 0
LAI 0
LRA 0 Sound off
BRS SPLMN05 Branch to SPLMN05
*
SPLMN10 REMD IFTC Clear IFTC to 0
LAMD PCNT Load PCNT
AI 1 Increment PCNT
BRS SPLMN40 PCNT Overflow ? Yes. Branch to SPLMN40
LMAD PCNT No. Save PCNT
BRS SPLMN00 Branch to SPLMN00
*
SPLMN40 LAMD CNTU Load CNTL
LBA
LAMD CNTL Load CNTU
P 2 Scale Data Pattern Generation
LMAD AWORK Save Scale Lower Data
LAB
LMAD BWORK Save Scale Upper Data
ALEI 0 Scale Upper Data <= $0 ? End Sound Play ?
BRS SPLMN90 Yes. Branch to SPLMN90
ALEI $E Scale Upper Data <= $E ?
BRS SPLMN20 Yes. Branch to SPLMN20
SEMD IMTB Timer B Interrupt Disable
REMD IFTB Clear IFTB to 0
LAI 0
LRA 0 R03 Output Terminal is "Low" Output
BRS SPLMN30 Branch to SPLMN30
*
SPLMN20 LAMD AWORK Load AWORK
LMAD TWBL Set TCB Reload Value Lower to Scale Data
LAMD BWORK Load BWORK
LMAD TWBU Set TCB Reload Value Upper to Scale Data
REMD IFTB Clear IFTB to 0
REMD IMTB Timer B Interrupt Enable
*
SPLMN30 LAMD CNTU Load Upper Counter
LBA
LAMD CNTL Load Lower Counter
P 3 Time Period Data Pattern Generation
LMAD TWCL Set TCC Reload Value Lower to Time Period Lower Data
LAB
LMAD TWCU Set TCC Reload Value Upper to Time Period Upper Data
*LAMD CNTU Load Upper Counter
LBA
LAMD CNTL Load Lower Counter
P 4 Time Counter Data Pattern Generation
LMAD PCNT Set PCNT to Time Counter Data
*SEC Set Carry Flag at 1
Rev. 1.0, 03/99, page 39 of 209
LAI 0
AMCD CNTL Increment Lower Counter
LMAD CNTL Save Lower Counter
LAI 0
AMCD CNTU If CNTL Overflow, Increment Upper Counter
LMAD CNTU Save Upper Counter
BR *+1
BRS SPLMN00 Branch to SPLMN00
*
SPLMN90 SEMD IMTB Timer B Interrupt Disable
LMID 0,CNTL Initialize Lower Counter
LMID 0,CNTU Initialize Upper Counter
LAI 0
LRA 0 Initialize R0 Port PDR
LMID 0,TWCL Initialize TCC Reload Value Lower
LMID 8,TWCU Initialize TCC Reload Value Upper
REMD IFTC Clear IFTC to 0
BRS SPLMN00 Branch to SPLMN00
*
************************************************************
* Timer B Interrupt Process
* ---Pulse Output Routine---
************************************************************
*
SPLINT REMD IFTB Clear IFTB to 0
*LMAD AESC Store Accumulator
LAB
LMAD BESC Store B Register
*TMD PLONF Pulse Enable Flag = "1" ?
BRS PLI00 Yes. Branch to PLI00
LAI 0 No. Stop Output Pulse
LRA 0 R03 Output Terminal is "Low" Output
BRS PLI99 Branch to PLI99
*
PLI00 LAMD PLCNT Load Pulse Counter Value
LBA Store Pulse Counter Value
ALEI 1 PLCNT <= $1 ? Is R03 Output Terminal "High" Output ?
BRS PLI10 Yes. Branch to PLI10
LAI 0 No. R03 Output Terminal is "Low" Output
BRS PLI20 Branch to PLI20
PLI10 LAI 8
PLI20 LRA 0 R03 Output Terminal is "High" Output
LAB Restore Pulse Counter Value
AI $F PLCNT + $F <= $F ? Pulse Counter = $0 ?
BRS PLI30 No. Branch to PLI30
LAI 3 Yes. Pulse Counter Initialize
PLI30 LMAD PLCNT Save Pulse Counter Value
*
PLI99 LAMD BESC Restore B Register
Rev. 1.0, 03/99, page 40 of 209
LBA
LAMD AESC Restore Accumulator
*RTNI Return from Interrupt
*
************************************************************
* Scale Data
************************************************************
*ORG $0200
*
*** 1st Cycle
*dc $1AB 'G' Data. TCB Reload Value = $AB
dc $17F 'C' Data. TCB Reload Value = $7F
dc $18E 'D' Data. TCB Reload Value = $8E
dc $19B 'E' Data. TCB Reload Value = $9B
dc $1A1 'F' Data. TCB Reload Value = $A1
*dc $1AB 'G' Data. TCB Reload Value = $AB
dc $17F 'C' Data. TCB Reload Value = $7F
dc $1FF ' ' Data. TCB Reload Value = $FF
dc $17F 'C' Data. TCB Reload Value = $7F
*dc $1B4 'A' Data. TCB Reload Value = $B4
dc $1A1 'F' Data. TCB Reload Value = $A1
dc $1AB 'G' Data. TCB Reload Value = $AB
dc $1B4 'A' Data. TCB Reload Value = $B4
dc $1BD 'B' Data. TCB Reload Value = $BD
*dc $1C1 'C' Data. TCB Reload Value = $C1
dc $17F 'C' Data. TCB Reload Value = $7F
dc $1FF ' ' Data. TCB Reload Value = $FF
dc $17F 'C' Data. TCB Reload Value = $7F
*dc $1A1 'F' Data. TCB Reload Value = $A1
dc $1AB 'G' Data. TCB Reload Value = $AB
dc $1A1 'F' Data. TCB Reload Value = $A1
dc $19B 'E' Data. TCB Reload Value = $9B
dc $18E 'D' Data. TCB Reload Value = $8E
*dc $19B 'E' Data. TCB Reload Value = $9B
dc $1A1 'F' Data. TCB Reload Value = $A1
dc $19B 'E' Data. TCB Reload Value = $9B
dc $18E 'D' Data. TCB Reload Value = $8E
dc $17F 'C' Data. TCB Reload Value = $7F
*dc $17A 'B' Data. TCB Reload Value = $7A
dc $17F 'C' Data. TCB Reload Value = $7F
dc $18E 'D' Data. TCB Reload Value = $8E
dc $19B 'E' Data. TCB Reload Value = $9B
Rev. 1.0, 03/99, page 41 of 209
dc $17F 'C' Data. TCB Reload Value = $7F
*dc $18E 'D' Data. TCB Reload Value = $8E
*
*** 2nd Cycle
*dc $1AB 'G' Data. TCB Reload Value = $AB
dc $17F 'C' Data. TCB Reload Value = $7F
dc $18E 'D' Data. TCB Reload Value = $8E
dc $19B 'E' Data. TCB Reload Value = $9B
dc $1A1 'F' Data. TCB Reload Value = $A1
*dc $1AB 'G' Data. TCB Reload Value = $AB
dc $17F 'C' Data. TCB Reload Value = $7F
dc $1FF ' ' Data. TCB Reload Value = $FF
dc $17F 'C' Data. TCB Reload Value = $7F
*dc $1B4 'A' Data. TCB Reload Value = $B4
dc $1A1 'F' Data. TCB Reload Value = $A1
dc $1AB 'G' Data. TCB Reload Value = $AB
dc $1B4 'A' Data. TCB Reload Value = $B4
dc $1BD 'B' Data. TCB Reload Value = $BD
*dc $1C1 'C' Data. TCB Reload Value = $C1
dc $17F 'C' Data. TCB Reload Value = $7F
dc $1FF ' ' Data. TCB Reload Value = $FF
dc $17F 'C' Data. TCB Reload Value = $7F
*dc $1A1 'F' Data. TCB Reload Value = $A1
dc $1AB 'G' Data. TCB Reload Value = $AB
dc $1A1 'F' Data. TCB Reload Value = $A1
dc $19B 'E' Data. TCB Reload Value = $9B
dc $18E 'D' Data. TCB Reload Value = $8E
*dc $19B 'E' Data. TCB Reload Value = $9B
dc $1A1 'F' Data. TCB Reload Value = $A1
dc $19B 'E' Data. TCB Reload Value = $9B
dc $18E 'D' Data. TCB Reload Value = $8E
dc $17F 'C' Data. TCB Reload Value = $7F
*dc $18E 'D' Data. TCB Reload Value = $8E
dc $19B 'E' Data. TCB Reload Value = $9B
dc $18E 'D' Data. TCB Reload Value = $8E
dc $17F 'C' Data. TCB Reload Value = $7F
dc $17A 'B' Data. TCB Reload Value = $7A
*dc $17F 'C' Data. TCB Reload Value = $7F
dc $1FF ' ' Data. TCB Reload Value = $FF
*dc $100 ' ' Data. TCB Reload Value = $00
*
Rev. 1.0, 03/99, page 42 of 209
************************************************************
* Time Period Data
************************************************************
*org $0300
*
*** 1st Cycle
*dc $138 'G' Time Period Data. TCC Reload Value = $38
dc $19C 'C' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
*dc $138 'G' Time Period Data. TCC Reload Value = $38
dc $16A 'C' Time Period Data. TCC Reload Value = $6A
dc $1CE ' ' Time Period Data. TCC Reload Value = $CE
dc $138 'C' Time Period Data. TCC Reload Value = $38
*dc $138 'A' Time Period Data. TCC Reload Value = $38
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
dc $19C 'G' Time Period Data. TCC Reload Value = $9C
dc $19C 'A' Time Period Data. TCC Reload Value = $9C
dc $19C 'B' Time Period Data. TCC Reload Value = $9C
*dc $138 'C' Time Period Data. TCC Reload Value = $38
dc $16A 'C' Time Period Data. TCC Reload Value = $6A
dc $1CE ' ' Time Period Data. TCC Reload Value = $CE
dc $138 'C' Time Period Data. TCC Reload Value = $38
*dc $138 'F' Time Period Data. TCC Reload Value = $38
dc $19C 'G' Time Period Data. TCC Reload Value = $9C
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
*dc $138 'E' Time Period Data. TCC Reload Value = $38
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
dc $19C 'C' Time Period Data. TCC Reload Value = $9C
*dc $138 'B' Time Period Data. TCC Reload Value = $38
dc $19C 'C' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'C' Time Period Data. TCC Reload Value = $9C
*dc $138 'D' Time Period Data. TCC Reload Value = $38
*
*** 2nd Cycle
Rev. 1.0, 03/99, page 43 of 209
*dc $138 'G' Time Period Data. TCC Reload Value = $38
dc $19C 'C' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
*dc $138 'G' Time Period Data. TCC Reload Value = $38
dc $16A 'C' Time Period Data. TCC Reload Value = $6A
dc $1CE ' ' Time Period Data. TCC Reload Value = $CE
dc $138 'C' Time Period Data. TCC Reload Value = $38
*dc $138 'A' Time Period Data. TCC Reload Value = $38
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
dc $19C 'G' Time Period Data. TCC Reload Value = $9C
dc $19C 'A' Time Period Data. TCC Reload Value = $9C
dc $19C 'B' Time Period Data. TCC Reload Value = $9C
*dc $138 'C' Time Period Data. TCC Reload Value = $38
dc $16A 'C' Time Period Data. TCC Reload Value = $6A
dc $1CE ' ' Time Period Data. TCC Reload Value = $CE
dc $138 'C' Time Period Data. TCC Reload Value = $38
*dc $138 'F' Time Period Data. TCC Reload Value = $38
dc $19C 'G' Time Period Data. TCC Reload Value = $9C
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
*dc $138 'E' Time Period Data. TCC Reload Value = $38
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
dc $19C 'C' Time Period Data. TCC Reload Value = $9C
*dc $138 'D' Time Period Data. TCC Reload Value = $38
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
dc $19C 'C' Time Period Data. TCC Reload Value = $9C
dc $19C 'B' Time Period Data. TCC Reload Value = $9C
*dc $138 'C' Time Period Data. TCC Reload Value = $38
dc $138 ' ' Time Period Data. TCC Reload Value = $38
*
************************************************************
* Times Counter Data
************************************************************
*org $0400
*
*** 1st Cycle
Rev. 1.0, 03/99, page 44 of 209
*dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
*dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F ' ' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10F 'A' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'A' Time Counter Data. PCNT = $F
dc $10F 'B' Time Counter Data. PCNT = $F
*dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F ' ' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
*dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10F 'B' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10D 'D' Time Counter Data. PCNT = $D
*
*** 2nd Cycle
*dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
*
Rev. 1.0, 03/99, page 45 of 209
dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F ' ' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10F 'A' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'A' Time Counter Data. PCNT = $F
dc $10F 'B' Time Counter Data. PCNT = $F
*dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F ' ' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
*dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F 'B' Time Counter Data. PCNT = $F
*dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
*dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10F 'B' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10D 'D' Time Counter Data. PCNT = $D
Rev. 1.0, 03/99, page 46 of 209
*** 2nd Cycle
dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
*dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F ' ' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10F 'A' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'A' Time Counter Data. PCNT = $F
dc $10F 'B' Time Counter Data. PCNT = $F
*dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F ' ' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
*dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F 'B' Time Counter Data. PCNT = $F
*
dc $10E 'C' Time Counter Data. PCNT = $E
dc $10F ' ' Time Counter Data. PCNT = $F
end
Rev. 1.0, 03/99, page 47 of 209
2. H4318/H4359
************************************************************
*
* HMCS400 Series Application Note
*
* 'Sound Play
* - Minuet : J.S.Bach'
*
* MCU : H4318/H4359
*
* External Clock : 4MHz
* Internal Clock : 1MHz
* Sub Clock : 32.768kHz
*
************************************************************
*
************************************************************
* Symbol Definition
************************************************************
*
IE equ 0,$000 Interrupt Enable Flag
RSP equ 1,$000 Reset Stack Pointer
IF0 equ 2,$000 INT0 Interrupt Request Flag
IM0 equ 3,$000 INT0 Interrupt Mask
*
IF1 equ 0,$001 INT1 Interrupt Request Flag
IM1 equ 1,$001 INT1 Interrupt Mask
IFTA equ 2,$001 Timer A Interrupt Request Flag
IMTA equ 3,$001 Timer A Interrupt Mask
*
IFTB equ 0,$002 Timer B Interrupt Request Flag
IMTB equ 1,$002 Timer B Interrupt Mask
IFTC equ 2,$002 Timer C Interrupt Request Flag
IMTC equ 3,$002 Timer C Interrupt Mask
*
IFAD equ 0,$003 A/D Converter Interrupt Request Flag
IMAD equ 1,$003 A/D Converter Interrupt Mask
IFS equ 2,$003 Serial Interrupt Request Flag
IMS equ 3,$003 Serial Interrupt Mask
*
PMRA equ $004 Port Mode Register
SMR equ $005 Serial Mode Register
SRL equ $006 Serial Data Register L
SRU equ $007 Serial Data Register U
TMA equ $008 Timer Mode Register A
TMB1 equ $009 Timer Mode Register B1
TRBL equ $00A Timer Read Register BL
TWBL equ $00A Timer Write Register BL
TRBU equ $00B Timer Read Register BU
TWBU equ $00B Timer Write Register BU
Rev. 1.0, 03/99, page 48 of 209
MIS equ $00C Miscellaneous Register
TMC equ $00D Timer Mode Register C
TRCL equ $00E Timer Read Register CL
TWCL equ $00E Timer Write Register CL
TRCU equ $00F Timer Read Register CU
TWCU equ $00F Timer Write Register CU
ACR equ $016 A/D Channel Register
ADRL equ $017 A/D Data Register L
ADRU equ $018 A/D Data Register U
AMR1 equ $019 A/D Mode Register 1
AMR2 equ $01A A/D Mode Register 2
*
WDON equ 1,$020 Watchdog on Flag
ADSF equ 2,$020 A/D Start Flag
*
ICSF equ 0,$021 Input Capture Status Flag
ICEF equ 1,$021 Input Capture Error Flag
IAOF equ 2,$021 IAD off Flag
RAME equ 3,$021 RAM Enable Flag
*
PMRB equ $024 Port Mode Register B
PMRC equ $025 Port Mode Register C
TMB2 equ $026 Timer Mode Register B2
DCD0 equ $02C D Port Data Control Register 0
DCD1 equ $02D D Port Data Control Register 1
DCD2 equ $02E D Port Data Control Register 2
DCR0 equ $030 R Port Data Control Register 0
DCR1 equ $031 R Port Data Control Register 1
DCR2 equ $032 R Port Data Control Register 2
DCR3 equ $033 R Port Data Control Register 3
DCR4 equ $034 R Port Data Control Register 4
DCR8 equ $038 R Port Data Control Register 8
*
************************************************************
* RAM ALLOCATION
************************************************************
*
AESC equ $040 Accumulator Escape
BESC equ $041 B Register Escape
*
PLCNT equ $090 Pulse Counter
*
PLFLG1 equ $091 Pulse Flag 1
PLONF equ 0,PLFLG1 Pulse Output Enable Flag
*
CNTL equ $093 Lower Counter
CNTU equ $094 Upper Counter
PCNT equ $095 Period Counter
AWORK equ $096 Accumulator Work RAM Area
BWORK equ $097 B Register Work RAM Area
*
Rev. 1.0, 03/99, page 49 of 209
************************************************************
* Vector Address
************************************************************
*org $0000
*JMPL SPLMN Reset Interrupt
JMPL SPLMN INT0 Interrupt
JMPL SPLMN INT1 Interrupt
JMPL SPLMN Timer A Interrupt
JMPL SPLINT Timer B Interrupt
JMPL SPLMN Timer C Interrupt
JMPL SPLMN A/D Converter Interrupt
JMPL SPLMN Serial Interrupt
*
************************************************************
* Main Program
************************************************************
*org $1000
*
SPLMN REMD RSP Reset Stack Pointer
*LAI 0
LRA 0 Initialize R0 Port PDR
LMID 8,DCR0 Initialize R03 Output Terminal Function
LMID 0,PMRA Initialize R03 Input/Output Terminal Function
*LMID 3,PLCNT Initialize Pulse Counter
LMID 0,CNTL Initialize Lower Counter
LMID 0,CNTU Initialize Upper Counter
LMID $F,PCNT Initialize Period Counter
SEMD PLONF Initialize Pulse Output Enable Flag
*LMID 8,TMC Initialize Timer C Function & Input Clock Period
REMD IFTC Clear IFTC to 0
*LMID $D,TMB1 Initialize Timer B Function & Input Clock Period
LMID 0,TMB2 Initialize Timer B Function
*SEMD IMTB Timer B Interrupt Disable
REMD IFTB Clear IFTB to 0
*SEMD IE All Interrupt Enable
*
SPLMN00 TMD IFTC IFTC = "1" ?
BRS SPLMN10 Yes. Branch to SPLMN10
BRS SPLMN00 No. Branch to SPLMN00
*REMD IFTC Clear IFTC to 0
LMID 9,TWCL Set TCC Reload Value Lower
Rev. 1.0, 03/99, page 50 of 209
LMID 0,TWCU Set TCC Reload Value Upper
*
SPLMN05 TMD IFTC IFTC = "1" ?
BRS SPLMN10 Yes. Branch to SPLMN10
SEMD IMTB Timer B Interrupt Disable
REMD IFTB Clear IFTB to 0
LAI 0
LRA 0 Sound off
BRS SPLMN05 Branch to SPLMN05
*
SPLMN10 REMD IFTC Clear IFTC to 0
LAMD PCNT Load PCNT
AI 1 Increment PCNT
BRS SPLMN40 PCNT Overflow ? Yes. Branch to SPLMN40
LMAD PCNT No. Save PCNT
BRS SPLMN00 Branch to SPLMN00
*
SPLMN40 LAMD CNTU Load CNTL
LBA
LAMD CNTL Load CNTU
P 2 Scale Data Pattern Generation
LMAD AWORK Save Scale Lower Data
LAB
LMAD BWORK Save Scale Upper Data
ALEI 0 Scale Upper Data <= $0 ? End Sound Play ?
BRS SPLMN90 Yes. Branch to SPLMN90
ALEI $E Scale Upper Data <= $E ?
BRS SPLMN20 Yes. Branch to SPLMN20
SEMD IMTB Timer B Interrupt Disable
REMD IFTB Clear IFTB to 0
LAI 0
LRA 0 R03 Output Terminal is "Low" Output
BRS SPLMN30 Branch to SPLMN30
*
SPLMN20 LAMD AWORK Load AWORK
LMAD TWBL Set TCB Reload Value Lower to Scale Data
LAMD BWORK Load BWORK
LMAD TWBU Set TCB Reload Value Upper to Scale Data
REMD IFTB Clear IFTB to 0
REMD IMTB Timer B Interrupt Enable
*
SPLMN30 LAMD CNTU Load Upper Counter
LBA
LAMD CNTL Load Lower Counter
P 3 Time Period Data Pattern Generation
LMAD TWCL Set TCC Reload Value Lower to Time Period Lower Data
LAB
LMAD TWCU Set TCC Reload Value Upper to Time Period Upper Data
*LAMD CNTU Load Upper Counter
LBA
Rev. 1.0, 03/99, page 51 of 209
LAMD CNTL Load Lower Counter
P 4 Time Counter Data Pattern Generation
LMAD PCNT Set PCNT to Time Counter Data
*SEC Set Carry Flag at 1
LAI 0
AMCD CNTL Increment Lower Counter
LMAD CNTL Save Lower Counter
LAI 0
AMCD CNTU If CNTL Overflow, Increment Upper Counter
LMAD CNTU Save Upper Counter
BR *+1
BRS SPLMN00 Branch to SPLMN00
*
SPLMN90 SEMD IMTB Timer B Interrupt Disable
LMID 0,CNTL Initialize Lower Counter
LMID 0,CNTU Initialize Upper Counter
LAI 0
LRA 0 Initialize R0 Port PDR
LMID 0,TWCL Initialize TCC Reload Value Lower
LMID 8,TWCU Initialize TCC Reload Value Upper
REMD IFTC Clear IFTC to 0
BRS SPLMN00 Branch to SPLMN00
*
************************************************************
* Timer B Interrupt Process
* ---Pulse Output Routine---
************************************************************
*
SPLINT REMD IFTB Clear IFTB to 0
*LMAD AESC Store Accumulator
LAB
LMAD BESC Store B Register
*TMD PLONF Pulse Enable Flag = "1" ?
BRS PLI00 Yes. Branch to PLI00
LAI 0 No. Stop Output Pulse
LRA 0 R03 Output Terminal is "Low" Output
BRS PLI99 Branch to PLI99
*
PLI00 LAMD PLCNT Load Pulse Counter Value
LBA Store Pulse Counter Value
ALEI 1 PLCNT <= $1 ? Is R03 Output Terminal "High" Output ?
BRS PLI10 Yes. Branch to PLI10
LAI 0 No. R03 Output Terminal is "Low" Output
BRS PLI20 Branch to PLI20
PLI10 LAI 8
PLI20 LRA 0 R03 Output Terminal is "High" Output
LAB Restore Pulse Counter Value
AI $F PLCNT + $F <= $F ? Pulse Counter = $0 ?
Rev. 1.0, 03/99, page 52 of 209
BRS PLI30 No. Branch to PLI30
LAI 3 Yes. Pulse Counter Initialize
PLI30 LMAD PLCNT Save Pulse Counter Value
*
PLI99 LAMD BESC Restore B Register
LBA
LAMD AESC Restore Accumulator
*RTNI Return from Interrupt
*
************************************************************
* Scale Data
************************************************************
*ORG $0200
*
*** 1st Cycle
*dc $1AB 'G' Data. TCB Reload Value = $AB
dc $17F 'C' Data. TCB Reload Value = $7F
dc $18E 'D' Data. TCB Reload Value = $8E
dc $19B 'E' Data. TCB Reload Value = $9B
dc $1A1 'F' Data. TCB Reload Value = $A1
*dc $1AB 'G' Data. TCB Reload Value = $AB
dc $17F 'C' Data. TCB Reload Value = $7F
dc $1FF ' ' Data. TCB Reload Value = $FF
dc $17F 'C' Data. TCB Reload Value = $7F
*dc $1B4 'A' Data. TCB Reload Value = $B4
dc $1A1 'F' Data. TCB Reload Value = $A1
dc $1AB 'G' Data. TCB Reload Value = $AB
dc $1B4 'A' Data. TCB Reload Value = $B4
dc $1BD 'B' Data. TCB Reload Value = $BD
*dc $1C1 'C' Data. TCB Reload Value = $C1
dc $17F 'C' Data. TCB Reload Value = $7F
dc $1FF ' ' Data. TCB Reload Value = $FF
dc $17F 'C' Data. TCB Reload Value = $7F
*dc $1A1 'F' Data. TCB Reload Value = $A1
dc $1AB 'G' Data. TCB Reload Value = $AB
dc $1A1 'F' Data. TCB Reload Value = $A1
dc $19B 'E' Data. TCB Reload Value = $9B
dc $18E 'D' Data. TCB Reload Value = $8E
*dc $19B 'E' Data. TCB Reload Value = $9B
dc $1A1 'F' Data. TCB Reload Value = $A1
dc $19B 'E' Data. TCB Reload Value = $9B
dc $18E 'D' Data. TCB Reload Value = $8E
dc $17F 'C' Data. TCB Reload Value = $7F
Rev. 1.0, 03/99, page 53 of 209
*dc $17A 'B' Data. TCB Reload Value = $7A
dc $17F 'C' Data. TCB Reload Value = $7F
dc $18E 'D' Data. TCB Reload Value = $8E
dc $19B 'E' Data. TCB Reload Value = $9B
dc $17F 'C' Data. TCB Reload Value = $7F
*dc $18E 'D' Data. TCB Reload Value = $8E
*
*** 2nd Cycle
*dc $1AB 'G' Data. TCB Reload Value = $AB
dc $17F 'C' Data. TCB Reload Value = $7F
dc $18E 'D' Data. TCB Reload Value = $8E
dc $19B 'E' Data. TCB Reload Value = $9B
dc $1A1 'F' Data. TCB Reload Value = $A1
*dc $1AB 'G' Data. TCB Reload Value = $AB
dc $17F 'C' Data. TCB Reload Value = $7F
dc $1FF ' ' Data. TCB Reload Value = $FF
dc $17F 'C' Data. TCB Reload Value = $7F
*dc $1B4 'A' Data. TCB Reload Value = $B4
dc $1A1 'F' Data. TCB Reload Value = $A1
dc $1AB 'G' Data. TCB Reload Value = $AB
dc $1B4 'A' Data. TCB Reload Value = $B4
dc $1BD 'B' Data. TCB Reload Value = $BD
*dc $1C1 'C' Data. TCB Reload Value = $C1
dc $17F 'C' Data. TCB Reload Value = $7F
dc $1FF ' ' Data. TCB Reload Value = $FF
dc $17F 'C' Data. TCB Reload Value = $7F
*dc $1A1 'F' Data. TCB Reload Value = $A1
dc $1AB 'G' Data. TCB Reload Value = $AB
dc $1A1 'F' Data. TCB Reload Value = $A1
dc $19B 'E' Data. TCB Reload Value = $9B
dc $18E 'D' Data. TCB Reload Value = $8E
*dc $19B 'E' Data. TCB Reload Value = $9B
dc $1A1 'F' Data. TCB Reload Value = $A1
dc $19B 'E' Data. TCB Reload Value = $9B
dc $18E 'D' Data. TCB Reload Value = $8E
dc $17F 'C' Data. TCB Reload Value = $7F
*dc $18E 'D' Data. TCB Reload Value = $8E
dc $19B 'E' Data. TCB Reload Value = $9B
dc $18E 'D' Data. TCB Reload Value = $8E
dc $17F 'C' Data. TCB Reload Value = $7F
dc $17A 'B' Data. TCB Reload Value = $7A
*
Rev. 1.0, 03/99, page 54 of 209
dc $17F 'C' Data. TCB Reload Value = $7F
dc $1FF ' ' Data. TCB Reload Value = $FF
*dc $100 ' ' Data. TCB Reload Value = $00
*
************************************************************
* Time Period Data
************************************************************
*org $0300
*
*** 1st Cycle
*dc $138 'G' Time Period Data. TCC Reload Value = $38
dc $19C 'C' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
*dc $138 'G' Time Period Data. TCC Reload Value = $38
dc $16A 'C' Time Period Data. TCC Reload Value = $6A
dc $1CE ' ' Time Period Data. TCC Reload Value = $CE
dc $138 'C' Time Period Data. TCC Reload Value = $38
*dc $138 'A' Time Period Data. TCC Reload Value = $38
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
dc $19C 'G' Time Period Data. TCC Reload Value = $9C
dc $19C 'A' Time Period Data. TCC Reload Value = $9C
dc $19C 'B' Time Period Data. TCC Reload Value = $9C
*dc $138 'C' Time Period Data. TCC Reload Value = $38
dc $16A 'C' Time Period Data. TCC Reload Value = $6A
dc $1CE ' ' Time Period Data. TCC Reload Value = $CE
dc $138 'C' Time Period Data. TCC Reload Value = $38
*dc $138 'F' Time Period Data. TCC Reload Value = $38
dc $19C 'G' Time Period Data. TCC Reload Value = $9C
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
*dc $138 'E' Time Period Data. TCC Reload Value = $38
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
dc $19C 'C' Time Period Data. TCC Reload Value = $9C
*dc $138 'B' Time Period Data. TCC Reload Value = $38
dc $19C 'C' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
Rev. 1.0, 03/99, page 55 of 209
dc $19C 'C' Time Period Data. TCC Reload Value = $9C
*dc $138 'D' Time Period Data. TCC Reload Value = $38
*
*** 2nd Cycle
*dc $138 'G' Time Period Data. TCC Reload Value = $38
dc $19C 'C' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
*dc $138 'G' Time Period Data. TCC Reload Value = $38
dc $16A 'C' Time Period Data. TCC Reload Value = $6A
dc $1CE ' ' Time Period Data. TCC Reload Value = $CE
dc $138 'C' Time Period Data. TCC Reload Value = $38
*dc $138 'A' Time Period Data. TCC Reload Value = $38
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
dc $19C 'G' Time Period Data. TCC Reload Value = $9C
dc $19C 'A' Time Period Data. TCC Reload Value = $9C
dc $19C 'B' Time Period Data. TCC Reload Value = $9C
*dc $138 'C' Time Period Data. TCC Reload Value = $38
dc $16A 'C' Time Period Data. TCC Reload Value = $6A
dc $1CE ' ' Time Period Data. TCC Reload Value = $CE
dc $138 'C' Time Period Data. TCC Reload Value = $38
*dc $138 'F' Time Period Data. TCC Reload Value = $38
dc $19C 'G' Time Period Data. TCC Reload Value = $9C
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
*dc $138 'E' Time Period Data. TCC Reload Value = $38
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
dc $19C 'C' Time Period Data. TCC Reload Value = $9C
*dc $138 'D' Time Period Data. TCC Reload Value = $38
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
dc $19C 'C' Time Period Data. TCC Reload Value = $9C
dc $19C 'B' Time Period Data. TCC Reload Value = $9C
*dc $138 'C' Time Period Data. TCC Reload Value = $38
dc $138 ' ' Time Period Data. TCC Reload Value = $38
*
************************************************************
* Time Counter Data
Rev. 1.0, 03/99, page 56 of 209
************************************************************
*org $0400
*
*** 1st Cycle
*dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
*dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F ' ' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10F 'A' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'A' Time Counter Data. PCNT = $F
dc $10F 'B' Time Counter Data. PCNT = $F
*dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F ' ' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
*dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10F 'B' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10D 'D' Time Counter Data. PCNT = $D
*
*** 2nd Cycle
*dc $10F 'G' Time Counter Data. PCNT = $F
Rev. 1.0, 03/99, page 57 of 209
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
*dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F ' ' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10F 'A' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'A' Time Counter Data. PCNT = $F
dc $10F 'B' Time Counter Data. PCNT = $F
*dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F ' ' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
*dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F 'B' Time Counter Data. PCNT = $F
*dc $10E 'C' Time Counter Data. PCNT = $E
dc $10F ' ' Time Counter Data. PCNT = $F
*end
Rev. 1.0, 03/99, page 58 of 209
3. H4369
************************************************************
*
* HMCS400 Series Application Note
*
* 'Sound Play
* - Minuet : J.S.Bach'
*
* MCU : H4369
*
* External Clock : 4MHz
* Internal Clock : 1MHz
* Sub Clock : 32.768kHz
*
************************************************************
*
************************************************************
* Symbol Definition
************************************************************
*
IE equ 0,$000 Interrupt Enable Flag
RSP equ 1,$000 Reset Stack Pointer
IF0 equ 2,$000 INT0 Interrupt Request Flag
IM0 equ 3,$000 INT0 Interrupt Mask
*
IF1 equ 0,$001 INT1 Interrupt Request Flag
IM1 equ 1,$001 INT1 Interrupt Mask
IFTA equ 2,$001 Timer A Interrupt Request Flag
IMTA equ 3,$001 Timer A Interrupt Mask
*
IFTB equ 0,$002 Timer B Interrupt Request Flag
IMTB equ 1,$002 Timer B Interrupt Mask
IFTC equ 2,$002 Timer C Interrupt Request Flag
IMTC equ 3,$002 Timer C Interrupt Mask
*
IFAD equ 0,$003 A/D Converter Interrupt Request Flag
IMAD equ 1,$003 A/D Converter Interrupt Mask
IFS equ 2,$003 Serial Interrupt Request Flag
IMS equ 3,$003 Serial Interrupt Mask
*
PMRA equ $004 Port Mode Register
SMR equ $005 Serial Mode Register
SRL equ $006 Serial Data Register L
SRU equ $007 Serial Data Register U
TMA equ $008 Timer Mode Register A
TMB1 equ $009 Timer Mode Register B1
TRBL equ $00A Timer Read Register BL
TWBL equ $00A Timer Write Register BL
TRBU equ $00B Timer Read Register BU
TWBU equ $00B Timer Write Register BU
Rev. 1.0, 03/99, page 59 of 209
MIS equ $00C Miscellaneous Register
TMC equ $00D Timer Mode Register C
TRCL equ $00E Timer Read Register CL
TWCL equ $00E Timer Write Register CL
TRCU equ $00F Timer Read Register CU
TWCU equ $00F Timer Write Register CU
*
ACR equ $016 A/D Channel Register
ADRL equ $017 A/D Data Register L
ADRU equ $018 A/D Data Register U
AMR1 equ $019 A/D Mode Register 1
AMR2 equ $01A A/D Mode Register 2
*
LSON equ 0,$020 Low Speed on Flag
WDON equ 1,$020 Watchdog on Flag
ADSF equ 2,$020 A/D Start Flag
DTON equ 3,$020 Direct Transfer on Flag
*
ICSF equ 0,$021 Input Capture Status Flag
ICEF equ 1,$021 Input Capture Error Flag
IAOF equ 2,$021 IAD off Flag
RAME equ 3,$021 RAM Enable Flag
*
PMRB equ $024 Port Mode Register B
PMRC equ $025 Port Mode Register C
TMB2 equ $026 Timer Mode Register B2
SSR1 equ $027 System Clock Selection Register 1
SSR2 equ $028 System Clock Selection Register 2
*
DCD0 equ $02C D Port Data Control Register 0
DCD1 equ $02D D Port Data Control Register 1
DCD2 equ $02E D Port Data Control Register 2
DCD3 equ $02F D Port Data Control Register 3
DCR0 equ $030 R Port Data Control Register 0
DCR1 equ $031 R Port Data Control Register 1
DCR2 equ $032 R Port Data Control Register 2
DCR3 equ $033 R Port Data Control Register 3
DCR4 equ $034 R Port Data Control Register 4
DCR5 equ $035 R Port Data Control Register 5
DCR6 equ $036 R Port Data Control Register 6
SCR7 equ $037 R Port Data Control Register 7
DCR8 equ $038 R Port Data Control Register 8
*
************************************************************
* RAM ALLOCATION
************************************************************
*
AESC equ $040 Accumulator Escape
BESC equ $041 B Register Escape
*
PLCNT equ $090 Pulse Counter
Rev. 1.0, 03/99, page 60 of 209
*
PLFLG1 equ $091 Pulse Flag 1
PLONF equ 0,PLFLG1 Pulse Output Enable Flag
*
CNTL equ $093 Lower Counter
CNTU equ $094 Upper Counter
PCNT equ $095 Period Counter
AWORK equ $096 Accumulator Work RAM Area
BWORK equ $097 B Register Work RAM Area
*
************************************************************
* Vector Address
************************************************************
*org $0000
*JMPL SPLMN Reset Interrupt
JMPL SPLMN INT0 Interrupt
JMPL SPLMN INT1 Interrupt
JMPL SPLMN Timer A Interrupt
JMPL SPLINT Timer B Interrupt
JMPL SPLMN Timer C Interrupt
JMPL SPLMN A/D Converter Interrupt
JMPL SPLMN Serial Interrupt
*
************************************************************
* Main Program
************************************************************
*org $1000
*
SPLMN REMD RSP Reset Stack Pointer
LMID $2,SSR1 Set System Clock to 1.6 - 5.0MHz
*LAI 0
LRA 0 Initialize R0 Port PDR
LMID 8,DCR0 Initialize R03 Output Terminal Function
LMID 0,PMRA Initialize R03 Input/Output Terminal Function
*LMID 3,PLCNT Initialize Pulse Counter
LMID 0,CNTL Initialize Lower Counter
LMID 0,CNTU Initialize Upper Counter
LMID $F,PCNT Initialize Period Counter
SEMD PLONF Initialize Pulse Output Enable Flag
*LMID 8,TMC Initialize Timer C Function & Input Clock Period
REMD IFTC Clear IFTC to 0
*LMID $D,TMB1 Initialize Timer B Function & Input Clock Period
LMID 0,TMB2 Initialize Timer B Function
*
Rev. 1.0, 03/99, page 61 of 209
SEMD IMTB Timer B Interrupt Disable
REMD IFTB Clear IFTB to 0
*SEMD IE All Interrupt Enable
*
SPLMN00 TMD IFTC IFTC = "1" ?
BRS SPLMN10 Yes. Branch to SPLMN10
BRS SPLMN00 No. Branch to SPLMN00
*REMD IFTC Clear IFTC to 0
LMID 9,TWCL Set TCC Reload Value Lower
LMID 0,TWCU Set TCC Reload Value Upper
*
SPLMN05 TMD IFTC IFTC = "1" ?
BRS SPLMN10 Yes. Branch to SPLMN10
SEMD IMTB Timer B Interrupt Disable
REMD IFTB Clear IFTB to 0
LAI 0
LRA 0 Sound off
BRS SPLMN05 Branch to SPLMN05
*
SPLMN10 REMD IFTC Clear IFTC to 0
LAMD PCNT Load PCNT
AI 1 Increment PCNT
BRS SPLMN40 PCNT Overflow ? Yes. Branch to SPLMN40
LMAD PCNT No. Save PCNT
BRS SPLMN00 Branch to SPLMN00
*
SPLMN40 LAMD CNTU Load CNTL
LBA
LAMD CNTL Load CNTU
P 2 Scale Data Pattern Generation
LMAD AWORK Save Scale Lower Data
LAB
LMAD BWORK Save Scale Upper Data
ALEI 0 Scale Upper Data <= $0 ? End Sound Play ?
BRS SPLMN90 Yes. Branch to SPLMN90
ALEI $E Scale Upper Data <= $E ?
BRS SPLMN20 Yes. Branch to SPLMN20
SEMD IMTB Timer B Interrupt Disable
REMD IFTB Clear IFTB to 0
LAI 0
LRA 0 R03 Output Terminal is "Low" Output
BRS SPLMN30 Branch to SPLMN30
*
SPLMN20 LAMD AWORK Load AWORK
LMAD TWBL Set TCB Reload Value Lower to Scale Data
LAMD BWORK Load BWORK
LMAD TWBU Set TCB Reload Value Upper to Scale Data
REMD IFTB Clear IFTB to 0
REMD IMTB Timer B Interrupt Enable
Rev. 1.0, 03/99, page 62 of 209
*
SPLMN30 LAMD CNTU Load Upper Counter
LBA
LAMD CNTL Load Lower Counter
P 3 Time Period Data Pattern Generation
LMAD TWCL Set TCC Reload Value Lower to Time Period Lower Data
LAB
LMAD TWCU Set TCC Reload Value Upper to Time Period Upper Data
*LAMD CNTU Load Upper Counter
LBA
LAMD CNTL Load Lower Counter
P 4 Time Counter Data Pattern Generation
LMAD PCNT Set PCNT to Time Counter Data
*SEC Set Carry Flag at 1
LAI 0
AMCD CNTL Increment Lower Counter
LMAD CNTL Save Lower Counter
LAI 0
AMCD CNTU If CNTL Overflow, Increment Upper Counter
LMAD CNTU Save Upper Counter
BR *+1
BRS SPLMN00 Branch to SPLMN00
*
SPLMN90 SEMD IMTB Timer B Interrupt Disable
LMID 0,CNTL Initialize Lower Counter
LMID 0,CNTU Initialize Upper Counter
LAI 0
LRA 0 Initialize R0 Port PDR
LMID 0,TWCL Initialize TCC Reload Value Lower
LMID 8,TWCU Initialize TCC Reload Value Upper
REMD IFTC Clear IFTC to 0
BRS SPLMN00 Branch to SPLMN00
*
************************************************************
* Timer B Interrupt Process
* ---Pulse Output Routine---
************************************************************
*
SPLINT REMD IFTB Clear IFTB to 0
*LMAD AESC Store Accumulator
LAB
LMAD BESC Store B Register
*TMD PLONF Pulse Enable Flag = "1" ?
BRS PLI00 Yes. Branch to PLI00
LAI 0 No. Stop Output Pulse
LRA 0 R03 Output Terminal is "Low" Output
BRS PLI99 Branch to PLI99
Rev. 1.0, 03/99, page 63 of 209
*
PLI00 LAMD PLCNT Load Pulse Counter Value
LBA Store Pulse Counter Value
ALEI 1 PLCNT <= $1 ? Is R03 Output Terminal "High" Output ?
BRS PLI10 Yes. Branch to PLI10
LAI 0 No. R03 Output Terminal is "Low" Output
BRS PLI20 Branch to PLI20
PLI10 LAI 8
PLI20 LRA 0 R03 Output Terminal is "High" Output
LAB Restore Pulse Counter Value
AI $F PLCNT + $F <= $F ? Pulse Counter = $0 ?
BRS PLI30 No. Branch to PLI30
LAI 3 Yes. Pulse Counter Initialize
PLI30 LMAD PLCNT Save Pulse Counter Value
*
PLI99 LAMD BESC Restore B Register
LBA
LAMD AESC Restore Accumulator
*RTNI Return from Interrupt
*
************************************************************
* Scale Data
************************************************************
*ORG $0200
*
*** 1st Cycle
*dc $1AB 'G' Data. TCB Reload Value = $AB
dc $17F 'C' Data. TCB Reload Value = $7F
dc $18E 'D' Data. TCB Reload Value = $8E
dc $19B 'E' Data. TCB Reload Value = $9B
dc $1A1 'F' Data. TCB Reload Value = $A1
*dc $1AB 'G' Data. TCB Reload Value = $AB
dc $17F 'C' Data. TCB Reload Value = $7F
dc $1FF ' ' Data. TCB Reload Value = $FF
dc $17F 'C' Data. TCB Reload Value = $7F
*dc $1B4 'A' Data. TCB Reload Value = $B4
dc $1A1 'F' Data. TCB Reload Value = $A1
dc $1AB 'G' Data. TCB Reload Value = $AB
dc $1B4 'A' Data. TCB Reload Value = $B4
dc $1BD 'B' Data. TCB Reload Value = $BD
*dc $1C1 'C' Data. TCB Reload Value = $C1
dc $17F 'C' Data. TCB Reload Value = $7F
dc $1FF ' ' Data. TCB Reload Value = $FF
dc $17F 'C' Data. TCB Reload Value = $7F
*
Rev. 1.0, 03/99, page 64 of 209
dc $1A1 'F' Data. TCB Reload Value = $A1
dc $1AB 'G' Data. TCB Reload Value = $AB
dc $1A1 'F' Data. TCB Reload Value = $A1
dc $19B 'E' Data. TCB Reload Value = $9B
dc $18E 'D' Data. TCB Reload Value = $8E
*dc $19B 'E' Data. TCB Reload Value = $9B
dc $1A1 'F' Data. TCB Reload Value = $A1
dc $19B 'E' Data. TCB Reload Value = $9B
dc $18E 'D' Data. TCB Reload Value = $8E
dc $17F 'C' Data. TCB Reload Value = $7F
*dc $17A 'B' Data. TCB Reload Value = $7A
dc $17F 'C' Data. TCB Reload Value = $7F
dc $18E 'D' Data. TCB Reload Value = $8E
dc $19B 'E' Data. TCB Reload Value = $9B
dc $17F 'C' Data. TCB Reload Value = $7F
*dc $18E 'D' Data. TCB Reload Value = $8E
*
*** 2nd Cycle
*dc $1AB 'G' Data. TCB Reload Value = $AB
dc $17F 'C' Data. TCB Reload Value = $7F
dc $18E 'D' Data. TCB Reload Value = $8E
dc $19B 'E' Data. TCB Reload Value = $9B
dc $1A1 'F' Data. TCB Reload Value = $A1
*dc $1AB 'G' Data. TCB Reload Value = $AB
dc $17F 'C' Data. TCB Reload Value = $7F
dc $1FF ' ' Data. TCB Reload Value = $FF
dc $17F 'C' Data. TCB Reload Value = $7F
*dc $1B4 'A' Data. TCB Reload Value = $B4
dc $1A1 'F' Data. TCB Reload Value = $A1
dc $1AB 'G' Data. TCB Reload Value = $AB
dc $1B4 'A' Data. TCB Reload Value = $B4
dc $1BD 'B' Data. TCB Reload Value = $BD
*dc $1C1 'C' Data. TCB Reload Value = $C1
dc $17F 'C' Data. TCB Reload Value = $7F
dc $1FF ' ' Data. TCB Reload Value = $FF
dc $17F 'C' Data. TCB Reload Value = $7F
*dc $1A1 'F' Data. TCB Reload Value = $A1
dc $1AB 'G' Data. TCB Reload Value = $AB
dc $1A1 'F' Data. TCB Reload Value = $A1
dc $19B 'E' Data. TCB Reload Value = $9B
dc $18E 'D' Data. TCB Reload Value = $8E
*dc $19B 'E' Data. TCB Reload Value = $9B
Rev. 1.0, 03/99, page 65 of 209
dc $1A1 'F' Data. TCB Reload Value = $A1
dc $19B 'E' Data. TCB Reload Value = $9B
dc $18E 'D' Data. TCB Reload Value = $8E
dc $17F 'C' Data. TCB Reload Value = $7F
*dc $18E 'D' Data. TCB Reload Value = $8E
dc $19B 'E' Data. TCB Reload Value = $9B
dc $18E 'D' Data. TCB Reload Value = $8E
dc $17F 'C' Data. TCB Reload Value = $7F
dc $17A 'B' Data. TCB Reload Value = $7A
*dc $17F 'C' Data. TCB Reload Value = $7F
dc $1FF ' ' Data. TCB Reload Value = $FF
*dc $100 ' ' Data. TCB Reload Value = $00
*
************************************************************
* Time Period Data
************************************************************
*org $0300
*
*** 1st Cycle
*dc $138 'G' Time Period Data. TCC Reload Value = $38
dc $19C 'C' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
*dc $138 'G' Time Period Data. TCC Reload Value = $38
dc $16A 'C' Time Period Data. TCC Reload Value = $6A
dc $1CE ' ' Time Period Data. TCC Reload Value = $CE
dc $138 'C' Time Period Data. TCC Reload Value = $38
*dc $138 'A' Time Period Data. TCC Reload Value = $38
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
dc $19C 'G' Time Period Data. TCC Reload Value = $9C
dc $19C 'A' Time Period Data. TCC Reload Value = $9C
dc $19C 'B' Time Period Data. TCC Reload Value = $9C
*dc $138 'C' Time Period Data. TCC Reload Value = $38
dc $16A 'C' Time Period Data. TCC Reload Value = $6A
dc $1CE ' ' Time Period Data. TCC Reload Value = $CE
dc $138 'C' Time Period Data. TCC Reload Value = $38
*dc $138 'F' Time Period Data. TCC Reload Value = $38
dc $19C 'G' Time Period Data. TCC Reload Value = $9C
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
Rev. 1.0, 03/99, page 66 of 209
*dc $138 'E' Time Period Data. TCC Reload Value = $38
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
dc $19C 'C' Time Period Data. TCC Reload Value = $9C
*dc $138 'B' Time Period Data. TCC Reload Value = $38
dc $19C 'C' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'C' Time Period Data. TCC Reload Value = $9C
*dc $138 'D' Time Period Data. TCC Reload Value = $38
*
*** 2nd Cycle
*dc $138 'G' Time Period Data. TCC Reload Value = $38
dc $19C 'C' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
*dc $138 'G' Time Period Data. TCC Reload Value = $38
dc $16A 'C' Time Period Data. TCC Reload Value = $6A
dc $1CE ' ' Time Period Data. TCC Reload Value = $CE
dc $138 'C' Time Period Data. TCC Reload Value = $38
*dc $138 'A' Time Period Data. TCC Reload Value = $38
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
dc $19C 'G' Time Period Data. TCC Reload Value = $9C
dc $19C 'A' Time Period Data. TCC Reload Value = $9C
dc $19C 'B' Time Period Data. TCC Reload Value = $9C
*dc $138 'C' Time Period Data. TCC Reload Value = $38
dc $16A 'C' Time Period Data. TCC Reload Value = $6A
dc $1CE ' ' Time Period Data. TCC Reload Value = $CE
dc $138 'C' Time Period Data. TCC Reload Value = $38
*dc $138 'F' Time Period Data. TCC Reload Value = $38
dc $19C 'G' Time Period Data. TCC Reload Value = $9C
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
*dc $138 'E' Time Period Data. TCC Reload Value = $38
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
dc $19C 'C' Time Period Data. TCC Reload Value = $9C
*
Rev. 1.0, 03/99, page 67 of 209
dc $138 'D' Time Period Data. TCC Reload Value = $38
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
dc $19C 'C' Time Period Data. TCC Reload Value = $9C
dc $19C 'B' Time Period Data. TCC Reload Value = $9C
*dc $138 'C' Time Period Data. TCC Reload Value = $38
dc $138 ' ' Time Period Data. TCC Reload Value = $38
*
************************************************************
* Time Counter Data
************************************************************
*org $0400
*
*** 1st Cycle
*dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
*dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F ' ' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10F 'A' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'A' Time Counter Data. PCNT = $F
dc $10F 'B' Time Counter Data. PCNT = $F
*dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F ' ' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
*dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*
Rev. 1.0, 03/99, page 68 of 209
dc $10F 'B' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10D 'D' Time Counter Data. PCNT = $D
*
*** 2nd Cycle
*dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
*dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F ' ' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10F 'A' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'A' Time Counter Data. PCNT = $F
dc $10F 'B' Time Counter Data. PCNT = $F
*dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F ' ' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
*dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F 'B' Time Counter Data. PCNT = $F
*dc $10E 'C' Time Counter Data. PCNT = $E
Rev. 1.0, 03/99, page 69 of 209
dc $10F ' ' Time Counter Data. PCNT = $F
*end
Rev. 1.0, 03/99, page 70 of 209
4. H4889
************************************************************
*
* HMCS400 Series Application Note
*
* 'Sound Play
* - Minuet : J.S.Bach'
*
* MCU : H4889
*
* External Clock : 4MHz
* Internal Clock : 1MHz
* Sub Clock : 32.768kHz
*
************************************************************
*
************************************************************
* Symbol Definition
************************************************************
*
IE equ 0,$000 Interrupt Enable Flag
RSP equ 1,$000 Reset Stack Pointer
IFWU equ 2,$000 WU0-WU3 Interrupt Request Flag
IMWU equ 3,$000 WU0-WU3 Interrupt Mask
*
IF0 equ 0,$001 INT0 Interrupt Request Flag
IM0 equ 1,$001 INT0 Interrupt Mask
IF1 equ 2,$001 INT1 Interrupt Request Flag
IM1 equ 3,$001 INT1 Interrupt Mask
*
IFTA equ 0,$002 Timer A Interrupt Request Flag
IMTA equ 1,$002 Timer A Interrupt Mask
IFTB equ 2,$002 Timer B Interrupt Request Flag
IMTB equ 3,$002 Timer B Interrupt Mask
*
IFTC equ 0,$003 Timer C Interrupt Request Flag
IMTC equ 1,$003 Timer C Interrupt Mask
IFAD equ 2,$003 A/D Converter Interrupt Request Flag
IMAD equ 3,$003 A/D Converter Interrupt Mask
*
SSR equ $004 System Clock selection Register
MIS equ $005 Miscellaneous Register
ESR equ $006 Edge Detect Selection Register
*
PMR0 equ $008 Port Mode Register 0
PMR1 equ $009 Port Mode Register 1
PMR2 equ $00A Port Mode Register 2
PMR3 equ $00B Port Mode Register 3
PMR4 equ $00C Port Mode Register 4
MSR1 equ $00D Module Standby Register 1
Rev. 1.0, 03/99, page 71 of 209
MSR2 equ $00E Module Standby register 2
TMA equ $00F Timer Mode Register A
TMB1 equ $010 Timer Mode Register B1
TMB2 equ $011 Timer Mode register B2
TRBL equ $012 Timer Read Register BL
TWBL equ $012 Timer Write Register BL
TRBU equ $013 Timer Read Register BU
TWBU equ $013 Timer Write Register BU
TMC1 equ $014 Timer Mode Register C1
TMC2 equ $015 Timer Mode Register C2
TRCL equ $016 Timer Read Register CL
TWCL equ $016 Timer Write Register CL
TRCU equ $017 Timer Read Register CU
TWCU equ $017 Timer Write Register CU
TMD1 equ $018 Timer Mode Register D1
TMD2 eqU $019 Timer Mode Register D2
TRDL equ $01A Timer Read Register DL
TWDL equ $01A Timer Write Register DL
TRDU equ $01B Timer Read Register DU
TWDU equ $01B Timer Write Register DU
*
LSON equ 0,$020 Low Speed on Flag
WDON equ 1,$020 Watchdog on Flag
ADSF equ 2,$020 A/D Start Flag
DTON equ 3,$020 Direct Transfer on Flag
*
ICSF equ 0,$021 Input Capture Status Flag
ICEF equ 1,$021 Input Capture Error Flag
GEF equ 3,$021 Gear Enable Flag
*
IFTD equ 2,$022 Timer D Interrupt Request Flag
IMTD equ 3,$022 Timer D Interrupt Mask
*
IFS equ 2,$023 Serial Interrupt Request Flag
IMS equ 3,$023 Serial Interrupt Mask
*
SMR1 equ $024 Serial Mode Register 1
SMR2 equ $025 Serial Mode Register 2
SRL equ $026 Serial Data Register L
SRU equ $027 Serial Data Register U
AMR equ $028 A/D Mode Register
*
ADRL equ $02A A/D Data Register L
ADRU equ $02B A/D Data Register U
LCR equ $02C LCD Control Register
LMR equ $02D LCD Mode Register
BMR equ $02E Buzzer Mode Register
*
DCD0 equ $030 D Port Data Control Register 0
DCD1 equ $031 D Port Data Control Register 1
DCD2 equ $032 D Port Data Control Register 2
Rev. 1.0, 03/99, page 72 of 209
*
DCR0 equ $034 R Port Data Control Register 0
DCR1 equ $035 R Port Data Control Register 1
DCR2 equ $036 R Port Data Control Register 2
DCR3 equ $037 R Port Data Control Register 3
DCR4 equ $038 R Port Data Control Register 4
DCR5 equ $039 R Port Data Control Register 5
DCR6 equ $03A R Port Data Control Register 6
DCR7 equ $03B R Port Data Control Register 7
DCR8 equ $03C R port Data Control Register 8
*
V equ $03F Bank Register
*
************************************************************
* RAM ALLOCATION
************************************************************
*
AESC equ $040 Accumulator Escape
BESC equ $041 B Register Escape
*
PLCNT equ $090 Pulse Counter
*
PLFLG1 equ $091 Pulse Flag 1
PLONF equ 0,PLFLG1 Pulse Output Enable Flag
*
CNTL equ $093 Lower Counter
CNTU equ $094 Upper Counter
PCNT equ $095 Period Counter
AWORK equ $096 Accumulator Work RAM Area
BWORK equ $097 B Register Work RAM Area
*
************************************************************
* Vector Address
************************************************************
*org $0000
*JMPL SPLMN Reset Interrupt
JMPL SPLMN WU0-WU3 Interrupt
JMPL SPLMN INT0 Interrupt
JMPL SPLMN INT1 Interrupt
JMPL SPLMN Timer A Interrupt
JMPL SPLINT Timer B/D Interrupt
JMPL SPLMN Timer C Interrupt
JMPL SPLMN A/D Converter/Serial Interrupt
*
************************************************************
* Main Program
************************************************************
*org $1000
Rev. 1.0, 03/99, page 73 of 209
*
SPLMN REMD RSP Reset Stack Pointer
LMID $2,SSR Set System Clock to 1.6 - 4.5MHz
*LAI $0
LRA $1 Initialize R1 Port PDR
LMID $4,DCR1 Initialize R12 Output Terminal Function
LMID $0,PMR2 Initialize R12 Input/Output Terminal Function
*LMID $3,PLCNT Initialize Pulse Counter
LMID $0,CNTL Initialize Lower Counter
LMID $0,CNTU Initialize Upper Counter
LMID $F,PCNT Initialize Period Counter
SEMD PLONF Initialize Pulse Output Enable Flag
*LMID $8,TMC1 Initialize Timer C Function & Input Clock Period
REMD IFTC Clear IFTC to 0
*LMID $D,TMB1 Initialize Timer B Function & Input Clock Period
LMID $0,TMB2 Initialize Timer B Function
*SEMD IMTB Timer B Interrupt Disable
REMD IFTB Clear IFTB to 0
*SEMD IE All Interrupt Enable
*
SPLMN00 TMD IFTC IFTC = "1" ?
BRS SPLMN10 Yes. Branch to SPLMN10
BRS SPLMN00 No. Branch to SPLMN00
*REMD IFTC Clear IFTC to 0
LMID $9,TWCL Set TCC Reload Value Lower
LMID $0,TWCU Set TCC Reload Value Upper
*
SPLMN05 TMD IFTC IFTC = "1" ?
BRS SPLMN10 Yes. Branch to SPLMN10
SEMD IMTB Timer B Interrupt Disable
REMD IFTB Clear IFTB to 0
LAI $0
LRA $1 Sound off
BRS SPLMN05 Branch to SPLMN05
*
SPLMN10 REMD IFTC Clear IFTC to 0
LAMD PCNT Load PCNT
AI $1 Increment PCNT
BRS SPLMN40 PCNT Overflow ? Yes. Branch to SPLMN40
LMAD PCNT No. Save PCNT
BRS SPLMN00 Branch to SPLMN00
*
SPLMN40 LAMD CNTU Load CNTL
LBA
Rev. 1.0, 03/99, page 74 of 209
LAMD CNTL Load CNTU
P $2 Scale Data Pattern Generation
LMAD AWORK Save Scale Lower Data
LAB
LMAD BWORK Save Scale Upper Data
ALEI $0 Scale Upper Data <= $0 ? End Sound Play ?
BRS SPLMN90 Yes. Branch to SPLMN90
ALEI $E Scale Upper Data <= $E ?
BRS SPLMN20 Yes. Branch to SPLMN20
SEMD IMTB Timer B Interrupt Disable
REMD IFTB Clear IFTB to 0
LAI $0
LRA $1 R12 Output Terminal is "Low" Output
BRS SPLMN30 Branch to SPLMN30
*
SPLMN20 LAMD AWORK Load AWORK
LMAD TWBL Set TCB Reload Value Lower to Scale Data
LAMD BWORK Load BWORK
LMAD TWBU Set TCB Reload Value Upper to Scale Data
REMD IFTB Clear IFTB to 0
REMD IMTB Timer B Interrupt Enable
*
SPLMN30 LAMD CNTU Load Upper Counter
LBA
LAMD CNTL Load Lower Counter
P $3 Time Period Data Pattern Generation
LMAD TWCL Set TCC Reload Value Lower to Time Period Lower Data
LAB
LMAD TWCU Set TCC Reload Value Upper to Time Period Upper Data
*LAMD CNTU Load Upper Counter
LBA
LAMD CNTL Load Lower Counter
P $4 Time Counter Data Pattern Generation
LMAD PCNT Set PCNT to Time Counter Data
*SEC Set Carry Flag at 1
LAI $0
AMCD CNTL Increment Lower Counter
LMAD CNTL Save Lower Counter
LAI $0
AMCD CNTU If CNTL Overflow, Increment Upper Counter
LMAD CNTU Save Upper Counter
BR *+1
BRS SPLMN00 Branch to SPLMN00
*
SPLMN90 SEMD IMTB Timer B Interrupt Disable
LMID $0,CNTL Initialize Lower Counter
LMID $0,CNTU Initialize Upper Counter
LAI $0
LRA $1 Initialize R1 Port PDR
Rev. 1.0, 03/99, page 75 of 209
LMID $0,TWCL Initialize TCC Reload Value Lower
LMID $8,TWCU Initialize TCC Reload Value Upper
REMD IFTC Clear IFTC to 0
BRS SPLMN00 Branch to SPLMN00
*
************************************************************
* Timer B Interrupt Process
* ---Pulse Output Routine---
************************************************************
*
SPLINT REMD IFTB Clear IFTB to 0
*LMAD AESC Store Accumulator
LAB
LMAD BESC Store B Register
*TMD PLONF Pulse Enable Flag = "1" ?
BRS PLI00 Yes. Branch to PLI00
LAI $0 No. Stop Output Pulse
LRA $1 R12 Output Terminal is "Low" Output
BRS PLI99 Branch to PLI99
*
PLI00 LAMD PLCNT Load Pulse Counter Value
LBA Store Pulse Counter Value
ALEI $1 PLCNT <= $1 ? Is R12 Output Terminal "High" Output ?
BRS PLI10 Yes. Branch to PLI10
LAI $0 No. R12 Output Terminal is "Low" Output
BRS PLI20 Branch to PLI20
PLI10 LAI $4
PLI20 LRA $1 R03 Output Terminal is "High" Output
LAB Restore Pulse Counter Value
AI $F PLCNT + $F <= $F ? Pulse Counter = $0 ?
BRS PLI30 No. Branch to PLI30
LAI $3 Yes. Pulse Counter Initialize
PLI30 LMAD PLCNT Save Pulse Counter Value
*
PLI99 LAMD BESC Restore B Register
LBA
LAMD AESC Restore Accumulator
*RTNI Return from Interrupt
*
************************************************************
* Scale Data
************************************************************
*ORG $0200
*
*** 1st Cycle
*dc $1AB 'G' Data. TCB Reload Value = $AB
Rev. 1.0, 03/99, page 76 of 209
dc $17F 'C' Data. TCB Reload Value = $7F
dc $18E 'D' Data. TCB Reload Value = $8E
dc $19B 'E' Data. TCB Reload Value = $9B
dc $1A1 'F' Data. TCB Reload Value = $A1
*dc $1AB 'G' Data. TCB Reload Value = $AB
dc $17F 'C' Data. TCB Reload Value = $7F
dc $1FF ' ' Data. TCB Reload Value = $FF
dc $17F 'C' Data. TCB Reload Value = $7F
*dc $1B4 'A' Data. TCB Reload Value = $B4
dc $1A1 'F' Data. TCB Reload Value = $A1
dc $1AB 'G' Data. TCB Reload Value = $AB
dc $1B4 'A' Data. TCB Reload Value = $B4
dc $1BD 'B' Data. TCB Reload Value = $BD
*dc $1C1 'C' Data. TCB Reload Value = $C1
dc $17F 'C' Data. TCB Reload Value = $7F
dc $1FF ' ' Data. TCB Reload Value = $FF
dc $17F 'C' Data. TCB Reload Value = $7F
*dc $1A1 'F' Data. TCB Reload Value = $A1
dc $1AB 'G' Data. TCB Reload Value = $AB
dc $1A1 'F' Data. TCB Reload Value = $A1
dc $19B 'E' Data. TCB Reload Value = $9B
dc $18E 'D' Data. TCB Reload Value = $8E
*dc $19B 'E' Data. TCB Reload Value = $9B
dc $1A1 'F' Data. TCB Reload Value = $A1
dc $19B 'E' Data. TCB Reload Value = $9B
dc $18E 'D' Data. TCB Reload Value = $8E
dc $17F 'C' Data. TCB Reload Value = $7F
*dc $17A 'B' Data. TCB Reload Value = $7A
dc $17F 'C' Data. TCB Reload Value = $7F
dc $18E 'D' Data. TCB Reload Value = $8E
dc $19B 'E' Data. TCB Reload Value = $9B
dc $17F 'C' Data. TCB Reload Value = $7F
*dc $18E 'D' Data. TCB Reload Value = $8E
*
*** 2nd Cycle
*dc $1AB 'G' Data. TCB Reload Value = $AB
dc $17F 'C' Data. TCB Reload Value = $7F
dc $18E 'D' Data. TCB Reload Value = $8E
dc $19B 'E' Data. TCB Reload Value = $9B
dc $1A1 'F' Data. TCB Reload Value = $A1
*dc $1AB 'G' Data. TCB Reload Value = $AB
dc $17F 'C' Data. TCB Reload Value = $7F
Rev. 1.0, 03/99, page 77 of 209
dc $1FF ' ' Data. TCB Reload Value = $FF
dc $17F 'C' Data. TCB Reload Value = $7F
*dc $1B4 'A' Data. TCB Reload Value = $B4
dc $1A1 'F' Data. TCB Reload Value = $A1
dc $1AB 'G' Data. TCB Reload Value = $AB
dc $1B4 'A' Data. TCB Reload Value = $B4
dc $1BD 'B' Data. TCB Reload Value = $BD
*dc $1C1 'C' Data. TCB Reload Value = $C1
dc $17F 'C' Data. TCB Reload Value = $7F
dc $1FF ' ' Data. TCB Reload Value = $FF
dc $17F 'C' Data. TCB Reload Value = $7F
*dc $1A1 'F' Data. TCB Reload Value = $A1
dc $1AB 'G' Data. TCB Reload Value = $AB
dc $1A1 'F' Data. TCB Reload Value = $A1
dc $19B 'E' Data. TCB Reload Value = $9B
dc $18E 'D' Data. TCB Reload Value = $8E
*dc $19B 'E' Data. TCB Reload Value = $9B
dc $1A1 'F' Data. TCB Reload Value = $A1
dc $19B 'E' Data. TCB Reload Value = $9B
dc $18E 'D' Data. TCB Reload Value = $8E
dc $17F 'C' Data. TCB Reload Value = $7F
*dc $18E 'D' Data. TCB Reload Value = $8E
dc $19B 'E' Data. TCB Reload Value = $9B
dc $18E 'D' Data. TCB Reload Value = $8E
dc $17F 'C' Data. TCB Reload Value = $7F
dc $17A 'B' Data. TCB Reload Value = $7A
*dc $17F 'C' Data. TCB Reload Value = $7F
dc $1FF ' ' Data. TCB Reload Value = $FF
*dc $100 ' ' Data. TCB Reload Value = $00
*
************************************************************
* Time Period Data
************************************************************
*org $0300
*
*** 1st Cycle
*dc $138 'G' Time Period Data. TCC Reload Value = $38
dc $19C 'C' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
*
Rev. 1.0, 03/99, page 78 of 209
dc $138 'G' Time Period Data. TCC Reload Value = $38
dc $16A 'C' Time Period Data. TCC Reload Value = $6A
dc $1CE ' ' Time Period Data. TCC Reload Value = $CE
dc $138 'C' Time Period Data. TCC Reload Value = $38
*dc $138 'A' Time Period Data. TCC Reload Value = $38
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
dc $19C 'G' Time Period Data. TCC Reload Value = $9C
dc $19C 'A' Time Period Data. TCC Reload Value = $9C
dc $19C 'B' Time Period Data. TCC Reload Value = $9C
*dc $138 'C' Time Period Data. TCC Reload Value = $38
dc $16A 'C' Time Period Data. TCC Reload Value = $6A
dc $1CE ' ' Time Period Data. TCC Reload Value = $CE
dc $138 'C' Time Period Data. TCC Reload Value = $38
*dc $138 'F' Time Period Data. TCC Reload Value = $38
dc $19C 'G' Time Period Data. TCC Reload Value = $9C
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
*dc $138 'E' Time Period Data. TCC Reload Value = $38
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
dc $19C 'C' Time Period Data. TCC Reload Value = $9C
*dc $138 'B' Time Period Data. TCC Reload Value = $38
dc $19C 'C' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'C' Time Period Data. TCC Reload Value = $9C
*dc $138 'D' Time Period Data. TCC Reload Value = $38
*
*** 2nd Cycle
*dc $138 'G' Time Period Data. TCC Reload Value = $38
dc $19C 'C' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
*dc $138 'G' Time Period Data. TCC Reload Value = $38
dc $16A 'C' Time Period Data. TCC Reload Value = $6A
dc $1CE ' ' Time Period Data. TCC Reload Value = $CE
dc $138 'C' Time Period Data. TCC Reload Value = $38
*dc $138 'A' Time Period Data. TCC Reload Value = $38
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
Rev. 1.0, 03/99, page 79 of 209
dc $19C 'G' Time Period Data. TCC Reload Value = $9C
dc $19C 'A' Time Period Data. TCC Reload Value = $9C
dc $19C 'B' Time Period Data. TCC Reload Value = $9C
*dc $138 'C' Time Period Data. TCC Reload Value = $38
dc $16A 'C' Time Period Data. TCC Reload Value = $6A
dc $1CE ' ' Time Period Data. TCC Reload Value = $CE
dc $138 'C' Time Period Data. TCC Reload Value = $38
*dc $138 'F' Time Period Data. TCC Reload Value = $38
dc $19C 'G' Time Period Data. TCC Reload Value = $9C
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
*dc $138 'E' Time Period Data. TCC Reload Value = $38
dc $19C 'F' Time Period Data. TCC Reload Value = $9C
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
dc $19C 'C' Time Period Data. TCC Reload Value = $9C
*dc $138 'D' Time Period Data. TCC Reload Value = $38
dc $19C 'E' Time Period Data. TCC Reload Value = $9C
dc $19C 'D' Time Period Data. TCC Reload Value = $9C
dc $19C 'C' Time Period Data. TCC Reload Value = $9C
dc $19C 'B' Time Period Data. TCC Reload Value = $9C
*dc $138 'C' Time Period Data. TCC Reload Value = $38
dc $138 ' ' Time Period Data. TCC Reload Value = $38
*
************************************************************
* Time Counter Data
************************************************************
*org $0400
*
*** 1st Cycle
*dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
*dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F ' ' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10F 'A' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
Rev. 1.0, 03/99, page 80 of 209
dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'A' Time Counter Data. PCNT = $F
dc $10F 'B' Time Counter Data. PCNT = $F
*dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F ' ' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
*dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10F 'B' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10D 'D' Time Counter Data. PCNT = $D
*
*** 2nd Cycle
*dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
*dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F ' ' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10F 'A' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'A' Time Counter Data. PCNT = $F
dc $10F 'B' Time Counter Data. PCNT = $F
*dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F ' ' Time Counter Data. PCNT = $F
Rev. 1.0, 03/99, page 81 of 209
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'G' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
*dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'F' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
*dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'E' Time Counter Data. PCNT = $F
dc $10F 'D' Time Counter Data. PCNT = $F
dc $10F 'C' Time Counter Data. PCNT = $F
dc $10F 'B' Time Counter Data. PCNT = $F
*dc $10E 'C' Time Counter Data. PCNT = $E
dc $10F ' ' Time Counter Data. PCNT = $F
*end
Rev. 1.0, 03/99, page 82 of 209
2.2 Stepping Motor Control
Stepping Moto r Control MCU:
H4344/H4318/H4359/
H4369/H4889
Functions Use d:
R2/R8 Port and Timer B
Specifications
1. The H4344/H4318/H4359/H4369/H4889 Series are used for stepping motor control. The
stepping motor is of the permanent magnet type.
2. The stepping motor repeats a forward run, stop, and reverse run cy cle.
3. The stepping motor is run for approximately 4 second s in forward, in stop, and in reverse.
4. Figure 1 shows the example stepping motor control circuit used in this example task.
Rev. 1.0, 03/99, page 83 of 209
H4344/H4318/H4359/
H4369/H4889
B
A
B
A
R2
3
/R8
3
*
R2
2
/R8
2
R2
1
/R8
1
R2
0
/R8
0
5 V
12 V
øB
øB
øA øA
A
B
A
B
Note: *R2
0
to R2
3
pins are used in the H4344/H4889 Series.
R8
0
to R8
3
pins are used in the H4318/H4359/H4369 Series.
Stepping motor driver
Permanent magnet type
stepping motor
Figure 1 Example Stepping Motor Control Circuit
Rev. 1.0, 03/99, page 84 of 209
Concepts
1. Stepping motors have superb starting, stopping, and positional control characteristics.
2. Stepping motors are synchronous motors that run in sync with the pulse signals output from a
pulse oscillator. The mo tor is run in sy nc with the pulse signals, so, b ecause there is no speed
fluctuation due to load fluctuations, it will stop exactly at the intended position.
3. Stepping motors have the following features:
a. The rotational angle of stepping motors is proportional to the number of input pulses.
b. There is minimal angle error per step, and no cumulative error.
c. Stepping motors have superb starting and stopping response.
d. By direct connection to the motor shaft, it’s possible to achieve synchronous rotation at
extremely low speeds.
e. The self holding capacity of stepping motors means that the stop position can be
maintained.
f. Superb control characteristics can be achieved using open-loop control.
4. The follo wing shows the meth od of excitation (the meth od of turning on the current to th e
windings of the stepping motor in order) of a 2-phase stepping motor.
• Single-phase excitatio n
In this method, on ly on e phase ex citation is performed at all times. This results in lo wer
power dissipation, but because of the small amount of damping, vibration is more likely.
Figure 2 shows the excitation sequence in single-phase excitation.
123456789
CW*
CCW
Note: *CW: Clockwise (as seen from axis)
CCW: Counterclockwise
A
B
A
B
Figure 2 Excita t ion Sequence in Single-Phase Excit ation
Rev. 1.0, 03/99, page 85 of 209
• Two-phase excitatio n
In this method, two-phase excitation is performed at all times. Twice the input is required
over single-phase excitation, but the output torque is greater and damping is superior.
Figure 3 shows the excitation sequence in two-phase excitation.
123456789
CW
CCW
A
B
A
B
Figure 3 Excitation Sequence in Two-Phase Excitation
• 1-2-phase excitatio n
In this method, single-phase excitation and two-phase excitation are alternated. When a
stepping motor is driven using this method, the motor’s step angle is halved. Because the
step angle is halved, running is smoother and there is minimal vibration. Figure 4 shows
the excitation sequence in 1-2-phase excitation.
123456789
CW
CCW
A
B
A
B
Figure 4 Excitation Sequence in 1-2-Phase Excitation
Rev. 1.0, 03/99, page 86 of 209
5. In this example task, the stepping motor is controlled using two-phase excitation. Figure 5
shows an example of port output when the moto r is run in the forward direction in this task.
P2
0
/P8
0
phase A
P2
1
/P8
1
phase B
P2
2
/P8
2
phase A
P2
3
/P8
3
phase B
Timer B
overflow cycle
Figure 5 Example Port Output With Mo tor Running in Forward Direction
Rev. 1.0, 03/99, page 87 of 209
Description of Functions
1. In this example task, we use a permanent magnet type of stepping motor (KP6P8-701 from
Japan Servo Co., Ltd.) Table 1 shows the standard specifications of the KP6P8-701. Figure 6
shows the wiring.
Table 1 KP6P8-701 Standard Specifications
Item Unit Value
Model No. — KP6P8-701
No. of phases — 2
Step angle deg./step 7.5
Voltage V 12
Current A/PHASE 0.33
Winding resistance Ω/PHASE 36
Inductance mH/PHASE 28
Maximum holding
torque gf·cm 800
Détente torque gf·cm 160
Rotor inertia gf·cm223.7
Weight kg 0.25
Insulation class — Type E or equivalent
Insulation resistance — 500 V DC 100 MΩ 1 min.
Dielectric strength — 500 V AC 50 Hz 1 min.
Operating
temperature range °C –10 to +45
Temperature rise deg 70
Lead specifications — AWG #22 UL3266
Rev. 1.0, 03/99, page 88 of 209
Brown
Red
Black
Orange Red Yellow
øB øB
øA
øA
Figure 6 KP6P8-701 Wiring
Rev. 1.0, 03/99, page 89 of 209
2. This section describes the functions of the H4344/H4318/H4359/H4369/H4889 used in
stepping motor control. Figure 7 is a block diagram of the functions used in this example task.
CPU
Timer B
reload timer
R2 port/R8 port
Pulse output
Output pulse cycle setting
Interrupt request by
timer B overflow
Setting of output pulse cycle by writing
reload value for timer counter B
Pulse output to motor (phases A, B, A, B)
P2
0
/P8
0
P2
1
/P8
1
P2
2
/P8
2
P2
3
/P8
3
ABAB
H4344/H4318/H4359/H4369/H4889 functions
Figure 7 Block Diagram of Functions H4344/H4318/H4359/H4369/H4889 Used
in Stepping Motor Control
• Timer B reload timer functio ns
Sets the output pulse cycle. The output pulse cycle is determined from the timer counter B
reload value. The reload value to be set is referenced from the data table.
• R2 port/R8 port functions
These are the output pins for the pulses (phases A, B,
A
,
B
) output to the stepping motor.
Rev. 1.0, 03/99, page 90 of 209
3. The following describes the functions of timer B and the R2/R8 port.
a. Figure 8 is a block diagram of timer B functions.
Timer B functions (reload timer functions)
Timer B interrupt cycle setting
TCB input clock setting
Prescaler S (PSS)
/2
/4
/8
/32
/128
/512
/2048
Selector
Selects division
ratio of 128
Clock obtained by dividing
system clock by 128
((4 MHz/4) / 128 = 7.8125 kHz)
Timer counter B Selection of reload
timer function
TCB
overflow
TCB reload
value setting
(TCBL) (TCBU)
Timer write register B
(TWBL) (TWBU)
Timer mode
register B1
(TMB1)
Timer B interrupt
request flag
(IFTB)
Interrupt request due
to TCB overflow
TCB reload value
setting
System
clock
(4 MHz/4)
EVNB pin
edge detection
TCB reload
value setting
Selection of
reload timer
function and
TCB input
clock
Figure 8 Block Diagram of Timer B Functions
Rev. 1.0, 03/99, page 91 of 209
b. Timer B is an 8-bit multifunction timer (free running/even t counter/reload timer/input
capture*1). In this example task, timer B is used as a reload timer. Table 2 describes the
timer B functions.
Table 2 Timer B Functions
Timer Mode Register B1 (TMB1)
Function TMB1 is a 4-bit write-only register. It selects the timer B function (free-running/reload
timer) and operating clock. TMB1 is initialized to $0 when reset and in stop mode.
Timer Write Register BL, U (TWBL, TWBU)
Function TWBL and TWBU form an 8-bit write-only register, which is made up of the lower digit
(TWBL) and upper digit (TWBU). TWBL and TWBU are used for the initial TCB
setting (the reload setting when operation as a reload timer).
Timer Counter B (TCB)
Function TCB is an 8-bit up-counter, which is incremented by the input internal clock. The TCB
input clock is selected using bits TMB12 to TMB10 of TMB1. The value written to
TWBL and TWBU is also written to TCB. When TCB overflows, the timer B interrupt
request flag (IFTB) is set to “1”. If, at this point, timer B is set as a reload timer, the
value of TWBL and TWBU is written to this counter and the count starts from this
value. TCB is initialized to $00 when reset and in stop mode.
Prescaler S (PSS)
Function PSS is an 11-bit counter to which the system clock is input when in active mode and
standby mode, and the subsystem clock is input when in subactive mode*2. PSS is
initialized to $000 at a reset, and starts to count the system clock when the reset is
canceled. PSS operation is halted when reset, in stop mode, and in watch mode*2.
However, it runs in other operating modes. The PSS output is shared by the internal
peripheral modules, the division ratio being set independently for each of the internal
peripheral modules.
Timer B Interrupt Request Flag (IFTB)
Function IFTB reflects the existence of the timer B interrupt request. When timer B overflows,
IFTB is set to “1 ”. IFTB can only be read/written to (only “0” can be written) using bit
operation commands. Note that IFTB is not automatically cleared even when the
interrupt is received, and must be cleared by writing “0” using software. IFTB is
cleared at a reset and in stop mode.
Timer B Interrupt Mask (IMTB)
Function IMTB is the bit that masks IFTB. When IFTB is set to “1” and, additionally, IMTB is
“0”, a timer B interrupt request is sent to the CPU (when IE = “1”). If IFTB is set to “1”
but IMTB is “1”, no interrupt request is sent to the CPU and the timer B interrupt is
held. IMTB can only be read or written to using bit operation commands. It is set to
“1” at a reset and in stop mode.
Notes: 1. Applies to H4318/H4359/H4369 Series only. In the H4344/H4889 Series, timer B has
no input capture fun ctio n.
2. Applies only to H4369/H4889 Series.
Rev. 1.0, 03/99, page 92 of 209
c. Figure 9 is a block diagram of the R2 port functions used in the H4344; figure 10 is a block
diagram of the R2 port functions used in the H4889; figure 11 is a block diagram of the R8
port functions used in the H4318/H4359/H4369.
Port data register
(PDR)
R2
0
to R2
3
pin
output data
R2
0
to R2
3
output
pin function setting Data control register
(DCR2)
R2 port functions R2
0
to R2
3
pin
output data settings
R2
0
to R2
3
I/O pin
function switching
R2
port
R2
0
pin
A phase output
R2
1
pin
B phase output
R2
2
pin
A phase output
R2
3
pin
B phase output
Figure 9 Block Diagram of Port R2 Functions in H4344 Series
Port data register
(PDR)
R2
0
to R2
3
output pin
function setting
R2
0
to R2
2
I/O pin function
setting
R2
0
to R2
3
pin
output data
R2
port
R2 port functions
R2
0
to R2
3
output pin
function setting
Data control register
(DCR2)
Port mode register 3
(PMR3)
R2
0
/TOC pin
A phase output
B phase output
A phase output
B phase output
R2
1
/SCK pin
R2
2
/SI/SO pin
R2
3
pin
R2
0
to R2
3
pin
output data setting
R2
0
to R2
3
I/O pin
function switching
R2
0
/TOC, R2
1
/SCK,
R2
2
/SI/SO pin
function switching
Figure 10 Block Diagram of Port R2 Functions in H4889 Series
Port data register
(PDR)
R8
0
to R8
3
pin
output data
R8
0
to R8
3
output
pin function setting Data control register
(DCR8)
R8 port functions Setting R8
0
to R8
3
pin output data
Switching of R8
0
to
R8
3
I/O pin functions
R8
port
R8
0
pin
A phase output
R8
1
pin
B phase output
R8
2
pin
A phase output
R8
3
pin
B phase output
Figure 11 Block Diagram of Port R8 Functions in H4318/H4359/H4369 Series
Rev. 1.0, 03/99, page 93 of 209
d. The R2 port in the H4344/H4889 and the R8 port in the H4318/H4359/H4369 are 4-bit I/O
ports. Both R2 and R8 are capable of 4-bit input using the LAR and LBR commands, and
4-bit output using th e LRA and LRB commands. The output data is stored in the PDR of
the respective pins.
In this example task, the R20 to R23 pins in the H4344/H4889 Series and the R80 to R83 pins
in the H4318/H4359/H4369 Series are set for output and used to output pulses to the
stepping motor.
Table 3 describes the functions of the R2 port in the H4344/H4889 and the R8 port in the
H4318/H4359/H4369.
Table 3 R2 Port Functions in H4344/H4889 and R8 Port Functions in
H4318/H4359/H4369
Data Control Register R2 (DCR2) Note: Applies to H4344/H4889 Series
Function DCR2 switches the I/O pin function of the R2 port. When any bit of DCR2 is cleared
to “0”, the output buffer (CMOS) of the corresponding pin is turned OFF and the
output is set to high impedance. When the res pective bit of DCR2 is set to “1”, the
output buffer of the corresponding pin is set ON and the corresponding PDR value is
output.
Data Control Register R8 (DCR8) Note: Applies to H4318/H4359/H4369 Series
Function DCR8 switches the I/O pin function of the R8 port. When any bit of DCR8 is cleared
to “0”, the output buffer (CMOS) of the corresponding pin is turned OFF and the
output is set to high impedance. When the res pective bit of DCR8 is set to “1”, the
output buffer of the corresponding pin is set ON and the corresponding PDR value is
output.
Port Mode Register 3 (PMR3) Note: Applies to H4889 Series
Function PMR3 is a 4-bit write-only register. Bits PMR33 to PMR30 switch the functions of the
R2 port’s dual-function pins.
Port Data Register (PDR)
Function The I/O pins of the R ports have bu ilt-in PDRs to store the output da ta. When the LRA
and LRB commands are execut ed, the con tents of the accumula tor (A) and B register
(B) are transferred to the PDR of the specified R port. When the corresponding bit of
the DCR of the R port is “1”, the output buffer of the appropriate pin is set ON and the
value in the PDR is output via that pin. The PDR is initialized to $F at a reset.
Rev. 1.0, 03/99, page 94 of 209
3. Table 4 sh ows the allocation of functions in this exam ple task.
Table 4 Function Allocation
Function Function Allocation
System clock The system clock is obtained by dividing the clock output from the system
clock oscillator by 4. It is used for operating the CPU and internal
peripheral modules. In this example task, a 4 MHz system clock oscillator
is used, so the clock supplied to the CPU and internal peripheral modules
is 1 MHz. The clock used by timer B is obtained by dividing the 1 MHz
clock at PSS.
PSS The clock input to timer B is obtained by dividing the system clock. The
clock supplied to timer B is obtained by divid ing the system clock by 128.
TCB This is an 8-bit up-counter. The count starts from the value set in TWBL
and TWBU. When an overflow occurs, IFTB is set to “1”. After an
overflow, the reload value set in TWBL and TWBU is set in TCB.
TWBL, TWBU The TCB reload value is set in TWBL and TWBU. The reload value is
determined from the pulse cycle to be output to the stepping motor.
TMB1 TMB1 selects the reload timer function for timer B and a clock obtained by
dividing the system clock by 128 as the TCB input clock.
IFTB IFTB reflects the existence of a ti mer B interrupt request. The pulse output
pin output level is set in the timer B interrupt processing.
IMTB Enables/disables timer B interrupt requests.
DCR2 (H4344/H4889)
DCR8 (H4318/H4359/
H4369)
Sets the R20 to R23 pin s (H4344/H4 889) and R 80 to R83 pins
(H4318/H4359/H4369 Series) as output pins.
PMR3 (H4889) Sets the R20/TOC dual-function pin as an R20 I/O pin and the R21/SCK
dual-function pin as an R21 pin.
PDR Stores the output data for the R20 to R23/R80 to R83 pins.
R20 to R23 pins Output pins for the pulse output to the stepping motor in the H4344/H488 9
Series.
R80 to R83 pins Output pins for the pulse output to the stepping motor in H4318/H4359/
H4369 Series.
Rev. 1.0, 03/99, page 95 of 209
Description of Operation
1. Figure 12 is a flowchart of the stepping motor control.
START
Initial control
Slue up control
Constant control
Slue down control
Stop control
Slue up control
Constant control
Slue down control
Stop control
Clockwise
(CW)
Stop
Counterclockwise
(CCW)
Stop
Figure 12 Flowchart of Stepping Motor Control
Rev. 1.0, 03/99, page 96 of 209
2. Figur e 13 shows the operating principle of initial control.
TCB
$FF
$00
$18
$6 $C $9 $3 $6 $6 $6$C $C $C$9 $9 $9$3 $3 $3
Time
29.696 ms
475.136 ms
R2
0
/R8
0
phase A
R2
1
/R8
1
phase B
R2
2
/R8
2
phase A
R2
3
/R8
3
phase B
Hardware processing
Software processing
1.
2.
3.
IFTB cleared to “0”.
COUNT0 decremented.
Corresponding data stored in
PDRs of P2
0
to P2
3
/P8
0
to P8
3
.
1.
2.
3.
TCB overflow.
IFTB set to “1”.
Value of TWCL and TWCU
written to TCB.
Hardware processing
Software processing
1.
2.
3.
IFTB cleared to “0”.
“1” set in IMTB to enable timer
B interrupt requests.
“1” set in IE to enable interrupts.
1.
2.
3.
TCB overflow.
IFTB set to “1”.
Value of TWCL and TWCU
written to TCB.
R2/R8
port PDR
Figure 13 Operating Principle of Initial Control
Rev. 1.0, 03/99, page 97 of 209
3. Figure 14 shows the operating principle of Slue up control when the motor is running
clockwise.
TCB
$FF
Time
$00
$DD
$CC
$AA
$11
$BB
30.592 ms 11.008 ms 8.832 ms 6.656 ms 4.480 ms
R2
0
/R8
0
phase A
R2
1
/R8
1
phase B
R2
2
/R8
2
phase A
R2
3
/R8
3
phase B
Hardware processing
Software processing
1.
2.
3.
IFTB cleared to “0”.
Corresponding data stored in
PDRs of P2
0
to P2
3
/P8
0
to P8
3
.
Pattern command reads TCB
reload value from data table and
sets TWBL/TWBU.
1.
2.
3.
TCB overflow.
IFTB set to “1”.
Value of TWCL and TWCU
written to TCB.
Hardware processing
Software processing
1.
2.
3.
IFTB cleared to “0”.
Corresponding data stored in
PDRs of P2
0
to P2
3
/P8
0
to P8
3
.
CNTADR set to $2, and COUNT2
to 0 set to $3E8.
1.
2.
3.
TCB overflow.
IFTB set to “1”.
Value of TWCL and TWCU
written to TCB.
Figure 14 Operating Principle of Slue up Control When Motor Running Clo c kwise
Rev. 1.0, 03/99, page 98 of 209
4. Figure 15 shows the operating principle of Constant control when the motor is running
clockwise.
TCB
$FF
$00
$DD
Time
Counter
values of
COUNT2,
COUNT1,
COUNT0
$3E8 $3E7 $3E6 $3E5 $3E4 $3E3 $3E2 $000$001$002$003$004$005$006$007 . . . . . .
4.480 ms
4.48 sec
R2
0
/R8
0
phase A
R2
1
/R8
1
phase B
R2
2
/R8
2
phase A
R2
3
/R8
3
phase B
Hardware processing
Software processing
1.
2.
3.
IFTB cleared to “0”.
Corresponding data stored in
PDRs of P2
0
to P2
3
/P8
0
to P8
3
.
CNTADR set to $4, and PLPADR
set to $D.
1.
2.
3.
TCB overflow.
IFTB set to “1”.
Value of TWCL and TWCU
written to TCB.
Hardware processing
Software processing
1.
2.
3.
IFTB cleared to “0”.
Corresponding data stored in
PDRs of P2
0
to P2
3
/P8
0
to P8
3
.
COUNT2 to COUNT0 decremented.
1.
2.
3.
TCB overflow.
IFTB set to “1”.
Value of TWCL and TWCU
written to TCB.
Figure 15 Operating Principle of Constant Control When Moto r Running Clockwise
Rev. 1.0, 03/99, page 99 of 209
5. Figure 16 shows the operating principle of Slue down control when the motor is running
clockwise.
TCB
$FF
Time
$00
$DD
$CC
$AA
$11
$BB
30.592 ms
11.008 ms
8.832 ms
6.656 ms4.480 ms
R2
0
/R8
0
phase A
R2
1
/R8
1
phase B
R2
2
/R8
2
phase A
R2
3
/R8
3
phase B
Hardware processing
Software processing
1.
2.
3.
IFTB cleared to “0”.
Corresponding data stored in
PDRs of P2
0
to P2
3
/P8
0
to P8
3
.
Pattern command reads TCB
reload value from data table and
sets TWBL/TWBU.
1.
2.
3.
TCB overflow.
IFTB set to “1”.
Value of TWCL and TWCU
written to TCB.
Hardware processing
Software processing
1.
2.
3.
IFTB cleared to “0”.
Corresponding data stored in
PDRs of P2
0
to P2
3
/P8
0
to P8
3
.
CNTADR set to $6, and COUNT2
to 0 set to $08D.
1.
2.
3.
TCB overflow.
IFTB set to “1”.
Value of TWCL and TWCU
written to TCB.
Figure 16 Operating Principle of Slue down Contro l When Motor Running Clockwise
Rev. 1.0, 03/99, page 100 of 209
6. Figure 17 shows the operating principle of Stop control when the motor is running clockwise.
TCB
$FF
$00
$18
Time
Counter
values of
COUNT2,
COUNT1,
COUNT0
$08D $08C $08B $08A $089 $088 $087 $000$001$002$003$004$005$006$007. . . . . .
29.696 ms
4.14744 sec
R2
0
/R8
0
phase A
R2
1
/R8
1
phase B
R2
2
/R8
2
phase A
R2
3
/R8
3
phase B
Hardware processing
Software processing
1.
2. IFTB cleared to “0”.
COUNT2 to COUNT0
decremented.
1.
2.
3.
TCB overflow.
IFTB set to “1”.
Value of TWCL and TWCU
written to TCB.
Hardware processing
Software processing
1.
2.
3.
IFTB cleared to “0”.
CNTADR set to $0, and
PLPADR set to $1.
FOWRDF set to “0”.
1.
2.
3.
TCB overflow.
IFTB set to “1”.
Value of TWCL and TWCU
written to TCB.
Figure 17 Operating Principle of Stop Control When Motor Running Clo c kwise
Rev. 1.0, 03/99, page 101 of 209
7. Figure 18 shows the operating principle of Slue up control when the motor is running
counterclockwise.
TCB
$FF
Time
$00
$DD
$CC
$AA
$11
$BB
30.592 ms 11.008 ms 8.832 ms 6.656 ms 4.480 ms
R2
0
/R8
0
phase A
R2
1
/R8
1
phase B
R2
2
/R8
2
phase A
R2
3
/R8
3
phase B
Hardware processing
Software processing
1.
2.
3.
IFTB cleared to “0”.
Corresponding data stored in
PDRs of P2
0
to P2
3
/P8
0
to P8
3
.
Pattern command reads TCB
reload value from data table and
sets TWBL/TWBU.
1.
2.
3.
TCB overflow.
IFTB set to “1”.
Value of TWCL and TWCU
written to TCB.
Hardware processing
Software processing
1.
2.
3.
IFTB cleared to “0”.
Corresponding data stored in
PDRs of P2
0
to P2
3
/P8
0
to P8
3
.
CNTADR set to $2, and COUNT2
to 0 set to $3E8.
1.
2.
3.
TCB overflow.
IFTB set to “1”.
Value of TWCL and TWCU
written to TCB.
Figure 18 Operating Principle of Slue up Contro l When Motor Running Counterclo ckwise
Rev. 1.0, 03/99, page 102 of 209
8. Figure 19 shows the operating principle of Constant control when the motor is running
counterclockwise.
TCB
$FF
$00
$DF
Time
Counter
values of
COUNT2,
COUNT1,
COUNT0
$3E8 $3E7 $3E6 $3E5 $3E4 $3E3 $3E2 $000$001$002$003$004$005$006$007 . . . . . .
4.224 ms
4.224 sec
R2
0
/R8
0
phase A
R2
1
/R8
1
phase B
R2
2
/R8
2
phase A
R2
3
/R8
3
phase B
Hardware processing
Software processing
1.
2.
3.
IFTB cleared to “0”.
Corresponding data stored in
PDRs of P2
0
to P2
3
/P8
0
to P8
3
.
COUNT2 to COUNT0
decremented.
1.
2.
3.
TCB overflow.
IFTB set to “1”.
Value of TWCL and TWCU
written to TCB.
Hardware processing
Software processing
1.
2.
3.
IFTB cleared to “0”.
Corresponding data stored in
PDRs of P2
0
to P2
3
/P8
0
to P8
3
.
CNTADR set to $4, and PLPADR
set to $D.
1.
2.
3.
TCB overflow.
IFTB set to “1”.
Value of TWCL and TWCU
written to TCB.
Figure 19 Operating Principle of Constant Control When Moto r Running
Counterclockwise
Rev. 1.0, 03/99, page 103 of 209
9. Figure 20 shows the operating principle of Slue down control when the motor is running
counterclockwise.
TCB
$FF
Time
$00
$DD
$CC
$AA
$11
$BB
30.592 ms
11.008 ms
8.832 ms
6.656 ms4.480 ms
R2
0
/R8
0
phase A
R2
1
/R8
1
phase B
R2
2
/R8
2
phase A
R2
3
/R8
3
phase B
Hardware processing
Software processing
1.
2.
3.
IFTB cleared to “0”.
Corresponding data stored in
PDRs of P2
0
to P2
3
/P8
0
to P8
3
.
Pattern command reads TCB
reload value from data table and
sets TWBL/TWBU.
1.
2.
3.
TCB overflow.
IFTB set to “1”.
Value of TWCL and TWCU
written to TCB.
Hardware processing
Software processing
1.
2.
3.
IFTB cleared to “0”.
Corresponding data stored in
PDRs of P2
0
to P2
3
/P8
0
to P8
3
.
CNTADR set to $6, and COUNT2
to 0 set to $08D.
1.
2.
3.
TCB overflow.
IFTB set to “1”.
Value of TWCL and TWCU
written to TCB.
Figure 20 Operating Principle of Slue down Contro l When Motor Running
Counterclockwise
Rev. 1.0, 03/99, page 104 of 209
10.Figure 21 shows the operating principle of Stop control when the motor is running
counterclockwise.
TCB
$FF
$00
$18
Time
Counter
values of
COUNT2,
COUNT1,
COUNT0
$08D $08C $08B $08A $089 $088 $087 $000$001$002$003$004$005$006$007. . . . . .
29.696 ms
4.14744 sec
R2
0
/R8
0
phase A
R2
1
/R8
1
phase B
R2
2
/R8
2
phase A
R2
3
/R8
3
phase B
Hardware processing
Software processing
1.
2. IFTB cleared to “0”.
COUNT2 to COUNT0
decremented.
1.
2.
3.
TCB overflow.
IFTB set to “1”.
Value of TWCL and TWCU
written to TCB.
Hardware processing
Software processing
1.
2.
3.
IFTB cleared to “0”.
CNTADR set to $0, and
PLPADR set to $1.
FOWRDF set to “0”.
1.
2.
3.
TCB overflow.
IFTB set to “1”.
Value of TWCL and TWCU
written to TCB.
Figure 21 Operating Principle of Stop Control When Motor Running Countercloc kwise
Rev. 1.0, 03/99, page 105 of 209
Description of Functions
1. Description of Modules
Table 5 describes the modules used in this example task.
Table 5 Description of Module s
Module Label Function
Main routine STEPMN This routine makes the initial stack pointer, RAM, I/O port,
and timer B settings, performs initial stepping motor control,
and enables interrupts.
Timer B interrupt
processing routine STEPCNT This routine saves the contents of the registers, makes table
branch settings, and restores the registers.
Pulse output
subroutine table PLOUT Branches to the subroutine for pulse output (POUT).
Decrement
subroutine table DEC Branches to the subroutine for decrementing the count
(DECR).
Pulse output POUT Rotates the output pulse data and stores it in the PDR of the
output port.
Decrement DECR Decrements the 12-bit counter made up of COUNT2,
COUNT1, and COUNT0.
Slue up control SLUP Reads the timer B reload value data using the pattern
command and, by increasing the output pulse cycle, performs
Slue up control of the stepping motor.
Constant control CNST Performs Constant control of the stepping motor by
maintaining the output pulse cycle at a constant rate.
Slue down control SLDOWN Reads the timer B reload value data using the pattern
command and, by decreasing the output pulse cycle,
performs Slue down control of the stepping motor.
Stop control STOP Performs Stop control by stopping the pulse output.
2. Description of Argu ments
No arguments are used in this example task.
Rev. 1.0, 03/99, page 106 of 209
3. Description of Internal Registers
a. Table 6 describes the internal registers used in the H4344.
Table 6 Internal Registers Used in H4344/H4318/H4359/H4369
Register Description RAM
Address Setting
IE Interrupt Enable Flag
This flag controls reception of all interrupts by the CPU.
• When IE = “0”, CPU reception of all interrupts is disabled.
• When IE = “1”, CPU reception is enabled.
0, $000 1
RSP Reset Stack Pointer
Clearing RSP to “0” initializes the stack pointer. 1, $000 0
IFTB Timer B Interrupt Request Flag
Reflects the existence of a timer B interrupt request.
• When IFTB = “0”, no timer B interrupt is requested.
• When IFTB = “1”, a timer B interrupt is requested.
0, $002 0
IMTB Timer B Interrupt Mask
This bit masks IFTB.
• When IMTB = “0”, IFTB is enabled.
• When IMTB = “1”, IFTB is masked.
1, $001 1
TMB1 Timer Mode Register B1
TMB13 selects the timer B functions. TMB12 to TMB10 select
the operating clock.
• When TMB13 = “1”, TMB12 = “0”, TMB11 = “1”, and TMB10
= “0”, timer B functions as a reload timer, and the operating
clock for timer B is set to the system clock divided by 128.
$009 $A
TWBL Timer Write Register BL
Sets the lower digit of the TCB reload value. $00A $8
TWBU Timer Write Register BU
Sets the upper digit of the TCB reload value. $00B $1
Rev. 1.0, 03/99, page 107 of 209
Table 6 Internal Registers Used in H4344/H4318/H4359/H4369 (cont)
Register Description RAM
Address Setting
TMB2 Timer Mode Register B2
Sets the input capture function and selects the detection edge
for EVNB pin input.
• When TMB22 = “0”, timer B functions as a free-
running/reload timer.
• When TMB22 = “1”, timer B functions as an input capture
timer.
Note: TMB22 is not used in the H4344.
• When TMB21 = “0” and TMB20 = “0”, no edge detection is
performed on EVNB pi n input.
$026 $0
SSR1 System Clock Selection Register 1
Sets the oscillation frequency of the system clock, sets the
division for the subsystem clock frequency, and sets the
subsystem clock oscillation in stop mode.
• When SSR11 = “0”, the system clock oscillation frequency is
set to 0.4 to 1MHz.
• When SSR11 = “1”, the system clock oscillation frequency is
set to 1.6 to 5 MHz.
Note: Applies only to H4369.
$027 $2
DCR2 Data Control Register R2
Controls the ON/OFF switching of the R2 port output buffer.
• When DCR23 to DCR20 = “0”, the output buffers of R23 to
R20 are OFF and R23 to R20 pi ns are set to high impedance.
• When DCR23 to DCR20 = “1”, the output buffers of R23 to
R20 are ON and the values of the corresponding PDRs are
output.
Note: Applies to H4344 only.
$032 $F
DCR8 Data Control Register R8
Controls the ON/OFF switching of the R8 port output buffer.
• When DCR83 to DCR80 = “0”, the output buffers of R83 to
R80 are OFF, and R83 to R80 pins are set to high impedance.
• When DCR83 to DCR80 = “1”, the output buffers of R83 to
R80 are ON and the values of the corresponding PDRs are
output.
Note: Applies to H4318/H4359/H4369 only.
$038 $F
Rev. 1.0, 03/99, page 108 of 209
b. Table 7 describes the internal registers used in the H4889.
Table 7 Internal Registers Used in H4889
Register Description RAM
Address Setting
IE Interrupt Enable Flag
This flag controls reception of all interrupts by the CPU.
• When IE = “0”, CPU reception of all interrupts is disabled.
• When IE = “1”, CPU reception is enabled.
0, $000 1
RSP Reset Stack Pointer
Clearing RSP to “0” initializes the stack pointer. 1, $000 0
IFTB Timer B Interrupt Request Flag
Reflects the existence of a timer B interrupt request.
• When IFTB = “0”, no timer B interrupt is requested.
• When IFTB = “1”, a timer B interrupt is requested.
2, $002 0
IMTB Timer B Interrupt Mask
This bit masks IFTB.
• When IMTB = “0”, IFTB is enabled.
• When IMTB = “1”, IFTB is masked.
3, $002 1
SSR System Clock Selection Register
Selects the system clock os cillation frequency, subsystem clock
frequency division, and, in stop mode, the subsystem clock
oscillation and system clock frequency division ratio.
• When SSR1 = “0”, the system clock oscillation frequency is
set to 0.4 to 1 MHz.
• When SSR1 = “1”, the system clock oscillation frequency is
set to 1.6 to 4.5 MHz.
$004 $2
PMR3 Port Mode Register 3
Sets the functions of the R22/SI/SO pin, R21/SCK pin, and
R20/TOC pin.
• When PMR33 = “0”, PMR32 = “0”, PRM31 = “0” and PRM30
= “0”, the R22/SI/SO pin functions as R22 I/O pin, R21/SCK
functions as R21 I/O pin, and R20/TOC functions as R20 I/O
pin.
$00B $0
Rev. 1.0, 03/99, page 109 of 209
Table 7 Internal Registers Used in H4889 (cont)
Register Description RAM
Address Setting
TMB1 Timer Mode Register B1
TMB13 selects the timer B function, TMB12 to TMB10 select the
operating cl oc k.
• When TMB13 = “1”, TMB12 = “0”, TMB11 = “1”, and TMB10
= “0”, timer B functions as a reload timer, and the timer B
clock is the system clock divided by 128.
$010 $A
TMB2 Timer Mode Register B2
Sets the timer B output mode and selects the detection edge for
EVNB pin input.
• When TMB22 = “0”, timer B output is set to toggle waveform.
• When TMB22 = “1”, timer B output is set to PWM.
• When TMB21 = “0” and TMB20 = “0”, no edge detection is
performed on EVNB pi n input.
$011 $0
TWBL Timer Write Register BL
Sets the lower digit of the TCB reload value. $012 $8
TWBU Timer Write Register BU
Sets the upper digit of the TCB reload value. $013 $1
DCR8 Data Control Register 8
Controls the ON/OFF switching of the R8 port output buffer.
• When DCR83 to DCR80 = “0”, the output buffers of R83 to
R80 are OFF, and the output pins are set to high impedance.
• When DCR83 to DCR80 = “1”, the output buffers of R83 to
R80 are ON and the values of the corresponding PDRs are
output.
$03C $F
Rev. 1.0, 03/99, page 110 of 209
4. Description of RAM
Table 8 describes the RAM used in this example task.
Table 8 RAM
Label Function RAM
Address Module
AESC Stores the contents of the accumulator
during timer B interrupt processing. $040 STEPCNT
BESC Stores the contents of the B register
during timer B interrupt processing. $041 STEPCNT
XESC Stores the contents of the X register
during timer B interrupt processing. $043 STEPCNT
YESC Stores the contents of the Y register
during timer B interrupt processing. $044 STEPCNT
PLDATA Stores the data for the pulse output
from the port. $050 STEPMN, POUT
CNTADR Stores the contents of the accumulator
used for spec ifying the address when
executing a table branch command.
$051 STEPMN, SLUP, CNST,
SLDOWN, STOP, STEPCNT
PLPADR Stores the contents of the accumulator
used for spec ifying the address when
executing a pattern command.
$052 STEPMN, SLUP, CNST,
SLDOWN, STOP
COUNT0 Stores bits 3 to 0 of the 12-bit counter
made up of COUNT0, COUNT1,
COUNT2.
$053 STEPMN, SLUP, SLDOWN,
DECR
COUNT1 Stores bits 7 to 4 of the 12-bit counter
made up of COUNT0, COUNT1,
COUNT2.
$054 SLUP, SLDOWN, DECR
COUNT2 Stores bits 11 to 8 of the 12-bit counter
made up of COUNT0, COUNT1,
COUNT2.
$055 SLUP, SLDOWN, DECR
FOWRDF This flag is used to identify the direction
(CW or CCW) of the stepping motor. 0, $05F STEPMN, STOP, POUT
Rev. 1.0, 03/99, page 111 of 209
Flow charts
1. H4344
a. Main Routine
STEPMN
Reset stack pointer
Initialize PLDATA to $3
Initialize CNTADR to $0
Initialize FOWRDF to “1”
Initialize PLPADR to $1
Set R2 port PDR to
$0 and initialize R2 port
Set DCR2 to $F and set
R2
0
to R2
3
I/O pins to
function as output pins
Set TMB1 to $A, timer B
to function as reload
timer, and TCB input
clock to system clock
divided by 128
Set TWBL to $8 and
TWBU to $1 to set the
TCB reload value to $18
Clear IFTB to “0”
Use BR command
to set ST to “1”
1
PLOUT
Set COUNT0 to $F
1
IFTB = “1”?
Clear IFTB to “0”
Add $F to COUNT0
to decrement COUNT0
COUNT0 = 0?
Clear IFTB to “0”
Clear IMTB to “0” to
enable timer B interrupts
Set IE to “1” to enable
interrupts
No
Yes
Yes
No
Rev. 1.0, 03/99, page 112 of 209
b. Timer B Interrupt Processing Routine
Make table branch
using value of
CNTADR
STEPCNT
Clear IFTB to “0”
Save registers
Restore registers
RTNI
2
c. Pulse Output
POUT
PLOUT
d. Decrement
DECR
DEC
Rev. 1.0, 03/99, page 113 of 209
e. Pulse Output
POUT
Store content of
PLDATA in accumulator
FOWRDF = “1”?
Store $8 in B register
Clear CA to “0”
Link accumulator and
CA and shift
1 bit right
CA = “1”?
Take the logical OR of
the contents of
accumulator and B
register and store result
in accumulator
Set content of
accumulator in PDR
of R2 port
Store content of
accumulator in PLDATA
RTN
Store $1 in B register
Clear CA to “0”
Link accumulator and
CA and rotate
1 bit left
CA = “1”?
Take the logical OR of
the contents of the
accumulator and B
register and store result
in accumulator
Set content of
accumulator in PDR
of R2 port
Store content of
accumulator in PLDATA
No No
Yes Yes
Yes
No
Rev. 1.0, 03/99, page 114 of 209
f. Decrement
DECR
Set $0 in accumulator
Subtract content of
accumulator and CA
from COUNT0, store the
result in the accumulator,
and store NB in CA
Clear CA to “0”
Store content of
accumulator in COUNT0
Set $0 in accumulator
Subtract content of
accumulator and CA
from COUNT1, store the
result in the accumulator,
and store NB in CA
Store content of
accumulator in COUNT1
Set $0 in accumulator
Subtract content of
accumulator and CA
from COUNT2, store the
result in the accumulator,
and store NB in CA
Store content of
accumulator in COUNT2
RTN
Rev. 1.0, 03/99, page 115 of 209
g. Slue Up Control
SLUP
PLOUT
Use BR command to
set ST to “1”
Store content of
PLPADR in accumulator
Set $0 in B register
Use P command
to read output pulse
cycle data from
data table and store
in accumulator and
B register
Store content of B
register in accumulator
Set content of
accumulator in TWBL
Increment content
of accumulator
A <= $0?
Store content of B
register in accumulator
Set content of
B register in TWBU
Store content of
PLPADR in accumulator
Store content of
accumulator in PLPADR
2
Set CNTADR to $2
Set COUNT0 to $8
Set COUNT1 to $E
Set COUNT2 to $3
2
Yes
No
Rev. 1.0, 03/99, page 116 of 209
h. Constant Control
CNST
Use BR command
to set ST to “1”
PLOUT
DEC
ST = “1”?
Set CNTADR to $4
Set PLPADR to $D
2
2
Yes
No
Rev. 1.0, 03/99, page 117 of 209
i. Slow Down Control
SLDOWN
PLOUT
Use BR command
to set ST to “1”
Store content of
PLPADR in accumulator
Set B register to $0
Use the P command
to read the output pulse
cycle data from the
data table, and store
in accumulator and
B register
Store contents of B
register in accumulator
Set contents of
accumulator in TWBL
Decrement contents
of accumulator
A <= $0?
Store contents of B
register in accumulator
Set contents of
B register in TWBU
Store contents of
PLPADR in accumulator
Store contents of
accumulator in PLPADR
2
Set CNTADR to $6
Set COUNT0 to $D
Set COUNT1 to $8
Set COUNT2 to $0
2
Yes
No
Rev. 1.0, 03/99, page 118 of 209
j. Stop Control
STOP
DEC
ST = “1”?
Set CNTADR to $0
Set PLPADR to $1
2
2
Yes
No
FOWRDF = “1”? Yes
No
Set FOWRDF to “1”
2
Clear FOWRDF to “0”
Rev. 1.0, 03/99, page 119 of 209
2. H4318/H4359/H4369
a. Main Routine
STEPMN
Initialize PLDATA to $3
Initialize CNTADR to $0
Initialize FOWRDF to “1”
Initialize PLPADR to $1
Set R8 port PDR to
$0 and initialize R8 port
Set DCR8 to $F and set
R8
0
to R8
3
I/O pins to
function as output pins
Set TMB1 to $A, timer B
to function as reload
timer, and TCB input
clock to system clock
divided by 128
Set TWBL to $8 and
TWBU to $1 to set the
TCB reload value to $18
Clear IFTB to “0”
Use BR command
to set ST to “1”
1
PLOUT
Set COUNT0 to $F
1
IFTB = “1”?
Clear IFTB to “0”
Add $F to COUNT0
to decrement COUNT0
COUNT0 = 0?
Clear IFTB to “0”
Clear IMTB to “0” to
enable timer B interrupts
Set IE to “1” to enable
interrupts
No
Yes
Yes
No
Set SSR11 to “1” to set
the system clock
to 1.6 to 5.0MHz
*
Note: * Applies to H4369 only
Reset stack pointer
Rev. 1.0, 03/99, page 120 of 209
b. Timer B Interrupt Processing Routine
Make table branch
using value of
CNTADR
STEPCNT
Clear IFTB to “0”
Save registers
Restore registers
RTNI
2
c. Pulse Output
POUT
PLOUT
d. Decrement
DECR
DEC
Rev. 1.0, 03/99, page 121 of 209
e. Pulse Output
POUT
Store content of
PLDATA in accumulator
FOWRDF = “1”?
Store $8 in B register
Clear CA to “0”
Link accumulator and
CA and shift
1 bit right
CA = “1”?
Take the logical OR of
the contents of
accumulator and B
register and store result
in accumulator
Set content of
accumulator in PDR
of R8 port
Store content of
accumulator in PLDATA
RTN
Store $1 in B register
Clear CA to “0”
Link accumulator and
CA and rotate
1 bit left
CA = “1”?
Take the logical OR of
the contents of the
accumulator and B
register and store result
in accumulator
Set content of
accumulator in PDR
of R8 port
Store content of
accumulator in PLDATA
No No
Yes Yes
Yes
No
Rev. 1.0, 03/99, page 122 of 209
f. Decrement
DECR
Set $0 in accumulator
Subtract content of
accumulator and CA
from COUNT0, store the
result in the accumulator,
and store NB in CA
Clear CA to “0”
Store content of
accumulator in COUNT0
Set $0 in accumulator
Subtract content of
accumulator and CA
from COUNT1, store the
result in the accumulator,
and store NB in CA
Store content of
accumulator in COUNT1
Set $0 in accumulator
Subtract content of
accumulator and CA
from COUNT2, store the
result in the accumulator,
and store NB in CA
Store content of
accumulator in COUNT2
RTN
Rev. 1.0, 03/99, page 123 of 209
g. Slue Up Control
SLUP
PLOUT
Use BR command to
set ST to “1”
Store content of
PLPADR in accumulator
Set $0 in B register
Use P command
to read output pulse
cycle data from
data table and store
in accumulator and
B register
Store content of B
register in accumulator
Set content of
accumulator in TWBL
Increment content
of accumulator
A <= $0?
Store content of B
register in accumulator
Set content of
B register in TWBU
Store content of
PLPADR in accumulator
Store content of
accumulator in PLPADR
2
Set CNTADR to $2
Set COUNT0 to $8
Set COUNT1 to $E
Set COUNT2 to $3
2
Yes
No
Rev. 1.0, 03/99, page 124 of 209
h. Constant Control
CNST
Use BR command
to set ST to “1”
PLOUT
DEC
ST = “1”?
Set CNTADR to $4
Set PLPADR to $D
2
2
Yes
No
Rev. 1.0, 03/99, page 125 of 209
i. Slue Down Control
SLDOWN
PLOUT
Use BR command
to set ST to “1”
Store content of
PLPADR in accumulator
Set B register to $0
Use the P command
to read the output pulse
cycle data from the
data table, and store
in accumulator and
B register
Store contents of B
register in accumulator
Set contents of
accumulator in TWBL
Decrement contents
of accumulator
A <= $0?
Store contents of B
register in accumulator
Set contents of
B register in TWBU
Store contents of
PLPADR in accumulator
Store contents of
accumulator in PLPADR
2
Set CNTADR to $6
Set COUNT0 to $D
Set COUNT1 to $8
Set COUNT2 to $0
2
Yes
No
Rev. 1.0, 03/99, page 126 of 209
j. Stop Control
STOP
DEC
ST = “1”?
Set CNTADR to $0
Set PLPADR to $1
2
2
Yes
No
FOWRDF = “1”? Yes
No
Set FOWRDF to “1”
2
Clear FOWRDF to “0”
Rev. 1.0, 03/99, page 127 of 209
3. H4889
a. Main Routine
STEPMN
Initialize PLDATA to $3
Initialize CNTADR to $0
Initialize FOWRDF to “1”
Initialize PLPADR to $1
Set R2 port PDR to
$0 and initialize R2 port
Set DCR2 to $F and set
R2
0
to R2
3
I/O pins to
function as output pins
Set TMB1 to $A, timer B
to function as reload
timer, and TCB input
clock to system clock
divided by 128
Set TWBL to $8 and
TWBU to $1 to set the
TCB reload value to $18
Clear IFTB to “0”
Use BR command
to set ST to “1”
1
PLOUT
Set COUNT0 to $F
1
IFTB = “1”?
Clear IFTB to “0”
Add $F to COUNT0
to decrement COUNT0
COUNT0 = 0?
Clear IFTB to “0”
Clear IMTB to “0” to
enable timer B interrupts
Set IE to “1” to enable
interrupts
No
Yes
Yes
No
Set SSR1 to “1” to set
the system clock
to 1.6 to 4.5 MHz
Reset stack pointer
Rev. 1.0, 03/99, page 128 of 209
b. Timer B Interrupt Processing Routine
Make table branch
using value of
CNTADR
STEPCNT
Clear IFTB to “0”
Save registers
Restore registers
RTNI
2
c. Pulse Output
POUT
PLOUT
d. Decrement
DECR
DEC
Rev. 1.0, 03/99, page 129 of 209
e. Pulse Output
POUT
Store content of
PLDATA in accumulator
FOWRDF = “1”?
Store $8 in B register
Clear CA to “0”
Link accumulator and
CA and rotate
1 bit right
CA = “1”?
Take the logical OR of
the contents of
accumulator and B
register and store result
in accumulator
Set content of
accumulator in PDR
of R2 port
Store content of
accumulator in PLDATA
RTN
Store $1 in B register
Clear CA to “0”
Link accumulator and
CA and rotate
1 bit left
CA = “1”?
Take the logical OR of
the contents of the
accumulator and B
register and store result
in accumulator
Set content of
accumulator in PDR
of R2 port
Store content of
accumulator in PLDATA
No No
Yes Yes
Yes
No
Rev. 1.0, 03/99, page 130 of 209
f. Decrement
DECR
Set $0 in accumulator
Subtract content of
accumulator and CA
from COUNT0, store the
result in the accumulator,
and store NB in CA
Clear CA to “0”
Store content of
accumulator in COUNT0
Set $0 in accumulator
Subtract content of
accumulator and CA
from COUNT1, store the
result in the accumulator,
and store NB in CA
Store content of
accumulator in COUNT1
Set $0 in accumulator
Subtract content of
accumulator and CA
from COUNT2, store the
result in the accumulator,
and store NB in CA
Store content of
accumulator in COUNT2
RTN
Rev. 1.0, 03/99, page 131 of 209
g. Slue Up Control
SLUP
PLOUT
Use BR command to
set ST to “1”
Store content of
PLPADR in accumulator
Set $0 in B register
Use P command
to read output pulse
cycle data from
data table and store
in accumulator and
B register
Store content of B
register in accumulator
Set content of
accumulator in TWBL
Increment content
of accumulator
A <= $0?
Store content of B
register in accumulator
Set content of
B register in TWBU
Store content of
PLPADR in accumulator
Store content of
accumulator in PLPADR
2
Set CNTADR to $2
Set COUNT0 to $8
Set COUNT1 to $E
Set COUNT2 to $3
2
Yes
No
Rev. 1.0, 03/99, page 132 of 209
h. Constant Control
CNST
Use BR command
to set ST to “1”
PLOUT
DEC
ST = “1”?
Set CNTADR to $4
Set PLPADR to $D
2
2
Yes
No
Rev. 1.0, 03/99, page 133 of 209
i. Slow Down Control
SLDOWN
PLOUT
Use BR command
to set ST to “1”
Store content of
PLPADR in accumulator
Set B register to $0
Use the P command
to read the output pulse
cycle data from the
data table, and store
in accumulator and
B register
Store contents of B
register in accumulator
Set contents of
accumulator in TWBL
Decrement contents
of accumulator
A <= $0?
Store contents of B
register in accumulator
Set contents of
B register in TWBU
Store contents of
PLPADR in accumulator
Store contents of
accumulator in PLPADR
2
Set CNTADR to $6
Set COUNT0 to $D
Set COUNT1 to $8
Set COUNT2 to $0
2
Yes
No
Rev. 1.0, 03/99, page 134 of 209
j. Stop Control
STOP
DEC
ST = “1”?
Set CNTADR to $0
Set PLPADR to $1
2
2
Yes
No
FOWRDF = “1”? Yes
No
Set FOWRDF to “1”
2
Clear FOWRDF to “0”
Rev. 1.0, 03/99, page 135 of 209
Program Listing
1. H4344
************************************************************
*
* H400 Series Application Note
* - Application Chapter -
*
* 'Stepping Motor Control'
*
* Function
* : Timer B Reload Timer
* : I/O Port
*
* MCU : H4344
*
* External Clock : 4MHz
* Internal Clock : 1MHz
*
************************************************************
*
************************************************************
* Symbol Definition
************************************************************
*
IE equ 0,$000 Interrupt Enable Flag
RSP equ 1,$000 Reset Stack Pointer
IF0 equ 2,$000 INT0 Interrupt Request Flag
IM0 equ 3,$000 INT0 Interrupt Mask
*
IFTB equ 0,$002 TIMER B Interrupt Request Flag
IMTB equ 1,$002 TIMER B Interrupt Mask
IFTC equ 2,$002 TIMER C Interrupt Request Flag
IMTC equ 3,$002 TIMER C Interrupt Mask
*
IFAD equ 0,$003 A/D Interrupt Request Flag
IMAD equ 1,$003 A/D Interrupt Mask
IFS equ 2,$003 SCI Interrupt Request Flag
IMS equ 3,$003 SCI Interrupt Mask
*
PMRA equ $004 Port Mode Register A
SMR equ $005 Serial Mode Register
SRL equ $006 Serial Data Register L
SRU equ $007 Serial Data Register U
*
TMB1 equ $009 Timer Mode Register B1
TRBL equ $00A Timer Read Register BL
TWBL equ $00A Timer Write register BL
TRBU equ $00B Timer Read Register BU
TWBU equ $00B Timer Write Register BU
Rev. 1.0, 03/99, page 136 of 209
MIS equ $00C Miscellaneous Register
TMC equ $00D Timer Mode Register C
TRCL equ $00E Timer Read Register CL
TWCL equ $00E Timer Write Register CL
TRCU equ $00F Timer Read Register CU
TWCU equ $00F Timer Write Register CU
*
ACR equ $016 A/D Control Register
ADRL equ $017 A/D Data Register L
ADRU equ $018 A/D Data Register U
AMR1 equ $019 A/D Mode Register 1
AMR2 equ $01A A/D Mode Register 2
*
WDON equ 1,$020 Watchdog on Flag
ADSF equ 2,$020 A/D Start Flag
*
IAOF equ 2,$021 IAD off Flag
RAME equ 3,$021 RAM Enable Flag
*
PMRB equ $024 Port Mode register B
PMRC equ $025 Port Mode Register C
TMB2 equ $026 Timer Mode Register B2
DCD0 equ $02C Data Control Register D0
DCD1 equ $02D Data Control Register D1
*
DCR0 equ $030 Data Control Register R0
DCR1 equ $031 Data Control Register R1
DCR2 equ $032 Data Control Register R2
DCR3 equ $033 Data Control Register R3
*
************************************************************
* RAM Allocation
************************************************************
*
AESC equ $040 A Escape RAM Area
BESC equ $041 B Escape RAM Area
WESC equ $042 W Escape RAM Area
XESC equ $043 X Escape RAM Area
YESC equ $044 Y Escape RAM Area
SXESC equ $045 SPX Escape RAM Area
SYESC equ $046 SPY Escape RAM Area
*
PLDATA equ $050 Pulse Data ($3 <-> $6 <-> $C <-> $9)
CNTADR equ $051 Control Process Address
PLPADR equ $052 Pulse Period Address
COUNT0 equ $053 Counter 0
COUNT1 equ $054 Counter 1
COUNT2 equ $055 Counter 2
*
FOWRDF equ 0,$05F Forward Flag( 1:Forward, 0:Reverce )
*
Rev. 1.0, 03/99, page 137 of 209
************************************************************
* Vector Address
************************************************************
*org $0000
*JMPL STEPMN Reset Interrupt
JMPL STEPMN INT0 Interrupt
*org $0008
*JMPL STEPCNT Timer B Interrupt
JMPL STEPMN Timer C Interrupt
JMPL STEPMN A/D Interrupt
JMPL STEPMN SCI Interrupt
*
************************************************************
* STEPMN : Main Program
************************************************************
*org $1000
*
STEPMN REMD RSP Stack Pointer Reset
*LMID $3,PLDATA Initialize Pulse Data
LMID $0,CNTADR Initialize Control Process Address
SEMD FOWRDF Set Forward Mode
LMID $1,PLPADR Initialize Pulse Period Address
*LAI $0 Initialize R2 Port Data Register
LRA $2
LMID $F,DCR2 Initialize R2 Port Output Terminal Function
*LMID $A,TMB1 Initialize Timer B (128tcyc,Reload Timer ON)
LMID $8,TWBL Initialize Period 29.696ms
LMID $1,TWBU
REMD IFTB Clear Timer B Interrupt Request Flag
*BR *+1 Set Status Flag
LMID $F,COUNT0 Initialize Counter 0
STMN10 CAL PLOUT Subroutine Call 'PLOUT'
*
STMN11 TMD IFTB 29.696ms Pass ?
BRS STMN12 Yes. Branch to STMN12
BRS STMN11 No. Branch to STMN11
*
STMN12 REMD IFTB Clear IFTB
LAMD COUNT0 Load Counter 0
AI $F Decrement Counter 0
LMAD COUNT0 Save Counter 0
BRS STMN10 16 times End ? No. Branch to STMN10
Rev. 1.0, 03/99, page 138 of 209
*REMD IFTB Clear Timer B Interrupt Request Flag
REMD IMTB Timer B Interrupt Enable
SEMD IE Interrupt Enable
*
STMN99 BRS STMN99 Infinite Loop
*
************************************************************
* STEPCNT : Stepping Motor Control
************************************************************
*
STEPCNT REMD IFTB Clear Timer B Interrupt Request Flag
*LMAD AESC Store Accumulator
LAB
LMAD BESC Store B Register
XSPX
LASPX
LMAD XESC Store X Register
XSPX
LAY
LMAD YESC Store Y Register
*LAMD CNTADR Load Control Process Address
LBI $0
TBR $2 Table Branch (CNTADR=0:SLUP, 2:CNST, 4:SLDOWN, 6:STOP)
*
STCNT90 LAMD YESC Restore Y Register
LYA
LAMD XESC Restore X Register
LXA
LAMD BESC Restore B Register
LBA
LAMD AESC Restore Accumulator
*RTNI Return from Interrupt
*
************************************************************
* SLUP : Slue up Control
************************************************************
*
SLUP BR *+1 Set Status Flag
CAL PLOUT Subroutine Jump to 'PLOUT'
LAMD PLPADR Load Pulse Period Address
LBI $0
P $1 Pattern Generation 'Output Pulse Period'
LAB
ALEI $0 A <= $0 ?
BRS SLUP10 Yes. Branch to SLUP10
LMAD TWBL Set Pulse Period Data Lower
LAB
Rev. 1.0, 03/99, page 139 of 209
LMAD TWBU Set Pulse Period Data Upper
LAMD PLPADR Load Pulse Period Address
AI $1 Increment Pulse Period Address
LMAD PLPADR Save Pulse Period Address
BR *+1
BRS STCNT90 Branch to STCNT90
*
SLUP10 LMID $2,CNTADR Set Constant Control Mode
LMID $8,COUNT0 Initialize Counter0 to COUNT0
LMID $E,COUNT1 12-bit Counter = H'3E8 = D'1000
LMID $3,COUNT2
BRS STCNT90 Branch to STCNT90
*
************************************************************
* CNST : Constant Control
************************************************************
*
CNST BR *+1 Set Status Flag
CAL PLOUT Subroutine Jump to 'PLOUT'
*CAL DEC Subroutine Jump to 'DEC'
BRS STCNT90 Counter = H'000 ? Yes. Branch to STCNT90
*LMID $4,CNTADR Set Slue down Control Mode
LMID $D,PLPADR Set Pulse Period Address
BRS STCNT90 Branch to STCNT90
*
************************************************************
* STDOWN : Slue down Control
************************************************************
*
SLDOWN BR *+1 Set Status Flag
CAL PLOUT Subroutine Jump to 'PLOUT'
LAMD PLPADR Load Pulse Period Address
LBI $0
P $1 Pattern Generation 'Output Pulse Period'
LAB
ALEI $0 A <= $0 ?
BRS SLDW10 Yes. Branch to SLDW10
LMAD TWBL Set Pulse Period Data Lower
LAB
LMAD TWBU Set Pulse Period Data Upper
LAMD PLPADR Load Pulse Period Address
AI $F Decrement Pulse Period Address
LMAD PLPADR Save Pulse Period Address
BR *+1
BRS STCNT90 Branch to STCNT90
*
SLDW10 LMID $6,CNTADR Set Stop Control Mode
LMID $D,COUNT0 Initialize COUNT0 to COUNT2
LMID $8,COUNT1 12-bit Counter = H'08D = D'141
Rev. 1.0, 03/99, page 140 of 209
LMID $0,COUNT2
BRS STCNT90 Branch to STCNT90
*
************************************************************
* STOP : Stop Control
************************************************************
*
STOP CAL DEC Subroutine Jump to 'DEC'
BRS STCNT90 ST = "1"? Yes. Branch to STCNT9
*LMID $0,CNTADR No. Set Slue up Control Mode
LMID $1,PLPADR Set Pulse period Address
TMD FOWRDF FOWRDF = "1" ?
BRS STOP10 Yes. Branch to STOP10
SEMD FOWRDF Set FOWRDF
BRS STCNT90 Branch to STCNT90
STOP10 REMD FOWRDF Reset FOWRDF
BRS STCNT90 Branch to STCNT90
*
************************************************************
* POUT : Output Pulse
************************************************************
*
POUT LAMD PLDATA Load Pulse Data
TMD FOWRDF FOWRDF = 1 ?
BRS POT20 Yes. Branch to POT20
*LBI $8 No.
REC Reset CA
ROTR Rotate Right A with Carry
TC CA = 1 ?
BRS POT10 Yes. Branch to POT10
BRS POT11 No. Branch to POT11
POT10 OR A = A OR B
POT11 LRA $2 Set R2 Port PDR
LMAD PLDATA Save Pulse Data
BRS POT99 Branch to POT99
*
POT20 LBI $1
REC Reset CA
ROTL Rotate Left A with Carry
TC CA = 1 ?
BRS POT21 Yes. Branch to POT21
BRS POT22 No. Branch to POT22
POT21 OR A = A OR B
POT22 LRA $2 Set R2 Port PDR
LMAD PLDATA Save Pulse Data
*
POT99 RTN Return from Subroutine
*
************************************************************
Rev. 1.0, 03/99, page 141 of 209
* DECR : Decrement Counter
************************************************************
*
DECR REC Reset Carry
LAI $0
SMCD COUNT0 A = COUNT0 - A - _CA
LMAD COUNT0 Save COUNT0
LAI $0
SMCD COUNT1 A = COUNT1 - A - _CA
LMAD COUNT1 Save COUNT1
LAI $0
SMCD COUNT2 A = COUNT2 - A - _CA
LMAD COUNT2 Save COUNT2
RTN Return from Subroutine
*
************************************************************
* Subroutine Table
************************************************************
*org $20
*
PLOUT BRL POUT Branch to POUT
DEC BRL DECR Branch to DECR
*
************************************************************
* Timer Period Data Table
************************************************************
*org $100
*dc $100 Start
dc $111 30.592ms
dc $1AA 11.008ms
dc $1BB 8.832ms
dc $1CC 6.656ms
dc $1CC 6.656ms
dc $1CC 6.656ms
dc $1DD 4.480ms
dc $1DD 4.480ms
dc $1DD 4.480ms
dc $1DD 4.480ms
dc $1DD 4.480ms
dc $1DD 4.480ms
dc $1DD 4.480ms
dc $100 End
*
************************************************************
* Pulse Motor Control Address
************************************************************
*org $200
Rev. 1.0, 03/99, page 142 of 209
*JMPL SLUP Jump to Slue up Control Routine
JMPL CNST Jump to Constant Control Routine
JMPL SLDOWN Jump to Slue down Control Routine
JMPL STOP Jump to Stop Control Routine
*end
Rev. 1.0, 03/99, page 143 of 209
2. H4318/H4359
************************************************************
*
* H400 Series Application Note
* - Application Chapter -
*
* 'Stepping Motor Control'
*
* Function
* : Timer B Reload Timer
* : I/O Port
*
* MCU : H4318/H4359
*
* External Clock : 4MHz
* Internal Clock : 1MHz
*
************************************************************
*
************************************************************
* Symbol Definition
************************************************************
*
IE equ 0,$000 Interrupt Enable Flag
RSP equ 1,$000 Reset Stack Pointer
IF0 equ 2,$000 INT0 Interrupt Request Flag
IM0 equ 3,$000 INT0 Interrupt Mask
*
IF1 equ 0,$001 INT1 Interrupt Request Flag
IM1 equ 1,$001 INT1 Interrupt Mask
IFTA equ 2,$001 TIMER A Interrupt Request Flag
IMTA equ 3,$001 TIMER A Interrupt Mask
*
IFTB equ 0,$002 TIMER B Interrupt Request Flag
IMTB equ 1,$002 TIMER B Interrupt Mask
IFTC equ 2,$002 TIMER C Interrupt Request Flag
IMTC equ 3,$002 TIMER C Interrupt Mask
*
IFAD equ 0,$003 A/D Interrupt Request Flag
IMAD equ 1,$003 A/D Interrupt Mask
IFS equ 2,$003 SCI Interrupt Request Flag
IMS equ 3,$003 SCI Interrupt Mask
*
PMRA equ $004 Port Mode Register A
SMR equ $005 Serial Mode Register
SRL equ $006 Serial Data Register L
SRU equ $007 Serial Data Register U
TMA equ $008 Timer Mode Register A
TMB1 equ $009 Timer Mode Register B1
TRBL equ $00A Timer Read Register BL
Rev. 1.0, 03/99, page 144 of 209
TWBL equ $00A Timer Write register BL
TRBU equ $00B Timer Read Register BU
TWBU equ $00B Timer Write Register BU
MIS equ $00C Miscellaneous Register
TMC equ $00D Timer Mode Register C
TRCL equ $00E Timer Read Register CL
TWCL equ $00E Timer Write Register CL
TRCU equ $00F Timer Read Register CU
TWCU equ $00F Timer Write Register CU
ACR equ $016 A/D Control Register
ADRL equ $017 A/D Data Register L
ADRU equ $018 A/D Data Register U
AMR1 equ $019 A/D Mode Register 1
AMR2 equ $01A A/D Mode Register 2
*
WDON equ 1,$020 Watchdog on Flag
ADSF equ 2,$020 A/D Start Flag
*
ICSF equ 0,$021 Input Capture Status Flag
ICEF equ 1,$021 Input Capture Error Flag
IAOF equ 2,$021 IAD off Flag
RAME equ 3,$021 RAM Enable Flag
*
PMRB equ $024 Port Mode register B
PMRC equ $025 Port Mode Register C
TMB2 equ $026 Timer Mode Register B2
DCD0 equ $02C Data Control Register D0
DCD1 equ $02D Data Control Register D1
DCD2 equ $02E Data Control Register D2
DCR0 equ $030 Data Control Register R0
DCR1 equ $031 Data Control Register R1
DCR2 equ $032 Data Control Register R2
DCR3 equ $033 Data Control Register R3
DCR4 equ $034 Data Control Register R4
DCR8 equ $038 Data Control Register R8
*
************************************************************
* RAM Allocation
************************************************************
*
AESC equ $040 A Escape RAM Area
BESC equ $041 B Escape RAM Area
WESC equ $042 W Escape RAM Area
XESC equ $043 X Escape RAM Area
YESC equ $044 Y Escape RAM Area
SXESC equ $045 SPX Escape RAM Area
SYESC equ $046 SPY Escape RAM Area
*
PLDATA equ $050 Pulse Data ($3 <-> $6 <-> $C <-> $9)
CNTADR equ $051 Control Process Address
PLPADR equ $052 Pulse Period Address
Rev. 1.0, 03/99, page 145 of 209
COUNT0 equ $053 Counter 0
COUNT1 equ $054 Counter 1
COUNT2 equ $055 Counter 2
*
FOWRDF equ 0,$05F Forward Flag( 1:Forward, 0:Reverce )
*
************************************************************
* Vector Address
************************************************************
*org $0000
*JMPL STEPMN Reset Interrupt
JMPL STEPMN INT0 Interrupt
JMPL STEPMN INT1 Interrupt
JMPL STEPMN Timer A Interrupt
JMPL STEPCNT Timer B Interrupt
JMPL STEPMN Timer C Interrupt
JMPL STEPMN A/D Interrupt
JMPL STEPMN SCI Interrupt
*
************************************************************
* STEPMN : Main Program
************************************************************
*org $1000
*
STEPMN REMD RSP Stack Pointer Reset
*LMID $3,PLDATA Initialize Pulse Data
LMID $0,CNTADR Initialize Control Process Address
SEMD FOWRDF Set Forward Mode
LMID $1,PLPADR Initialize Pulse Period Address
*LAI $0 Initialize R8 Port Data Register
LRA $8
LMID $F,DCR8 Initialize R8 Port Output Terminal Function
*LMID $A,TMB1 Initialize Timer B (128tcyc,Reload Timer ON)
LMID $8,TWBL Initialize Period 29.696ms
LMID $1,TWBU
REMD IFTB Clear Timer B Interrupt Request Flag
*BR *+1 Set Status Flag
LMID $F,COUNT0 Initialize Counter 0
STMN10 CAL PLOUT Subroutine Call 'PLOUT'
*
STMN11 TMD IFTB 29.696ms Pass ?
BRS STMN12 Yes. Branch to STMN12
BRS STMN11 No. Branch to STMN11
*
Rev. 1.0, 03/99, page 146 of 209
STMN12 REMD IFTB Clear IFTB
LAMD COUNT0 Load Counter 0
AI $F Decrement Counter 0
LMAD COUNT0 Save Counter 0
BRS STMN10 16 times End ? No. Branch to STMN10
*REMD IFTB Clear Timer B Interrupt Request Flag
REMD IMTB Timer B Interrupt Enable
SEMD IE Interrupt Enable
*
STMN99 BRS STMN99 Infinite Loop
*
************************************************************
* STEPCNT : Stepping Motor Control
************************************************************
*
STEPCNT REMD IFTB Clear Timer B Interrupt Request Flag
*LMAD AESC Store Accumulator
LAB
LMAD BESC Store B Register
XSPX
LASPX
LMAD XESC Store X Register
XSPX
LAY
LMAD YESC Store Y Register
*LAMD CNTADR Load Control Process Address
LBI $0
TBR $2 Table Branch (CNTADR=0:SLUP, 2:CNST, 4:SLDOWN, 6:STOP)
*
STCNT90 LAMD YESC Restore Y Register
LYA
LAMD XESC Restore X Register
LXA
LAMD BESC Restore B Register
LBA
LAMD AESC Restore Accumulator
*RTNI Return from Interrupt
*
************************************************************
* SLUP : Slue up Control
************************************************************
*
SLUP BR *+1 Set Status Flag
CAL PLOUT Subroutine Jump to 'PLOUT'
LAMD PLPADR Load Pulse Period Address
LBI $0
P $1 Paturn Generation 'Output Pulse Period'
Rev. 1.0, 03/99, page 147 of 209
LAB
ALEI $0 A <= $0 ?
BRS SLUP10 Yes. Branch to SLUP10
LMAD TWBL Set Pulse Period Data Lower
LAB
LMAD TWBU Set Pulse Period Data Upper
LAMD PLPADR Load Pulse Period Address
AI $1 Increment Pulse Period Address
LMAD PLPADR Save Pulse Period Address
BR *+1
BRS STCNT90 Branch to STCNT90
*
SLUP10 LMID $2,CNTADR Set Constant Control Mode
LMID $8,COUNT0 Initialize Counter0 to COUNT0
LMID $E,COUNT1 12-bit Counter = H'3E8 = D'1000
LMID $3,COUNT2
BRS STCNT90 Branch to STCNT90
*
************************************************************
* CNST : Constant Control
************************************************************
*
CNST BR *+1 Set Status Flag
CAL PLOUT Subroutine Jump to 'PLOUT'
*CAL DEC Subroutine Jump to 'DEC'
BRS STCNT90 Counter = H'000 ? Yes. Branch to STCNT90
*LMID $4,CNTADR Set Slue down Control Mode
LMID $D,PLPADR Set Pulse Period Address
BRS STCNT90 Branch to STCNT90
*
************************************************************
* STDOWN : Slue down Control
************************************************************
*
SLDOWN BR *+1 Set Status Flag
CAL PLOUT Subroutine Jump to 'PLOUT'
LAMD PLPADR Load Pulse Period Address
LBI $0
P $1 Pattern Generation 'Output Pulse Period'
LAB
ALEI $0 A <= $0 ?
BRS SLDW10 Yes. Branch to SLDW10
LMAD TWBL Set Pulse Period Data Lower
LAB
LMAD TWBU Set Pulse Period Data Upper
LAMD PLPADR Load Pulse Period Address
AI $F Decrement Pulse Period Address
LMAD PLPADR Save Pulse Period Address
BR *+1
Rev. 1.0, 03/99, page 148 of 209
BRS STCNT90 Branch to STCNT90
*
SLDW10 LMID $6,CNTADR Set Stop Control Mode
LMID $D,COUNT0 Initialize COUNT0 to COUNT2
LMID $8,COUNT1 12-bit Counter = H'08D = D'141
LMID $0,COUNT2
BRS STCNT90 Branch to STCNT90
*
************************************************************
* STOP : Stop Control
************************************************************
*
STOP CAL DEC Subroutine Jump to 'DEC'
BRS STCNT90 ST = "1"? Yes. Branch to STCNT9
*LMID $0,CNTADR No. Set Slue up Control Mode
LMID $1,PLPADR Set Pulse period Address
TMD FOWRDF FOWRDF = "1" ?
BRS STOP10 Yes. Branch to STOP10
SEMD FOWRDF Set FOWRDF
BRS STCNT90 Branch to STCNT90
STOP10 REMD FOWRDF Reset FOWRDF
BRS STCNT90 Branch to STCNT90
*
************************************************************
* POUT : Output Pulse
************************************************************
*
POUT LAMD PLDATA Load Pulse Data
TMD FOWRDF FOWRDF = 1 ?
BRS POT20 Yes. Branch to POT20
*LBI $8 No.
REC Reset CA
ROTR Rotate Right A with Carry
TC CA = 1 ?
BRS POT10 Yes. Branch to POT10
BRS POT11 No. Branch to POT11
POT10 OR A = A OR B
POT11 LRA $8 Set R8 Port PDR
LMAD PLDATA Save Pulse Data
BRS POT99 Branch to POT99
*
POT20 LBI $1
REC Reset CA
ROTL Rotate Left A with Carry
TC CA = 1 ?
BRS POT21 Yes. Branch to POT21
BRS POT22 No. Branch to POT22
POT21 OR A = A OR B
POT22 LRA $8 Set R8 Port PDR
Rev. 1.0, 03/99, page 149 of 209
LMAD PLDATA Save Pulse Data
*
POT99 RTN Return from Subroutine
*
************************************************************
* DECR : Decrement Counter
************************************************************
*
DECR REC Reset Carry
LAI $0
SMCD COUNT0 A = COUNT0 - A - _CA
LMAD COUNT0 Save COUNT0
LAI $0
SMCD COUNT1 A = COUNT1 - A - _CA
LMAD COUNT1 Save COUNT1
LAI $0
SMCD COUNT2 A = COUNT2 - A - _CA
LMAD COUNT2 Save COUNT2
RTN Return from Subroutine
*
************************************************************
* Subroutine Table
************************************************************
*org $20
*
PLOUT BRL POUT Branch to POUT
DEC BRL DECR Branch to DECR
*
************************************************************
* Timer Period Data Table
************************************************************
*org $100
*dc $100 Start
dc $111 30.592ms
dc $1AA 11.008ms
dc $1BB 8.832ms
dc $1CC 6.656ms
dc $1CC 6.656ms
dc $1CC 6.656ms
dc $1DD 4.480ms
dc $1DD 4.480ms
dc $1DD 4.480ms
dc $1DD 4.480ms
dc $1DD 4.480ms
dc $1DD 4.480ms
dc $1DD 4.480ms
dc $100 End
*
Rev. 1.0, 03/99, page 150 of 209
************************************************************
* Pulse Motor Control Address
************************************************************
*org $200
*JMPL SLUP Jump to Slue up Control Routine
JMPL CNST Jump to Constant Control Routine
JMPL SLDOWN Jump to Slue down Control Routine
JMPL STOP Jump to Stop Control Routine
*end
Rev. 1.0, 03/99, page 151 of 209
3. H4369
************************************************************
*
* H400 Series Application Note
* - Application Chapter -
*
* 'Stepping Motor Control'
*
* Function
* : Timer B Reload Timer
* : I/O Port
*
* MCU : H4369
*
* External Clock : 4MHz
* Internal Clock : 1MHz
* Sub Clock : 32.768kHz
*
************************************************************
*
************************************************************
* Symbol Definition
************************************************************
*
IE equ 0,$000 Interrupt Enable Flag
RSP equ 1,$000 Reset Stack Pointer
IF0 equ 2,$000 INT0 Interrupt Request Flag
IM0 equ 3,$000 INT0 Interrupt Mask
*
IF1 equ 0,$001 INT1 Interrupt Request Flag
IM1 equ 1,$001 INT1 Interrupt Mask
IFTA equ 2,$001 TIMER A Interrupt Request Flag
IMTA equ 3,$001 TIMER A Interrupt Mask
*
IFTB equ 0,$002 TIMER B Interrupt Request Flag
IMTB equ 1,$002 TIMER B Interrupt Mask
IFTC equ 2,$002 TIMER C Interrupt Request Flag
IMTC equ 3,$002 TIMER C Interrupt Mask
*
IFAD equ 0,$003 A/D Interrupt Request Flag
IMAD equ 1,$003 A/D Interrupt Mask
IFS equ 2,$003 SCI Interrupt Request Flag
IMS equ 3,$003 SCI Interrupt Mask
*
PMRA equ $004 Port Mode Register A
SMR equ $005 Serial Mode Register
SRL equ $006 Serial Data Register L
SRU equ $007 Serial Data Register U
TMA equ $008 Timer Mode Register A
TMB1 equ $009 Timer Mode Register B1
Rev. 1.0, 03/99, page 152 of 209
TRBL equ $00A Timer Read Register BL
TWBL equ $00A Timer Write register BL
TRBU equ $00B Timer Read Register BU
TWBU equ $00B Timer Write Register BU
MIS equ $00C Miscellaneous Register
TMC equ $00D Timer Mode Register C
TRCL equ $00E Timer Read Register CL
TWCL equ $00E Timer Write Register CL
TRCU equ $00F Timer Read Register CU
TWCU equ $00F Timer Write Register CU
*
ACR equ $016 A/D Control Register
ADRL equ $017 A/D Data Register L
ADRU equ $018 A/D Data Register U
AMR1 equ $019 A/D Mode Register 1
AMR2 equ $01A A/D Mode Register 2
*
LSON equ 0,$020 LSON Flag
WDON equ 1,$020 Watchdog on Flag
ADSF equ 2,$020 A/D Start Flag
DTON equ 3,$020 DTON Flag
*
ICSF equ 0,$021 Input Capture Status Flag
ICEF equ 1,$021 Input Capture Error Flag
IAOF equ 2,$021 IAD off Flag
RAME equ 3,$021 RAM Enable Flag
*
PMRB equ $024 Port Mode register B
PMRC equ $025 Port Mode Register C
TMB2 equ $026 Timer Mode Register B2
SSR1 equ $027 System Clock Selection Register 1
SSR2 equ $028 System Clock Selection Register 2
*
DCD0 equ $02C Data Control Register D0
DCD1 equ $02D Data Control Register D1
DCD2 equ $02E Data Control Register D2
DCD3 equ $02F Data Control Register D3
DCR0 equ $030 Data Control Register R0
DCR1 equ $031 Data Control Register R1
DCR2 equ $032 Data Control Register R2
DCR3 equ $033 Data Control Register R3
DCR4 equ $034 Data Control Register R4
DCR5 equ $035 Data Control Register R5
DCR6 equ $036 Data Control Register R6
DCR7 equ $037 Data Control Register R7
DCR8 equ $038 Data Control Register R8
DCR9 equ $039 Data Control Register R9
*
************************************************************
* RAM Allocation
************************************************************
Rev. 1.0, 03/99, page 153 of 209
*
AESC equ $040 A Escape RAM Area
BESC equ $041 B Escape RAM Area
WESC equ $042 W Escape RAM Area
XESC equ $043 X Escape RAM Area
YESC equ $044 Y Escape RAM Area
SXESC equ $045 SPX Escape RAM Area
SYESC equ $046 SPY Escape RAM Area
*
PLDATA equ $050 Pulse Data ($3 <-> $6 <-> $C <-> $9)
CNTADR equ $051 Control Process Address
PLPADR equ $052 Pulse Period Address
COUNT0 equ $053 Counter 0
COUNT1 equ $054 Counter 1
COUNT2 equ $055 Counter 2
*
FOWRDF equ 0,$05F Forward Flag( 1:Forward, 0:Reverce )
*
************************************************************
* Vector Address
************************************************************
*org $0000
*JMPL STEPMN Reset Interrupt
JMPL STEPMN INT0 Interrupt
JMPL STEPMN INT1 Interrupt
JMPL STEPMN Timer A Interrupt
JMPL STEPCNT Timer B Interrupt
JMPL STEPMN Timer C Interrupt
JMPL STEPMN A/D Interrupt
JMPL STEPMN SCI Interrupt
*
************************************************************
* STEPMN : Main Program
************************************************************
*org $1000
*
STEPMN REMD RSP Stack Pointer Reset
LMID $2,SSR1 Initialize System Clock
*LMID $3,PLDATA Initialize Pulse Data
LMID $0,CNTADR Initialize Control Process Address
SEMD FOWRDF Set Forward Mode
LMID $1,PLPADR Initialize Pulse Period Address
*LAI $0 Initialize R8 Port Data Register
LRA $8
LMID $F,DCR8 Initialize R8 Port Output Terminal Function
*
Rev. 1.0, 03/99, page 154 of 209
LMID $A,TMB1 Initialize Timer B (128tcyc,Reload Timer ON)
LMID $8,TWBL Initialize Period 29.696ms
LMID $1,TWBU
REMD IFTB Clear Timer B Interrupt Request Flag
*BR *+1 Set Status Flag
LMID $F,COUNT0 Initialize Counter 0
STMN10 CAL PLOUT Subroutine Call 'PLOUT'
*
STMN11 TMD IFTB 29.696ms Pass ?
BRS STMN12 Yes. Branch to STMN12
BRS STMN11 No. Branch to STMN11
*
STMN12 REMD IFTB Clear IFTB
LAMD COUNT0 Load Counter 0
AI $F Decrement Counter 0
LMAD COUNT0 Save Counter 0
BRS STMN10 16 times End ? No. Branch to STMN10
*REMD IFTB Clear Timer B Interrupt Request Flag
REMD IMTB Timer B Interrupt Enable
SEMD IE Interrupt Enable
*
STMN99 BRS STMN99 Infinite Loop
*
************************************************************
* STEPCNT : Stepping Motor Control
************************************************************
*
STEPCNT REMD IFTB Clear Timer B Interrupt Request Flag
*LMAD AESC Store Accumulator
LAB
LMAD BESC Store B Register
XSPX
LASPX
LMAD XESC Store X Register
XSPX
LAY
LMAD YESC Store Y Register
*LAMD CNTADR Load Control Process Address
LBI $0
TBR $2 Table Branch (CNTADR=0:SLUP, 2:CNST, 4:SLDOWN, 6:STOP)
*
STCNT90 LAMD YESC Restore Y Register
LYA
LAMD XESC Restore X Register
LXA
LAMD BESC Restore B Register
LBA
Rev. 1.0, 03/99, page 155 of 209
LAMD AESC Restore Accumulator
*RTNI Return from Interrupt
*
************************************************************
* SLUP : Slue up Control
************************************************************
*
SLUP BR *+1 Set Status Flag
CAL PLOUT Subroutine Jump to 'PLOUT'
LAMD PLPADR Load Pulse Period Address
LBI $0
P $1 Pattern Generation 'Output Pulse Period'
LAB
ALEI $0 A <= $0 ?
BRS SLUP10 Yes. Branch to SLUP10
LMAD TWBL Set Pulse Period Data Lower
LAB
LMAD TWBU Set Pulse Period Data Upper
LAMD PLPADR Load Pulse Period Address
AI $1 Increment Pulse Period Address
LMAD PLPADR Save Pulse Period Address
BR *+1
BRS STCNT90 Branch to STCNT90
*
SLUP10 LMID $2,CNTADR Set Constant Control Mode
LMID $8,COUNT0 Initialize Counter0 to COUNT0
LMID $E,COUNT1 12-bit Counter = H'3E8 = D'1000
LMID $3,COUNT2
BRS STCNT90 Branch to STCNT90
*
************************************************************
* CNST : Constant Control
************************************************************
*
CNST BR *+1 Set Status Flag
CAL PLOUT Subroutine Jump to 'PLOUT'
*CAL DEC Subroutine Jump to 'DEC'
BRS STCNT90 Counter = H'000 ? Yes. Branch to STCNT90
*LMID $4,CNTADR Set Slue down Control Mode
LMID $D,PLPADR Set Pulse Period Address
BRS STCNT90 Branch to STCNT90
*
************************************************************
* STDOWN : Slue down Control
************************************************************
*
SLDOWN BR *+1 Set Status Flag
CAL PLOUT Subroutine Jump to 'PLOUT'
Rev. 1.0, 03/99, page 156 of 209
LAMD PLPADR Load Pulse Period Address
LBI $0
P $1 Pattern Generation 'Output Pulse Period'
LAB
ALEI $0 A <= $0 ?
BRS SLDW10 Yes. Branch to SLDW10
LMAD TWBL Set Pulse Period Data Lower
LAB
LMAD TWBU Set Pulse Period Data Upper
LAMD PLPADR Load Pulse Period Address
AI $F Decrement Pulse Period Address
LMAD PLPADR Save Pulse Period Address
BR *+1
BRS STCNT90 Branch to STCNT90
*
SLDW10 LMID $6,CNTADR Set Stop Control Mode
LMID $D,COUNT0 Initialize COUNT0 to COUNT2
LMID $8,COUNT1 12-bit Counter = H'08D = D'141
LMID $0,COUNT2
BRS STCNT90 Branch to STCNT90
*
************************************************************
* STOP : Stop Control
************************************************************
*
STOP CAL DEC Subroutine Jump to 'DEC'
BRS STCNT90 ST = "1"? Yes. Branch to STCNT9
*LMID $0,CNTADR No. Set Slue up Control Mode
LMID $1,PLPADR Set Pulse period Address
TMD FOWRDF FOWRDF = "1" ?
BRS STOP10 Yes. Branch to STOP10
SEMD FOWRDF Set FOWRDF
BRS STCNT90 Branch to STCNT90
STOP10 REMD FOWRDF Reset FOWRDF
BRS STCNT90 Branch to STCNT90
*
************************************************************
* POUT : Output Pulse
************************************************************
*
POUT LAMD PLDATA Load Pulse Data
TMD FOWRDF FOWRDF = 1 ?
BRS POT20 Yes. Branch to POT20
*LBI $8 No.
REC Reset CA
ROTR Rotate Right A with Carry
TC CA = 1 ?
BRS POT10 Yes. Branch to POT10
BRS POT11 No. Branch to POT11
Rev. 1.0, 03/99, page 157 of 209
POT10 OR A = A OR B
POT11 LRA $8 Set R8 Port PDR
LMAD PLDATA Save Pulse Data
BRS POT99 Branch to POT99
*
POT20 LBI $1
REC Reset CA
ROTL Rotate Left A with Carry
TC CA = 1 ?
BRS POT21 Yes. Branch to POT21
BRS POT22 No. Branch to POT22
POT21 OR A = A OR B
POT22 LRA $8 Set R8 Port PDR
LMAD PLDATA Save Pulse Data
*
POT99 RTN Return from Subroutine
*
************************************************************
* DECR : Decrement Counter
************************************************************
*
DECR REC Reset Carry
LAI $0
SMCD COUNT0 A = COUNT0 - A - _CA
LMAD COUNT0 Save COUNT0
LAI $0
SMCD COUNT1 A = COUNT1 - A - _CA
LMAD COUNT1 Save COUNT1
LAI $0
SMCD COUNT2 A = COUNT2 - A - _CA
LMAD COUNT2 Save COUNT2
RTN Return from Subroutine
*
************************************************************
* Subroutine Table
************************************************************
*org $20
*
PLOUT BRL POUT Branch to POUT
DEC BRL DECR Branch to DECR
*
************************************************************
* Timer Period Data Table
************************************************************
*org $100
*dc $100 Start
dc $111 30.592ms
dc $1AA 11.008ms
Rev. 1.0, 03/99, page 158 of 209
dc $1BB 8.832ms
dc $1CC 6.656ms
dc $1CC 6.656ms
dc $1CC 6.656ms
dc $1DD 4.480ms
dc $1DD 4.480ms
dc $1DD 4.480ms
dc $1DD 4.480ms
dc $1DD 4.480ms
dc $1DD 4.480ms
dc $1DD 4.480ms
dc $100 End
*
************************************************************
* Pulse Motor Control Address
************************************************************
*org $200
*JMPL SLUP Jump to Slue up Control Routine
JMPL CNST Jump to Constant Control Routine
JMPL SLDOWN Jump to Slue down Control Routine
JMPL STOP Jump to Stop Control Routine
*end
Rev. 1.0, 03/99, page 159 of 209
4. H4889
************************************************************
*
* H400 Series Application Note
* - Application Chapter -
*
* 'Stepping Motor Control'
*
* Function
* : Timer B Reload Timer
* : I/O Port
*
* MCU : H4889
*
* External Clock : 4MHz
* Internal Clock : 1MHz
* Sub Clock : 32.768kHz
*
************************************************************
*
************************************************************
* Symbol Definition
************************************************************
*
IE equ 0,$000 Interrupt Enable Flag
RSP equ 1,$000 Reset Stack Pointer
IFWU equ 2,$000 _WU0-_WU3 Interrupt Request Flag
IMWU equ 3,$000 _WU0-_WU3 Interrupt Mask
*
IF0 equ 0,$001 _INT0 Interrupt Request Flag
IM0 equ 1,$001 _INT0 Interrupt Mask
IF1 equ 2,$001 _INT1 Interrupt request Flag
IM1 equ 3,$001 _INT1 Interrupt Mask
*
IFTA equ 0,$002 Timer A Interrupt Request Flag
IMTA equ 1,$002 Timer A Interrupt Mask
IFTB equ 2,$002 Timer B Interrupt Request Flag
IMTB equ 3,$002 Timer B Interrupt Mask
*
IFTC equ 0,$003 Timer C Interrupt Request Flag
IMTC equ 1,$003 Timer C Interrupt Mask
IFAD equ 2,$003 A/D Converter Interrupt Request Flag
IMAD equ 3,$003 A/D Converter Interrupt Mask
*
SSR equ $004 System Clock Selection Register
MIS equ $005 Miscellaneous Register
ESR equ $006 Edge Detection Selection Register
*
PMR0 equ $008 Port Mode Register 0
PMR1 equ $009 Port Mode Register 1
Rev. 1.0, 03/99, page 160 of 209
PMR2 equ $00A Port Mode Register 2
PMR3 equ $00B Port Mode Register 3
PMR4 equ $00C Port Mode Register 4
MSR1 equ $00D Module Standby Register 1
MSR2 equ $00E Module Standby Register 2
TMA equ $00F Timer Mode Register A
TMB1 equ $010 Timer Mode Register B1
TMB2 equ $011 Timer Mode Register B2
TRBL equ $012 Timer Read Register BL
TWBL equ $012 Timer Write Register BL
TRBU equ $013 Timer Read Register BU
TWBU equ $013 Timer Write Register BU
TMC1 equ $014 Timer Mode Register C1
TMC2 equ $015 Timer Mode Register C2
TRCL equ $016 Timer Read Register CL
TWCL equ $016 Timer Write Register CL
TRCU equ $017 Timer Read Register CU
TWCU equ $017 Timer Write Register CU
TMD1 equ $018 Timer Mode Register D1
TMD2 equ $019 Timer Mode Register D2
TRDL equ $01A Timer Read Register DL
TWDL equ $01A Timer Write Register DL
TRDU equ $01B Timer read Register DU
TWDU equ $01B Timer Write register DU
*
LSON equ 0,$020 Low Speed on Flag
WDON equ 1,$020 Watchdog on Flag
ADSF equ 2,$020 A/D Start Flag
DTON equ 3,$020 DTON Flag
*
ICSF equ 0,$021 Input Capture Status Flag
ICEF equ 1,$021 Input Capture Error Flag
GEF equ 3,$021 Gear Enable Flag
*
IFTD equ 2,$022 Timer D Interrupt Request Flag
IMTD equ 3,$022 Timer D Interrupt Mask
*
IFS equ 2,$023 Serial Interrupt Request Flag
IMS equ 3,$023 Serial Interrupt Mask
*
SMR1 equ $024 Serial Mode Register 1
SMR2 equ $025 Serial Mode Register 2
SRL equ $026 Serial Data Register L
SRU equ $027 Serial Data Register U
AMR equ $028 A/D Mode Register
*
ADRL equ $02A A/D Data Register L
ADRU equ $02B A/D Data Register U
LCR equ $02C LCD Control Register
LMR equ $02D LCD Mode Register
BMR equ $02E Buzzer Mode Register
Rev. 1.0, 03/99, page 161 of 209
*
DCD0 equ $030 Data Control Register D0
DCD1 equ $031 Data Control Register D1
DCD2 equ $032 Data Control Register D2
*
DCR0 equ $034 Data Control Register R0
DCR1 equ $035 Data Control Register R1
DCR2 equ $036 Data Control Register R2
DCR3 equ $037 Data Control Register R3
DCR4 equ $038 Data Control Register R4
DCR5 equ $039 Data Control Register R5
DCR6 equ $03A Data Control Register R6
DCR7 equ $03B Data Control Register R7
DCR8 equ $03C Data Control Register R8
*
V equ $03F Bank Register
*
************************************************************
* RAM Allocation
************************************************************
*
AESC equ $040 A Escape RAM Area
BESC equ $041 B Escape RAM Area
WESC equ $042 W Escape RAM Area
XESC equ $043 X Escape RAM Area
YESC equ $044 Y Escape RAM Area
SXESC equ $045 SPX Escape RAM Area
SYESC equ $046 SPY Escape RAM Area
*
PLDATA equ $090 Pulse Data ($3 <-> $6 <-> $C <-> $9)
CNTADR equ $091 Control Process Address
PLPADR equ $092 Pulse Period Address
COUNT0 equ $093 Counter 0
COUNT1 equ $094 Counter 1
COUNT2 equ $095 Counter 2
*
FOWRDF equ 0,$09F Forward Flag( 1:Forward, 0:Reverce )
*
************************************************************
* Vector Address
************************************************************
*org $0000
*JMPL STEPMN Reset Interrupt
JMPL STEPMN _WU0-_WU3 Interrupt
JMPL STEPMN _INT0 Interrupt
JMPL STEPMN _INT1 Interrupt
JMPL STEPMN Timer A Interrupt
JMPL STEPCNT Timer B/D Interrupt
JMPL STEPMN Timer C Interrupt
Rev. 1.0, 03/99, page 162 of 209
JMPL STEPMN A/D Converter / Serial Interrupt
*
************************************************************
* STEPMN : Main Program
************************************************************
*org $1000
*
STEPMN REMD RSP Stack Pointer Reset
LMID $2,SSR Initialize System Clock
*LMID $3,PLDATA Initialize Pulse Data
LMID $0,CNTADR Initialize Control Process Address
SEMD FOWRDF Set Forward Mode
LMID $1,PLPADR Initialize Pulse Period Address
*LAI $0 Initialize R2 Port Data Register
LRA $2
LMID $F,DCR2 Initialize R2 Port Output Terminal Function
*LMID $A,TMB1 Initialize Timer B (128tcyc,Reload Timer ON)
LMID $8,TWBL Initialize Period 29.696ms
LMID $1,TWBU
REMD IFTB Clear Timer B Interrupt Request Flag
*BR *+1 Set Status Flag
LMID $F,COUNT0 Initialize Counter 0
STMN10 CAL PLOUT Subroutine Call 'PLOUT'
*
STMN11 TMD IFTB 29.696ms Pass ?
BRS STMN12 Yes. Branch to STMN12
BRS STMN11 No. Branch to STMN11
*
STMN12 REMD IFTB Clear IFTB
LAMD COUNT0 Load Counter 0
AI $F Decrement Counter 0
LMAD COUNT0 Save Counter 0
BRS STMN10 16 times End ? No. Branch to STMN10
*REMD IFTB Clear Timer B Interrupt Request Flag
REMD IMTB Timer B Interrupt Enable
SEMD IE Interrupt Enable
*
STMN99 BRS STMN99 Infinite Loop
*
************************************************************
* STEPCNT : Stepping Motor Control
************************************************************
*
STEPCNT REMD IFTB Clear Timer B Interrupt Request Flag
*
Rev. 1.0, 03/99, page 163 of 209
LMAD AESC Store Accumulator
LAB
LMAD BESC Store B Register
XSPX
LASPX
LMAD XESC Store X Register
XSPX
LAY
LMAD YESC Store Y Register
*LAMD CNTADR Load Control Process Address
LBI $0
TBR $2 Table Branch (CNTADR=0:SLUP, 2:CNST, 4:SLDOWN, 6:STOP)
*
STCNT90 LAMD YESC Restore Y Register
LYA
LAMD XESC Restore X Register
LXA
LAMD BESC Restore B Register
LBA
LAMD AESC Restore Accumulator
*RTNI Return from Interrupt
*
************************************************************
* SLUP : Slue up Control
************************************************************
*
SLUP BR *+1 Set Status Flag
CAL PLOUT Subroutine Jump to 'PLOUT'
LAMD PLPADR Load Pulse Period Address
LBI $0
P $1 Pattern Generation 'Output Pulse Period'
LAB
ALEI $0 A <= $0 ?
BRS SLUP10 Yes. Branch to SLUP10
LMAD TWBL Set Pulse Period Data Lower
LAB
LMAD TWBU Set Pulse Period Data Upper
LAMD PLPADR Load Pulse Period Address
AI $1 Increment Pulse Period Address
LMAD PLPADR Save Pulse Period Address
BR *+1
BRS STCNT90 Branch to STCNT90
*
SLUP10 LMID $2,CNTADR Set Constant Control Mode
LMID $8,COUNT0 Initialize Counter0 to COUNT0
LMID $E,COUNT1 12-bit Counter = H'3E8 = D'1000
LMID $3,COUNT2
BRS STCNT90 Branch to STCNT90
*
Rev. 1.0, 03/99, page 164 of 209
************************************************************
* CNST : Constant Control
************************************************************
*
CNST BR *+1 Set Status Flag
CAL PLOUT Subroutine Jump to 'PLOUT'
*CAL DEC Subroutine Jump to 'DEC'
BRS STCNT90 Counter = H'000 ? Yes. Branch to STCNT90
*LMID $4,CNTADR Set Slue down Control Mode
LMID $D,PLPADR Set Pulse Period Address
BRS STCNT90 Branch to STCNT90
*
************************************************************
* STDOWN : Slue down Control
************************************************************
*
SLDOWN BR *+1 Set Status Flag
CAL PLOUT Subroutine Jump to 'PLOUT'
LAMD PLPADR Load Pulse Period Address
LBI $0
P $1 Pattern Generation 'Output Pulse Period'
LAB
ALEI $0 A <= $0 ?
BRS SLDW10 Yes. Branch to SLDW10
LMAD TWBL Set Pulse Period Data Lower
LAB
LMAD TWBU Set Pulse Period Data Upper
LAMD PLPADR Load Pulse Period Address
AI $F Decrement Pulse Period Address
LMAD PLPADR Save Pulse Period Address
BR *+1
BRS STCNT90 Branch to STCNT90
*
SLDW10 LMID $6,CNTADR Set Stop Control Mode
LMID $D,COUNT0 Initialize COUNT0 to COUNT2
LMID $8,COUNT1 12-bit Counter = H'08D = D'141
LMID $0,COUNT2
BRS STCNT90 Branch to STCNT90
*
************************************************************
* STOP : Stop Control
************************************************************
*
STOP CAL DEC Subroutine Jump to 'DEC'
BRS STCNT90 ST = "1"? Yes. Branch to STCNT9
*LMID $0,CNTADR No. Set Slue up Control Mode
LMID $1,PLPADR Set Pulse period Address
TMD FOWRDF FOWRDF = "1" ?
Rev. 1.0, 03/99, page 165 of 209
BRS STOP10 Yes. Branch to STOP10
SEMD FOWRDF Set FOWRDF
BRS STCNT90 Branch to STCNT90
STOP10 REMD FOWRDF Reset FOWRDF
BRS STCNT90 Branch to STCNT90
*
************************************************************
* POUT : Output Pulse
************************************************************
*
POUT LAMD PLDATA Load Pulse Data
TMD FOWRDF FOWRDF = 1 ?
BRS POT20 Yes. Branch to POT20
*LBI $8 No.
REC Reset CA
ROTR Rotate Right A with Carry
TC CA = 1 ?
BRS POT10 Yes. Branch to POT10
BRS POT11 No. Branch to POT11
POT10 OR A = A OR B
POT11 LRA $2 Set R2 Port PDR
LMAD PLDATA Save Pulse Data
BRS POT99 Branch to POT99
*
POT20 LBI $1
REC Reset CA
ROTL Rotate Left A with Carry
TC CA = 1 ?
BRS POT21 Yes. Branch to POT21
BRS POT22 No. Branch to POT22
POT21 OR A = A OR B
POT22 LRA $2 Set R2 Port PDR
LMAD PLDATA Save Pulse Data
*
POT99 RTN Return from Subroutine
*
************************************************************
* DECR : Decrement Counter
************************************************************
*
DECR REC Reset Carry
LAI $0
SMCD COUNT0 A = COUNT0 - A - _CA
LMAD COUNT0 Save COUNT0
LAI $0
SMCD COUNT1 A = COUNT1 - A - _CA
LMAD COUNT1 Save COUNT1
LAI $0
SMCD COUNT2 A = COUNT2 - A - _CA
LMAD COUNT2 Save COUNT2
Rev. 1.0, 03/99, page 166 of 209
RTN Return from Subroutine
*
************************************************************
* Subroutine Table
************************************************************
*org $20
*
PLOUT BRL POUT Branch to POUT
DEC BRL DECR Branch to DECR
*
************************************************************
* Timer Period Data Table
************************************************************
*org $100
*dc $100 Start
dc $111 30.592ms
dc $1AA 11.008ms
dc $1BB 8.832ms
dc $1CC 6.656ms
dc $1CC 6.656ms
dc $1CC 6.656ms
dc $1DD 4.480ms
dc $1DD 4.480ms
dc $1DD 4.480ms
dc $1DD 4.480ms
dc $1DD 4.480ms
dc $1DD 4.480ms
dc $1DD 4.480ms
dc $100 End
*
************************************************************
* Pulse Motor Control Address
************************************************************
*org $200
*JMPL SLUP Jump to Slue up Control Routine
JMPL CNST Jump to Constant Control Routine
JMPL SLDOWN Jump to Slue down Control Routine
JMPL STOP Jump to Stop Control Routine
*end
Rev. 1.0, 03/99, page 167 of 209
2.3 Key Scan and 7-Segment LED Display
Key Scan and 7-Segment
LED Display MCU:
H4318/H4359/H4369 Functions Used:
R1, R2, R3 Ports, D Port, and Timer A
Specifications
1. As shown in figure 1, the H4318/H4359/H4369 Series are used to construct a key matrix key-
scanning function and 7-segment LED display.
2. Numbers 0 to F are assigned to the 16 keys and the number (0 to F of the pressed key) is
displayed on LED0, which is one of four 7-segment LEDs (LED0 to LED3).
3. Two keys cannot be pressed simultaneously (the result is invalid).
4. Key chattering is suppressed in software.
5. Figure 2 shows the key configuration and number allocation. Figure 3 shows an example 7-
segment LED display.
6. Figure 4 shows the connection of H4318/H4359/H4369 and keys and 7-segment LED.
H4318/H4359/H4369
Strb0/LED a
Strb1/LED b
Strb2/LED c
Strb3/LED d
Strb4/LED e
Strb5/LED f
Strb6/LED g
Strb7/LED h
Ret1
Ret0 20 4 6 8 A C E
31 5 7 9 B F
LED3 LED2 LED1 LED0
LED deg3
LED deg2
LED deg1
LED deg0
D3
D2
D1
D0
R31
R30
R10
R11
R12
R13
R20
R21
R22
R23
LED a
LED b
LED c
LED d
LED e
LED f
LED g
LED h
Strb0
Strb1
Strb2
Strb3
Strb4
Strb5
Strb6
Strb7
D
Figure 1 Key Scan and 7-Segment LED Display
Rev. 1.0, 03/99, page 168 of 209
9
B D F
1 3 5 7
8 A C E
0 2 4 6
Figure 2 Key Conf iguration and Assig ned Numbers
a
b
dce
fg
h
LED deg0
LED a
LED b
LED c
LED d
LED e
LED f
LED g
LED h
Figure 3 Example 7-Segment LED Display
Rev. 1.0, 03/99, page 169 of 209
H4318/H4359/H4369
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
LED3
abcde f gh
a
b
dc
e
fg
h
LED2
abcde f gh
a
b
dc
e
fg
h
LED1
abcde f gh
a
b
dc
e
fg
h
LED0
abcde f gh
a
b
dc
e
fg
h
V
CC
Key matrix
R1
0
R1
1
R1
2
R1
3
R2
0
R2
1
R2
2
R2
3
R3
0
R3
1
D
0
D
1
D
2
D
3
Figure 4 Connection of H4318/H4359/H4369 and keys and 7-Segment LED
Rev. 1.0, 03/99, page 170 of 209
Concepts
1. Key Scan
Figure 5 is a timing ch art of the key scanning operation.
a. A “Low” signal is output from P10 pin, and a strobe signal output to the STrb0 row of the
key matrix.
b. The key data for the Ret0 row of the key matrix is read from R30 and R31 pins when the
strobe signal is output.
c. Key depression is detected from the data read from the pins.
d. The strobe signal is shifted and steps a to c repeated.
P1
0
pin
P1
1
pin
P1
2
pin
P1
3
pin
P2
0
pin
P2
1
pin
P2
2
pin
P2
3
pin
Strobe signal
2.048 ms
Key data
for Strb0 row
Key data
for Strb1 row
Key data
for Strb2 row
Key data
for Strb3 row
Key data
for Strb4 row
Key data
for Strb5 row
Key data
for Strb6 row
Key data
for Strb7 row
P3
0
and
P3
1
pins
Figure 5 Timing Chart for Key Scanning Operation
Rev. 1.0, 03/99, page 171 of 209
2. Chattering Suppression
Figure 6 is a timing chart for chattering suppression.
a. Key data is sampled at intervals of 10.24 ms.
b. The data is checked to see if the same data is obtained 3 times in succession.
c. If the key data is not the same for all 3 times, key depression is ignored.
d. If the key data is the same fo r all 3 times, the key is assumed to be depressed and the key
data is taken to be valid.
1
2
3
OFF
ON 10.24 ms
ON
OFF
Key
depression
signal
Timing for
reading key
data
Timing for
validating
key data
Notes: : Key data for time before last.
: Key data for last time.
: Present key data.
ON
12
3
2
1
Chattering
Figure 6 Timing Chart for Chattering Suppression
Rev. 1.0, 03/99, page 172 of 209
2. LED Display
Table 1 shows the relationship between 7-segment LED display, port output and segment data.
Table 1 Relationship Between LED Di splay, Port Output, and Segment Data
R1 and R2 Port Output Segment Data
LED Display R10R11R12R13R20R21R22R23SEG0L SEG0U
00000011 $0 $C
10011111 $9 $F
00100101 $4 $A
00001101 $0 $B
10011001 $9 $9
01001001 $2 $9
01000001 $2 $8
00011011 $8 $D
Rev. 1.0, 03/99, page 173 of 209
Table 1 Relationship Between LED Di splay, Port Output, and Segment Data (cont)
R1 and R2 Port Output Segment Data
LED Display R10R11R12R13R20R21R22R23SEG0L SEG0U
00000001 $0 $8
00001001 $0 $9
00010001 $8 $8
11000001 $3 $8
01100011 $6 $C
10000101 $1 $A
01100001 $6 $8
01110001 $E $8
Rev. 1.0, 03/99, page 174 of 209
Description of Functions
1. This section describes the functions of the H4318/H4359/H4369 used in key scanning and 7-
segment LED display. Figure 7 is a block diagram of the functions used in this example task.
R1 port R2 port R3 port
D port
Timer A
(free-running timer)
H4318/H4359/
H4369
CPU
Key scan control
7-segment
LED display control
Key return
data
Key Strobe
signal/LED
output signal
LED control signal
Timer A
interrupt
request
D
3
D
2
D
1
D
0
LED deg0
LED deg1
LED deg2
LED deg3
R1
3
R1
2
R1
1
R1
0
R2
3
R2
2
R2
1
R2
0
R3
3
R3
2
Strb3/LED d
Strb2/LED c
Strb1/LED b
Strb0/LED a
Strb7/LED h
Strb6/LED g
Strb5/LED f
Strb4/LED e
Ret1
Ret0
H4318/H4359/H4369 functions
Interrupt cycle setting
Figure 7 Block Diagram of H4318/H4359/H4369 Functions Used in Key Scanning and
7-Segment LED Display
Rev. 1.0, 03/99, page 175 of 209
2. Descriptions of Functions of Timer A, R1/R2/R3 Ports, and D Port.
a. Figure 8 is a block diagram of the timer A functions.
/2
/4
/8
/32
/128
/512
/1024
/2048
Timer A functions
TCA input clock setting
Interrupt cycle setting
Prescaler S (PSS)
System
clock
(4 MHz/4)
(4 MHz/4) / 8 =
125 kHz
Timer mode
register A
(TCA)
Timer A interrupt
request flag
(IFTA)
Timer counter A
(TCA)
System clock
division setting
(division by 8)
TCA input
clock
selection
Interrupt
request
due to TCA
overflow
Selector
TCA overflow
256/125 kHz =
2.048 ms
Figure 8 Block Diagram of Timer A Functions
Rev. 1.0, 03/99, page 176 of 209
b. Timer A is an 8-bit free-running timer. However, in the H4369, it can also be used as a
time based real-time clock using the system clock oscillator (32.768 kHz). Table 2
describes the timer A functions.
Table 2 Timer A Functions
Timer Mode Register A (TMA)
Function TMA is a 4-bit write-only register. It selects the division ratio of the prescaler S, which
is the clock source for timer A. TMA is initialized to $0 when reset and in stop mode.
In the H4318/H4359 TMA bit 3 (TMA3) cannot be used. In the H4369, TMA3 selects
the prescaler (PSS or PSW), which is the clock source of timer A.
Timer Counter A (TCA)
Function TCA is an 8-bit up-counter, which is incremented by the input internal clock. The TCA
input clock is selected by TMA. TCA cannot be read or written to . When TCA
overflows, the timer A interrupt request flag (IFTA) is set to “1”. TCA is initialized to
$00 when reset and in stop mode.
Prescaler S (PSS)
Function PSS is an 11-bit counter to which the system clock is in put when in active mode and
standby mode, and the subsystem clock is input when in subactive mode*. PSS is
initialized to $000 at a reset, and the system clock count starts when the reset is
canceled. PSS operation is halted when reset, in stop mode, and in watch mode*.
However, it runs in other operating modes. The PSS output is shared by the internal
peripheral modules, the division ratio being set independently for each of the internal
peripheral modules.
Timer A Interrupt Request Flag (IFTA)
Function IFTA reflects the existence of the timer A interrupt request. When timer A overflows,
IFTA is set to “1 ”. IFTA can only be read/written to (only “0” can be written) using bit
operation commands. Note that IFTA is not automatically cleared ev en when the
interrupt is received, and must be cleared by writing “0” using software. IFTA is
cleared at a reset and in stop mode.
Timer A Interrupt Mask (IMTA)
Function IMTA is the bit that masks IFTA. When IFTA is set to “1” and, additionally, IMTA is
“0”, a timer A interrupt request is sent to the CPU (when IE = “1”). If IFTA is set to “1”
but IMTA is “1”, no interrupt request is sent to the CPU and the timer A interrupt is
held. IMTA can only be read or written to using bit operation commands. It is set to
“1” at a reset and in stop mode.
Note: * Applies to H4369 only.
Rev. 1.0, 03/99, page 177 of 209
c. Ports R1, R2, and R3 are 4-bit I/O ports, accessed in units of 4 bits. Each of ports R1 to R3
are accessed in 4-bit units using the output commands (LRA and LRB) to control the
output level High/Low. The output data is stored in the port data registers (PDR) of the
respective pins. The input commands (LAR and LBR) are used for 4-bit access to read the
pin levels.
d. Table 3 describes the functions of the R1, R2, and R3 ports.
Table 3 Functions of R1, R2, and R3 Ports
Data Control Register R1 (DCR1)
Function DCR1 switches the I/O pin function of the R1 port. When any bit of DCR1 is cleared
to “0”, the output buffer (CMOS) of the corresponding pin is turned OFF and the
output is set to high impedance. When the res pective bit of DCR1 is set to “1”, the
output buffer of the corresponding pin is set ON and the corresponding PDR value is
output.
Data Control Register R2 (DCR2)
Function DCR2 switches the I/O pin function of the R2 port. When any bit of DCR2 is cleared
to “0”, the output buffer (CMOS) of the corresponding pin is turned OFF and the
output is set to high impedance. When the res pective bit of DCR2 is set to “1”, the
output buffer of the corresponding pin is set ON and the corresponding PDR value is
output.
Data Control Register R3 (DCR3)
Function DCR3 switches the I/O pin function of the R3 port. When any bit of DCR3 is cleared
to “0”, the output buffer (CMOS) of the corresponding pin is turned OFF and the
output is set to high impedance. When the res pective bit of DCR3 is set to “1”, the
output buffer of the corresponding pin is set ON and the corresponding PDR value is
output.
Port Data Register (PDR)
Function The I/O pins of the R ports have bu ilt-in PDRs to store the output da ta. When the LRA
and LRB commands are execut ed, the con tents of the accumula tor (A) and B register
(B) are transferred to the PDR of the specified R port. When the corresponding DCR
of the R port is “1”, the output buffer of the appropriate pin is set ON and the value in
the PDR is output via that pin. The PDR is initialized to $F at a reset.
A/D Mode Register 1 (AMR1)
Function AMR1 is a 4-bit write-only register. Bits AMR13 to AMR10 switch the functions of the
ports dual-function pins.
Rev. 1.0, 03/99, page 178 of 209
e. The D ports are 1-bit input output ports, accessed in 1-bit units. Pins D0 to D3 are accessed
in 1-bit units using the output commands (SED, SEDD, RED, an d REDD) to control the
High/Low output level. The output data is stored in the PDR of the respective pin. Pins D0
to D3 are also accessed in 1-bit units using the input co mmands (TD and TDD) to test the
pin level.
f. Table 4 describes the functions of the D ports.
Table 4 D Port Functions
Data Control Register D0 (DCD0)
Function DCD0 switches the I/O pin function of pins D0 to D3. When any bit of DCD0 is cleared
to “0”, the output buffer (CMOS) of the corresponding pin is turned OFF and the
output is set to high impedance. When the res pective bit of DCD0 is set to “1”, the
output buffer of the corresponding pin is set ON and the corresponding PDR value is
output.
Port Data Register (PDR)
Function The I/O pins D0 to D8 have built-in PDRs to store the output data. When the SED or
SEDD commands are executed for pins D0 to D8, the corresponding PDR is set to “1”.
When the RED or REDD commands are executed, the corresponding PDR is cleared
to “0”. When a corresponding bit to DCD0 to DCD2 is “1”, the output buffer of that pin
is turned ON and the value in the PDR is output via that pin. The PDR is set to “1” at
a reset an in stop mode.
Port Mode Register A (PMRA)
Function PMRA is a 4-bit write-only register. PMRA3 switches the function of the D3/BUZZ pin.
Port Mode Register B (PMRB)
Function PMRB is a 4-bit write-only register. PMRB0 switches the functions of the D0/
INT
0 pin,
PMRB1 switches D1/
INT
1, and PMRB2 switches D2/EVNB.
Rev. 1.0, 03/99, page 179 of 209
3. Table 5 describes the allocation of functions in this example task.
Table 5 Allocation of Functions
Function Function Allocation
System clock The system clock is obtained by dividing the clock output from the system
clock oscillator by 4. It is used for operating the CPU and internal peripheral
modules. In this example task, a 4 MHz system clock oscillator is used, so
the clock supplied to the CPU and internal peripheral modules is 1 MHz. The
clock used by timer B and timer C is obtained by dividing the 1 MHz clock at
PSS.
PSS Generates the clock input to timer A by dividing the system clock. The clock
input to timer A is obtained by dividing the system clock by 8.
TCA This 8-bit up-counter counts on the input internal clock ((4 MHz/4) / 8 = 125
kHz). IFTA is set to “1” when TCA overflows.
TMA Selects the system clock divided by 8 as the TCA input clock.
IFTA Reflects the existence of timer A interrupt requests.
IMTA Enables/disables timer A interrupt requests.
DCD0 Sets D0 to D3 to function as output pins.
DCR1 Sets R10 to R13 of the R1 port to function as output pins.
DCR2 Sets R20 to R23 of the R2 port to function as output pins.
DCR3 Sets R30 and R31 of the R3 port to function as output pins.
PDR Stores the data output from the respective pins.
AMR1 Sets the R30/AN0 to R33/AN3 pins to function as R30 to R33 I/O pi ns.
PMRA Sets the D3/BUZZ pin to function as a D3 I/O pin.
PMRB Sets the D0/
INT
0 pin to function as D0 I/O pin, D1/
INT
1 pin to function as D1 I/O
pin, and D2/EVNB pin to function as D2 I/O pin.
Pins R10 to R13Output pins for Strb0/LED a to Strb3/LED d signals.
Pins R20 to R23Output pins for Strb4/LED e to Strb7/LED h signals.
Pins R30 and R31Input pins for Ret0 and Ret1 signals.
Pins D0 to D3Output pins for LED deg1 to LED deg3 signals.
Rev. 1.0, 03/99, page 180 of 209
Description of Operation
1. Figure 9 shows the operating principles of key scanning and th e 7-segment LED display.
2.048 ms 2.048 ms 2.048 ms 2.048 ms 2.048 ms
$FF
$00
TCA
LED3 on
“No display” LED2 on
“No display” LED1 on
“No display” LED0 on
“0” display Key scan
R1
0
pin
R1
1
pin
R1
2
pin
R1
3
pin
R2
0
pin
R2
1
pin
R2
2
pin
R2
3
pin
Hardware processing
Software processing
1.
2. Clear IFTA to “0”.
Output LED display data for
LED3 to 0 from pins R1
0
to
R1
3
and R2
0
to R2
3
.
1.
2. TCA overflows.
IFTA set to “1”.
Hardware processing
Software processing
1.
2. Clear IFTA to “0”.
Output strobe signal from
pins R1
0
to R1
3
and R2
0
to
R2
3
and store input data for
pins R3
0
and R3
1
in RAM.
1.
2. TCA overflows.
IFTA set to “1”.
Figure 9 Operating Principles of Key Scanning and 7-Segment LED Display
Rev. 1.0, 03/99, page 181 of 209
Description of Software
1. Description of Modules
Table 6 shows the modules used in this example task.
Table 6 Module s
Module Label Functions
Main routine LDKYMN This routine makes the initial stack pointer, RAM, I/O port,
and timer A settings, enables interrupts, and calls the
KEYDEC and LEDDSP subroutines.
Key decoder KEYDEC Converts to key data on completion of key scanning, judges if
the key data is the same three times in succession, and
suppresses chattering.
LED display LEDDSP When the key data is the same three times in succession and
is therefore taken to be valid, this routine converts the key
data to LED display data and displays the number of the
depressed key on the 7-segment LED.
Timer A interrupt
processing routine LDKYINT Saves the registers, calls the LED and KEY subroutines, and
restores registers.
LED control LED Controls the lighting of LED0 to LED3.
Key scan KEY Performs key scanning by outp utting a strobe signal and
storing the da ta input to pins R30 and R31 in RAM .
2. Description of Argu ments
No arguments are used in this example task.
Rev. 1.0, 03/99, page 182 of 209
3. Description of Internal Registers
Table 7 describes the internal registers used in this example task.
Table 7 Internal Registers Used in Example Task
Register Description RAM
Address Setting
IE Interrupt Enable Flag
Controls the CPU can receive any interrupts.
• When IE = “0”, CPU reception of all interrupts is disabled.
• When IE = “1”, CPU reception is enabled.
0, $000 1
RSP Reset Stack Pointer
The stack pointer is initialized by clearing RSP to “0”. 1, $000 0
IFTA Timer A Interrupt Request Flag
Reflects the existence of a timer A interrupt request.
• When IFTA = “0”, there is no timer A interrupt request.
• When IFTA = “1”, there is a timer A interrupt request.
2, $001 0
IMTA Timer A Interrupt Mask
This bit masks IFTA.
• When IMTA = “0”, IFTA is enabled.
• When IMTA = “1”, IFTA is masked.
3, $001 0
PMRA Port Mode Register A
Switches the function of the D3/BUZZ pin.
• When PMRA = “0”, the D3/BUZZ pin functions as the D3 I/O
pin.
• When PMRA = “1”, the D3/BUZZ pin functions as the BUZZ
output pin.
$004 $0
TMA Timer Mode Register A
Selects the timer A clock source and the input clock cycle.
• When TMA3 = “0”, the timer A clock source is the PSS.
However, this applies only to the H4369. In the
H4318/H4359, TMA3 cannot be used.
• When TMA2 = “1” and TMA1 = “0”, and TMA0 = “1”, the
timer A input clock cycle is set to 8 µs.
$008 $5
Rev. 1.0, 03/99, page 183 of 209
Table 7 Internal Registers Used in Example Task (cont)
Register Description RAM
Address Setting
AMR1 A/D mode register (AMR1)
Switches the function of the R3 port’s dual-function pins.
• When AMR13 = “0”, the R33/AN3 pin functions as the R33 I/O
pin.
• When AMR13 = “1”, the R33/AN3 pin functions as the AN3
input pin.
• When AMR12 = “0”, the R32/AN2 pin functions as the R32 I/O
pin.
• When AMR12 = “1”, the R32/AN2 pin functions as the AN2
input pin.
• When AMR11 = “0”, the R31/AN1 pin functions as the R31 I/O
pin.
• When AMR11 = “1”, the R31/AN1 pin functions as the AN1
input pin.
• When AMR10 = “0”, the R30/AN0 pin functions as the R30 I/O
pin.
• When AMR10 = “1”, the R30/AN0 pin functions as the AN0
input pin.
$019 $0
PMRB Port Mode Register B (PMRB)
Switches the function of the D port’s dual-function pins.
• When PMRB2 = “0”, the D2/EVNB pin functi ons as the D2 I/O
pin.
• When PMRB2 = “1”, the D2/EVNB pin functions as the EVNB
input pin.
• When PMRB1 = “0”, the D1/
INT
1
pin functions as the D1 I/O
pin.
• When PMRB1 = “1”, the D1/
INT
1 pin functions as the
INT
1
input pin.
• When PMRB0 = “0”, the D0/
INT
0 pin functions as the D0 I/O
pin.
• When PMRB0 = “1”, the D0/
INT
0 pin functions as the
INT
0
input pin.
$024 $0
Rev. 1.0, 03/99, page 184 of 209
Table 7 Internal Registers Used in Example Task (cont)
Register Description RAM
Address Setting
SSR1 System Clock Selection Register 1
Selects the system clock os cillation frequency, subsystem clock
frequency division, and, in stop mode, the subsystem clock
oscillation.
• When SSR11 = “0”, the system clock oscillation frequency is
set to 0.4 to 1 MHz.
• When SSR11 = “1”, the system clock oscillation frequency is
set to 1.6 to 5 MHz.
Note: Applicable only to H4369.
$027 $2
DCD0 Data Control Register D0
Controls the ON/OFF state of the D port output buffer.
• When DCD03 to DCD00 = “0”, the output buffers of the D3 to
D0 pins are OFF and output set to high impedance.
• When DCD03 to DCD00 = “1”, the output buffers of the D3 to
D0 pins are ON and the values of the corresponding PDRs
are output.
$02C $F
DCR1 Data Control Register R1
Controls the ON/OFF state of the R1 port output buffer.
• When DCR13 to DCR10 = “0”, the output buffers of the R13
to R10 pins are OFF and output set to high impedance.
• When DCR13 to DCR10 = “1”, the output buffers of the R13
to R10 pins are ON and the values of the corresponding
PDRs are output.
$030 $F
DCR2 Data Control Register R2
DCR2 switches the output buffer of the R2 port ON/OFF.
• When DCR23 to DCR20 = “0”, the output buffers of pins R23
to R20 are OFF and the pins are in the high impedance
state.
• When DCR23 to DCR20 = “1”, The output buffers of pins
R23 to R20 are ON and the values in the corresponding
PDRs are output.
$031 $F
Rev. 1.0, 03/99, page 185 of 209
Table 7 Internal Registers Used in Example Task (cont)
Register Description RAM
Address Setting
DCR3 Data Control Register R3
DCR3 switches the output buffer of the R3 port ON/OFF.
• When DCR33 to DCR30 = “0”, the output buffers of pins R33
to R30 are OFF and the pins are in the high impedance
state.
• When DCR33 to DCR30 = “1”, The output buffers of pins
R33 to R30 are ON and the values in the corresponding
PDRs are output.
$032 $0
4. Description of RAM
Table 8 describes the RAM used in this example task.
Table 8 RAM
Label Description RAM
Address Module
AESC Stores content of accumulator when processing
timer A interrupt. $040 LDKYINT
BESC Stores content of B register when processing timer A
interrupt. $041 LDKYINT
XESC Stores content of X register when processing timer A
interrupt. $043 LDKYINT
YESC Stores content of Y register when processing timer A
interrupt. $044 LDKYINT
DIGCNT Counter to control output to 7-segment LED. $054 LDKYMN,
LED, KEY
SEG0L Stores lower 4 bits of display data output to LED0. $050 LDKYMN,
LEDDSP, LED
SEG1L Stores lower 4 bits of display data output to LED1. $051 LDKYMN,
LEDDSP, LED
SEG2L Stores lower 4 bits of display data output to LED2. $052 LDKYMN,
LEDDSP, LED
SEG3L Stores lower 4 bits of display data output to LED3. $053 LDKYMN,
LEDDSP, LED
SEG0U Stores upper 4 bits of display data output to LED0. $060 LDKYMN,
LEDDSP, LED
Rev. 1.0, 03/99, page 186 of 209
Table 8 RAM (cont)
Label Description RAM
Address Module
SEG1U Stores upper 4 bits of display data output to LED1. $061 LDKYMN,
LEDDSP, LED
SEG2U Stores upper 4 bits of display data output to LED2. $062 LDKYMN,
LEDDSP, LED
SEG3U Stores upper 4 bits of display data output to LED3. $063 LDKYMN,
LEDDSP, LED
KEYFLG Stores KEYONF and KDECONF. $080 —
KEYONF Flag showing end of key scann ing. 0, $080 LDKYMN,
KEYDEC, KEY
KDECONF Flag confirming key data. 1, $080 LDKYMN,
KEYDEC,
LEDDSP
KONNEW Stores new key data $07F KEYDEC,
LEDDSP
KONOLD Stores old key data $07E KEYDEC
CHATCNT Counter to suppress chattering $07D LDKYMN,
KEYDEC
STRBU Stores upper 4 bi ts of output strobe signal $079 KEY
STRBL Stores lower 4 bits of output stro be sig nal $078 KEY
Rev. 1.0, 03/99, page 187 of 209
Flowcharts
1. Main Routine
LDKYMN
Reset stack pointer
Set SSR11 to “1” to set
system clock to 1.6 to
5.0 MHz
Initialize R1 port PDR
to $F
Initialize R2 port PDR
to $F
Initialize D0 port PDR
to 0
Initialize D1 port PDR
to 0
Initialize D2 port PDR
to 0
Initialize D3 port PDR
to 0
Set DCR1 to $F to set
the R1
3
to R1
0
I/O pins
to function as output pins
Set DCR2 to $F to set
the R2
3
to R2
0
I/O pins
to function as output pins
Set DCD0 to $F to set
the D
3
to D
0
I/O pins to
function as output pins
Set TMA to $5 to select
the system clock divided
by 8 as the timer A
input clock
1
Clear IMTA to “0” to
enable timer A
interrupts
Clear IFTA to “0”
Initialize DIGCNT
to $0
Initialize KEYFLG
to $0
Initialize CHATCNT
to $0
Initialize SEG0U to
SEG3U and SEG0L
to SEG3L to $F
1
Set IE to “1” to enable
interrupts
KEYDEC
LEDDSP
*
Note: * Applies to H4369 only
Rev. 1.0, 03/99, page 188 of 209
2. Key Decoder
KEYONF = “1”?
Set B register $F
Set X register to $7
Set Y register to $0
Store the contents of
RAM at address
indicated by X and Y
registers in accumulator
Link contents of
accumulator with CA
and rotate 1 bit left
Stores contents of
accumulator in address
indicated by X and Y
registers
Decrement content
of Y register
Y != $4?
CA = “1”?
Store content of B
register in accumulator
Store content of
accumulator in
KONNEW
23
Decrement content
of B register
B >= $1?
3
No
Yes
Yes
No
Yes
No
Yes
No
KEYDEC
Rev. 1.0, 03/99, page 189 of 209
A != KONOLD?
Store content of
accumulator in
KONNEW
Increment CHATCNT
No
Yes
2
3
CHATCNT <=$2?
Set KDECONF to “1”
Clear KEYONF to “0”
RTN
Yes
No
Initialize CHATCNT
to $0
Store content of
accumulator in
KONOLD
Rev. 1.0, 03/99, page 190 of 209
3. LED Display
LEDDSP
Initialize SEG0U to
SEG3U and SEG0L
to SEG3L to $F
Clear KDECONF to “0”
KDECONF = “1”?
Use the pattern
commands to read
corresponding segment
data from data table
according to content
of KONNEW
Store read segment
data in SEG0L and
SEG0U
RTN
No
Yes
Rev. 1.0, 03/99, page 191 of 209
4. Timer A Interrupt Processing Routine
LDKYINT
Clear IFTA to “0”
Save registers
LED
Use BR command
to set ST to “1”
KEY
Restore registers
RTNI
Rev. 1.0, 03/99, page 192 of 209
5. LED Control
LED
DIGCNT != $4?
Store content of
DIGCNT in accumulator
Store content of
accumulator in Y register
Clear PDR of D port at
address indicated by Y
register to “0”
Decrement content
of Y register
Y >= 1?
Store lower digit of
segment data at address
indicated by Y register in
PDR of R1 port
Store upper digit of
segment data at address
indicated by Y register in
PDR of R2 port
Set PDR of D port at
address indicated
by Y register to “1”
Store content of Y
register in DIGCNT
Clear CA to “0”
Set CA to “1”
4
Clear ST to “0”
RTN
CA = “1”?
4
Yes
No
No
Yes
Store $3 in Y register
No
Yes
Set ST to “1”
Rev. 1.0, 03/99, page 193 of 209
6. Key Scan
KEY
Set STRBU to $F
Set STRBL to $E
Set X register to $7
Set Y register to $4
Set content of STRBU
in PDR of R2 port
Set content of STRBL
in PDR of R1 port
NOP
NOP
NOP
Store contents of R3
port PDR in RAM
indicated by X and Y
registers
Set B register to $1
Set Y register to $4
Store contents of RAM
at address specified
by X and Y registers
in accumulator
5
Link content of
accumulator with CA
and rotate 1 bit right
5
Store content of
accumulator in RAM
at address indicated
by X and Y registers
Decrement content
of Y register
Y >= 1?
Decrement content
of B register
B >= 1?
Set CA to “1”
Store content of STRBL
in accumulator
Link content of
accumulator with CA
and rotate 1 bit left
Store content of
accumulator in STRBL
Store content of STRBU
in accumulator
Link content of
accumulator with CA
and rotate 1 bit left
6
Store content of
accumulator in STRBU
6
CA = 1?
Set KEYONF to “1”
Initialize DIGCNT
to $4
RTN
9
9
7
8
Yes
No
Yes
Yes
No
8
7
No
Rev. 1.0, 03/99, page 194 of 209
Program Listing
1. H4318/H4359
************************************************************
*
* H400 Series Application Note
* - Application Chapter -
*
* 'Keyscan & 8-segment LED Display'
*
* Function
* : Timer A Free Running Timer
* : I/O Port (D0-D3, R1-R3 Port)
*
* MCU : H4318/H4359
*
* External Clock : 4MHz
* Internal Clock : 1MHz
*
************************************************************
*
************************************************************
* Symbol Definition
************************************************************
*
IE equ 0,$000 Interrupt Request Flag
RSP equ 1,$000 Reset Stack Pointer
IF0 equ 2,$000 _INT0 Interrupt Request Flag
IM0 equ 3,$000 _INT0 Interrupt Mask
*
IF1 equ 0,$001 _INT1 Interrupt Request Flag
IM1 equ 1,$001 _INT1 Interrupt Mask
IFTA equ 2,$001 Timer A Interrupt Request Flag
IMTA equ 3,$001 Timer A Interrupt Mask
*
IFTB equ 0,$002 Timer B Interrupt Request Flag
IMTB equ 1,$002 Timer B Interrupt Mask
IFTC equ 2,$002 Timer C Interrupt Request Flag
IMTC equ 3,$002 Timer C Interrupt Mask
*
IFAD equ 0,$003 A/D Converter Interrupt Request Flag
IMAD equ 1,$003 A/D Converter Interrupt Mask
IFS equ 2,$003 Serial Interrupt Request Flag
IMS equ 3,$003 Serial Interrupt Mask
*
PMRA equ $004 Port Mode Register A
SMR equ $005 Serial Mode Register
SRL equ $006 Serial Data Register L
SRU equ $007 Serial Data Register U
TMA equ $008 Timer Mode Register A
Rev. 1.0, 03/99, page 195 of 209
TMB1 equ $009 Timer Mode Register B1
TRBL equ $00A Timer Read Register BL
TWBL equ $00A Timer Write Register BL
TRBU equ $00B Timer Read Register BU
TWBU equ $00B Timer Write Register BU
MIS equ $00C Miscellaneous register
TMC equ $00D Timer Mode Register C
TRCL equ $00E Timer Read Register CL
TWCL equ $00E Timer Write Register CL
TRCU equ $00F Timer Read Register CU
TWCU equ $00F Timer Write Register CU
ACR equ $016 A/D Control Register
ADRL equ $017 A/D Data Register L
ADRU equ $018 A/D Data Register U
AMR1 equ $019 A/D Mode Register 1
AMR2 equ $01A A/D Mode Register 2
*
WDON equ 1,$020 Watchdog on Flag
ADSF equ 2,$020 A/D Start Flag
*
ICSF equ 0,$021 Input Capture Status Flag
ICEF equ 1,$021 Input Capture Error Flag
IAOF equ 2,$021 I_AD off Flag
RAME equ 3,$021 RAM Enable Flag
*
PMRB equ $024 Port Mode Register B
PMRC equ $025 Port Mode Register C
TMB2 equ $026 Timer Mode Register B2
DCD0 equ $02C Data Control Register D0
DCD1 equ $02D Data Control Register D1
DCD2 equ $02E Data Control Register D2
DCR0 equ $030 Data Control Register R0
DCR1 equ $031 Data Control Register R1
DCR2 equ $032 Data Control register R2
DCR3 equ $033 Data Control Register R3
DCR4 equ $034 Data Control Register R4
DCR8 equ $038 Data Control Register R8
*
************************************************************
* Ram Allocation
************************************************************
*
AESC equ $040 A Escape RAM Area
BESC equ $041 B Escape RAM Area
WESC equ $042 W Escape RAM Area
XESC equ $043 X Escape RAM Area
YESC equ $044 Y Escape RAM Area
SXESC equ $045 SPX Escape RAM Area
SYESC equ $046 SPY Escape RAM Area
*
DIGCNT equ $054 LED Digit Counter
Rev. 1.0, 03/99, page 196 of 209
*
SEG0U equ $060 LED Display Data 0 Upper
SEG1U equ $061 LED Display Data 1 Upper
SEG2U equ $062 LED Display Data 2 Upper
SEG3U equ $063 LED Display Data 3 Upper
*
SEG0L equ $050 LED Display Data 0 Lower
SEG1L equ $051 LED Display Data 1 Lower
SEG2L equ $052 LED Display Data 2 Lower
SEG3L equ $053 LED Display Data 3 Lower
*
KEYFLG equ $080 Key Flag Area
KEYONF equ 0,KEYFLG Key on Flag
KDECONF equ 1,KEYFLG Key Decode on Flag
*
KONNEW equ $07F Key New Data
KONOLD equ $07E Key Old Data
CHATCNT equ $07D Chattering Counter
KEYYADR equ $07A
STRBU equ $079 Key Strobe Data UpperPPER
STRBL equ $078 Key Strobe Data Lower
*
************************************************************
* Vector Address
************************************************************
*org $0000
*JMPL LDKYMN Reset Interrupt
JMPL LDKYMN _INT0 Interrupt
JMPL LDKYMN _INT1 Interrupt
JMPL LDKYINT Timer A Interrupt
JMPL LDKYMN Timer B Interrupt
JMPL LDKYMN Timer C Interrupt
JMPL LDKYMN A/D Converter Interrupt
JMPL LDKYMN SCI Interrupt
*
************************************************************
* LDKYMN : Main Program
************************************************************
*org $1000
*
LDKYMN REMD RSP Reset Stack Pointer
*LAI $F
LRA $1 Initialize R1 Port PDR
LRA $2 Initialize R2 Port PDR
REDD $0 Initialize D0 Port PDR
REDD $1 Initialize D1 Port PDR
REDD $2 Initialize D2 Port PDR
Rev. 1.0, 03/99, page 197 of 209
REDD $3 Initialize D3 Port PDR
LMID $F,DCR1 Initialize R1 Port Terminal Function
LMID $F,DCR2 Initialize R2 Port Terminal Function
LMID $F,DCD0 Initialize D0-D3 Port Terminal Function
*LMID $5,TMA Initialize Timer A Input Clock Period
REMD IMTA Timer A Interrupt Enable
REMD IFTA Clear IFTA
*LMID $0,DIGCNT Initialize LED Digit Counter
LMID $0,KEYFLG Initialize Key on Flag & Key Decode on Flag
LMID $0,CHATCNT Initialize Chattering Counter
*LXI $6 Initialize LED Display Data
XSPX
LXI $5
LYI $3
LAI $F
LKMN10 LMAX
LMADYX
BRS LKMN10
*SEMD IE Interrupt Enable
*
LKMN90 CALL KEYDEC Subroutine Jump to KEYDEC
CALL LEDDSP Subroutine Jump to LEDDSP
BRS LKMN90 Branch to LKMN90
*
************************************************************
* KEYDEC : Key Decoder
************************************************************
*
KEYDEC TMD KEYONF KEYONF = "1" ? Keyscan End ?
BRS KD10 Yes. Branch to KD10
BRS KD90 NO. Branch to KD90
*
KD10 LBI $F
LXI $7
KD12 LYI $0
KD15 LAM Load Key Data
ROTL Rotate Left with Carry
LMAIY Save Key Data. Increment Y Register
YNEI $4 Y+1 != 0
BRS KD15 Yes. Branch to KD15
TC No. CA = 1 ?
BRS KD16 Yes. Branch to KD16
LAB
LMAD KONNEW Save Key on New Data
BRS KD20
KD16 DB Decrement B Register. B >= 1 ?
BRS KD12 Yes. Branch to KD12
Rev. 1.0, 03/99, page 198 of 209
BRS KD90 No. Branch to KD90
*
KD20 LMAD KONNEW Load Key on New Data
ANEMD KONOLD Key on New Data != Key on Old Data ?
BRS KD21 Yes. Branch to KD21
LAMD CHATCNT Load Chattering Counter
AI $1 Increment Chattering Counter
LMAD CHATCNT Save Chattering Counter
ALEI $2 A <= $2 ?
BRS KD90 Yes. Branch to KD90
SEMD KDECONF Set Key Decode on Flag
BRS KD90 Branch to KD90
KD21 LMID $0,CHATCNT Initialize Chattering Counter
LMAD KONOLD Save Key on Old Data
*
KD90 REMD KEYONF Clear Key on Flag
RTN Return
*
************************************************************
* LEDDSP : LED Display
************************************************************
*
LEDDSP TMD KDECONF KDECONF = 1 ?
BRS LDSP10 Yes. Branch to LDSP10
BRS LDSP90 No. Branch to LDSP90
*
LDSP10 REMD KDECONF Clear Key Decode on Flag
*LXI $6 Initialize LED Display Data
XSPX
LXI $5
LYI $3
LAI $F
LDSP20 LMAX
LMADYX End ?
BRS LDSP20 No. Branch to LDSP20
*LAMD KONNEW Load Key Data
LBI $0
P $F Pattern Generation
LMAD SEG0L Save LED Display Data Lower
LAB
LMAD SEG0U Save LED Display Data Upper
*
LDSP90 RTN Return from Subroutine
*
************************************************************
* LDKYINT : Timer A Interrupt Routine
************************************************************
*
LDKYINT REMD IFTA Clear Timer A Interrupt Request Flag
Rev. 1.0, 03/99, page 199 of 209
*LMAD AESC Store Accumulator
LAB
LMAD BESC Store B Register
XSPX
LASPX
LMAD XESC Store X Register
XSPX
LAY
LMAD YESC Store Y Register
*BR *+1 Set Status Flag
CALL LED Subroutine Jump to 'LED'
CALL KEY Subroutine Jump to 'KEY'
*LAMD YESC Restore Y Register
LYA
LAMD XESC Restore X Register
LXA
LAMD BESC Restore B Register
LBA
LAMD AESC Restore Accumulator
*RTNI Return from Interrupt
*
************************************************************
* LED : LED Control
************************************************************
*
LED INEMD $4,DIGCNT DIGCNT = 4 ?
BRS LED00 No. Branch to LED00
LYI $3 Yes. Initialize DIGCNT
BRS LED10 Branch to LED10
LED00 LAMD DIGCNT Load DIGCNT
LYA
RED Turn off Now Digit
DY D >= 1 ?
BRS LED10 Yes. Branch to LED10
SEC No. Set CA
BRS LED20 Branch to LED20
LED10 LXI $5 Load LED Display Data
LAM
LRA $1 Output Display Data Lower to R1 Port
LXI $6
LAM
LRA $2 Output Display Data Upper to R2 Port
SED Turn on Next Digit
LAY
LMAD DIGCNT Save DIGCNT
REC Reset CA
LED20 TC Test CA
Rev. 1.0, 03/99, page 200 of 209
*RTN Return from Subroutine
*
************************************************************
* KEY : Key Scan
************************************************************
*
KEY LMID $F,STRBU Initialize Strobe Data Upper
LMID $E,STRBL Initialize Strobe Data Lower
LXI $7
*
KEY00 LYI $4
LAMD STRBU Load Strobe Data Upper
LRA $2 Output Strobe Data Upper to R2 Port
LAMD STRBL Load Strobe Data Lower
LRA $1 Output Strobe Data Lower to R1 Port
NOP Wait
NOP Wait
NOP Wait
LAR $3 Input Key Return Data
LMA Save Key Return Data
*LBI $1
KEY10 LYI $4
KEY20 LAM Load Key Return Data
ROTR Rotate Right with Carry
LMADY Save Key Return Data. Y >= 1 ?
BRS KEY20 Yes. Branch to KEY20
DB Decrement B Register. B >= 1 ?
BRS KEY10 Yes. Branch to KEY10
*SEC Set CA
LAMD STRBL Load Strobe Data
ROTL Rotate Left with Carry
LMAD STRBL Save Strobe Data
LAMD STRBU Load Strobe Data
ROTL Rotate Left with Carry
LMAD STRBU Save Strobe Data
TC CA = 1 ?
BRS KEY00 Yes. Branch to KEY20
*SEMD KEYONF Set KEYONF
*
KEY90 LMID $4,DIGCNT Initialize DIGCNT
*RTN
*
************************************************************
* LED Display Data Table
************************************************************
*
Rev. 1.0, 03/99, page 201 of 209
org $F00
*dc $1C0 LED Display Data "0"
dc $1F9 LED Display Data "1"
dc $1A4 LED Display Data "2"
dc $1B0 LED Display Data "3"
dc $199 LED Display Data "4"
dc $192 LED Display Data "5"
dc $182 LED Display Data "6"
dc $1D8 LED Display Data "7"
dc $180 LED Display Data "8"
dc $190 LED Display Data "9"
dc $188 LED Display Data "A"
dc $183 LED Display Data "B"
dc $1C6 LED Display Data "C"
dc $1A1 LED Display Data "D"
dc $186 LED Display Data "E"
dc $18E LED Display Data "F"
*end
Rev. 1.0, 03/99, page 202 of 209
2. H4369
************************************************************
*
* H400 Series Application Note
* - Application Chapter -
*
* 'Keyscan & 8-segment LED Display'
*
* Function
* : Timer A Free Running Timer
* : I/O Port (D0-D3, R1-R3 Port)
*
* MCU : H4369
*
* External Clock : 4MHz
* Internal Clock : 1MHz
* Sub Clock : 32.768kHz
*
************************************************************
*
************************************************************
* Symbol Definition
************************************************************
*
IE equ 0,$000 Interrupt Request Flag
RSP equ 1,$000 Reset Stack Pointer
IF0 equ 2,$000 _INT0 Interrupt Request Flag
IM0 equ 3,$000 _INT0 Interrupt Mask
*
IF1 equ 0,$001 _INT1 Interrupt Request Flag
IM1 equ 1,$001 _INT1 Interrupt Mask
IFTA equ 2,$001 Timer A Interrupt Request Flag
IMTA equ 3,$001 Timer A Interrupt Mask
*
IFTB equ 0,$002 Timer B Interrupt Request Flag
IMTB equ 1,$002 Timer B Interrupt Mask
IFTC equ 2,$002 Timer C Interrupt Request Flag
IMTC equ 3,$002 Timer C Interrupt Mask
*
IFAD equ 0,$003 A/D Converter Interrupt Request Flag
IMAD equ 1,$003 A/D Converter Interrupt Mask
IFS equ 2,$003 Serial Interrupt Request Flag
IMS equ 3,$003 Serial Interrupt Mask
*
PMRA equ $004 Port Mode Register A
SMR equ $005 Serial Mode Register
SRL equ $006 Serial Data Register L
SRU equ $007 Serial Data Register U
TMA equ $008 Timer Mode Register A
TMB1 equ $009 Timer Mode Register B1
Rev. 1.0, 03/99, page 203 of 209
TRBL equ $00A Timer Read Register BL
TWBL equ $00A Timer Write Register BL
TRBU equ $00B Timer Read Register BU
TWBU equ $00B Timer Write Register BU
MIS equ $00C Miscellaneous register
TMC equ $00D Timer Mode Register C
TRCL equ $00E Timer Read Register CL
TWCL equ $00E Timer Write Register CL
TRCU equ $00F Timer Read Register CU
TWCU equ $00F Timer Write Register CU
ACR equ $016 A/D Control Register
ADRL equ $017 A/D Data Register L
ADRU equ $018 A/D Data Register U
AMR1 equ $019 A/D Mode Register 1
AMR2 equ $01A A/D Mode Register 2
*
LSON equ 0,$020 LSON Flag
WDON equ 1,$020 Watchdog on Flag
ADSF equ 2,$020 A/D Start Flag
DTON equ 3,$020 DTON Flag
*
ICSF equ 0,$021 Input Capture Status Flag
ICEF equ 1,$021 Input Capture Error Flag
IAOF equ 2,$021 I_AD off Flag
RAME equ 3,$021 RAM Enable Flag
*
PMRB equ $024 Port Mode Register B
PMRC equ $025 Port Mode Register C
TMB2 equ $026 Timer Mode Register B2
SSR1 equ $027 System Clock Selection Register 1
SSR2 equ $028 System Clock Selection register 2
*
DCD0 equ $02C Data Control Register D0
DCD1 equ $02D Data Control Register D1
DCD2 equ $02E Data Control Register D2
DCD3 equ $02F Data Control Register D3
*
DCR0 equ $030 Data Control Register R0
DCR1 equ $031 Data Control Register R1
DCR2 equ $032 Data Control register R2
DCR3 equ $033 Data Control Register R3
DCR4 equ $034 Data Control Register R4
DCR5 equ $035 Data Control Register R5
DCR6 equ $036 Data Control Register R6
DCR7 equ $037 Data Control Register R7
DCR8 equ $038 Data Control Register R8
DCR9 equ $039 Data Control Register R9
*
************************************************************
* Ram Allocation
************************************************************
Rev. 1.0, 03/99, page 204 of 209
*
AESC equ $040 A Escape RAM Area
BESC equ $041 B Escape RAM Area
WESC equ $042 W Escape RAM Area
XESC equ $043 X Escape RAM Area
YESC equ $044 Y Escape RAM Area
SXESC equ $045 SPX Escape RAM Area
SYESC equ $046 SPY Escape RAM Area
*
DIGCNT equ $054 LED Digit Counter
*
SEG0U equ $060 LED Display Data 0 Upper
SEG1U equ $061 LED Display Data 1 Upper
SEG2U equ $062 LED Display Data 2 Upper
SEG3U equ $063 LED Display Data 3 Upper
*
SEG0L equ $050 LED Display Data 0 Lower
SEG1L equ $051 LED Display Data 1 Lower
SEG2L equ $052 LED Display Data 2 Lower
SEG3L equ $053 LED Display Data 3 Lower
*
KEYFLG equ $080 Key Flag Area
KEYONF equ 0,KEYFLG Key on Flag
KDECONF equ 1,KEYFLG Key Decode on Flag
*
KONNEW equ $07F Key New Data
KONOLD equ $07E Key Old Data
CHATCNT equ $07D Chattering Counter
KEYYADR equ $07A
STRBU equ $079 Key Strobe Data UpperPPER
STRBL equ $078 Key Strobe Data Lower
*
************************************************************
* Vector Address
************************************************************
*org $0000
*JMPL LDKYMN Reset Interrupt
JMPL LDKYMN _INT0 Interrupt
JMPL LDKYMN _INT1 Interrupt
JMPL LDKYINT Timer A Interrupt
JMPL LDKYMN Timer B Interrupt
JMPL LDKYMN Timer C Interrupt
JMPL LDKYMN A/D Converter Interrupt
JMPL LDKYMN SCI Interrupt
*
************************************************************
* LDKYMN : Main Program
************************************************************
*
Rev. 1.0, 03/99, page 205 of 209
org $1000
*
LDKYMN REMD RSP Reset Stack Pointer
LMID $2,SSR1 Initialize System Clock
*LAI $F
LRA $1 Initialize R1 Port PDR
LRA $2 Initialize R2 Port PDR
REDD $0 Initialize D0 Port PDR
REDD $1 Initialize D1 Port PDR
REDD $2 Initialize D2 Port PDR
REDD $3 Initialize D3 Port PDR
LMID $F,DCR1 Initialize R1 Port Terminal Function
LMID $F,DCR2 Initialize R2 Port Terminal Function
LMID $F,DCD0 Initialize D0-D3 Port Terminal Function
*LMID $5,TMA Initialize Timer A Input Clock Period
REMD IMTA Timer A Interrupt Enable
REMD IFTA Clear IFTA
*LMID $0,DIGCNT Initialize LED Digit Counter
LMID $0,KEYFLG Initialize Key on Flag & Key Decode on Flag
LMID $0,CHATCNT Initialize Chattering Counter
*LXI $6 Initialize LED Display Data
XSPX
LXI $5
LYI $3
LAI $F
LKMN10 LMAX
LMADYX
BRS LKMN10
*SEMD IE Interrupt Enable
*
LKMN90 CALL KEYDEC Subroutine Jump to KEYDEC
CALL LEDDSP Subroutine Jump to LEDDSP
BRS LKMN90 Branch to LKMN90
*
************************************************************
* KEYDEC : Key Decoder
************************************************************
*
KEYDEC TMD KEYONF KEYONF = "1" ? Keyscan End ?
BRS KD10 Yes. Branch to KD10
BRS KD90 NO. Branch to KD90
*
KD10 LBI $F
LXI $7
KD12 LYI $0
KD15 LAM Load Key Data
Rev. 1.0, 03/99, page 206 of 209
ROTL Rotate Left with Carry
LMAIY Save Key Data. Increment Y Register
YNEI $4 Y+1 != 0
BRS KD15 Yes. Branch to KD15
TC No. CA = 1 ?
BRS KD16 Yes. Branch to KD16
LAB
LMAD KONNEW Save Key on New Data
BRS KD20
KD16 DB Decrement B Register. B >= 1 ?
BRS KD12 Yes. Branch to KD12
BRS KD90 No. Branch to KD90
*
KD20 LMAD KONNEW Load Key on New Data
ANEMD KONOLD Key on New Data != Key on Old Data ?
BRS KD21 Yes. Branch to KD21
LAMD CHATCNT Load Chattering Counter
AI $1 Increment Chattering Counter
LMAD CHATCNT Save Chattering Counter
ALEI $2 A <= $2 ?
BRS KD90 Yes. Branch to KD90
SEMD KDECONF Set Key Decode on Flag
BRS KD90 Branch to KD90
KD21 LMID $0,CHATCNT Initialize Chattering Counter
LMAD KONOLD Save Key on Old Data
*
KD90 REMD KEYONF Clear Key on Flag
RTN Return
*
************************************************************
* LEDDSP : LED Display
************************************************************
*
LEDDSP TMD KDECONF KDECONF = 1 ?
BRS LDSP10 Yes. Branch to LDSP10
BRS LDSP90 No. Branch to LDSP90
*
LDSP10 REMD KDECONF Clear Key Decode on Flag
*LXI $6 Initialize LED Display Data
XSPX
LXI $5
LYI $3
LAI $F
LDSP20 LMAX
LMADYX End ?
BRS LDSP20 No. Branch to LDSP20
*LAMD KONNEW Load Key Data
LBI $0
P $F Pattern Generation
Rev. 1.0, 03/99, page 207 of 209
LMAD SEG0L Save LED Display Data Lower
LAB
LMAD SEG0U Save LED Display Data Upper
*
LDSP90 RTN Return from Subroutine
*
************************************************************
* LDKYINT : Timer A Interrupt Routine
************************************************************
*
LDKYINT REMD IFTA Clear Timer A Interrupt Request Flag
*LMAD AESC Store Accumulator
LAB
LMAD BESC Store B Register
XSPX
LASPX
LMAD XESC Store X Register
XSPX
LAY
LMAD YESC Store Y Register
*BR *+1 Set Status Flag
CALL LED Subroutine Jump to 'LED'
CALL KEY Subroutine Jump to 'KEY'
*LAMD YESC Restore Y Register
LYA
LAMD XESC Restore X Register
LXA
LAMD BESC Restore B Register
LBA
LAMD AESC Restore Accumulator
*RTNI Return from Interrupt
*
************************************************************
* LED : LED Control
************************************************************
*
LED INEMD $4,DIGCNT DIGCNT = 4 ?
BRS LED00 No. Branch to LED00
LYI $3 Yes. Initialize DIGCNT
BRS LED10 Branch to LED10
LED00 LAMD DIGCNT Load DIGCNT
LYA
RED Turn off Now Digit
DY D >= 1 ?
BRS LED10 Yes. Branch to LED10
SEC No. Set CA
BRS LED20 Branch to LED20
Rev. 1.0, 03/99, page 208 of 209
LED10 LXI $5 Load LED Display Data
LAM
LRA $1 Output Display Data Lower to R1 Port
LXI $6
LAM
LRA $2 Output Display Data Upper to R2 Port
SED Turn on Next Digit
LAY
LMAD DIGCNT Save DIGCNT
REC Reset CA
LED20 TC Test CA
*RTN Return from Subroutine
*
************************************************************
* KEY : Key Scan
************************************************************
*
KEY LMID $F,STRBU Initialize Strobe Data Upper
LMID $E,STRBL Initialize Strobe Data Lower
LXI $7
*
KEY00 LYI $4
LAMD STRBU Load Strobe Data Upper
LRA $2 Output Strobe Data Upper to R2 Port
LAMD STRBL Load Strobe Data Lower
LRA $1 Output Strobe Data Lower to R1 Port
NOP Wait
NOP Wait
NOP Wait
LAR $3 Input Key Return Data
LMA Save Key Return Data
*LBI $1
KEY10 LYI $4
KEY20 LAM Load Key Return Data
ROTR Rotate Right with Carry
LMADY Save Key Return Data. Y >= 1 ?
BRS KEY20 Yes. Branch to KEY20
DB Decrement B Register. B >= 1 ?
BRS KEY10 Yes. Branch to KEY10
*SEC Set CA
LAMD STRBL Load Strobe Data
ROTL Rotate Left with Carry
LMAD STRBL Save Strobe Data
LAMD STRBU Load Strobe Data
ROTL Rotate Left with Carry
LMAD STRBU Save Strobe Data
TC CA = 1 ?
BRS KEY00 Yes. Branch to KEY20
Rev. 1.0, 03/99, page 209 of 209
*SEMD KEYONF Set KEYONF
*
KEY90 LMID $4,DIGCNT Initialize DIGCNT
*RTN
*
************************************************************
* LED Display Data Table
************************************************************
*org $F00
*dc $1C0 LED Display Data "0"
dc $1F9 LED Display Data "1"
dc $1A4 LED Display Data "2"
dc $1B0 LED Display Data "3"
dc $199 LED Display Data "4"
dc $192 LED Display Data "5"
dc $182 LED Display Data "6"
dc $1D8 LED Display Data "7"
dc $180 LED Display Data "8"
dc $190 LED Display Data "9"
dc $188 LED Display Data "A"
dc $183 LED Display Data "B"
dc $1C6 LED Display Data "C"
dc $1A1 LED Display Data "D"
dc $186 LED Display Data "E"
dc $18E LED Display Data "F"
*end
