Publication#
ISPM4A
Rev:
M
Amendment/
0
Issue Date:
September 2006
Lead-
Free
Package
Options
Available!
ispMACH
™
4A CPLD Family
High Performance E
2
CMOS
®
In-System Programmable Logic
FEATURES
◆
High-performance, E
2
CMOS 3.3-V & 5-V CPLD families
◆
Flexible architecture for rapid logic designs
— Excellent First-Time-Fit
TM
and refit feature
— SpeedLocking
TM
performance for guaranteed fixed timing
— Central, input and output switch matrices for 100% routability and 100% pin-out retention
◆
High speed
— 5.0ns t
PD
Commercial and 7.5ns t
PD
Industrial
— 182MHz f
CNT
◆
32 to 512 macrocells; 32 to 768 registers
◆
44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages
◆
Flexible architecture for a wide range of design styles
— D/T registers and latches
— Synchronous or asynchronous mode
— Dedicated input registers
— Programmable polarity
— Reset/ preset swapping
◆
Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— JTAG (IEEE 1149.1) compliant for boundary scan testing
— 3.3-V & 5-V JTAG in-system programming
— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system designs
— Programmable pull-up or Bus-Friendly
TM
inputs and I/Os
— Hot-socketing
— Programmable security bit
— Individual output slew rate control
◆
Advanced E
2
CMOS process provides high-performance, cost-effective solutions
◆
Lead-free package options
2 ispMACH 4A Family
Table 1. ispMACH 4A Device Features
3.3 V Devices
Feature M4A3-32 M4A3-64 M4A3-96 M4A3-128 M4A3-192 M4A3-256 M4A3-384 M4A3-512
Macrocells 32 64 96 128 192 256 384 512
User I/O options 32 32/64 48 64 96 128/160/192 160/192 160/192/256
t
PD
(ns) 5.0 5.5 5.5 5.5 6.0 5.5 6.5 7.5
f
CNT
(MHz) 182 167 167 167 160 167 154 125
t
COS
(ns) 4.0 4.0 4.0 4.0 4.5 4.0 4.5 5.5
t
SS
(ns) 3.0 3.5 3.5 3.5 3.5 3.5 3.5 5.0
Static Power (mA) 20 25/52 40 55 85 110/150 149/155 179
JTAG Compliant Yes Yes Yes Yes Yes Yes Yes Yes
PCI Compliant Yes Yes Yes Yes Yes Yes Yes Yes
5 V Devices
Feature M4A5-32 M4A5-64 M4A5-96 M4A5-128 M4A5-192 M4A5-256
Macrocells 32 64 96 128 192 256
User I/O options 32 32 48 64 96 128
t
PD
(ns) 5.0 5.5 5.5 5.5 6.0 6.5
f
CNT
(MHz) 182 167 167 167 160 154
t
COS
(ns) 4.0 4.0 4.0 4.0 4.5 5.0
t
SS
(ns) 3.0 3.5 3.5 3.5 3.5 3.5
Static Power (mA) 20 25 40 55 74 110
JTAG Compliant Yes Yes Yes Yes Yes Yes
PCI Compliant Yes Yes Yes Yes Yes Yes
ispMACH 4A Family 3
GENERAL DESCRIPTION
The ispMA CH
™
4A family from Lattice offers an ex ceptionally flexible architecture and deliv ers a superior
Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools .
The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market,
g reater flexibility and lower cost. The ispMACH 4A devices offer densities ranging from 32 to 512
macrocells with 100% utilization and 100% pin-out retention. The ispMA CH 4A families offer 5-V (M4A5-
xxx) and 3.3-V (M4A3-xxx) operation.
ispMACH 4A products are 5-V or 3.3-V in-system prog rammable through the JTAG (IEEE Std. 1149.1)
interface. JTAG boundar y scan testing also allows product testability on automated test equipment for
device connectivity.
All ispMA CH 4A family members deliv er First-Time-Fit and easy system integration with pin-out retention
after any design change and refit. For both 3.3-V and 5-V operation, ispMACH 4A products can deliver
guaranteed fixed timing as fast as 5.0 ns t
PD
and 182 MHz f
CNT
through the SpeedLocking feature when
using up to 20 product terms per output (Table 2).
Note:
1. C = Commercial, I = Industrial
Table 2. ispMACH 4A Speed Grades
Device
Speed Grade
-5 -55 -6 -65 -7 -10 -12 -14
M4A3-32
M4A5-32 C C, I C, I I
M4A3-64/32
M4A5-64/32 C C, I C, I I
M4A3-64/64 C C, I C, I I
M4A3-96
M4A5-96 C C, I C, I I
M4A3-128
M4A5-128 C C, I C, I I
M4A3-192
M4A5-192 C C, I C, I I
M4A3-256/128 C C C, I C, I I
M4A5-256/128 C C C, I I
M4A3-256/192
M4A3-256/160 C C, I I
M4A3-384 C C, I C, I I
M4A3-512 C C, I C, I I
4 ispMACH 4A Family
The ispMACH 4A family offers 20 density-I/O combinations in Thin Quad Flat Pack (TQFP), Plastic
Quad Flat Pack (PQFP), Plastic Leaded Chip Car rier (PLCC), Ball Grid Array (BGA), fine-pitch BGA
(fpBGA), and chip-array BGA (caBGA) packages ranging from 44 to 388 pins (Table 3). It also offers I/O
safety features for mixed-voltage designs so that the 3.3-V devices can accept 5-V inputs, and 5-V devices
do not overdrive 3.3-V inputs. Additional features include Bus-Friendly inputs and I/Os, a programmable
power-down mode for extra power savings and individual output slew rate control for the highest speed
transition or for the lowest noise transition.
Table 3. ispMACH 4A Package and I/O Options
(Number of I/Os and dedicated inputs in Table)
3.3 V Devices
Package M4A3-32 M4A3-64 M4A3-96 M4A3-128 M4A3-192 M4A3-256 M4A3-384 M4A3-512
44-pin PLCC 32+2 32+2
44-pin TQFP 32+2 32+2
48-pin TQFP 32+2 32+2
100-pin TQFP 64+6 48+8 64+6
100-pin PQFP 64+6
100-ball caBGA 64+6
144-pin TQFP 96+16
144-ball fpBGA 96+16
208-pin PQFP 128+14, 160 160 160
256-ball fpBGA 128+14, 192 192 192
256-ball BGA 128+14 192
388-ball fpBGA 256
5 V Devices
Package M4A5-32 M4A5-64 M4A5-96 M4A5-128 M4A5-192 M4A5-256
44-pin PLCC 32+2 32+2
44-pin TQFP 32+2 32+2
48-pin TQFP 32+2 32+2
100-pin TQFP 48+8 64+6
100-pin PQFP 64+6
144-pin TQFP 96+16
208-pin PQFP 128+14
ispMACH 4A Family 5
FUNCTIONAL DESCRIPTION
The fundamental architecture of ispMACH 4A devices (Figure 1) consists of multiple, optimized PAL
®
blocks interconnected b y a central switch matrix. The central switch matrix allows comm unication between
PAL blocks and routes inputs to the PAL blocks . Together, the PAL blocks and central switch matrix allo w
the logic designer to create large designs in a single device instead of having to use multiple devices.
The key to being able to make effective use of these devices lies in the interconnect schemes. In the
ispMACH 4A architecture, the macrocells are flexibly coupled to the product terms through the logic
allocator, and the I/O pins are flexibly coupled to the macrocells due to the output switch matrix. In
addition, more input routing options are provided b y the input switc h matrix. These resources provide the
flexibility needed to fit designs efficiently.
Notes:
1. 16 for ispMACH 4A devices with 1:1 macrocell-I/O cell ratio (see next page).
2. Block clocks do not go to I/O cells in M4A(3,5)-32/32.
3. M4A(3,5)-192, M4A(3,5)-256, M4A3-384, and M4A3-512 have dedicated clock pins which cannot be used as inputs and do not connect to the central switch
matrix.
I/O
Pins
Clock/Input
Pins
Central Switch Matrix
I/O
Pins
I/O
Pins
Dedicated
Input Pins
PAL Block
PAL Block
Logic
Allocator
with XOR
Output/
Buried
Macrocells
33/
34/
36 1616
Clock
Generator
Logic
Array
Output Switch Matrix
Input
Switch
Matrix
I/O Cells
16
16
8
Note 1
Note 2
Note 3
4
PAL Block
17466G-001
Figure 1. ispMACH 4A Block Diagram and PAL Block Structure
6 ispMACH 4A Family
Table 4. Architectural Summary of ispMACH 4A devices
The Macrocell-I/O cell ratio is defined as the number of macrocells versus the number of I/O cells
internally in a PAL block (Table 4).
The central switch matrix takes all dedicated inputs and signals from the input switch matrices and routes
them as needed to the PAL blocks . Feedback signals that return to the same PAL block still must go through
the central switch matrix. This mechanism ensures that PAL blocks in ispMACH 4A devices communicate
with each other with consistent, predictable delays.
The central switch matrix makes a ispMA CH 4A device more adv anced than simply several PAL devices on
a single chip. It allows the designer to think of the device not as a collection of blocks, but as a single
programmable device; the software partitions the design into PAL blocks through the central switc h matrix
so that the designer does not have to be concer ned with the internal architecture of the device.
Each PAL block consists of:
◆
Product-term array
◆
Logic allocator
◆
Macrocells
◆
Output switch matrix
◆
I/O cells
◆
Input switch matrix
◆
Clock generator
Notes:
1. M4A3-64/64 internal switch matrix functionality embedded in central switch matrix.
ispMACH 4A Devices
M4A3-64/32, M4A5-64/32
M4A3-96/48, M4A5-96/48
M4A3-128/64, M4A5-128/64
M4A3-192/96, M4A5-192/96
M4A3-256/128, M4A5-256/128
M4A3-384
M4A3-512
M4A3-32/32
M4A5-32/32
M4A3-64/64
M4A3-256/160
M4A3-256/192
Macrocell-I/O Cell Ratio 2:1 1:1
Input Switch Matrix Yes Yes
1
Input Registers Yes No
Central Switch Matrix Yes Yes
Output Switch Matrix Yes Yes
ispMACH 4A Family 7
Product-Term Array
The product-term ar ray consists of a number of product ter ms that form the basis of the logic being
implemented. The inputs to the AND gates come from the central switch matrix (T able 5), and are provided
in both true and complement forms for efficient logic implementation.
Logic Allocator
Within the logic allocator, product terms are allocated to macrocells in “product term clusters.” The
availability and distribution of product term clusters are automatically considered by the software as it fits
functions within a PAL block. The size of a product term cluster has been optimized to provide high
utilization of product terms, making complex functions using many product terms possible. Yet when few
product terms are used, there will be a minimal number of unused—or wasted—product terms left over.
The product term clusters available to each macrocell within a PAL block are shown in Tables 6 and 7.
Each product term cluster is associated with a macrocell. The size of a cluster depends on the configuration
of the associated macrocell. When the macrocell is used in synchronous mode
(Figure 2a), the basic cluster has 4 product terms. W hen the associated macrocell is used in asynchronous
mode (Figure 2b), the cluster has 2 product terms. Note that if the product term cluster is routed to a
different macrocell, the allocator configuration is not determined by the mode of the macrocell actually
being driv en. The configuration is alwa ys set b y the mode of the macrocell that the cluster will dri v e if not
routed away, regardless of the actual routing.
In addition, there is an extra product term that can either join the basic cluster to give an extended cluster,
or driv e the second input of an ex clusi v e-OR gate in the signal path. If included with the basic cluster, this
provides for up to 20 product ter ms on a synchronous function that uses four extended 5-product-term
clusters. A similar asynchronous function can have up to 18 product terms.
When the extra product term is used to extend the cluster, the value of the second XOR input can be
prog rammed as a 0 or a 1, giving polarity control. The possible configurations of the logic allocator are
shown in Figures 3 and 4.
Table 5. PAL Block Inputs
Device Number of Inputs to PAL Block
M4A3-32/32 and M4A5-32/32
M4A3-64/32 and M4A5-64/32
M4A3-64/64
M4A3-96/48 and M4A5-96/48
M4A3-128/64 and M4A5-128/64
33
33
33
33
33
M4A3-192/96 and M4A5-192/96
M4A3-256/128 and M4A5-256/128 34
34
M4A3-256/160 and M4A3-256/192
M4A3-384
M4A3-512
36
36
36
8 ispMACH 4A Family
Table 6. Logic Allocator for All ispMACH 4A Devices (except M4A(3,5)-32/32)
Output Macrocell Available Clusters Output Macrocell Available Clusters
M
0
C
0
, C
1
, C
2
M
8
C
7
,
C
8
, C
9
, C
10
M
1
C
0
, C
1
, C
2
, C
3
M
9
C
8
, C
9
, C
10
, C
11
M
2
C
1
, C
2
, C
3
, C
4
M
10
C
9
, C
10
, C
11
, C
12
M
3
C
2
, C
3
, C
4
, C
5
M
11
C
10
, C
11
, C
12
, C
13
M
4
C
3
, C
4
, C
5
, C
6
M
12
C
11
, C
12
, C
13
, C
14
M
5
C
4
, C
5
, C
6
, C
7
M
13
C
12
, C
13
, C
14
, C
15
M
6
C
5
, C
6
, C
7
,
C8M14 C13, C14, C15
M7C6, C7, C8, C9M15 C14, C15
Table 7. Logic Allocator for M4A(3,5)-32/32
Output Macrocell Available Clusters Output Macrocell Available Clusters
M0C0, C1, C2M8C8, C9, C10
M1C0, C1, C2, C3M9C8, C9, C10, C11
M2C1, C2, C3, C4M10 C9, C10, C11, C12
M3C2, C3, C4, C5M11 C10, C11, C12, C13
M4C3, C4, C5, C6M12 C11, C12, C13, C14
M5C4, C5, C6, C7M13 C12, C13, C14, C15
M6C5, C6, C7M14 C13, C14, C15
M7C6, C7M15 C14, C15
0 Default
0 Default
Prog. Polarity
To n-1
To n-2
From n-1
To n+1
From n+1
From n+2
Basic Product
Term Cluster
Extra
Product
Term
Logic Allocator
nn
To Macrocell
n
0 Default
0 Default
Prog. Polarity
To n-1
To n-2
From n-1
To n+1
From n+1
From n+2
Basic Product
Term Cluster
Extra
Product
Term
Logic Allocator
nn
To Macrocell
n
17466G-006
Figure 2. Logic Allocator: Configuration of Cluster “n” Set by Mode of Macrocell “n”
17466G-005
a. Synchronous Mode
b . Asynchronous Mode
ispMACH 4A Family 9
Note that the configuration of the logic allocator has absolutely no impact on the speed of the signal. All
configurations have the same delay. T his means that designers do not have to decide between optimizing
resources or speed; both can be optimized.
If not used in the cluster, the extra product term can act in conjunction with the basic cluster to provide
XOR logic for such functions as data comparison, or it can work with the D-,T-type f lip-flop to provide
for J-K, and S-R register operation. In addition, if the basic cluster is routed to another macrocell, the extra
product term is still available for logic . In this case , the first X OR input will be a logic 0. This circuit has the
flexibility to route product terms elsewhere without giving up the use of the macrocell.
Product term clusters do not “wrap” around a PAL block. This means that the macrocells at the ends of
the block have fewer product terms available.
0
17466G-007
Figure 3. Logic Allocator Configurations: Synchronous Mode
a. Basic cluster with XOR b. Extended cluster, active high c. Extended cluster, active low
d. Basic cluster routed away;
single-product-term, active high e. Extended cluster routed away
0
17466G-008
Figure 4. Logic Allocator Configurations: Asynchronous Mode
b. Extended cluster, active high c. Extended cluster, active low
e. Extended cluster routed away
d. Basic cluster routed away;
single-product-term, active high
a. Basic cluster with XOR
10 ispMACH 4A Family
Macrocell
The macrocell consists of a storage element, routing resources, a clock multiplexer, and initialization
control. The macrocell has two fundamental modes: sync hronous and async hronous (Figure 5). The mode
chosen only affects clocking and initialization in the macrocell.
In either mode, a combinatorial path can be used. For combinatorial logic, the synchronous mode will
generally be used, since it provides more product terms in the allocator.
SWAP
D/T/L Q
AP AR
Power-Up
Reset
PAL-Block
Initialization
Product Terms
From Logic Allocator
Block CLK0
Block CLK1
Block CLK2
Block CLK3
To Output and Input
Switch Matrices
Common PAL-block resource
Individual macrocell resources
From
PAL-Clock
Generator
D/T/L Q
AP AR
Power-Up
Reset
Individual
Initialization
Product Term
From Logic
Allocator
Block CLK0
Block CLK1
To Output and Input
Switch Matrices
Individual Clock
Product Term
From PAL-Block
Clock Generator
SWAP
17466G-010
Figure 5. Macrocell
17466G-009
a. Synchronous mode
b . Asynchronous mode
ispMACH 4A Family 11
The flip-f lop can be configured as a D-type or T-type latch. J-K or S-R registers can be synthesized. The
primary flip-flop configurations are shown in Figure 6, although others are possible. Flip-flop functionality
is defined in Table 8. Note that a J-K latch is inadvisable as it will cause oscillation if both J and K inputs
are HIGH.
DQ
AP AR DQ
AP AR
LQ
AP AR LQ
AP AR
G
G
TQ
AP AR
17466G-011
Figure 6. Primary Macrocell Configurations
g. Combinatorial with programmable polarity
a. D-type with XOR b. D-type with programmable D polarity
c. Latch with XOR d. Latch with programmable D polarity
e. T-type with programmable T polarity
f. Combinatorial with XOR
12 ispMACH 4A Family
Note:
1. Polarity of CLK/LE can be programmed
Although the macrocell shows only one input to the register , the XOR gate in the logic allocator allows the
D-, T-type register to emulate J-K, and S-R behavior. In this case, the available product terms are divided
between J and K (or S and R). When configured as J-K, S-R, or T -type , the extra product term must be used
on the XOR gate input for f lip-flop emulation. In any register type, the polarity of the inputs can be
programmed.
The clock input to the flip-flop can select any of the four PAL block cloc ks in synchronous mode, with the
additional choice of either polarity of an individual product term clock in the asynchronous mode.
The initialization circuit de pends on the mode. In synchronous mode (Figure 7), asynchronous reset and
preset are provided, each driven by a product term common to the entire PAL block.
Table 8. Register/Latch Operation
Configuration Input(s) CLK/LE 1Q+
D-type Register D=X
D=0
D=1
0,1, ↓ (↑)
↑ (↓)
↑ (↓)
Q
0
1
T-type Register T=X
T=0
T=1
0, 1, ↓ (↑)
↑ (↓)
↑ (↓)
Q
Q
Q
D-type Latch D=X
D=0
D=1
1(0)
0(1)
0(1)
Q
0
1
Power-Up
Reset
AP
D/T/L AR
Q
PAL-Block
Initialization
Product Terms
a. Power-up reset
Power-Up
Preset
AP
D/L
PAL-Block
Initialization
Product Terms
AR
Q
17466G-012 17466G-013
Figure 7. Synchronous Mode Initialization Configurations
b. Power-up preset
ispMACH 4A Family 13
A reset/preset swapping feature in each macrocell allows for reset and preset to be exchang ed, providing
flexibility. In asynchronous mode (Figure 8), a single individual product term is provided for initialization.
It can be selected to control reset or preset.
Note that the reset/preset swapping selection feature effects power-up reset as well. T he initialization
functionality of the flip-flops is illustrated in Table 9. T he macrocell sends its data to the output switch
matrix and the input switch matrix. The output switch matrix can route this data to an output if so desired.
The input switch matrix can send the signal back to the central switch matrix as feedback.
Note:
1. Transparent latch is unaffected by AR, AP
Table 9. Asynchronous Reset/Preset Operation
AR AP CLK/LE1Q+
0 0 X See Table 8
01X1
10X0
11X0
Power-Up
Reset
AP
D/L/T AR
Q
Individual
Reset
Product Term
a. Reset
Power-Up
Preset
AP
D/L/T AR
Q
Individual
Preset
Product Term
b. Preset
17466G-014 17466G-015
Figure 8. Asynchronous Mode Initialization Configurations
14 ispMACH 4A Family
Output Switch Matrix
The output switch matrix allows macrocells to be connected to any of sev eral I/O cells within a P AL bloc k.
This provides high f lexibility in determining pinout and allows design chang es to occur without effecting
pinout.
In ispMACH 4A devices with 2:1 Macrocell-I/O cell ratio, each PAL block has twice as many macrocells
as I/O cells. The ispMACH 4A output switch matrix allows for half of the macrocells to drive I/O cells
within a P AL block, in combinations according to Figure 9. Each I/O cell can choose from eight macrocells;
each macrocell has a c hoice of four I/O cells. The ispMACH 4A devices with 1:1 Macrocell-I/O cell ratio
allow each macrocell to drive one of eight I/O cells (Figure 9).
Table 10. Output Switch Matrix Combinations for ispMACH 4A Devices with 2:1 Macrocell-I/O Cell Ratio
Macrocell Routable to I/O Cells
M0, M1 I/O0, I/O5, I/O6, I/O7
M2, M3 I/O0, I/O1, I/O6, I/O7
M4, M5 I/O0, I/O1, I/O2, I/O7
M6, M7 I/O0, I/O1, I/O2, I/O3
M8, M9 I/O1, I/O2, I/O3, I/O4
M10, M11 I/O2, I/O3, I/O4, I/O5
M0
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Each macrocell can drive
one of 4 I/O cells in
ispMACH 4A devices with
2:1 macrocell-I/O cell ratio.
Each I/O cell can
choose one of 8
macrocells in
all ispMACH 4A
devices.
macrocells
MUX
I/O cell
M0
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
Each macrocell can drive
one of 8 I/O cells in
ispMACH 4A devices with 1:1
macrocell-I/O cell ratio except
M4A(3, 5)-32/32 devices.
M0
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
Each macrocell can drive
one of 8 I/O cells in
M4A(3, 5)-32/32 devices.
Figure 9. ispMACH 4A Output Switch Matrix
ispMACH 4A Family 15
M12, M13 I/O3, I/O4, I/O5, I/O6
M14, M15 I/O4, I/O5, I/O6, I/O7
I/O Cell Available Macrocells
I/O0 M0, M1, M2, M3, M4, M5, M6, M7
I/O1 M2, M3, M4, M5, M6, M7, M8, M9
I/O2 M4, M5, M6, M7, M8, M9, M10, M11
I/O3 M6, M7, M8, M9, M10, M11, M12, M13
I/O4 M8, M9, M10, M11, M12, M13, M14, M15
I/O5 M0, M1, M10, M11, M12, M13, M14, M15
I/O6 M0, M1, M2, M3, M12, M13, M14, M15
I/O7 M0, M1, M2, M3, M4, M5, M14, M15
Table 11. Output Switch Matrix Combinations for M4A3-256/160 and M4A3-256/192
Macrocell Routable to I/O Cells
M0 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M1 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M2 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M3 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M4 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M5 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M6 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M7 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M8 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
M9 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
M10 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
M11 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
M12 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
M13 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
M14 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
M15 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
I/O Cell Available Macrocells
I/O0 M0 M1 M2 M3 M4 M5 M6 M7
I/O1 M0 M1 M2 M3 M4 M5 M6 M7
I/O2 M0 M1 M2 M3 M4 M5 M6 M7
I/O3 M0 M1 M2 M3 M4 M5 M6 M7
I/O4 M0 M1 M2 M3 M4 M5 M6 M7
I/O5 M0 M1 M2 M3 M4 M5 M6 M7
I/O6 M0 M1 M2 M3 M4 M5 M6 M7
I/O7 M0 M1 M2 M3 M4 M5 M6 M7
Table 10. Output Switch Matrix Combinations for ispMACH 4A Devices with 2:1 Macrocell-I/O Cell Ratio
Macrocell Routable to I/O Cells
16 ispMACH 4A Family
Table 13. Output Switch Matrix Combinations for M4A3-64/64
I/O8 M8 M9 M10 M11 M12 M13 M14 M15
I/O9 M8 M9 M10 M11 M12 M13 M14 M15
I/O10 M8 M9 M10 M11 M12 M13 M14 M15
I/O11 M8 M9 M10 M11 M12 M13 M14 M15
I/O12 M8 M9 M10 M11 M12 M13 M14 M15
I/O13 M8 M9 M10 M11 M12 M13 M14 M15
I/O14 M8 M9 M10 M11 M12 M13 M14 M15
I/O15 M8 M9 M10 M11 M12 M13 M14 M15
Table 12. Output Switch Matrix Combinations for M4A(3,5)-32/32
Macrocell Routable to I/O Cells
M0, M1, M2, M3, M4, M5, M6, M7 I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7
M8, M9, M10, M11, M12, M13, M14, M15 I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15
I/O Cell Available Macrocells
I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7 M0, M1, M2, M3, M4, M5, M6, M7
I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15 M8, M9, M10, M11, M12, M13, M14, M15
Macrocell Routable to I/O Cells
MO, M1 I/O0, I/O1, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15
M2, M3 I/O0, I/O1, I/O2, I/O3, I/O12, I/O13, I/O14, I/O15
M4, M5 I/O0, I/O1, I/O2,I/O3, I/O4,I/O5, I/O14, I/O15
M6, M7 I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7
M8, M9 I/O2, I/O3, I/O4, I/O5, I/O6, I/O7, I/O8, I/O9
M10, M11 I/O4, I/O5, I/O6, I/O7, I/O8, I/O9, I/O10, I/O11
M12, M13 I/O6, I/O7, I/O8, I/O9, I/O10, I/O11, I/O12, I/O13
M14, M15 I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15
I/O Cell Available Macrocells
I/O0, I/O1 M0, M1, M2, M3, M4, M5, M6, M7
I/O2, I/O3 M2, M3, M4, M5, M6, M7, M8, M9
I/O4, I/O5 M4, M5, M6, M7, M8, M9, M10, M11
I/O6, I/O7 M6, M7, M8, M9, M10, M11, M12, M13
I/O8, I/O9 M8, M9, M10, M11, M12, M13, M14, M15
I/O10, I/O11 M0, M1, M10, M11, M12, M13, M14, M15
I/O12, I/O13 M0, M1, M2, M3, M12, M13, M14, M15
I/O14, I/O15 M0, M1, M2, M3, M4, M5, M14, M15
Table 11. Output Switch Matrix Combinations for M4A3-256/160 and M4A3-256/192
Macrocell Routable to I/O Cells
ispMACH 4A Family 17
I/O Cell
The I/O cell (Figures 10 and 11) simply consists of a programmable output enable, a feedback path, and
flip-flop (except ispMACH 4A devices with 1:1 macrocell-I/O cell ratio). An individual output enable
product term is provided for each I/O cell. The feedback signal drives the input switch matrix.
The I/O cell (Figure 10) contains a flip-flop , whic h provides the capability for storing the input in a D-type
register or latch. The clock can be any of the PAL block clocks. Both the direct and registered versions of
the input are sent to the input switch matrix. This allows for suc h functions as “time-domain-m ultiplex ed”
data comparison, where the first data value is stored, and then the second data value is put on the I/O pin
and compared with the previous stored value.
Note that the flip-flop used in the ispMA CH 4A I/O cell is independent of the flip-flops in the macrocells .
It powers up to a logic low.
Zero-Hold-Time Input Register
The ispMA CH 4A devices hav e a zero-hold-time (ZHT) fuse which controls the time dela y associated with
loading data into all I/O cell registers and latches . When programmed, the ZHT fuse increases the data path
setup delays to input storage elements, matching equivalent delays in the clock path. When the fuse is erased,
the setup time to the input storage element is minimized. T his feature facilitates doing worst-case designs
for which data is loaded from sources which have low (or zero) minimum output propagation delays from
clock edges.
D/L
Q
Block CLK3
Block CLK2
Block CLK1
Block CLK0
To Input
Switch
Matrix
Individual
Output Enable
Product Term
From Output
Switch Matrix
17466G-017 17466G-018
Figure 10. I/O Cell for ispMACH 4A Devices with 2:1
Macrocell-I/O Cell Ratio Figure 11. I/O Cell for ispMACH 4A Devices with 1:1
Macrocell-I/O Cell Ratio
To Input
Switch
Matrix
Individual
Output Enable
Product Term
From Output
Switch Matrix
Power-up reset
18 ispMACH 4A Family
Input Switch Matrix
The input switch matrix (Figures 12 and 13) optimizes routing of inputs to the central switch matrix.
Without the input switch matrix, each input and feedback signal has only one way to enter the central switch
matrix. The input switch matrix provides additional ways for these signals to enter the central switch matrix.
To Central Switch Matrix
From Macrocell 2
From Input Cell
Direct
From Macrocell 1
Registered/Latched
17466G-002 17466G-003
Figure 12. ispMACH 4A with 2:1 Macrocell-I/O Cell
Ratio - Input Switch Matrix Figure 13. ispMACH 4A with 1:1 Macrocell-I/O Cell
Ratio - Input Switch Matrix
To Central Switch Matrix
From Macrocell
From I/O Pin
ispMACH 4A Family 19
PAL Block Clock Generation
Each ispMACH 4A device has four clock pins that can also be used as inputs. These pins drive a clock
generator in each PAL block (Figure 14). The clock generator provides four clock signals that can be used
anywhere in the PAL block. These four PAL block clock signals can consist of a large number of
combinations of the true and complement edg es of the global clock signals. Table 14 lists the possible
combinations.
1. M4A(3,5)-32/32 and M4A(3,5)-64/32 have only two clock pins, GCLK0 and GCLK1. GCLK2 is tied to GCLK0, and GCLK3 is tied to GCLK1.
Note:
1. Values in parentheses are for the M4A(3,5)-32/32 and M4A(3,5)-64/32.
This feature provides high f lexibility for partitioning state machines and dual-phase clocks. It also allows
latches to be driven with either polarity of latch enable, and in a master-slave configuration.
Table 14. PAL Block Clock Combinations1
Block CLK0 Block CLK1 Block CLK2 Block CLK3
GCLK0
GCLK1
GCLK0
GCLK1
X
X
X
X
GCLK1
GCLK1
GCLK0
GCLK0
X
X
X
X
X
X
X
X
GCLK2 (GCLK0)
GCLK3 (GCLK1)
GCLK2 (GCLK0)
GCLK3 (GCLK1)
X
X
X
X
GCLK3 (GCLK1)
GCLK3 (GCLK1)
GCLK2 (GCLK0)
GCLK2 (GCLK0)
GCLK0
GCLK1
GCLK2
GCLK3
Block CLK0
(GCLK0 or GCLK1)
Block CLK1
(GCLK1 or GCLK0)
Block CLK2
(GCLK2 or GCLK3)
Block CLK3
(GCLK3 or GCLK2)
17466G-004
Figure 14. PAL Block Clock Generator 1
20 ispMACH 4A Family
ispMACH 4A TIMING MODEL
The primary focus of the ispMACH 4A timing model is to accurately represent the timing in a ispMACH
4A device, and at the same time, be easy to understand. T his model accurately describes all combinatorial
and registered paths through the device, making a distinction between internal feedback and external
feedback. A signal uses internal feedback when it is fed back into the switc h matrix or block without ha ving
to g o through the output buffer. The input register specifications are also reported as internal feedback.
When a signal is fed back into the switch matrix after having gone through the output buffer, it is using
external feedback.
The parameter, tBUF, is defined as the time it takes to go from feedback through the output buffer to the
I/O pad. If a signal goes to the internal feedback rather than to the I/O pad, the parameter designator is
followed by an “i”. By adding tBUF to this internal parameter, the external parameter is derived. For
example, tPD = tPDi + tBUF. A diagram representing the modularized ispMA CH 4A timing model is shown
in Figure 15. R efer to the application note entitled MACH 4 Timing and High Speed Design for a more detailed
discussion about the timing parameters.
SPEEDLOCKING FOR GUARANTEED FIXED TIMING
The ispMA CH 4A architecture allo ws allocation of up to 20 product terms to an individual macrocell with
the assistance of an XOR gate without incurring additional timing delays.
The design of the switch matrix and PAL blocks guarantee a fixed pin-to-pin delay that is independent of
the logic required by the design. Other competitive CPLDs incur serious timing delays as product terms
expand beyond their typical 4 or 5 product ter m limits. Speed and SpeedLocking combine to give designs
easy access to the performance required in today’s designs.
(External Feedback)
(Internal Feedback)
INPUT REG/
INPUT LATCH
tSIRS
tHIRS
tSIL
tHIL
tSIRZ
tHIRZ
tSILZ
tHILZ
tPDILi
tICOSi
tIGOSi
tPDILZi
Q
tSS(T)
tSA(T)
tH(S/A)
tS(S/A)L
tH(S/A)L
tSRR
tPDi
tPDLi
tCO(S/A)i
tGO(S/A)i
tSRi
COMB/DFF/TFF/
LATCH/SR*/JK*
S/R
IN
BLK CLK
OUT
tPL
tBUF
tEA
tER
tSLW
Q
Central
Switch
Matrix
*emulated
17466G-025
Figure 15. ispMACH 4A Timing Model
ispMACH 4A Family 21
IEEE 1149.1-COMPLIANT BOUNDARY SCAN TESTABILITY
All ispMACH 4A devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This
allows functional testing of the circuit board on whic h the device is mounted through a serial scan path that
can access all critical logic nodes. Inter nal registers are linked internally, allowing test data to be shifted in
and loaded directly onto test nodes, or test node data to be captured and shifted out for verification. In
addition, these devices can be linked into a board-level serial scan path for more complete board-level
testing.
IEEE 1149.1-COMPLIANT IN-SYSTEM PROGRAMMING
Prog ramming devices in-system provides a number of significant benefits including: rapid prototyping,
lower inventory levels, higher quality, and the ability to make in-field modifications. All ispMACH 4A
devices provide In-System Programming (ISP) capability through their Boundary ScanTest Access Por ts.
This capability has been implemented in a manner that ensures that the port remains compliant to the IEEE
1149.1 standard. By using IEEE 1149.1 as the communication interface through which ISP is achieved,
customers get the benefit of a standard, well-defined interface.
ispMACH 4A devices can be programmed across the commercial temperature and voltage range. The PC-
based ispVM™ software facilitates in-system programming of ispMACH 4A devices. ispVM takes the
JEDEC file output produced by the design implementation software, along with information about the
JTAG chain, and creates a set of vectors that are used to drive the JTAG chain. ispVM software can use
these vectors to dri v e a JTAG c hain via the parallel port of a PC. Alternativ ely, ispVM software can output
files in formats understood by common automated test equipment. This equpment can then be used to
prog ram ispMACH 4A devices during the testing of a circuit board.
PCI COMPLIANT
ispMACH 4A devices in the -5/-55/-6/-65/-7/-10/-12 speed grades are compliant with the PCI Local Bus
Specification version 2.1, published by the PCI Special Interest Group (SIG). T he 5-V devices are fully PCI-
compliant. The 3.3-V devices are mostly compliant but do not meet the PCI condition to clamp the inputs
as they rise above VCC because of their 5-V input tolerant feature.
SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS
Both the 3.3-V and 5-V VCC ispMACH 4A devices are safe for mixed supply voltage system designs. The
5-V devices will not overdrive 3.3-V devices above the output voltag e of 3.3 V, while they accept inputs
from other 3.3-V devices . The 3.3-V device will accept inputs up to 5.5 V. Both the 5-V and 3.3-V v ersions
have the same high-speed performance and provide easy-to-use mixed-voltage design capability.
PULL UP OR BUS-FRIENDLY INPUTS AND I/Os
All ispMA CH 4A devices ha v e inputs and I/Os which feature the Bus-F riendly circuitry incorporating two
inver ters in series which loop back to the input. This double inversion weakly holds the input at its last
driven logic state. While it is good design practice to tie unused pins to a known state, the Bus-Friendly input
structure pulls pins away from the input threshold v oltage where noise can cause high-frequency switching .
At power-up, the Bus-Friendly latches are reset to a logic level “1.” For the circuit diagram, please refer to
the document entitled MACH Endurance Characteristics on the Lattice Data Book CD-ROM or Lattice web
site.
All ispMACH 4A devices have a programmable bit that configures all inputs and I/Os with either pull-up
or Bus-Friendly characteristics. If the device is configured in pull-up mode, all inputs and I/O pins are
22 ispMACH 4A Family
weakly pulled up. For the circuit diagram, please refer to the document entitled MACH Endurance
Characteristics on the Lattice Data Book CD-ROM or Lattice web site.
POWER MANAGEMENT
Each individual PAL block in ispMACH 4A devices features a programmable low-power mode, which
results in power savings of up to 50%. The signal speed paths in the low-power PAL block will be slower
than those in the non-low-power PAL block. T his feature allows speed critical paths to r un at maximum
frequency while the rest of the signal paths operate in the low-power mode.
PROGRAMMABLE SLEW RATE
Each ispMA CH 4A device I/O has an indi vidually programmable output slew rate control bit. Each output
can be individually configured for the higher speed transition (3 V/ns) or for the lower noise transition (1
V/ns). For high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer
reflections, less noise, and keep ground bounce to a minimum. For designs with shor t traces or well
terminated lines, the fast slew rate can be used to achieve the highest speed. The slew rate is adjusted
independent of power.
POWER-UP RESET/SET
All flip-flops power up to a kno wn state for predictable system initialization. If a macrocell is configured to
SET on a signal from the control generator, then that macrocell will be SET during device power-up. If a
macrocell is configured to RESET on a signal from the control generator or is not configured for set/reset,
then that macrocell will RESET on power-up. To guarantee initialization values, the VCC rise must be
monotonic, and the clock must be inactive until the reset delay time has elapsed.
SECURITY BIT
A prog rammable security bit is provided on the ispMACH 4A devices as a deter rent to unauthorized
copying of the ar ray configuration patter ns. Once programmed, this bit defeats readback of the
prog rammed pattern by a device prog rammer, securing proprietary designs from competitors.
Programming and verification are also defeated by the security bit. The bit can only be reset by erasing the
entire device.
HOT SOCKETING
ispMACH 4A devices are well-suited for those applications that require hot socketing capability. Hot
sock eting a device requires that the device, when pow ered down, can tolerate activ e signals on the I/Os and
inputs without being damaged. Additionally, it requires that the effects of the powered-down MACH
devices be minimal on active signals.