MTP3055VL Preferred Device Power MOSFET 12 Amps, 60 Volts, Logic Level N-Channel TO-220 http://onsemi.com This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature 12 AMPERES 60 VOLTS RDS(on) = 180 m N-Channel D MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-Source Voltage VDSS 60 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDGR 60 Vdc Gate-Source Voltage - Continuous - Single Pulse (tp 50 s) VGS VGSM 15 20 Vdc Vpk ID ID 12 8.0 42 Adc PD 48 0.32 Watts W/C TJ, Tstg -55 to 175 C 72 mJ Rating Drain Current - Continuous @ 25C Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) Total Power Dissipation @ 25C Derate above 25C Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 12 Apk, L = 1.0 mH, RG =25 ) Thermal Resistance - Junction to Case - Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds IDM EAS RJC RJA 3.13 62.5 TL 260 G S MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain 4 Apk TO-220AB CASE 221A STYLE 5 1 2 3 MTP3055VL LLYWW 1 Gate C/W C 3 Source 2 Drain MTP3055VL LL Y WW = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device MTP3055VL Package Shipping TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. (c) Semiconductor Components Industries, LLC, 2006 August, 2006 - Rev. 4 1 Publication Order Number: MTP3055VL/D MTP3055VL ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 62 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 1.0 - 1.6 3.0 2.0 - Vdc mV/C - 0.12 0.18 Ohm - - 1.6 - 2.6 2.5 gFS 5.0 8.8 - mhos Ciss - 410 570 pF Coss - 114 160 Crss - 21 40 td(on) - 9.0 20 tr - 85 190 td(off) - 14 30 tf - 43 90 QT - 8.1 10 Q1 - 1.8 - Q2 - 4.2 - Q3 - 3.8 - - - 0.97 0.86 1.3 - trr - 55.7 - ta - 37 - tb - 18.7 - QRR - 0.116 - - 3.5 4.5 - - 7.5 - OFF CHARACTERISTICS V(BR)DSS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0) IGSS Adc ON CHARACTERISTICS (Note 1) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 5.0 Vdc, ID = 6.0 Adc) RDS(on) Drain-Source On-Voltage (VGS = 5.0 Vdc) (ID = 12 Adc) (ID = 6.0 Adc, TJ = 150C) VDS(on) Forward Transconductance (VDS = 8.0 Vdc, ID = 6.0 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2) Turn-On Delay Time (VDD = 30 Vdc, ID = 12 Adc, VGS = 5.0 Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (See Figure 8) (VDS = 48 Vdc, ID = 12 Adc, VGS = 5.0 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 1) (IS = 12 Adc, VGS = 0 Vdc) (IS = 12 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (See Figure 14) (IS = 12 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 2 nH nH MTP3055VL TYPICAL ELECTRICAL CHARACTERISTICS 24 4.5 V 16 I D , DRAIN CURRENT (AMPS) I D , DRAIN CURRENT (AMPS) 20 4V 12 3.5 V 8 3V 4 0 0.32 1 2 4 3 20 16 12 8 2.5 3.0 3.5 4.0 4.5 5.5 5.0 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 0.20 TJ = 100C 0.14 25C -55C 0.08 0 4 20 8 12 16 ID, DRAIN CURRENT (AMPS) 24 TJ = 25C 0.22 0.17 5V 0.12 0.07 VGS = 10 V 0 4 100 I DSS , LEAKAGE (nA) 1.5 1.0 0.5 25 50 75 100 125 150 20 24 VGS = 0 V VGS = 5 V ID = 6 A 0 8 12 16 ID, DRAIN CURRENT (AMPS) Figure 4. On-Resistance versus Drain Current and Gate Voltage 2.0 -25 6.0 0.27 Figure 3. On-Resistance versus Drain Current and Temperature RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 100C VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS = 5 V 0 -50 TJ = -55C 25C 0 2.0 5 0.26 0.02 VDS 10 V 4 2.5 V R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0 R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 24 5V VGS = 10 V TJ = 25C 100C 1.0 0.1 175 TJ = 125C 10 TJ, JUNCTION TEMPERATURE (C) 30 10 20 40 50 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage 0 http://onsemi.com 3 60 MTP3055VL POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 1400 1200 C, CAPACITANCE (pF) VGS = 0 V VDS = 0 V TJ = 25C Ciss 1000 800 600 Ciss Crss 400 Coss 200 0 Crss 10 5 0 VGS 5 10 15 20 25 VDS GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation http://onsemi.com 4 60 QT 50 4 40 VGS 30 Q2 Q1 2 0 20 ID = 12 A TJ = 25C 0 Q3 2 VDS 4 6 8 10 0 10 1000 VDD = 30 V ID = 12 A VGS = 5 V TJ = 25C t, TIME (ns) 6 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) MTP3055VL tr 100 tf td(off) 10 1 td(on) 1 10 QT, TOTAL CHARGE (nC) RG, GATE RESISTANCE (OHMS) Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance 100 DRAIN-TO-SOURCE DIODE CHARACTERISTICS 12 I S , SOURCE CURRENT (AMPS) 10 VGS = 0 V TJ = 25C 8 6 4 2 0 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.0 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. http://onsemi.com 5 MTP3055VL SAFE OPERATING AREA 75 VGS = 5 V SINGLE PULSE TC = 25C 10 s 10 100 s 1 ms 10 ms 1.0 dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.1 1.0 ID = 12 A EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) I D , DRAIN CURRENT (AMPS) 100 50 25 0 100 10 25 50 75 100 125 150 175 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1.0 D = 0.5 0.2 0.1 0.1 0.05 P(pk) 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 t1 t2 DUTY CYCLE, D = t1/t2 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01 Figure 13. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 6 RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+00 1.0E+01 MTP3055VL PACKAGE DIMENSIONS TO-220 THREE-LEAD TO-220AB CASE 221A-09 ISSUE AA SEATING PLANE -T- B F T C S 4 DIM A B C D F G H J K L N Q R S T U V Z A Q 1 2 3 U H K Z L R V J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. G D N INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 --- --- 0.080 STYLE 5: PIN 1. 2. 3. 4. MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 --- --- 2.04 GATE DRAIN SOURCE DRAIN ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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