M36W0R6040T7ZAQE - MICRON TECHNOLOGY

April 2009 209220 - Rev 3 1/24

M36W0Rx0x0x7

32- or 64-Mbit (2 or 4 Mbits x 16, multiple bank, burst) flash memory

and 8-Mbit (512 Kbit x16) or 16-Mbit (1 Mbit x 16) PSRAM MCP

Features

Multichip package

– 1 die of 32 or 64 Mbits (2 or 4 Mbits x 16)

flash memory

– 1 die of 8 Mbits (512 Kbits x 16) or 16 Mbits

(1 Mbit x 16) PSRAM

Supply voltage

–V

DDF = VDDQ = VDDP = 1.7 V to 1.95 V

Electronic signature

– Manufacturer code: 20h

– Device codes (32-Mbit flash device)

Top - M36W0R5030T7 and

M36W0R5040T7: 8814h

Bottom - M36W0R5030B7 and

M36W0R5040B7: 8815h

– Device codes (8-Mbit flash devices)

Top - M36W0R6040T7: 8810h

Bottom - M36W0R6040B7: 8811h

Density and Packaging:

– RoHS compliant

Flash memory

Programming time

–10μs by word typical for fast factory

program

– Double/quadruple word program option

Memory blocks

– Multiple bank memory array: 4-Mbit banks

– Parameter blocks (top or bottom location)

Synchronous/asynchronous read

– Synchronous burst read mode: 66 MHz

– Asynchronous page read mode

– Random access times: 70 ns

Synchronous burst read suspend

Dual operations

– Program erase in 1 bank, read in others

– No delay between read and write

operations

Block locking

– All blocks locked at power-up

– Any combination of blocks can be locked

–WP

for block lock-down

Security

– 128-bit user programmable OTP cells

– 64-bit unique device number

Common flash interface (CFI)

100,000 program/erase cycles per block

PSRAM

Access time: 60 ns

Low standby current: 70 μA

Deep power-down current: 10 μA

Table 1. Device summary

M36W0Rx0x0x7

M36W0R5030T7 M36W0R5030B7

M36W0R5040T7 M36W0R5040B7

M36W0R6040T7 M36W0R6040B7

FBGA

Stacked TFBGA88 (ZAQ)

8 x 10 mm

www.numonyx.com

Contents M36W0Rx0x0x7
2/24  
Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal descriptions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1 Address inputs (A0-A21)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  10
2 Data input/output (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  10
3 Flash Chip Enable (EF)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  10
4 Flash Output Enable (GF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  10
5 Flash Write Enable (WF)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  10
6 Flash Write Protect (WPF)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11
7 Flash Reset (RPF)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11
8 Flash Latch Enable (LF)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11
9 Flash Clock (KF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11
10 Flash Wait (WAITF)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11
11 PSRAM Chip Enable (EP)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11
12 PSRAM Output Enable (GP)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
13 PSRAM Write Enable (WP)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
14 PSRAM Upper Byte Enable (UBP)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
15 PSRAM Lower Byte Enable (LBP)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
16 VDDF supply voltage  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
17 VDDP supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
18 VDDQ supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
19 VPPF program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13
20 VSS ground  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13
Functional description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DC and AC parameters  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package mechanical  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Part numbering  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

M36W0Rx0x0x7 Contents

3/24

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

List of tables M36W0Rx0x0x7

4/24

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 3. Main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 5. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 6. Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 7. Stacked TFBGA88 8 x 10 mm - 8 x 10 ball array, 0.8 mm pitch, package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 8. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 9. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

M36W0Rx0x0x7 List of figures

5/24

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2. TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 3. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 4. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 5. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 6. Stacked TFBGA88 8 x 10 mm - 8 x 10 active ball array, 0.8 mm pitch, package outline . . 20

Description M36W0Rx0x0x7

6/24

1 Description

The M36W0R5030x7, M36W0R5040x7, and M36W0R6040x7 combine two memory

devices in a multichip package:

a 32- or 64-Mbit, multiple bank flash memory, the M58WR032KT/B or

M58WR064KT/B, respectively.

a 8- or 16-Mbit PSRAM, the M69KB012AB or M69KB024AB, respectively.

Recommended operating conditions do not allow more than one memory to be active at the

same time.

The purpose of this document is to describe how the two memory components operate with

respect to each other. It must be read in conjunction with the datasheets of the

M58WR032KT/B or M58WR064KT/B, and M69KB012AB or M69KB024AB, respectively,

which fully detail all the specifications required to operate the flash memory and PSRAM

components.

The memory is offered in a stacked TFBGA88 (8 x 10 mm, 8 x 10 ball array, 0.8 mm pitch)

package, and is supplied with all the bits erased (set to ‘1’).

M36W0Rx0x0x7 Description

7/24

Figure 1. Logic diagram

1. Amax is equal to A20 in the M36W0R50x0x7 and A21 in the M36W0R6040x7.

Ai11080f

A0-Amax

(1)

DQ0-DQ15

M36W0R5030x7

M36W0R5040x7

M36W0R6040x7

VSS

DDF

PPF

DDP

WAIT

DDQ

Description M36W0Rx0x0x7

8/24

Table 2. Signal names(1)

1. A0-A18 (in the case of an 8-Mbit PSRAM) or A0-A19 (in the case of a 16-Mbit PSRAM) are common to the

flash memory and the PSRAM.

Name Function

A0-A18 Common address inputs

DQ0-DQ15 Common data input/output

VDDF Flash Memory power supply

VDDQ Common flash and PSRAM power supply for I/O buffers

VPPF Common flash optional supply voltage for fast program and erase

VSS Ground

VCCP PSRAM power supply

NC Not connected internally

DU Do not use as internally connected

Flash memory control functions

A19-A20, A20, or

A20-A21(2)

2. A19-A20 for the M36W0R5030x7, A20 for the M36W0R5040x7, and A20-A21 for the M36W0R6040x7.

Address inputs for the flash memory only

EFChip Enable input

GFOutput Enable input

LFLatch Enable input

KFBurst Clock

WAITFWait data in burst mode

WFWrite Enable input

RPFReset input

WPFWrite Protect input

PSRAM control functions

EPChip Enable input

GPOutput Enable input

WPWrite Enable input

UBPUpper Byte Enable input

LBPLower Byte Enable input

M36W0Rx0x0x7 Description

9/24

Figure 2. TFBGA connections (top view through package)

87654321

B A21

A4 A11

DU DU

VSS

A19A18

A5 A12

VSS

NCLBP

A3 A13

VPPF

NCA17

A10A20

A2 A15

WPF

NCA7

A14A8

A1 A16

RPF

UBP

WAIT

DQ13

A0 DQ5

DQ10

DQ2DQ8

DQ7DQ14

GPDQ12

DQ3

DQ1DQ0

DQ15DQ6DQ4

DQ11

DQ9GF

VDDQ

EFNC

VCCP

VSS

VSS VSS

VSS

VDDF

VDDQ

VSS

DU DU

AI08525d

VDDF NC

WPEP

NC NC NC

VDDQ

Signal descriptions M36W0Rx0x0x7

10/24

2 Signal descriptions

See Figure 1: Logic diagram and Table 2: Signal names for a brief overview of the signals

connected to this device.

2.1 Address inputs (A0-A21)

Addresses A0-A18 are common inputs for the flash memory and PSRAM components. The

address inputs select the cells in the memory array to access during bus read operations.

During bus write operations they control the commands sent to the command interface of

the flash memory program/erase controller, and they select the cells to access in the

PSRAM.

Addresses A19-A20 (for the M36W0R5030x7), A20 (for the M36W0R5040x7), and A20-A21

(for the M36W0R6040x7) are inputs for the flash memory component only. The flash

memory is accessed through the Chip Enable signals (EF) and through the Write Enable

(WF) signal.

2.2 Data input/output (DQ0-DQ15)

For the flash memory, the data I/O outputs the data stored at the selected address during a

bus read operation or inputs a command or the data to be programmed during a write bus

operation.

For the PSRAM, the upper byte data inputs/outputs carry the data to or from the upper part

of the selected address during a write or read operation, when upper byte enable (UBP) is

driven Low.

Likewise, the lower byte data inputs/outputs carry the data to or from the lower part of the

selected address during a write or read operation, when Lower Byte Enable (LBP) is driven

Low.

2.3 Flash Chip Enable (EF)

The Chip Enable inputs activate the memory control logics, input buffers, decoders and

sense amplifiers. When Chip Enable is Low, VIL, and Reset is High, VIH, the device is in

active mode. When Chip Enable is at VIH the flash memory is deselected, the outputs are

high impedance and the power consumption is reduced to the standby level.

2.4 Flash Output Enable (GF)

The Output Enable pins control data outputs during flash memory bus read operations.

2.5 Flash Write Enable (WF)

The Write Enable controls the bus write operation of the flash memories’ command

interface. The data and address inputs are latched on the rising edge of Chip Enable or

Write Enable, whichever occurs first.

M36W0Rx0x0x7 Signal descriptions

11/24

2.6 Flash Write Protect (WPF)

Write Protect is an input that gives an additional hardware protection for each block. When

Write Protect is Low, VIL, lock-down is enabled and the protection status of the locked-down

blocks cannot be changed. When Write Protect is at High, VIH, lock-down is disabled and

the locked-down blocks can be locked or unlocked (refer to the lock status table in

M58WR032KT/B and M58WR064KT/B datasheet).

2.7 Flash Reset (RPF)

The Reset input provides a hardware reset of the memory. When Reset is at VIL, the

memory is in reset mode: the outputs are high impedance and the current consumption is

reduced to the Reset supply current IDD2. Refer to the M58WR032KT/B or M58WR064KT/B

datasheet for the value of IDD2. After Reset all blocks are in the locked state and the

configuration register is reset. When Reset is at VIH, the device is in normal operation. Upon

exiting reset mode the device enters asynchronous read mode, but a negative transition of

Chip Enable or Latch Enable is required to ensure valid data outputs.

The Reset pin can be interfaced with 3 V logic without any additional circuitry. It can be tied

to VRPH (refer to the M58WR032KT/B or M58WR064KT/B datasheet).

2.8 Flash Latch Enable (LF)

Latch Enable latches the address bits on its rising edge. The address latch is transparent

when Latch Enable is Low, VIL, and it is inhibited when Latch Enable is High, VIH. Latch

Enable can be kept Low (also at board level) when the Latch Enable function is not required

or supported.

2.9 Flash Clock (KF)

The Clock input synchronizes the flash memory to the microcontroller during synchronous

read operations; the address is latched on a Clock edge (rising or falling, according to the

configuration settings) when Latch Enable is at VIL. Clock is ‘don't care’ during

asynchronous read and in write operations.

2.10 Flash Wait (WAITF)

WAIT is a flash output signal used during synchronous read to indicate whether the data on

the output bus are valid. This output is high impedance when flash Chip Enable is at VIH or

flash Reset is at VIL. It can be configured to be active during the wait cycle or one clock

cycle in advance. The WAITF signal is not gated by Output Enable.

2.11 PSRAM Chip Enable (EP)

When asserted (Low), the Chip Enable, EP, activates the memory state machine, address

buffers and decoders, allowing read and write operations to be performed. When de-

asserted (High), all other pins are ignored and the device is automatically put in low-power

standby mode.

Signal descriptions M36W0Rx0x0x7

12/24

2.12 PSRAM Output Enable (GP)

The Output Enable, GP, provides a high speed tri-state control, allowing fast read/write

cycles to be achieved with the common I/O data bus.

2.13 PSRAM Write Enable (WP)

The Write Enable, WP, controls the bus write operation of the memory.

2.14 PSRAM Upper Byte Enable (UBP)

The Upper Byte Enable, UBP, gates the data on the upper byte data inputs/outputs (DQ8-

DQ15) to or from the upper part of the selected address during a write or read operation.

2.15 PSRAM Lower Byte Enable (LBP)

The Lower Byte Enable, LBP, gates the data on the lower byte data inputs/outputs (DQ0-

DQ7) to or from the lower part of the selected address during a write or read operation.

2.16 VDDF supply voltage

VDDF provides the power supply to the internal core of the flash memory component. It is the

main power supplies for all flash memory operations (read, program, and erase).

2.17 VDDP supply voltage

The VDDP supply voltage supplies the power for all operations (read or write) and for driving

the refresh logic, even when the device is not being accessed.

2.18 VDDQ supply voltage

VDDQ provides the power supply for the flash memory and PSRAM I/O pins. This allows all

outputs to be powered independently of the flash memory and PSRAM core power supplies:

VDDF and VDDP, respectively.

M36W0Rx0x0x7 Signal descriptions

13/24

2.19 VPPF program supply voltage

VPPF is both a flash memory control input and a flash memory power supply pin. The two

functions are selected by the voltage range applied to the pin.

If VPPF is kept in a low voltage range (0 V to VDDQ) VPPF is seen as a control input. In this

case a voltage lower than VPPLKF provides absolute protection against program or erase,

while VPPF > VPP1F enables these functions (see the M58WR032KT/B and

M58WR064KT/B datasheet for the relevant values). VPPF is only sampled at the beginning

of a program or erase; a change in its value after the operation has started does not have

any effect and program or erase operations continue.

If VPPF is in the range of VPPHF it acts as a power supply pin. In this condition VPPF must be

stable until the program/erase algorithm is completed.

2.20 VSS ground

VSS is the common ground reference for all voltage measurements in the flash (core and I/O

buffers) and PSRAM chips.

Note: Each flash memory device in a system should have its supply voltage (VDDF) and the

program supply voltage VPPF decoupled with a 0.1 µF ceramic capacitor close to the pin

(high-frequency, inherently-low inductance capacitors should be as close as possible to the

package). See Figure 5: AC measurement load circuit. The PCB track widths should be

sufficient to carry the required VPPF program and erase currents.

Functional description M36W0Rx0x0x7

14/24

3 Functional description

The flash memory and PSRAM components have separate power supplies but share the

same grounds. They are distinguished by two Chip Enable inputs: EF for the flash memory

and EP for the PSRAM.

Recommended operating conditions do not allow more than one device to be active at a

time. The most common example is simultaneous read operations on the flash memory and

the PSRAM which would result in a data bus contention. Therefore, it is recommended to

put the other devices in the high impedance state when reading the selected device.

M36W0Rx0x0x7 Functional description

15/24

Figure 3. Functional block diagram

1. Address inputs corresponding to the M36W0R5030x7 devices.

2. Address inputs corresponding to the M36W0R5040x7 devices.

3. Address inputs corresponding to the M36W0R6040x7 devices.

AI08449e

DQ0-DQ15

DDF

A0-A18

(1)

or A0-A19

(2)(3)

A19-20

(1)

A20

(2)

or A20-A21

(3)

8 or 16-Mbit

PSRAM

WAIT

32 or 64-Mbit

flash

memory

DDP

PPF

DDQ

Functional description M36W0Rx0x0x7

16/24

Table 3. Main operating modes(1)

Operation EFGFWFLRPFWAIT(2) EPGPWPUBPLBPDQ15-DQ0

Flash read VIL VIL VIH VIL(3) VIH

PSRAM must be disabled

Flash data out

Flash write VIL VIH VIL VIL(3) VIH Flash data in

Flash address

latch VIL XV

IH VIL VIH

Flash data out or Hi-

Z(4)

Flash output

disable VIL VIH VIH XV

IH Flash Hi-Z

Flash standby VIH XX X V

IH Hi-Z Any PSRAM mode is

allowed

Flash Hi-Z

Flash reset X X X X VIL Hi-Z Flash Hi-Z

PSRAM read Flash memory must be disabled VIL VIL VIH VIL VIL PSRAM data out

PSRAM write VIL XV

IL VIL VIL PSRAM data in

PSRAM standby

Any flash mode is allowed.

VIH X X X X PSRAM Hi-Z

PSRAM deep

power-down VIH X X X X PSRAM Hi-Z

1. X = ‘don't care’.

2. WAIT signal polarity is configured using the Set Configuration Register command. Refer to M58WR032KT/B and

M58WR064KT/B datasheet for details.

3. L can be tied to VIH if the valid address has been previously latched.

4. Depends on GF.

M36W0Rx0x0x7 Maximum ratings

17/24

4 Maximum ratings

Stressing the device above the rating listed in Table 4: Absolute maximum ratings may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the operating sections of

this specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

Table 4. Absolute maximum ratings

Symbol Parameter

Value

Unit

Min Max

TAAmbient operating temperature –40 85 °C

TBIAS Temperature under bias –40 125 °C

TSTG Storage temperature –55 125 °C

VIO Input or output voltage –0.5 3.3 V

VDDF Flash memory core supply voltage –0.2 2.45 V

VDDQ Input/output supply voltage –0.2 2.45 V

VDDP PSRAM supply voltage –0.5 3.3 V

VPPF Flash memory program voltage –0.2 10 V

IOOutput short circuit current 100 mA

tVPPFH Time for VPPF at VPPFH 100 hours

DC and AC parameters M36W0Rx0x0x7

18/24

5 DC and AC parameters

This section summarizes the operating measurement conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC characteristics tables in this

section are derived from tests performed under the measurement conditions summarized in

Ta bl e 5 . Designers should check that the operating conditions in their circuit match the

operating conditions when relying on the quoted parameters.

Figure 4. AC measurement I/O waveform

Table 5. Operating and AC measurement conditions

Parameter

Flash memory PSRAM

Unit

Min Max Min Max

VDDF supply voltage 1.7 1.95 – – V

VDDP supply voltage – – 1.7 1.95 V

VDDQ supply voltage 1.7 1.95 – – V

VPPF supply voltage (factory environment) 8.5 9.5 – – V

VPPF supply voltage (application environment) –0.4 VDDQ +0.4 – – V

Ambient operating temperature –40 85 –40 85 °C

Load capacitance (CL)3050pF

Input rise and fall times 5 2 ns

Input pulse voltages 0 to VDDQ 0 to VDDP V

Input and output timing ref. voltages VDDQ/2 VDDP/2 V

AI06161

VDDQ

VDDQ/2

M36W0Rx0x0x7 DC and AC parameters

19/24

Figure 5. AC measurement load circuit

Please refer to the M58WR032KT/B and M58WR064KT/B and M69KB012AB or

M69KB024AB datasheets for further DC and AC characteristics values and illustrations.

Table 6. Device capacitance(1)

1. Sampled only, not 100% tested.

Symbol Parameter Test condition Min Max Unit

CIN Input capacitance VIN = 0 V 12 pF

COUT Output capacitance VOUT = 0 V 15 pF

AI10061

VDDQ

CL includes JIG capacitance

22kΩ

DEVICE

UNDER

TEST

0.1µF

VDDQ

22kΩ

0.1µF

VDDF

Package mechanical M36W0Rx0x0x7

20/24

6 Package mechanical

To meet environmental requirements, Numonyx offers the M36W0R50x0x7 and

M36W0R6040x7 in RoHS compliant packages, which have a lead-free second-level

interconnect. In compliance with JEDEC standard JESD97, the category of second-level

interconnect is marked on the package and on the inner box label. The maximum ratings

related to soldering conditions are also marked on the inner box label.

Note: RoHS compliant specifications are available at www.numonyx.com.

Figure 6. Stacked TFBGA88 8 x 10 mm - 8 x 10 active ball array, 0.8 mm pitch,

package outline

1. Drawing is not to scale.

BGA-Z42

ddd

BALL "A1"

FE FE1

M36W0Rx0x0x7 Package mechanical

21/24

Table 7. Stacked TFBGA88 8 x 10 mm - 8 x 10 ball array, 0.8 mm pitch, package

mechanical data

Symbol

Millimeters Inches

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.200 0.0079

A2 0.850 0.0335

b 0.350 0.300 0.400 0.0138 0.0118 0.0157

D 8.000 7.900 8.100 0.3150 0.3110 0.3189

D1 5.600 0.2205

ddd 0.100 0.0039

E 10.000 9.900 10.100 0.3937 0.3898 0.3976

E1 7.200 0.2835

E2 8.800 0.3465

e 0.800 – – 0.0315 – –

FD 1.200 0.0472

FE 1.400 0.0551

FE1 0.600 0.0236

SD 0.400 0.0157

SE 0.400 0.0157

Part numbering M36W0Rx0x0x7

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7 Part numbering

Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of

available options (speed, package, etc.) or for further information on any aspect of this

device, please contact the Numonyx sales office nearest to you.

Table 8. Ordering information scheme

Example: M36 W 0 R 6 0 4 0 T 7 ZAQ E

Device type

M36 = multichip package (multiple flash + RAM)

Flash 1 architecture

W = multiple bank, burst mode

Flash 2 architecture

0 = none present

Operating voltage

R = VDDF = VDDQ =VCCP = 1.7 V to 1.95 V

Flash 1 density

5 = 32-Mbit

6 = 64-Mbit

Flash 2 density

0 = none present

RAM 1 density

3 = 8-Mbit

4 = 16-Mbit

RAM 0 density

0 = none present

Parameter blocks location

T = top boot block flash

B = bottom boot block flash

Product version

7 = 65 nm flash technology, 70 ns; 0.125?m RAM

Package

ZAQ = stacked TFBGA88 8 x 10 mm - 8 x 10 active ball array, 0.8 mm pitch

Option

E = RoHS compliant package, standard packing

F = RoHS compliant package, tape and reel packing

M36W0Rx0x0x7 Revision history

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8 Revision history

Table 9. Document revision history

Date Version Revision Details

30-Jun-2008 1 Initial release.

29-Sep-2008 2 Change from T=-30°C to T=-40°C.

31-Mar-2009 3 Replaced references to ECOPACK with RoHS compliant.

Changed footnote 1 in figure1.

M36W0Rx0x0x7

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