APW7212 1MHz, High-Efficiency, Step-Up Converter with Load Disconnection Features General Description * Wide 0.8V to VOUT Input Voltage Range * Low 1.05V (typical) Start-Up Voltage The APW7212 is a synchronous rectifier, fixed switching frequency (1MHz typical), and current-mode step-up * Low 40A No Load Bias Current * 100mA Output from a Single AA Cell Input * 250mA Output from a Dual AA Cell Input * Internal Synchronous Rectifier regulator. The device allows use of small inductors and output capacitors for portable devices. The current-mode control scheme provides fast transient response and good output voltage accuracy. At light loads, the APW7212 will automatically enter in pulse frequency modulation(PFM) operation to reduce * Up to 92% Efficiency * <1A Quiescent Current during Shutdown * Current-Mode Operation with Internal Compen- the dominant switching losses. During PFM operation, the IC consumes very low quiescent current and main- sation - Stable with Ceramic Output Capacitors tains high efficiency over the complete load range. The device has a 1.05V start-up voltage and can operate with - Fast Line Transient Response input voltage down to 0.8V after start-up. * Fixed 1MHz Oscillator Frequency * 1.2A Current-Limit Protection The APW7212 also includes current-limit and over-temperature shutdown to prevent damage in the event of an * Built-In Soft-Start * Over-Temperature Protection with Hysteresis * Available in a 2mmx2mm TDFN2x2-8 and TSOT- output overload. The APW7212 is available in 2mmx2mm TDFN2x2-8 and TSOT-23-6A packages. 23-6A Packages * Simplified Application Circuit Halogen and Lead Free Available (RoHS Compliant) L1 4.7H VIN Applications 0.8V to VOUT * Cell Phone and Smart Phone * PDA, PMP, and MP3 * Digital Camera * Boost Regulator PFM/ PWM C1 4.7F PWM 8 SW 1 VOUT VOUT 2 R1 VIN FB 4 APW7212 3 EN 5 PS R2 C2 22F GND 6 GND 7 Pin Configuration VIN VOUT EN FB 1 2 3 4 8 7 6 5 TDFN2x2-8 (Top View) SW GND GND PS 6 VIN 5 VOUT 4 EN SW 1 GND 2 FB 3 TSOT-23-6A (Top View) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.4 - Apr., 2012 1 www.anpec.com.tw APW7212 Ordering and Marking Information Package Code QB : TDFN2x2-8 CT : TSOT-23-6A Operating Ambient Temperature Range I : -40 to 85oC Handling Code TR : Tape & Reel Assembly Material G: Halogen and Lead Free Device APW7212 Assembly Material Handling Code Temperature Range Package Code APW7212 QB: 7212 X X - Date Code APW7212 CT: W12X X - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines "Green" to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Symbol (Note 1) Rating Unit VIN Supply Voltage (VIN to GND) -0.3 ~ 7 V VOUT VOUT to GND Voltage -0.3 ~ 7 V VSW SW to GND Voltage -0.3 ~ 7 V FB, EN and PS to GND Voltage -0.3 ~ 7 V VIN TJ Parameter Maximum Junction Temperature TSTG Storage Temperature TSDR Maximum Lead Soldering Temperature, 10 Seconds 150 C -65 ~ 150 C 260 C Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol Parameter Thermal Resistance -Junction to Ambient Typical Value Unit TDFN2x2-8 85 C/W TSOT-23-6A 220 (Note 2) JA Note 2: JA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of package is soldered directly on the PCB. Copyright ANPEC Electronics Corp. Rev. A.4 - Apr., 2014 2 www.anpec.com.tw APW7212 Recommended Operating Conditions (Note 3) Symbol VIN Parameter EB, EN and PS to GND Voltage L CIN COUT Range Unit 0.8 ~ VOUT V -0.3 ~ VOUT +0.3 V 1.5 ~ 10 H 4.7 ~ F 3.7 ~ F VIN Input Voltage Inductor Input Capacitor Output Capacitor TA Ambient Temperature -40 ~ 85 C TJ Junction Temperature -40 ~ 125 C Note 3: Refer to the application circuit for further information. Electrical Characteristics Refer to the typical application circuits. These specifications apply over VIN = 1.2V, VOUT = 3.3V, IOUT = 0mA, TA = -40C to 85C, unless otherwise noted. Typical values are at TA = 25C. Symbol Parameter Test Conditions APW7212 Min. Typ. Max. Unit SUPPLY VOLTAGE AND CURRENT VIN VOUT Minimum Start-up Voltage RL = 3k - 1.05 1.2 Minimum Operating Voltage after Stat-up VEN = VIN - 0.8 0.9 V Output Voltage Range 1.8 - 5.5 - 40 60 IDD1 No Switching Quiescent Current Measured form VOUT, VFB = 1.3V, VOUT = 3.3V, TA=25C IDD2 VIN Quiescent Current Measured from VIN, VIN = 1.2V, TA=25C - 0.5 1 ISD Shutdown Current VEN = GND, VIN = 1.2V - 0.1 1 V A A REFERENCE AND OUTPUT VOLTAGES VREF IFB -1.5% 1.23 +1.5% TA = -40 ~ 85C -2% - +2% VFB = 1.3V -50 - 50 nA FB = GND 0.75 1 1.25 MHz VOUT = 3.3V - 0.35 - VOUT = 5V - 0.3 - VOUT = 3.3V - 0.6 - VOUT = 5V - 0.55 - N-FET Switch Leakage Current VSW = 5V - 0.05 1 A P-FET Switch Leakage Current VSW = 0V, VOUT = 5V - 0.05 1 A 0.9 1.2 - A - 10 - ns 80 85 95 % Regulated Feedback Voltage FB Input Current TA = 0 ~ 85C V INTERNAL POWER SWITCH FSW Switching Frequency RN-FET N-FET Switch On Resistance RP-FET P-FET Switch On Resistance ILIM N-FET Switch Current-Limit Dead-Time (Note 4) DMAX SW Maximum Duty Cycle Copyright ANPEC Electronics Corp. Rev. A.4 - Apr., 2014 3 www.anpec.com.tw APW7212 Electrical Characteristics (Cont.) Refer to the typical application circuits. These specifications apply over VIN = 1.2V, VOUT = 3.3V, IOUT = 0mA, TA = -40C to 85C, unless otherwise noted. Typical values are at TA = 25C. Symbol Parameter Test Conditions APW7212 Min. Typ. Max. Unit CONTROL STAGE EN PS EN Input Low Threshold - - 0.4 EN Input High Threshold 1 - - PS Input Low Threshold - - 0.4 PS Input High Threshold 1 - - V V IEN EN Input Leakage Current VEN = 5V or GND - 0.4 1 A IPS PS Input Leakage Current VPS = 5V or GND - 0.1 1 A TJ Rising - 150 - C - 30 - C OVER-TEMPERATURE PROTECTION TOTP Over-Temperature Protection (Note 4) Over-Temperature Protection Hysteresis (Note 4) Note 4: Guaranteed by design, not production tested. Copyright ANPEC Electronics Corp. Rev. A.4 - Apr., 2014 4 www.anpec.com.tw APW7212 Typical Operating Characteristics 100 100 90 90 80 80 70 70 60 Efficiency (%) Efficiency (%) (Refer to the application circuit in the section"Typical Application Circuits", VIN=1.5V, VOUT=3.3V, TA=25oC unless otherwise specified ) Efficiency vs. Load Current Efficiency vs. Load Current VIN=2.4V 50 VIN=1.8V 40 . 30 VIN=1.2V 20 VOUT = 3.3V L = 4.7H COUT = 22F VIN=0.9V 10 60 50 VIN=2.4V 40 VIN=1.8V 30 20 10 0 0 0.1 1 10 0.1 1000 100 1 Load Current, I OUT(mA) 400 90 350 No Load Input Current, IIN(uA) 100 80 70 60 VIN=3.6V 50 VIN=2.4V 40 30 VIN=1.8V 20 VIN=1.2V 10 VOUT = 5V L = 4.7H COUT = 22F 1 10 100 1000 No Load Input Current vs. Supply Voltage 100 300 250 200 150 VOUT = 3.3V L = 4.7H COUT = 22F 100 50 0 0 0.1 10 Load Current, I OUT(mA) Efficiency vs. Load Current Efficiency (%) VOUT = 4V L = 4.7H COUT = 22F VIN=1.2V 0 1000 Load Current, I OUT(mA) 0.5 1 1.5 2 2.5 3 3.5 Supply Voltage, VIN(V) Start-up Voltage vs. Load Current 300 Load Current, IOUT(mA) 250 200 150 100 VOUT = 3.3V L = 4.7H COUT = 22F 50 0 0 0.5 1 1.5 2 2.5 3 3.5 Start-up Voltage, VIN (V) Copyright ANPEC Electronics Corp. Rev. A.4 - Apr., 2014 5 www.anpec.com.tw APW7212 Operating Waveforms (Refer to the application circuit in the section "Typical Application Circuits", VIN=1.5V, VOUT=3.3V,TA=25oC unless otherwise specified) Load Transient Response Load Transient Response VOUT ,200mV/Div, AC 1 VOUT ,200mV/Div, AC 1 L=4.7H, VIN=1.5V, COUT=22F 200mA 2 IOUT, 0.1A/Div 100mA IOUT, 100mA/Div 10mA L=4.7H, VIN=1.5V, COUT=22F 2 Time: 100s/Div Time: 100s/Div Line Transient Response No Load Start-up 1 110mA 2.5V VEN 1.5V VIN, 0.5V/Div VOUT, 1V/Div 1 VOUT,200mV/Div,AC 2 2 IIN, 0.2A/Div 3 IOUT = 100mA L=4.7H, VIN=1.5V, IOUT=0mA Time: 100s/Div Time: 500s/Div Normal Operating Waveform Normal Operating Waveform VOUT, 10mV/Div, AC 1 VOUT,10mV/Div, AC VLX, 2V/Div, DC VLX, 2V/Div, DC 2 2 IL, 200mA/Div 3 3 IOUT = 200mA IL, 500mA/Div Time: 500ns/Div Copyright ANPEC Electronics Corp. Rev. A.4 - Apr., 2014 IOUT = 20mA Time: 10s/Div 6 www.anpec.com.tw APW7212 Pin Description PIN FUNCTION NO. NAME TDFN2x2-8 TSOT-23-6A 1 6 VIN 2 5 VOUT 3 4 EN Enable Control Input. Forcing this pin above 1.0V enables the device. Forcing this pin below 0.4V to shut it down. In shutdown, all functions are disabled to decrease the supply current below 1A. 4 3 FB Feedback Input. The device senses feedback voltage via FB and regulate the voltage at 1.23V. Connecting FB with a resistor-divider from the output set the output voltage in the range from 1.8 to 5.5V. Pulse Skipping Mode Selection. Pulling this pin to logic high to force boost converter enter PWM mode. Pulling it low to automatic switch under PFM (Pulse Frequency Mode) and PWM mode. Do not leave this pin floating. This pin internally connects to GND for TSOT-23-6 package. Supply Voltage Input Pin. Converter output and control circuitry bias supply pin. 5 - PS 6, 7 2 GND Power and signal ground pin. 8 1 SW Switch pin. Connect this pin to inductor. - - Exposed PAD Copyright ANPEC Electronics Corp. Rev. A.4 - Apr., 2014 Connected this pad to GND. 7 www.anpec.com.tw APW7212 Block Diagram PS VIN From VOUT Low Voltage Start-up VMAX Control (APW7212CT only) VOUT MUX EN Zero-Crossing Comparator Shutdown Control SW Logic Control Gate Control OverTemperature Protection Currentlimit Slope Compensation Current Sense Amplifier Oscillator Error Amplifier ICMP From VMAX Control FB COMP Softstart EAMP VREF 1.23V GND Typical Application Circuit L1 8 SW VOUT 4.7H VIN R1 1 C1 4.7F 0.8V to VOUT FB 4 VIN APW7212 3 PWM VOUT 2 5 R2 C2 22F GND 6 7 GND EN PS PFM/ PWM Copyright ANPEC Electronics Corp. Rev. A.4 - Apr., 2014 8 www.anpec.com.tw APW7212 Function Description Main Control Loop Load Disconnect The APW7212 is a constant frequency, synchronous rectifier, and current-mode switching regulator. In normal Driving EN to ground places the APW7212 in shutdown mode. When in shutdown, the internal power MOSFET turns off, all internal circuitry shuts down and the quies- operation, the internal N-channel power MOSFET is turned on each cycle when the oscillator sets an internal RS cent supply current reduces to 1A maximum. A special circuit is applied to disconnect the load from the latch and turned off when an internal comparator (ICMP) resets the latch. The peak inductor current which ICMP input during shutdown the converter. In conventional synchronous rectifier circuits, the back-gate diode of the high- resets the RS latch is controlled by the voltage on the COMP node, which is the output of the error amplifier side P-FET is forward biased in shutdown and allows current flowing from the battery to the output. However, (EAMP). An external resistive divider connected between VOUT and ground allows the EAMP to receive an output this device uses a special circuit, which takes the cathode of the back-gate diode of the high-side P-FET and feedback voltage VFB at FB pin. When the load current increases, it causes a slightly decrease in VFB relative to disconnects it from the source when the regulator is shutdown. The benefit of this feature for the system de- the 1.23V reference, which in turn causes the COMP voltage to increase until the average inductor current matches sign engineer is that the battery is not depleted during shutdown of the converter. No additional components the new load current. must be added to the design to make sure that the battery is disconnected from the output of the converter. Start-up A start-up oscillator circuit is integrated in the APW7212. When the device enables, the circuit pumps the output Current-Limit Protection voltage high. Once the output voltage reaches 1.6V (typ), the main DC-DC circuitry turns on and boosts the output The APW7212 monitors the inductor current, flowing through the N-FET, and limits the current peak at current- voltage to the final regulation voltage. limit level to prevent loads and the APW7212 from damages during overload conditions. Automatic PFM/PWM mode Switch The APW7212 is a fixed frequency PWM peak current modulation control step-up converter. At light loads, the Over-Temperature Protection (OTP) The over-temperature circuit limits the junction temperature of the APW7212. When the junction temperature ex- APW7212 will automatically enter in pulse frequency modulation operation to reduce the dominant switching ceeds 150oC, a thermal sensor turns off the both N-FET and P-FET, allowing the devices to cool. The thermal losses. In PFM operation, the inductor current may reach zero or reverse on each pulse. A zero current comparator sensor allows the converters to start a soft-start process and regulate the output voltage again after the junction turns off the P-channel synchronous MOSFET, forcing DCM(Discontinuous Current Mode) operation at light load. temperature cools by 30oC. The OTP is designed with a 30oC hysteresis to lower the average Junction Tempera- These controls get very low quiescent current, help to maintain high efficiency over the complete load range. ture (TJ) during continuous thermal overload conditions, increasing the lifetime of the device. Synchronous Rectification The internal synchronous rectifier eliminates the need for an external Schottky diode, thus reducing cost and board space. During the cycle off-time, the P-FET turns on and shunts the FET body diode. As a result, the synchronous rectifier significantly improves efficiency without the addition of an external component. Conversion efficiency can be as high as 92%. Copyright ANPEC Electronics Corp. Rev. A.4 - Apr., 2014 9 www.anpec.com.tw APW7212 Application Information Input Capacitor Selection The peak inductor current is calculated as below: The input capacitor (CIN) reduces the current peaks drawn from the input supply and reduces noise injection into IPEAK = IIN(MAX) + the IC. The reflected ripple voltage will be smaller with larger CIN. For reliable operation, it is recommended to VIN select the capacitor voltage rating at least 1.2 times higher than the maximum input voltage. The capacitors should IIN IL 1 VIN (VOUT - VIN ) 2 VOUT L FSW LX N-FET CIN IOUT D1 VOUT ESR ISW be placed close to the VIN and GND. COUT Inductor Selection For high efficiencies, the inductor should have a low DC resistance to minimize conduction losses. Especially at IL high-switching frequencies the core material has a higher impact on efficiency. When using small chip inductors, ILIM IPEAK the efficiency is reduced mainly due to higher inductor core losses. This needs to be considered when select- IL IIN ing the appropriate inductor. The inductor value determines the inductor ripple current. The larger the inductor ISW value, the smaller the inductor ripple current and the lower the conduction losses of the converter. Conversely, larger inductor values cause a slower load transient response. A reasonable starting point for setting ripple current, IL, is 30% to 50% of the average inductor current. The recommended inductor value can be calculated as below: ID 2 V V - VIN L IN OUT V F I SW OUT ( MAX ) OUT IL IL(AVG) IOUT Output Capacitor Selection where The current-mode control scheme of the APW7212 allows the use of tiny ceramic capacitors. The higher ca- VIN = input voltage VOUT = output voltage pacitor value provides the good load transients response. Ceramic capacitors with low ESR values have the lowest FSW = switching frequency in MHz IOUT = maximum output current in amp. output voltage ripple and are recommended. If required, tantalum capacitors may be used as well. The output ripple = Efficiency IL /IL(AVG) = (0.3 to 0.5 typical) is the sum of the voltages across the ESR and the ideal output capacitor. IOUT VOUT - VIN COUT VOUT FSW To avoid saturation of the inductor, the inductor should be rated at least for the maximum input current of the con- VCOUT verter plus the inductor ripple current. The maximum input current is calculated as below: VOUT = VESR + VCOUT IIN(MAX) = VESR IPEAK RESR IOUT(MAX) VOUT VIN Copyright ANPEC Electronics Corp. Rev. A.4 - Apr., 2014 10 www.anpec.com.tw APW7212 Application Information (Cont.) Layout Consideration Output Capacitor Selection (Cont.) Where IPEAK is the peak inductor current. For ceramic ca- VIN pacitor application, the output voltage ripple is dominated by the VCOUT. When choosing the input and output ce- C2 C1 L1 Via to VIN ramic capacitors, the X5R or X7R with their good temperature and voltage characteristics are recommended. 3 4 5 8 7 R1 Output Voltage Setting SW GND 6 GND 1 VOUT 2 PWM PFM/PWM PS A resistive divider sets the output voltage. The external R2 resistive divider is connected to the output, allowing remote voltage sensing as shown in "Typical Application APW7212 Layout Suggestion Circuits". A suggestion of the maximum value of R1 is 2M and R2 is 600k to keep the minimum current that VIN provides enough noise rejection ability through the resistor divider. The output voltage can be calculated as L1 C1 GND below: R1 R1 = 1.231 + VOUT = VREF 1 + R2 R2 Via To VIN R2 SW Layout Consideration FB GND R1 For all switching power supplies, the layout is an important step in the design, especially at high peak currents VEN C2 VOUT Via To VOUT and switching frequencies. If the layout is not done carefully, the regulator may show noise problems and APW7212 Layout Suggestion duty cycle jitter. 1. Since the VOUT supplies IC bias voltage, the output capacitor should be placed close to the VOUT and GND. Connecting the capacitor with VOUT and GND pins by short and wide tracks without using any via holes for good filtering and minimizing the voltage ripple. 2. To minimize copper trace connections that can inject noise into the system, the inductor should be placed as close as possible to the SW pin to minimize the noise coupling into other circuits. 3. Since the feedback pin and network is a high impedance circuit the feedback network should be routed away from the inductor. The feedback pin and feedback network should be shielded with a ground plane or trace to minimize noise coupling into this circuit. 4. A star ground connection or ground plane minimizes ground shifts and noise is recommended. Copyright ANPEC Electronics Corp. Rev. A.4 - Apr., 2014 11 www.anpec.com.tw APW7212 Package Information TDFN2x2-8 D A b E (Top View) A1 D2 A3 4 E2 1 Pin 1 Corner L K (Bottom View) 5 8 e TDFN2x2-8 S Y M B O L MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 0.012 0.083 INCHES MILLIMETERS A3 0.008 REF 0.20 REF b 0.18 0.30 0.007 D 1.90 2.10 0.075 D2 1.00 1.60 0.039 0.063 0.083 0.039 E 1.90 2.10 0.075 E2 0.60 1.00 0.024 e 0.50 BSC L 0.30 K 0.20 0.020 BSC 0.012 0.45 0.018 0.008 Note : 1. Followed from JEDEC MO-229 WCCD-3. Copyright ANPEC Electronics Corp. Rev. A.4 - Apr., 2014 12 www.anpec.com.tw APW7212 Package Information TSOT-23-6A D e E E1 SEE VIEW A b c 0.25 A GAUGE PLANE SEATING PLANE L A1 A2 e1 VIEW A TSOT-23-6A S Y M B O L MIN. MAX. MIN. MAX. A 0.70 1.00 0.028 0.039 A1 0.01 0.10 0.000 0.004 A2 0.70 0.90 0.028 0.035 b 0.30 0.50 0.012 0.020 c 0.08 0.20 0.003 0.008 D 2.70 3.10 0.106 0.122 0.118 0.071 INCHES MILLIMETERS E 2.60 3.00 0.102 E1 1.40 1.80 0.055 e 0.95 BSC 0.037 BSC e1 1.90 BSC 0.075 BSC L 0.30 0.60 0 8 0.012 0.024 0 8 Note : Dimension D and E1 do not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.4 - Apr., 2014 13 www.anpec.com.tw APW7212 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TDFN2x2-8 Application TSOT-23-6A A H T1 C d D W E1 F 178.02.00 50 MIN. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 8.00.20 1.750.10 3.500.05 P0 P1 P2 D0 D1 T A0 B0 K0 4.00.10 4.00.10 2.00.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.4 3.35 MIN 3.35 MIN 1.300.20 A H T1 C d D W E1 F 178.02.00 50 MIN. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 8.00.30 1.750.10 3.50.05 P0 P1 P2 D0 D1 T A0 B0 K0 4.00.10 4.00.10 2.00.05 1.5+0.10 -0.00 1.0 MIN. 0.6+0.00 -0.40 3.200.20 3.100.20 1.500.20 (mm) Copyright ANPEC Electronics Corp. Rev. A.4 - Apr., 2014 14 www.anpec.com.tw APW7212 Devices Per Unit Package Type Unit Quantity TDFN2x2-8 Tape & Reel 3000 TSOT-23-6A Tape & Reel 3000 Taping Direction Information TDFN2x2-8 USER DIRECTION OF FEED TSOT-23-6 USER DIRECTION OF FEED AAAX AAAX Copyright ANPEC Electronics Corp. Rev. A.4 - Apr., 2014 AAAX AAAX 15 AAAX AAAX AAAX www.anpec.com.tw APW7212 Classification Profile Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 C 150 C 60-120 seconds 150 C 200 C 60-120 seconds 3 C/second max. 3 C/second max. 183 C 60-150 seconds 217 C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 C/second max. 6 C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Copyright ANPEC Electronics Corp. Rev. A.4 - Apr., 2014 16 www.anpec.com.tw APW7212 Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process - Classification Temperatures (Tc) Package Thickness <2.5 mm 2.5 mm Volume mm <350 235 C 220 C 3 Volume mm 350 220 C 220 C 3 Table 2. Pb-free Process - Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm - 2.5 mm 2.5 mm Volume mm <350 260 C 260 C 250 C 3 Volume mm 350-2000 260 C 250 C 245 C 3 Volume mm >2000 260 C 245 C 245 C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Description 5 Sec, 245C 1000 Hrs, Bias @ Tj=125C 168 Hrs, 100%RH, 2atm, 121C 500 Cycles, -65C~150C VHBM2KV VMM200V 10ms, 1tr100mA Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.4 - Apr., 2014 17 www.anpec.com.tw