Copyright ANPEC Electronics Corp.
Rev. A.4 - Apr., 2012
APW7212
www.anpec.com.tw1
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
1MHz, High-Efficiency, Step-Up Converter with Load Disconnection
The APW7212 is a synchronous rectifier, fixed switching
frequency (1MHz typical), and current-mode step-up
regulator. The device allows use of small inductors and
output capacitors for portable devices. The current-mode
control scheme provides fast transient response and
good output voltage accuracy.
Features
•Wide 0.8V to VOUT Input Voltage Range
•Low 1.05V (typical) Start-Up Voltage
•Low 40µA No Load Bias Current
•100mA Output from a Single AA Cell Input
• 250mA Output from a Dual AA Cell Input
•Internal Synchronous Rectifier
•Up to 92% Efficiency
•<1µA Quiescent Current during Shutdown
•Current-Mode Operation with Internal Compen-
sation
- Stable with Ceramic Output Capacitors
- Fast Line Transient Response
•Fixed 1MHz Oscillator Frequency
•1.2A Current-Limit Protection
•Built-In Soft-Start
•Over-Temperature Protection with Hysteresis
•Available in a 2mmx2mm TDFN2x2-8 and TSOT-
23-6A Packages
•Halogen and Lead Free Available
(RoHS Compliant)
Applications
General Description
•Cell Phone and Smart Phone
•PDA, PMP, and MP3
•Digital Camera
•Boost Regulator
The APW7212 also includes current-limit and over-tem-
perature shutdown to prevent damage in the event of an
output overload.
The APW7212 is available in 2mmx2mm TDFN2x2-8 and
TSOT-23-6A packages.
Simplified Application Circuit
At light loads, the APW7212 will automatically enter in
pulse frequency modulation(PFM) operation to reduce
the dominant switching losses. During PFM operation,
the IC consumes very low quiescent current and main-
tains high efficiency over the complete load range. The
device has a 1.05V start-up voltage and can operate with
input voltage down to 0.8V after start-up.
Pin Configuration
1
6
54
3
28
7SW
GND
GND
PS
VOUT
FB
VIN
EN
TDFN2x2-8
(Top View)
4 EN
6 VIN
GND 2 5 VOUT
FB 3
SW 1
TSOT-23-6A
(Top View)
VIN
SW VOUT
EN
VOUT
FB
3
8
4
1
2
C2
22µF
C1
4.7µFR2
VIN
0.8V to VOUT
R1
APW7212
GND
L1
4.7µH
6
PS
5
PFM/
PWM
PWM GND 7
Copyright ANPEC Electronics Corp.
Rev. A.4 - Apr., 2014
APW7212
www.anpec.com.tw2
Symbol
Parameter Rating Unit
VIN VIN Supply Voltage (VIN to GND) -0.3 ~ 7 V
VOUT VOUT to GND Voltage -0.3 ~ 7 V
VSW SW to GND Voltage -0.3 ~ 7 V
FB, EN and PS to GND Voltage -0.3 ~ 7 V
TJ Maximum Junction Temperature 150 °C
TSTG Storage Temperature -65 ~ 150 °C
TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 °C
Absolute Maximum Ratings (Note 1)
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Ordering and Marking Information
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Symbol
Parameter Typical Value Unit
θJA Thermal Resistance -Junction to Ambient (Note 2)
TDFN2x2-8
TSOT-23-6A
85
220 °C/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of package is soldered directly on the PCB.
Thermal Characteristics
Package Code
QB : TDFN2x2-8 CT : TSOT-23-6A
Operating Ambient Temperature Range
I : -40 to 85oC
Handling Code
TR : Tape & Reel
Assembly Material
G: Halogen and Lead Free Device
X - Date Code
APW7212
Handling Code
Temperature Range
Package Code
Assembly Material
APW7212 QB: 7212
X
X - Date Code
APW7212 CT: W12X
Copyright ANPEC Electronics Corp.
Rev. A.4 - Apr., 2014
APW7212
www.anpec.com.tw3
Recommended Operating Conditions (Note 3)
Symbol
Parameter Range Unit
VIN VIN Input Voltage 0.8 ~ VOUT V
EB, EN and PS to GND Voltage -0.3 ~ VOUT +0.3 V
L Inductor 1.5 ~ 10 µH
CIN Input Capacitor 4.7 ~ µF
COUT Output Capacitor 3.7 ~ µF
TA Ambient Temperature -40 ~ 85 °C
TJ Junction Temperature -40 ~ 125 °C
Note 3: Refer to the application circuit for further information.
Electrical Characteristics
Refer to the typical application circuits. These specifications apply over VIN = 1.2V, VOUT = 3.3V, IOUT = 0mA, TA = -40°C to 85°C, unless
otherwise noted. Typical values are at TA = 25°C.
APW7212
Symbol
Parameter Test Conditions Min.
Typ.
Max.
Unit
SUPPLY VOLTAGE AND CURRENT
Minimum Start-up Voltage RL = 3kΩ - 1.05
1.2
VIN Minimum Operating Voltage after
Stat-up VEN = VIN - 0.8 0.9 V
VOUT Output Voltage Range 1.8 - 5.5 V
IDD1 No Switching Quiescent Current
Measured form VOUT, VFB = 1.3V,
VOUT = 3.3V, TA=25°C - 40 60
IDD2 VIN Quiescent Current Measured from VIN, VIN = 1.2V, TA=25°C - 0.5 1 µA
ISD Shutdown Current VEN = GND, VIN = 1.2V - 0.1 1 µA
REFERENCE AND OUTPUT VOLTAGES
TA = 0 ~ 85°C -1.5%
1.23
+1.5%
VREF Regulated Feedback Voltage TA = -40 ~ 85°C -2% - +2%
V
IFB FB Input Current VFB = 1.3V -50 - 50 nA
INTERNAL POWER SWITCH
FSW Switching Frequency FB = GND 0.75
1 1.25
MHz
VOUT = 3.3V - 0.35
-
RN-FET N-FET Switch On Resistance VOUT = 5V - 0.3 - Ω
VOUT = 3.3V - 0.6 -
RP-FET P-FET Switch On Resistance VOUT = 5V - 0.55
- Ω
N-FET Switch Leakage Current
VSW = 5V - 0.05
1 µA
P-FET Switch Leakage Current VSW = 0V, VOUT = 5V - 0.05
1 µA
ILIM N-FET Switch Current-Limit 0.9 1.2 - A
Dead-Time (Note 4) - 10 - ns
DMAX SW Maximum Duty Cycle 80 85 95 %
Copyright ANPEC Electronics Corp.
Rev. A.4 - Apr., 2014
APW7212
www.anpec.com.tw4
Electrical Characteristics (Cont.)
APW7212
Symbol Parameter Test Conditions Min.
Typ. Max.
Unit
CONTROL STAGE
EN EN Input Low Threshold - - 0.4
EN Input High Threshold 1 - - V
PS PS Input Low Threshold - - 0.4
PS Input High Threshold 1 - - V
IEN EN Input Leakage Current VEN = 5V or GND - 0.4 1 µA
IPS PS Input Leakage Current VPS = 5V or GND - 0.1 1 µA
OVER-TEMPERATURE PROTECTION
TOTP Over-Temperature
Protection (Note 4) TJ Rising - 150 - °C
Over-Temperature
Protection Hysteresis (Note 4)
- 30 - °C
Refer to the typical application circuits. These specifications apply over VIN = 1.2V, VOUT = 3.3V, IOUT = 0mA, TA = -40°C to 85°C, unless
otherwise noted. Typical values are at TA = 25°C.
Note 4: Guaranteed by design, not production tested.
Copyright ANPEC Electronics Corp.
Rev. A.4 - Apr., 2014
APW7212
www.anpec.com.tw5
Typical Operating Characteristics
(Refer to the application circuit in the section"Typical Application Circuits", VIN=1.5V, VOUT=3.3V, TA=25oC unless
otherwise specified )
Efficiency vs. Load Current
Efficiency (%)
Load Current, IOUT(mA)
0
10
20
30
40
50
60
70
80
90
100
0.1 1 10 100 1000
.VIN=1.8V
VIN=0.9V
VIN=1.2V
VIN=2.4V
VOUT = 3.3V
L = 4.7µH
COUT = 22µF
Efficiency vs. Load Current
Efficiency (%)
Load Current, IOUT(mA)
0
10
20
30
40
50
60
70
80
90
100
0.1 1 10 100 1000
VIN=1.2V
VIN=2.4V
VIN=1.8V
VOUT = 4V
L = 4.7µH
COUT = 22µF
Efficiency (%)
Efficiency vs. Load Current
Load Current, IOUT(mA)
0
10
20
30
40
50
60
70
80
90
100
0.1 1 10 100 1000
VIN=3.6V
VIN=2.4V
VIN=1.2V
VIN=1.8V VOUT = 5V
L = 4.7µH
COUT = 22µF
No Load Input Current vs. Supply
Voltage
No Load Input Current, IIN(uA)
Supply Voltage, VIN(V)
0
50
100
150
200
250
300
350
400
00.5 11.5 22.5 33.5
VOUT = 3.3V
L = 4.7µH
COUT = 22µF
Load Current, IOUT(mA)
Start-up Voltage vs. Load Current
Start-up Voltage, VIN (V)
0
50
100
150
200
250
300
00.5 11.5 22.5 33.5
VOUT = 3.3V
L = 4.7µH
COUT = 22µF
Copyright ANPEC Electronics Corp.
Rev. A.4 - Apr., 2014
APW7212
www.anpec.com.tw6
Operating Waveforms
(Refer to the application circuit in the section “Typical Application Circuits”, VIN=1.5V, VOUT=3.3V,TA=25oC unless
otherwise specified)
Time: 500ns/Div
Normal Operating Waveform
3
2
VOUT, 10mV/Div, AC
VLX, 2V/Div, DC
IL, 200mA/Div
IOUT = 200mA
2
1
Load Transient Response
VOUT ,200mV/Div, AC
IOUT, 100mA/Div 100mA
L=4.7µH, VIN=1.5V, COUT=22µF
Time: 100µs/Div
200mA
Load Transient Response
2
1
Time: 100µs/Div
VOUT ,200mV/Div, AC
10mA
110mAIOUT, 0.1A/Div
L=4.7µH, VIN=1.5V, COUT=22µF
Time: 500µs/Div
No Load Start-up
2
1
3
VOUT, 1V/Div
IIN, 0.2A/Div
VEN
L=4.7µH, VIN=1.5V, IOUT=0mA
Line Transient Response
2
1
VOUT,200mV/Div,AC
VIN, 0.5V/Div1.5V
2.5V
IOUT = 100mA
Time: 100µs/Div
Time: 10µs/Div
Normal Operating Waveform
3
2
1VOUT,10mV/Div, AC
VLX, 2V/Div, DC
IL, 500mA/Div IOUT = 20mA
Copyright ANPEC Electronics Corp.
Rev. A.4 - Apr., 2014
APW7212
www.anpec.com.tw7
Pin Description
PIN
NO.
TDFN2x2-8
TSOT-23-6A
NAME FUNCTION
1 6 VIN Supply Voltage Input Pin.
2 5 VOUT Converter output and control circuitry bias supply pin.
3 4 EN Enable Control Input. Forcing this pin above 1.0V enables the device. Forcing this
pin below 0.4V to shut it down. In shutdown, all functions are disabled to decrease
the supply current below 1µA.
4 3 FB Feedback Input. The device senses feedback voltage via FB and regulate the
voltage at 1.23V. Connecting FB with a resistor-divider from the output set the
output voltage in the range from 1.8 to 5.5V.
5 - PS
Pulse Skipping Mode Selection. Pulling this pin to logic high to force boost converter
enter PWM mode. Pulling it low to automatic switch under PFM (Pulse Frequency
Mode) and PWM mode. Do not leave this pin floating. This pin internally connects to
GND for TSOT-23-6 package.
6, 7 2 GND Power and signal ground pin.
8 1 SW Switch pin. Connect this pin to inductor.
- -
Exposed
PAD
Connected this pad to GND.
Copyright ANPEC Electronics Corp.
Rev. A.4 - Apr., 2014
APW7212
www.anpec.com.tw8
Block Diagram
Typical Application Circuit
VIN
SW VOUT
EN
VOUT
FB
3
8
4
1
2
C2
22µF
C1
4.7µFR2
VIN
0.8V to VOUT
R1
APW7212
GND
L1
4.7µH
6
PS
5
PFM/
PWM
PWM GND 7
VMAX
Control
Oscillator
Logic Control
VIN
GND
SW
Over-
Temperature
Protection
EAMP
COMP
ICMP
Soft-
start
Error
Amplifier
Current Sense
Amplifier
Current-
limit
Slope
Compensation
Low
Voltage
Start-up VOUT
Zero-Crossing
Comparator
PS
Shutdown
Control
MUX
Gate
Control
FB
EN
From VOUT
From
VMAX
Control VREF
1.23V
(APW7212CT only)
Σ
Copyright ANPEC Electronics Corp.
Rev. A.4 - Apr., 2014
APW7212
www.anpec.com.tw9
Function Description
Main Control Loop
Start-up
The APW7212 is a constant frequency, synchronous
rectifier, and current-mode switching regulator. In normal
operation, the internal N-channel power MOSFET is turned
on each cycle when the oscillator sets an internal RS
latch and turned off when an internal comparator (ICMP)
resets the latch. The peak inductor current which ICMP
resets the RS latch is controlled by the voltage on the
COMP node, which is the output of the error amplifier
(EAMP). An external resistive divider connected between
VOUT and ground allows the EAMP to receive an output
feedback voltage VFB at FB pin. When the load current
increases, it causes a slightly decrease in VFB relative to
the 1.23V reference, which in turn causes the COMP volt-
age to increase until the average inductor current matches
the new load current.
A start-up oscillator circuit is integrated in the APW7212.
When the device enables, the circuit pumps the output
voltage high. Once the output voltage reaches 1.6V (typ),
the main DC-DC circuitry turns on and boosts the output
voltage to the final regulation voltage.
Automatic PFM/PWM mode Switch
The APW7212 is a fixed frequency PWM peak current
modulation control step-up converter. At light loads, the
APW7212 will automatically enter in pulse frequency
modulation operation to reduce the dominant switching
losses. In PFM operation, the inductor current may reach
zero or reverse on each pulse. A zero current comparator
turns off the P-channel synchronous MOSFET, forcing
DCM(Discontinuous Current Mode) operation at light load.
These controls get very low quiescent current, help to
maintain high efficiency over the complete load range.
Synchronous Rectification
The internal synchronous rectifier eliminates the need
for an external Schottky diode, thus reducing cost and
board space. During the cycle off-time, the P-FET turns
on and shunts the FET body diode. As a result, the syn-
chronous rectifier significantly improves efficiency with-
out the addition of an external component. Conversion
efficiency can be as high as 92%.
Load Disconnect
Driving EN to ground places the APW7212 in shutdown
mode. When in shutdown, the internal power MOSFET
turns off, all internal circuitry shuts down and the quies-
cent supply current reduces to 1µA maximum.
A special circuit is applied to disconnect the load from the
input during shutdown the converter. In conventional syn-
chronous rectifier circuits, the back-gate diode of the high-
side P-FET is forward biased in shutdown and allows
current flowing from the battery to the output. However,
this device uses a special circuit, which takes the cath-
ode of the back-gate diode of the high-side P-FET and
disconnects it from the source when the regulator is
shutdown. The benefit of this feature for the system de-
sign engineer is that the battery is not depleted during
shutdown of the converter. No additional components
must be added to the design to make sure that the bat-
tery is disconnected from the output of the converter.
Current-Limit Protection
The APW7212 monitors the inductor current, flowing
through the N-FET, and limits the current peak at current-
limit level to prevent loads and the APW7212 from dam-
ages during overload conditions.
Over-Temperature Protection (OTP)
The over-temperature circuit limits the junction tempera-
ture of the APW7212. When the junction temperature ex-
ceeds 150oC, a thermal sensor turns off the both N-FET
and P-FET, allowing the devices to cool. The thermal
sensor allows the converters to start a soft-start process
and regulate the output voltage again after the junction
temperature cools by 30oC. The OTP is designed with a
30oC hysteresis to lower the average Junction Tempera-
ture (TJ) during continuous thermal overload conditions,
increasing the lifetime of the device.
Copyright ANPEC Electronics Corp.
Rev. A.4 - Apr., 2014
APW7212
www.anpec.com.tw10
The input capacitor (CIN) reduces the current peaks drawn
from the input supply and reduces noise injection into
the IC. The reflected ripple voltage will be smaller with
larger CIN. For reliable operation, it is recommended to
select the capacitor voltage rating at least 1.2 times higher
than the maximum input voltage. The capacitors should
be placed close to the VIN and GND.
Application Information
Input Capacitor Selection
Inductor Selection
whereVIN = input voltage
VOUT = output voltage
FSW = switching frequency in MHz
IOUT = maximum output current in amp.
η = Efficiency
∆IL /IL(AVG) = (0.3 to 0.5 typical)
To avoid saturation of the inductor, the inductor should be
rated at least for the maximum input current of the con-
verter plus the inductor ripple current. The maximum in-
put current is calculated as below:
The peak inductor current is calculated as below:
Output Capacitor Selection
The current-mode control scheme of the APW7212 al-
lows the use of tiny ceramic capacitors. The higher ca-
pacitor value provides the good load transients response.
Ceramic capacitors with low ESR values have the lowest
output voltage ripple and are recommended. If required,
tantalum capacitors may be used as well. The output ripple
is the sum of the voltages across the ESR and the ideal
output capacitor.
For high efficiencies, the inductor should have a low DC
resistance to minimize conduction losses. Especially at
high-switching frequencies the core material has a higher
impact on efficiency. When using small chip inductors,
the efficiency is reduced mainly due to higher inductor
core losses. This needs to be considered when select-
ing the appropriate inductor. The inductor value deter-
mines the inductor ripple current. The larger the inductor
value, the smaller the inductor ripple current and the lower
the conduction losses of the converter. Conversely, larger
inductor values cause a slower load transient response.
A reasonable starting point for setting ripple current, ∆IL,
is 30% to 50% of the average inductor current. The rec-
ommended inductor value can be calculated as below:
( )
∆
η
⋅
⋅−
⋅
≥
AVGL
L
)MAX(OUTSW
INOUT
2
OUT
IN
II
IFVV
V
V
L
η⋅⋅
=IN
OUT)MAX(OUT
)MAX(IN VVI
I
(
)
SWOUT
INOUTIN
)MAX(INPEAK FLVVVV
2
1
II ⋅⋅ −⋅
⋅+=
VIN VOUT
IL
N-FET
LX IOUT
ISW
CIN
COUT
IIN
ILIM
IL
IPEAK
IIN
IOUT
ISW
ID
D1
∆IL
ESR
⋅
−
⋅≅∆SWOUT
INOUT
OUT
OUT
COUT FVVV
C
I
V
ESRPEAKESR RIV⋅≅∆
ΔVOUT = ΔVESR + ΔVCOUT
Copyright ANPEC Electronics Corp.
Rev. A.4 - Apr., 2014
APW7212
www.anpec.com.tw11
Application Information (Cont.)
Output Voltage Setting
A resistive divider sets the output voltage. The external
resistive divider is connected to the output, allowing re-
mote voltage sensing as shown in “Typical Application
Circuits”. A suggestion of the maximum value of R1 is
2MΩ and R2 is 600kΩ to keep the minimum current that
provides enough noise rejection ability through the re-
sistor divider. The output voltage can be calculated as
below:
+=
+⋅=2R1R
123.1
2R1R
1VV REFOUT
Layout Consideration
For all switching power supplies, the layout is an impor-
tant step in the design, especially at high peak currents
and switching frequencies. If the layout is not done
carefully, the regulator may show noise problems and
duty cycle jitter.
1. Since the VOUT supplies IC bias voltage, the output
capacitor should be placed close to the VOUT and
GND. Connecting the capacitor with VOUT and GND
pins by short and wide tracks without using any via
holes for good filtering and minimizing the voltage
ripple.
2. To minimize copper trace connections that can inject
noise into the system, the inductor should be placed
as close as possible to the SW pin to minimize the
noise coupling into other circuits.
3. Since the feedback pin and network is a high imped-
ance circuit the feedback network should be routed
away from the inductor. The feedback pin and feed-
back network should be shielded with a ground plane
or trace to minimize noise coupling into this circuit.
4. A star ground connection or ground plane minimizes
ground shifts and noise is recommended.
Where IPEAK is the peak inductor current. For ceramic ca-
pacitor application, the output voltage ripple is dominated
by the ∆VCOUT. When choosing the input and output ce-
ramic capacitors, the X5R or X7R with their good tem-
perature and voltage characteristics are recommended.
Output Capacitor Selection (Cont.)Layout Consideration
1
6
54
3
2
8
7SW
GND
GND
PS
VOUT
R2
R1
C1C2
L1
PFM/PWM
PWM
VIN
Via to VIN
APW7212 Layout Suggestion
GND
R1
R2
Via To VOUT
L1
VOUT
VEN
GND
FB
C1
C2
SW
VIN
Via To VIN
APW7212 Layout Suggestion
Copyright ANPEC Electronics Corp.
Rev. A.4 - Apr., 2014
APW7212
www.anpec.com.tw12
Package Information
TDFN2x2-8
S
Y
M
B
O
LMIN.MAX.
0.80
0.00
0.18 0.30
1.00 1.60
0.05
0.60
A
A1
b
D
D2
E
E2
e
L
MILLIMETERS
A30.20 REF
TDFN2x2-8
0.30 0.45
1.00
0.008 REF
MIN.MAX.
INCHES
0.031
0.000
0.007 0.012
0.039 0.063
0.024
0.012 0.018
0.70
0.039
0.028
0.002
0.50 BSC 0.020 BSC
1.90 2.10 0.075 0.083
1.90 2.10 0.075 0.083
K0.20 0.008
Note : 1. Followed from JEDEC MO-229 WCCD-3.
e
LKE2
Pin 1 Corner
D2
A3
A1
b
A
E
D
(Top View)
(Bottom View)
41
85
Copyright ANPEC Electronics Corp.
Rev. A.4 - Apr., 2014
APW7212
www.anpec.com.tw13
Package Information
TSOT-23-6A
Note : Dimension D and E1 do not include mold flash, protrusions or gate
burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil
per side.
De
e1
b
E1
E
c
SEE VIEW A
A2A1
A
VIEW A
L
0.25
SEATING PLANE
GAUGE PLANE
0.020
0.008
0.004
0.024
0.035
0.039
MAX.
0.30L
0°
E
e
e1
E1
D
c
b
0.08
0.30
0.012
0.60
8° 0° 8°
0.95 BSC
1.90 BSC
0.50
0.20
0.075 BSC
0.037 BSC
0.012
0.003
MILLIMETERS
MIN.
S
Y
M
B
O
L
A1
A2
A
0.01
0.70
TSOT-23-6A
MAX.
0.90
0.10
1.00
MIN.
0.000
0.028
INCHES
2.70 3.10 0.106 0.122
2.60 3.00 0.102 0.118
1.40 1.80 0.055 0.071
0.70 0.028
θ
Copyright ANPEC Electronics Corp.
Rev. A.4 - Apr., 2014
APW7212
www.anpec.com.tw14
Application
A H T1 C d D W E1 F
178.0±2.00
50 MIN.
8.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
8.0±0.20
1.75±0.10
3.50±0.05
P0 P1 P2 D0 D1 T A0 B0 K0
TDFN2x2-8
4.0±0.10
4.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.4 3.35 MIN
3.35 MIN
1.30±0.20
Application
A H T1 C d D W E1 F
178.0±2.00
50 MIN.
8.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
8.0±0.30
1.75±0.10
3.5±0.05
P0 P1 P2 D0 D1 T A0 B0 K0
TSOT-23-6A
4.0±0.10
4.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.0 MIN.
0.6+0.00
-0.40
3.20±0.20
3.10±0.20
1.50±0.20
(mm)
Carrier Tape & Reel Dimensions
H
T1
A
d
A
E1
A
B
W
F
T
P0
OD0
BA0
P2
K0
B0
SECTION B-B
SECTION A-A
OD1
P1
Copyright ANPEC Electronics Corp.
Rev. A.4 - Apr., 2014
APW7212
www.anpec.com.tw15
Devices Per Unit
Package Type Unit Quantity
TDFN2x2-8 Tape & Reel 3000
TSOT-23-6A Tape & Reel 3000
Taping Direction Information
TDFN2x2-8
TSOT-23-6
USER DIRECTION OF FEED
USER DIRECTION OF FEED
AAAX AAAX AAAX AAAX AAAX AAAX AAAX
Copyright ANPEC Electronics Corp.
Rev. A.4 - Apr., 2014
APW7212
www.anpec.com.tw16
Classification Profile
Classification Reflow Profiles
Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Average ramp-up rate
(Tsmax to TP) 3 °C/second max. 3 °C/second max.
Liquidous temperature (TL)
Time at liquidous (tL) 183 °C
60-150 seconds 217 °C
60-150 seconds
Peak package body Temperature
(Tp)* See Classification Temp in table 1 See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc) 20** seconds 30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max. 6 °C/second max.
Time 25°C to peak temperature 6 minutes max. 8 minutes max.
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Copyright ANPEC Electronics Corp.
Rev. A.4 - Apr., 2014
APW7212
www.anpec.com.tw17
Classification Reflow Profiles (Cont.)
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
350-2000 Volume mm3
>2000
<1.6 mm 260 °C 260 °C 260 °C
1.6 mm – 2.5 mm 260 °C 250 °C 245 °C
≥2.5 mm 250 °C 245 °C 245 °C
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
≥350
<2.5 mm 235 °C 220 °C
≥2.5 mm 220 °C 220 °C
Test item Method Description
SOLDERABILITY JESD-22, B102 5 Sec, 245°C
HOLT JESD-22, A108 1000 Hrs, Bias @ Tj=125°C
PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C
TCT JESD-22, A104 500 Cycles, -65°C~150°C
HBM MIL-STD-883-3015.7 VHBM≧2KV
MM JESD-22, A115 VMM≧200V
Latch-Up JESD 78 10ms, 1tr≧100mA
Reliability Test Program
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
