CY74FCT2652ATQC - Texas Instruments

8-Bit Registered Transceive

CY74FCT2652T

SCCS044 - May 1994 - Revised March 2000

Data sheet acquired from Cypress Semiconductor Corporation.

Data sheet modiﬁed to remove devices not offered.

1CY54/

Features

•Function and pinout compatible with FCT and F logic

•FCT-C speed at 5.4 ns max. (Com’l)

FCT-A speed at 6.3 ns max. (Com’l)

•25Ωoutputseriesresistorstoreducetransmissionline

reﬂection noise

•Reduced VOH (typically = 3.3V) versions of equivalent

FCT functions

•Edge-rate control circuitry for signiﬁcantly improved

noise characteristics

•Power-off disable feature

•Matched rise and fall times

•Fully compatible with TTL input and output logic levels

•Sink current 12 mA

Source current 15 mA

•ESD > 2000V

•Independent register for A and B buses

•Multiplexed real-time and stored data transfer

•Extended commercial temp. range of –40˚C to +85˚C

Functional Description

The FCT2652T consists of bus transceiver circuits, D-type

ﬂip-ﬂops, and control circuitry arranged for multiplexed trans-

mission of data directly from the input bus or from the internal

storage registers. GAB and GBA control pins are provided to

control the transceiver functions. SAB andSBAcontrol pins are

provided to select either real-time or stored data tr ansf er.

The circuitry used for select control will eliminate the typical

decoding glitch that occurs in a multiplexer during transition

between stored and real-time data. A LOW input level selects

real-time data and a HIGH selects stored data. Data on the A

or B data bus, or both, can be stored in the internal D ﬂip-ﬂops

by LOW-to-HIGH transitions at the appropriate clock pins

(CPAB or CPBA), regardless of the select or enable control

pins. When SAB and SBA are in the real-time transfer mode,

it is also possible to store data without using the internal

D-type ﬂip-ﬂops by simultaneously enabling GAB and GBA. In

this configuration, each output reinforces its input. Thus, when all

other data sources to the two sets of bus lines are at high imped-

ance, each set of b us lines will remain at its last state .

On-chip termination resistors are added to the outputs to

reduce system noise caused by reﬂections. The FCT2652T

can replace the FCT652T to reduce noise in existing designs.

The outputs are designed with a power-off disable feature to

allow for live insertion of boards

LogicBlockDiagram Pin Configurations

FCT2652T–1

TO 7 OTHERCHANNELS

CPAB

SAB

SBA

GBA

GAB

CPBA

BREG

AREG

1OF8CHANNELS

VCC

FCT2652T–3

Top View

CPAB

CPBA

SAB SBAGAB GBA

GND

SOIC/QSOP

CY74FCT2652T

Function Table[1]

Inputs Data I/O Operation or FunctionGAB GBA CPAB CPBA SAB SBA A1 thru A8B1 thru B8

HH or L H or L X

XInput Input Isolation

Store A and B Data

HH or L X

X[1 ] X

XInput

Input Unspeciﬁed[2]

Output Store A, Hold B

Store A in both registers

LH or L X

X[1] Unspeciﬁed[2]

Output Input

Input Hold A, Store B

Store B in both registers

H or L X

HOutput Input Real-Time B Data to A Bus

Stored B Data to A Bus

H or L X

XInput Output Real-Time A Data to B Bus

Stored A Data to B Bus

H L H or L H or L H H Output Output Stored A Data to B Bus

and Stored B Data to A Bus

Notes:

1. Select control=L: clocks can occur simultaneously.

Select control=H: clocks must be staggered in order to load both registers. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care.

BUS BBUS A

GAB

LGBA

LCPAB

XCPBA

XSAB

XSBA

BUS BBUS A

GAB

GBA

CPAB

CPBA

XSAB

SBA

BUS BBUS A

GAB

HGBA

HCPAB

XCPBA

XSAB

LSBA

BUS BBUS A

GAB

HGBA

LCPAB

HorL CPBA

HorL SAB

HSBA

Real-Time Transfer

Bus B to Bus A Real-TimeTransfer

Bus A to Bus B

StoreDatafrom A and/or B Transferred Stored Data

to A and/or B

CY74FCT2652T

Maximum Ratings[3, 4]

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–65°C to +135°C

Supply Voltage to Ground Potential...............–0.5V to +7.0V

DC Input Voltage............................................–0.5V to +7.0V

DC Output Voltage.........................................–0.5V to +7.0V

DC Output Current (Maximum Sink Current/Pin.......)120 mA

Power Dissipation..........................................................0.5W

Static Discharge Voltage............................................>2001V

(per MIL-STD-883, Method 3015)

Operating Range

Range Ambient

Temperature VCC

Commercial –40°C to +85°C 5V ± 5%

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Typ.[5] Max. Unit

VOH Output HIGH Voltage VCC=Min., IOH=−15 mA 2.4 3.3 V

VOL Output LOW Voltage VCC=Min., IOL=12 mA 0.3 0.55 V

ROUT Output Resistance VCC=Min., IOL=12 mA 20 25 40 Ω

VIH Input HIGH Voltage 2.0 V

VIL Input LOW Voltage 0.8 V

VHHysteresis[6] All inputs 0.2 V

VIK Input Clamp Diode Voltage VCC=Min., IIN=−18 mA –0.7 –1.2 V

IIH Input HIGH Current VCC=Max., VIN=VCC 5µA

IIH Input HIGH Current VCC=Max., VIN=2.7V ±1µA

IIL Input LOW Current VCC=Max., VIN=0.5V ±1µA

IOZH Off State HIGH-Level Output

Current VCC=Max., VOUT=2.7V 10 µA

IOZL Off State LOW-Level Output

Current VCC=Max., VOUT=0.5V –10 µA

IOS Output Short Circuit Current[7] VCC=Max., VOUT=0.0V –60 –120 –225 mA

IOFF Power-Off Disable VCC=0V, VOUT=4.5V ±1µA

Capacitance[6]

Parameter Description Test Conditions Typ.[5] Max. Unit

CIN Input Capacitance 5 10 pF

COUT Output Capacitance 9 12 pF

Notes:

2. The data output functions may be enabled or disabled by various signals at the GAB or GBA inputs. Data input functions are always enabled, i.e., data at the

bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.

3. Unless otherwise noted, these limits are over the operating free-air temperature range.

4. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.

5. Typical values are at VCC=5.0V, TA=+25˚C ambient.

6. This parameter is speciﬁed but not tested.

7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample

and hold techniques are preferable in order to minimize internal chip heating and more accurately reﬂect operational values. Otherwise prolonged shorting

of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter

tests, IOS tests should be performed last.

CY74FCT2652T

Power Supply Characteristics

Parameter Description Test Conditions Typ.[5] Max. Unit

ICC Quiescent Power Supply Current VCC=Max., VIN ≤0.2V, VIN ≥VCC-0.2V 0.1 0.2 mA

∆ICC Quiescent Power Supply Current

(TTL inputs HIGH) VCC=Max., VIN=3.4V,[8]

f1=0, Outputs Open 0.5 2.0 mA

ICCD Dynamic Power Supply Current[9] VCC=Max., One Input Toggling,

50% Duty Cycle, Outputs Open,

GAB=GND, GBA=GND,

VIN ≤0.2V or VIN ≥VCC-0.2V

0.06 0.12 mA/M

ICTotal Power Supply Current[10] VCC=Max., f0=10 MHz,

50% Duty Cycle, Outputs Open,

One Bit Toggling at f1=5 MHz,

GAB=GND, GBA=GND, SAB=CPAB=GND

SBA=VCC, VIN ≤0.2V or VIN≥VCC-0.2V

0.7 1.4 mA

VCC=Max., f0=10 MHz,

50% Duty Cycle, Outputs Open,

One Bit Toggling at f1=5 MHz,

GAB=GND, GBA=GND, SAB=CPAB=GND

SBA=VCC, VIN =3.4V or VIN =GND

1.2 3.4 mA

VCC=Max., f0=10 MHz,

50% Duty Cycle, Outputs Open,

Eight Bits Toggling at f1=5 MHz,

GAB=GBA=GND, SAB=CPAB=GND

SBA=VCC, VIN ≤0.2V or VIN ≥VCC-0.2V

2.8 5.6[11] mA

VCC=Max., f0=10 MHz, 50% Duty Cycle,

Outputs Open,

Eight Bits Toggling at f1=5 MHz,

GAB=GBA=GND, SAB=CPAB=GND

SBA= VCC, VIN= 3.4V or VIN = GND

5.1 14.6[11] mA

Notes:

8. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.

9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.

10. IC=I

QUIESCENT + IINPUTS + IDYNAMIC

IC=I

CC+∆ICCDHNT+ICCD(f0/2 + f1N1)

ICC = Quiescent Current with CMOS input levels

∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)

DH= Duty Cycle for TTL inputs HIGH

NT= Number of TTL inputs at DH

ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)

f0= Clock frequency for registered devices, otherwise zero

f1= Input signal frequency

N1= Number of inputs changing at f1

All currents are in milliamps and all frequencies are in megahertz.

11. Values for these conditions are examples of the ICC formula. These limits are speciﬁed but not tested.

CY74FCT2652T

Document #: 38-00344-B

Switching Characteristics[12] Over the Operating Range[13 ]

Parameter Description CY74FCT2652AT CY74FCT2652CT Fig.

No.[14]

Min. Max. Min. Max. Unit

tPLH

tPHL Propagation Delay

Bus to Bus 1.5 6.3 1.5 5.4 ns 1, 3

tPZH

tPZL Output Enable Time Enable to Bus 1.5 9.8 1.5 7.8 ns 1, 7, 8

tPHZ

tPLZ Output Disable Time Enable to Bus 1.5 6.3 1.5 6.3 ns 1, 7, 8

tPLH

tPHL Propagation Delay

Clock to Bus 1.5 6.3 1.5 5.7 ns 1, 5

tPLH

tPHL Propagation Delay

SBA or SAB to A or B 1.5 7.7 1.5 6.2 ns 1, 5

tSSet-Up Time

HIGH or LOW

Bus to Clock

2.0 2.0 ns 4

tHHold Time HIGH or LOW

Bus to Clock 1.5 1.5 ns 4

tWClock Pulse Width,[15]

HIGH or LOW 5.0 5.0 ns 5

Ordering Information

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

5.4 CY74FCT2652CTQCT Q13 24-Lead (150-Mil) QSOP Commercial

6.3 CY74FCT2652ATQCT Q13 24-Lead (150-Mil) QSOP Commercial

Notes:

12. AC Characteristics speciﬁed with CL=50 pF as shown in Figure 1 in “Parameter Measurement Information” in the General Information section.

13. Minimum limits are speciﬁed but not tested on Propagation Delays.

14. See “Parameter Measurement Information” in the General Information section.

15. With one data channel toggling, tW(L)=tW(H)=4.0 ns and tr=tf=1.0 ns.

CY74FCT2652T

Package Diagrams

24-Lead Quarter Size Outline Q13

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