EFR32BG12 Blue Gecko Bluetooth ®Low

Energy SoC Family Data Sheet

The Blue Gecko Bluetooth Low Energy family of SoCs is part of

the Wireless Gecko portfolio. Blue Gecko SoCs are ideal for ena-

bling energy-friendly Bluetooth 5 networking for IoT devices.

The single-die solution provides industry-leading energy efficiency, ultra-fast wakeup

times, a scalable power amplifier, an integrated balun and no-compromise MCU fea-

Blue Gecko applications include:

• 12-channel Peripheral Reflex System,

Low-Energy Sensor Interface & Multi-

channel Capacitive Sense Interface

• Autonomous Hardware Crypto Accelerator

and True Random Number Generator

• Integrated PA with up to 19 dBm transmit

power for 2.4 GHz and 20 dBm for Sub-

GHz radios

• Integrated balun for 2.4 GHz

• Commercial and Retail Lighting and Sensing

Timers and Triggers

Real Time

Counter and

Serial

I/O Ports Analog I/F

Low Energy

External

General

Purpose I/O

Pin Wakeup

EM3—StopEM2—Deep SleepEM1—Sleep EM4—Hibernate EM4—ShutoffEM0—Active

Clock Management

Capacitive Sense

Sensor Interface Op-Amp

The EFR32BG12 highlighted features are listed below.

DSP instruction and floating-point unit for efficient signal

• Embedded Trace Macrocell (ETM) for advanced debugging

• Up to 1024 kB flash program memory

• Up to 256 kB RAM data memory

• 2.4 GHz and Sub-GHz radio operation

• 1.5 μA EM2 DeepSleep current (16 kB RAM retention and

RTCC running from LFRCO)

• Wake on Radio with signal strength detection, preamble

pattern detection, frame detection and timeout

• -95.2 dBm sensitivity @ 1 Mbit/s GFSK

• -91.3 dBm sensitivity @ 2 Mbit/s GFSK

• -120.6 dBm sensitivity at 2.4 kbps GFSK (868 MHz)

• Proprietary Protocols

• Wireless M-Bus (OPNs supporting Sub-GHz)

• Low Power Wide Area Networks (OPNs supporting Sub-

• General Purpose CRC

• True Random Number Generator

• Hardware Cryptographic Acceleration for AES 128/256,

SHA-1, SHA-2 (SHA-224 and SHA-256) and ECC

• 3 + 4 Compare/Capture/PWM channels

EFR32BG12P433F1024GL125-B • Bluetooth Low

• 2.4 GHz @ 19 dBm

• Sub-GHz @ 20 dBm

EFR32BG12P433F1024GM48-B • Bluetooth Low

• 2.4 GHz @ 19 dBm

EFR32BG12P332F1024GL125-B • Bluetooth Low

2.4 GHz @ 10 dBm 1024 256 65 BGA125

EFR32BG12P332F1024GM48-B • Bluetooth Low

2.4 GHz @ 10 dBm 1024 256 31 QFN48

EFR32BG12P232F1024GL125-B • Bluetooth Low

2.4 GHz @ 10 dBm 1024 128 65 BGA125

EFR32BG12P132F1024GM48-B • Bluetooth Low

2.4 GHz @ 0 dBm 1024 128 31 QFN48

Tape and Reel (Optional)

Pin Count

Flash Memory Size in kB

Device Configuration

Port K

Port J

Port I

Port F

Port A

Mux & FB

DC-DC

Debug Signals

Serial Wire

and ETM

The 2.4 GHz antenna interface consists of two pins (2G4RF_IOP and 2G4RF_ION) that interface directly to the on-chip BALUN. The

sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple samples.

The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide range of

The CSEN module is a dedicated Capacitive Sensing block for implementing touch-sensitive user interface elements such a switches

and sliders. The CSEN module uses a charge ramping measurement technique, which provides robust sensing even in adverse condi-

multiple pins and store results to memory through DMA. Several channels can also be shorted together to measure the combined ca-

pacitance or implement wake-on-touch from very low energy modes. Hardware includes a digital accumulator and an averaging filter,

as well as digital threshold comparators to reduce software overhead.

ended channel, or two opamps are used to provide differential outputs. The VDAC may be used for a number of different applications

such as sensor interfaces or sound output. The VDAC can generate high-resolution analog signals while the MCU is operating at low

frequencies and with low total power consumption. Using DMA and a timer, the VDAC can be used to generate waveforms without any

CPU intervention. The VDAC is available in all energy modes down to and including EM3.

The opamps are low power amplifiers with a high degree of flexibility targeting a wide variety of standard opamp application areas. With

flexible built-in programming for gain and interconnection they can be configured to support multiple common opamp functions. All pins

are also available externally for filter configurations. Each opamp has a rail to rail input and a rail to rail output. They can be used in

conjunction with the VDAC module or in stand-alone configurations. The opamps save energy, PCB space, and cost as compared with

standalone opamps because they are integrated on-chip.

• ARM Cortex-M4 RISC processor achieving 1.25 Dhrystone MIPS/MHz

• Memory Protection Unit (MPU) supporting up to 8 memory segments

• Up to 1024 kB flash program memory

• Up to 256 kB RAM data memory

• Configuration and event handling of all modules

• 2-pin Serial-Wire debug interface

from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code

is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a

The Linked Direct Memory Access (LDMA) controller allows the system to perform memory operations independently of software. This

device specific implementation of the features. Remaining modules support full configuration.

WTIMER0 with DTI WTIM0_CC[2:0], WTIM0_CDTI[2:0]

• Typical values are based on TAMB=25 °C and VDD= 3.3 V, by production test and/or technology characterization.

• Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output pow-

er-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna.

• Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature,

unless stated otherwise.

Refer to 4.1.2.1 General Operating Conditions for more details about operational supply and temperature limits.

the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure

to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and relia-

Voltage on HFXO pins VHFXOPIN -0.3 — 1.4 V

Input RF level on pins

2G4RF_IOP and

Voltage differential between

RF pins (2G4RF_IOP -

Absolute voltage on RF pins

Total current into VDD power

Total current into VSS

ground lines

Current per I/O pin IIOMAX Sink — — 50 mA

Current for all I/O pins IIOALLMAX Sink — — 200 mA

Junction temperature TJ-G grade devices -40 — 105 °C

• IOVDD ≤ AVDD

• RFVDD ≤ AVDD

• PAVDD ≤ AVDD

Operating ambient tempera-

IOVDD operating supply volt-

age (All IOVDD pins)

DECOUPLE output capaci-

Difference between AVDD

and VREGVDD, ABS(AVDD-

HFCORECLK frequency fCORE VSCALE2, MODE = WS1 — — 40 MHz

3. VREGVDD must be tied to AVDD. Both VREGVDD and AVDD minimum voltages must be satisfied for the part to operate. .

4. The system designer should consult the characteristic specs of the capacitor used on DECOUPLE to ensure its capacitance val-

Thermal Resistance THETAJA QFN48 Package, 2-Layer PCB,

Minimum and maximum values in this table represent the worst conditions across supply voltage and process variation at T = 25 °C.

Current consumption in EM1

mode with all peripherals dis-

Current consumption in EM1

mode with all peripherals dis-

abled and voltage scaling

Current consumption in EM3

mode, with voltage scaling

Current consumption in

EM4H mode, with voltage

scaling enabled

°C. Minimum and maximum values in this table represent the worst conditions across supply voltage and process variation at T = 25

reception (MCU in EM1 @

transmit mode (MCU in EM1

Wakeup time from EM1 tEM1_WU — 3 — AHB

Wake up from EM2 tEM2_WU Code execution from flash — 10.1 — μs

3. Scaling down from VSCALE2 to VSCALE0 requires approximately 2.8 μs + 29 HFCLKs.

4. Scaling up from VSCALE0 to VSCALE2 requires approximately 30.3 μs + 28 HFCLKs.

DVDD BOD threshold VDVDDBOD DVDD rising — — 1.62 V

DVDD BOD hysteresis VDVDDBOD_HYST — 18 — mV

DVDD BOD response time tDVDDBOD_DELAY Supply drops at 0.1V/μs rate — 2.4 — μs

AVDD BOD threshold VAVDDBOD AVDD rising — — 1.8 V

RF synthesizer frequency

LO tuning frequency resolu-

tion with 38.4 MHz crystal

Frequency deviation resolu-

tion with 38.4 MHz crystal

tion with 38.4 MHz crystal

Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.

RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.

Minimum active TX Power POUTMIN CW -30 — dBm

Output power step size POUTSTEP -5 dBm< Output power < 0 dBm — 1 — dB

Output power variation vs

supply at POUTMAX

Output power variation vs

temperature at POUTMAX

Output power variation vs RF

frequency at POUTMAX

RF tuning frequency range FRANGE 2400 — 2483.5 MHz

1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-

RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.

FCC Part 15.109(a)

Level above which

Level below which

1% PER sensitivity SENS2GFSK 2 Mbps 2GFSK signal — -89.6 — dBm

RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.45 GHz. Maximum duty cycle of

In-band spurious emissions,

Emissions of harmonics out-

of-band, per FCC part

Spurious emissions out-of-

band, per FCC part 15.247,

excluding harmonics cap-

Spurious emissions out-of-

band; per ETSI 300.328

Spurious emissions per ETSI