V-Data VDAAA1916 PC-100/CL2 SDRAM Unbuffered DIMM 64Mx64bits SDRAM DIMM based on 32Mx8, 4Bank, 8K Refresh, 3.3V SDRAM General Description Features The VDAAA1916 is 64Mx64 bits Synchronous DRAM Modules, The modules are composed of sixteen 32Mx8 bits CMOS Synchronous DRAMs in TSOP-II 400mil 54pin package and one 2Kbit EEPROM in 8pin TSSOP(TSOP) package on a 168pin glass-epoxy printed circuit board. The V-Data is a Dual In-line Memory Module and is intended for mounting onto 168-pins edge connector sockets. Fully synchronous operation referenced to the positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock. The data paths are internally pipelined to achieve very high bandwidth. *PC-100/CL2 support *Auto refresh and self refresh *8192 refresh cycles / 64ms *Single 3.30.3V power supply *All device pins are compatible with LVTTL interface *Data mask function by DQM *Serial Presence Detect with EEPROM *Module bank : two physical bank *PCB : B6986RAB,Height (28.00mm),double sided component, Four layers Ordering Information. Part No. Frequency Bank Ref. Package VDAAA1916 100Mhz/CL2 4 Banks 8K TSOP II Pin Assignment FRONT SIDE BACK SIDE PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME 1 VSS 22 NC 43 VSS 64 VSS 85 VSS 106 NC 127 VSS 148 VSS 2 3 DQ0 DQ1 23 24 VSS NC 44 45 65 66 DQ21 DQ22 86 87 DQ32 107 DQ33 108 4 5 DQ2 DQ3 25 26 NC VCC 46 DQM2 67 47 DQM3 68 DQ23 VCC 88 89 DQ34 109 NC 130 DQM6 151 DQ55 DQ35 110 VCC 131 DQM7 152 VCC 6 7 VCC DQ4 27 /WE 48 28 DQM0 49 NC VCC 69 70 DQ24 DQ25 90 91 VCC 111 /CAS 132 NC 153 DQ56 DQ36 112 DQM4 133 VCC 154 DQ57 8 9 DQ5 DQ6 29 DQM1 50 30 /CS0 51 NC NC 71 72 DQ26 DQ27 92 93 DQ37 113 DQM5 134 DQ38 114 NC 135 NC NC 155 DQ58 156 DQ59 10 11 DQ7 DQ8 31 32 NC VSS 52 53 NC NC 73 74 VCC DQ28 94 95 DQ39 115 /RAS 136 DQ40 116 VSS 137 NC NC 157 VCC 158 DQ60 12 13 VSS DQ9 33 34 A0 A2 54 55 VSS DQ16 75 76 DQ29 DQ30 96 97 VSS 117 DQ41 118 A1 A3 138 VSS 159 DQ61 139 DQ48 160 DQ62 14 15 DQ10 DQ11 35 36 A4 A6 56 57 DQ17 DQ18 77 78 DQ31 VSS 98 99 DQ42 119 DQ43 120 A5 A7 140 DQ49 161 DQ63 141 DQ50 162 VSS 16 17 DQ12 DQ13 37 A8 58 38 A10/AP 59 DQ19 VCC 79 80 CK2 NC 100 DQ44 121 101 DQ45 122 142 DQ51 163 143 VSS 164 CK3 NC 18 19 VCC DQ14 39 40 BA1 VCC 60 61 DQ20 NC 81 82 WP SDA 102 VCC 123 A11 144 DQ52 165 103 DQ46 124 VCC 145 NC 166 SA0 SA1 20 21 DQ15 NC 41 42 VCC CK0 62 63 NC NC 83 84 SCL 104 DQ47 125 VCC 105 NC 126 Rev 1 April, 2001 NC /CS2 1 VSS NC A9 BA0 CK1 NC 128 CKE0 149 DQ53 129 NC 150 DQ54 146 147 NC NC 167 SA2 168 VCC V-Data VDAAA1916 Pin Description PIN NAME FUNCTION CK0~2 System Clock Active on the positive edge to sample all inputs. CKE0~1 Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least on cycle prior new command. Disable input buffers for power down in standby /CS0~3 Chip Select Disables or Enables device operation by masking or enabling all input except CK, CKE and L(U)DQM A0~A12 Address BA0~BA1 Banks Select Row / Column address are multiplexed on the same pins. Selects bank to be activated during row address latch time. Selects bank for read / write during column address latch time. DQ0~DQ63 Data DQM0~7 Data inputs / outputs are multiplexed on the same pins. Data Mask Makes data output Hi-Z, /RAS Row Address Strobe Latches row addresses on the positive edge of the CLK with /RAS low /CAS Column Address Strobe Latches Column addresses on the positive edge of the CLK with /CAS low /WE Write Enable Enables write operation and row recharge. VDD/VSS Power Supply/Ground Power and Ground for the input buffers and the core logic. SDA Serial data I/O EEPROM serial data I/O SCL Serial clock EEPROM clock input Address in EEPROM EEPROM address input WP Write Protect for EEPROM Write Protect for Serial Presence Detect on DIMM NC No Connection This pin is recommended to be left No Connection on the device. SA0~2 Rev 1 April, 2001 2 V-Data VDAAA1916 Block Diagram /S3 /S2 /S1 /S1 DQM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM /CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 D10 DQM /CS D2 DQM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM /CS D8 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM /CS D0 DQM3 DQM /CS D11 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM /CS D3 DQM1 DQM /CS D9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM /CS D1 DQM4 DQM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM /CS D14 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM /CS D6 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM /CS D12 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM /CS D4 DQM5 DQM7 DQM /CS D15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM /CS D7 /CAS : D0 ~D15 /WE /WE : D0 ~D15 A0~A11 A0~A11:D0~D15 BA0/BA1 BA0/BA1:D0~D15 VCC D0~D15 VSS D0~D15 D13 CK : 2 SDRAMs /RAS : D0 ~D15 /RAS /CAS DQM /CS CK0 10 Ohm CK : 2 SDRAMs CK : 2 SDRAMs 10 Ohm SPD SCL WP 47K Ohms Rev 1 April, 2001 SDA A0 A1 A2 SA0 SA1 SA2 3 CK3 CK : 2 SDRAMs 10 Ohm VCC CKE : D8~D15 CK : 2 SDRAMs 10 Ohm 3.3 pF CK : 2 SDRAMs CKE : D0~D7 10K Ohm D5 CK : 2 SDRAMs 3.3 pF 3.3 pF CKE1 DQM /CS CK2 CK : 2 SDRAMs CK1 CKE0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 3.3 pF V-Data VDAAA1916 Absolute Maximum Ratings Parameter Symbol Value Unit VIN, Vout -1.0 ~ 4.6 V VDD, VDDQ -1.0 ~ 4.6 V TSTG -55 ~ +150 Power dissipation PD 16 W Short circuit current IOS 50 mA Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC Operating Condition Voltage referenced to Vss = 0V, TA = 0 to 70 Parameter Symbol Min Typ Max Unit VDD, VDDQ 3.0 3.3 3.6 V Input logic high voltage VIH 2.0 3.0 VDD+0.3 V 1 Input logic low voltage VIL -0.3 0 0.8 V 2 Output logic high voltage VOH 2.4 - - V IOH=-2mA Output logic low voltage VOL - - 0.4 V IOL=2mA Input leakage current IIL -5 - 5 uA 3 Output leakage current IOL -5 - 5 uA 4 Note Supply voltage Note Note : 1. VIH (max)=4.6V AC for pulse width 10ns acceptable. 2.VIL(min)=-1.5V AC for pulse width 10ns acceptable. 3.Any input 0V VIN VDD + 0.3V, all other pins are not under test = 0V. 4.Dout is disabled, 0V VOUT VDD. AC Operating Condition Voltage referenced to Vss = 0V, TA = 0 to 70 Parameter Symbol Value Unit VIH / VIL 2.4 / 0.4 V Vtrip 1.4 V Input rise / fall time TR / tF 1 Ns Output timing measurement reference level Voutfef 1.4 V CL 50 pF AC input high / low level voltage Input timing measurement reference level voltage Output load capacitance for access time measurement Note: 1. 3.15V VDD 2 3.6V 2. Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF). For details, refer to AC/DC output load circuit. Rev 1 April, 2001 4 V-Data VDAAA1916 Capacitance TA=25, f-=1Mhz, VDD=3.3V Parameter Pin Input capacitance Symbol Min Max Unit CLK Cl1 25 40 pF A0~A11,BA0,BA1,CKE,/CS,/RAS, Cl2 40 55 pF CI/O 5 15 pF /CAS,/WE,DQM Data input / output capacitance DQM Output load circuit 3.3 V 1200 ohms VOH(DC) = 2.4V,I OH= -2mA Output VOL(DC) = 0.4V,I OL= 2mA 50 pF 870 ohms DC Characteristics I Parameter Symbol Min Max Unit Note Input leakage current ILI -1 1 uA 1 Output leakage current ILO -1 1 uA 2 Output high voltage VOH 2.4 - V IOH = -4mA Output low voltage VOL - 0.4 V IOL = 4mA Note : 1.VIN = 0 TO 3.6V, All other pins are not tested under VIN = 0V. 2.DOUT is disabled, VOUT = 0 to 3.6. Rev 1 April, 2001 5 V-Data VDAAA1916 DC Characteristics II Parameter Symbol Test condition Speed Unit Note 1,400 mA 1 Burst length=1, One bank active Operating Current Precharge standby IDD1 IDD2P tRCtRC(min),IOL=0mA CKEVIL(max), tCK=min 32 current in power down mode mA IDD2PS CKEVIL(max), tCK= 32 CKEVIH(min), /CSVIH(min), tCK=min input signals are Precharge standby IDD2N changed one time during 2clks. current in Non power All other pins VDD-0.2V or down mode 0.2V 320 mA CKEVIH(min), tCK= IDD2NS 160 Input signals are stable. Active standby IDD3P CKEVIL(max), tCK=min 120 mA current in power down mode IDD3PS CKEVIL(max), tCK= 120 CKEVIH(min), /CSVIH(min), tCK=min input signals are Active standby IDD3N changed one time during 2clks. current in Non power All other pins VDD-0.2V or down mode 0.2V 640 mA CKEVIH(min), tCK= IDD3NS 640 Input signals are stable. tCKtCK(min),IOL=0 mA Burst mode operating IDD4 current 1,600 mA 1 3,840 mA 2 32 mA All banks active tRRCtRRC(min), All banks Auto refresh current IDD5 active Self refresh current IDD6 CKE0.2V Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open. 2. Min. of tRRC is shown at AC characteristics. Rev 1 April, 2001 6 V-Data VDAAA1916 AC Characteristics VDAAA1916 Parameter Symbol Unit Min Note Max System clock /CAS Latency = 3 tCK3 7.5 Cycle time /CAS Latency = 2 tCK2 10 Clock high pulse width tCHW 2.5 ns 1 Clock low pulse width tCLW 2.5 ns 1 Access time form /CAS Latency = 3 tAC3 5.4 ns 2 clock /CAS Latency = 2 tAC2 6 Operation tRC 65 Auto Refresh tRRC 65 /RAS to /CAS delay tRCD 20 /RAS active time tRAS 45 /RAS precharge time tRP 20 ns /RAS to /RAS bank active delay tRRD 15 ns /CAS to /CAS delay tCCD 1 CLK Write command to data - in delay tWTL 0 CLK Data - in to precharge command tDPL 2 CLK Data - in active command tDAL 5 CLK DQM to data - out Hi-Z tDQZ 2 CLK DQM to data - in mask tDQM 0 CLK Data - out hold time tOH 2.7 ns Data - input setup time tDS 1.5 ns 1 Data - input hold time tDH 0.8 ns 1 Address setup time tAS 1.5 ns 1 Address hold time tAH 0.8 ns 1 CKE setup time tCKS 1.5 ns 1 CKE hold time tCKH 0.8 ns 1 Command setup time tCS 1.5 ns 1 Command hold time tCH 0.8 ns 1 CLK to data output in low Z-time tOLZ 1 ns MRS to new command tMRD 2 CLK Power down exit time tPDE 1 CLK Self refresh exit time tSRE 1 CLK Refresh time tREF 1000 /RAS cycle time ns ns 100K 64 Note : 1. Assume tR / tF (input rise and fall time) is 1 ns. 2. Access times to be measured with input signals of 1v / ns edge rate. 3.A new command can be given tRRC after self refresh exit. Rev 1 April, 2001 ns 7 ns ms 3 V-Data VDAAA1916 Command Truth-Table Command CKEn-1 CKEn /CS /RAS /CAS /WE DQM Mode Register Set H X L L L L X OP code H X X X No Operation H X X X L H H H Bank Active H X L L H H X H X L H L H X ADDR A10/AP RA Read BA V L CA Read with Auto Precharge Write H X L H L L X CA Write with Auto Precharge H X L L H L X Precharge select Bank Burst Stop H DQM H Auto Refresh H H L L L Entry H L L L X L H H H X Exit L H L X X L H X X X H X X X Precharge L H H H Power down H X X X L H H H H X X X L V V V Exit Rev 1 April, 2001 L X X L X H X X L Clock Suspend V H H H L X H L X V H H H X L Entry V X X X Self Refresh Exit L H Precharge All Bank Entry V H X H X 8 X X V-Data VDAAA1916 Package Information Units : Inches (Millimeters) 5.250 (133.350) R 0.079 (R 2.000) 0.157 0.004 (4.000 0.100) 0.700 (17.780) 0.118 (3.000) 0.350 (8.890) B A .118DIA 0.004 (3.000DIA 0.100) 0.250 (6.350) 0.250 (6.350) .450 (11.430) C 0.100 Min (2.540 Min) 1.102 (28.000) 0.089 (2.26) 5.014 (127.350) 0.118 (3.000) 1.450 (36.830) 2.150 (54.61) 4.550 (115.57) 0.200 Min (5.08 Min) 0.150 Max (3.81 Max) 0.100 Min 0.250 (6.350) 0.250 (6.350) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100) Detail A Rev 1 April, 2001 (2.540 Min) 0.050 0.0039 (1.270 0.10) 0.039 0.002 (1.000 0.050) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100) Detail B 0.008 0.006 (0.200 0.150) 0.050 (1.270) Detail C 9