S1C60N01 - Epson Company - Datasheet.Live

MF943-03

Technical Manual

CMOS 4-BIT SINGLE CHIP MICROCOMPUTER

S1C60N01 Technical Hardware/S1C60N01 Technical Software

S1C60N01

NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko

Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any

liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or

circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such

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products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from

the Ministry of International Trade and Industry or other approval from another government agency.

PREFACE

This manual is individualy described about the hardware and the software

of the S1C60N01.

I. S1C60N01 Technical Hardware

This part explains the function of the S1C60N01, the circuit configu-

rations, and details the controlling method.

II. S1C60N01 Technical Software

This part explains the programming method of the S1C60N01.

Hardware

Software

The information of the product number change

Configuration of product number

Devices

Comparison table between new and previous number

S1C60 Family processors

Starting April 1, 2001, the product number will be changed as listed below. To order from April 1,

2001 please use the new product number. For further information, please contact Epson sales

representative.

S1 C60N01 F0A01 Packing specification

Specification

Package (D: die form; F: QFP)

Model number

Model name (C: microcomputer, digital products)

Product classification (S1: semiconductor)

Development tools

S5U1 C60R08 D1 1Packing specification

Version (1: Version 1 ∗2)

Tool type (D1: Development Tool ∗1)

Corresponding model number (60R08: for S1C60R08)

Tool classification (C: microcomputer use)

Product classification

(S5U1: development tool for semiconductor products)

∗1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.)

∗2: Actual versions are not written in the manuals.

Previous No.

E0C6001

E0C6002

E0C6003

E0C6004

E0C6005

E0C6006

E0C6007

E0C6008

E0C6009

E0C6011

E0C6013

E0C6014

E0C60R08

New No.

S1C60N01

S1C60N02

S1C60N03

S1C60N04

S1C60N05

S1C60N06

S1C60N07

S1C60N08

S1C60N09

S1C60N11

S1C60N13

S1C60140

S1C60R08

S1C62 Family processors

Previous No.

E0C621A

E0C6215

E0C621C

E0C6S27

E0C6S37

E0C623A

E0C623E

E0C6S32

E0C6233

E0C6235

E0C623B

E0C6244

E0C624A

E0C6S46

New No.

S1C621A0

S1C62150

S1C621C0

S1C6S2N7

S1C6S3N7

S1C6N3A0

S1C6N3E0

S1C6S3N2

S1C62N33

S1C62N35

S1C6N3B0

S1C62440

S1C624A0

S1C6S460

Previous No.

E0C6247

E0C6248

E0C6S48

E0C624C

E0C6251

E0C6256

E0C6292

E0C6262

E0C6266

E0C6274

E0C6281

E0C6282

E0C62M2

E0C62T3

New No.

S1C62470

S1C62480

S1C6S480

S1C624C0

S1C62N51

S1C62560

S1C62920

S1C62N62

S1C62660

S1C62740

S1C62N81

S1C62N82

S1C62M20

S1C62T30

Comparison table between new and previous number of development tools

Development tools for the S1C60/62 Family

Previous No.

ASM62

DEV6001

DEV6002

DEV6003

DEV6004

DEV6005

DEV6006

DEV6007

DEV6008

DEV6009

DEV6011

DEV60R08

DEV621A

DEV621C

DEV623B

DEV6244

DEV624A

DEV624C

DEV6248

DEV6247

New No.

S5U1C62000A

S5U1C60N01D

S5U1C60N02D

S5U1C60N03D

S5U1C60N04D

S5U1C60N05D

S5U1C60N06D

S5U1C60N07D

S5U1C60N08D

S5U1C60N09D

S5U1C60N11D

S5U1C60R08D

S5U1C621A0D

S5U1C621C0D

S5U1C623B0D

S5U1C62440D

S5U1C624A0D

S5U1C624C0D

S5U1C62480D

S5U1C62470D

Previous No.

DEV6262

DEV6266

DEV6274

DEV6292

DEV62M2

DEV6233

DEV6235

DEV6251

DEV6256

DEV6281

DEV6282

DEV6S27

DEV6S32

DEV6S37

EVA6008

EVA6011

EVA621AR

EVA621C

EVA6237

EVA623A

New No.

S5U1C62620D

S5U1C62660D

S5U1C62740D

S5U1C62920D

S5U1C62M20D

S5U1C62N33D

S5U1C62N35D

S5U1C62N51D

S5U1C62560D

S5U1C62N81D

S5U1C62N82D

S5U1C6S2N7D

S5U1C6S3N2D

S5U1C6S3N7D

S5U1C60N08E

S5U1C60N11E

S5U1C621A0E2

S5U1C621C0E

S5U1C62N37E

S5U1C623A0E

Previous No.

EVA623B

EVA623E

EVA6247

EVA6248

EVA6251R

EVA6256

EVA6262

EVA6266

EVA6274

EVA6281

EVA6282

EVA62M1

EVA62T3

EVA6S27

EVA6S32R

ICE62R

KIT6003

KIT6004

KIT6007

New No.

S5U1C623B0E

S5U1C623E0E

S5U1C62470E

S5U1C62480E

S5U1C62N51E1

S5U1C62N56E

S5U1C62620E

S5U1C62660E

S5U1C62740E

S5U1C62N81E

S5U1C62N82E

S5U1C62M10E

S5U1C62T30E

S5U1C6S2N7E

S5U1C6S3N2E2

S5U1C62000H

S5U1C60N03K

S5U1C60N04K

S5U1C60N07K

S1C60N01

Technical Hardware

Hardware

S1C60N01 TECHNICAL HARDWARE EPSON I-i

CONTENTS

CHAPTER 1 INTRODUCTION............................................................... I-1

1.1 Configuration ................................................................... I-1

1.2 Features .......................................................................... I-2

1.3 Block Diagram ................................................................. I-3

1.4 Pin Layout Diagram......................................................... I-4

1.5 Pin Description ................................................................ I-5

CHAPTER 2 POWER SUPPLY AND INITIAL RESET ................................ I-6

2.1 Power Supply .................................................................. I-6

2.2 Initial Reset...................................................................... I-8

Oscillation detection circuit...................................... I-9

Reset pin (RESET) .................................................... I-9

Simultaneous high input to input ports (K00–K03) ... I-9

Internal register following initialization.................... I-10

2.3 Test Pin (TEST).............................................................. I-10

CHAPTER 3 CPU, ROM, RAM ............................................................ I-11

3.1 CPU................................................................................ I-11

3.2 ROM ............................................................................... I-12

3.3 RAM ............................................................................... I-12

I-ii EPSON S1C60N01 TECHNICAL HARDWARE

CONTENTS

CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION ...................... I-13

4.1 Memory Map .................................................................. I-13

4.2 Oscillation Circuit............................................................ I-18

Crystal oscillation circuit......................................... I-18

CR oscillation circuit ............................................... I-19

4.3 Input Ports (K00–K03).................................................... I-20

Configuration of input port...................................... I-20

Interrupt function ................................................... I-20

Mask option ............................................................ I-22

Control of input port ............................................... I-23

4.4 Output Ports (R00, R01)................................................. I-25

Configuration of output port.................................... I-25

Mask option ............................................................ I-26

Control of output port ............................................. I-28

4.5 I/O Ports (P00–P03) ....................................................... I-31

Configuration of I/O port ........................................ I-31

I/O control register and I/O mode........................... I-32

Mask option ............................................................ I-32

Control of I/O port .................................................. I-33

4.6 LCD Driver (COM0–COM3, SEG0–SEG19) .................. I-35

Configuration of LCD driver..................................... I-35

Cadence adjustment of oscillation frequency ........... I-41

Mask option (segment allocation)............................. I-42

Control of LCD driver .............................................. I-44

4.7 Clock Timer .................................................................... I-45

Configuration of clock timer .................................... I-45

Interrupt function ................................................... I-46

Control of clock timer.............................................. I-47

4.8 Heavy Load Protection Function .................................... I-49

Operation of heavy load protection function ............ I-49

Control of heavy load protection function ................ I-50

Hardware

S1C60N01 TECHNICAL HARDWARE EPSON I-iii

CONTENTS

4.9 Interrupt and HALT......................................................... I-51

Interrupt factors...................................................... I-53

Specific masks and factor flags for interrupt............ I-54

Interrupt vectors ..................................................... I-54

Control of interrupt ................................................. I-55

CHAPTER 5 BASIC EXTERNAL WIRING DIAGRAM.............................I-56

CHAPTER 6 ELECTRICAL CHARACTERISTICS .................................... I-58

6.1 Absolute Maximum Rating ............................................. I-58

6.2 Recommended Operating Conditions ............................ I-59

6.3 DC Characteristics ......................................................... I-60

6.4 Analog Circuit Characteristics

and Power Current Consumption ................................... I-62

6.5 Oscillation Characteristics .............................................. I-66

CHAPTER 7 PACKAGE ...................................................................... I-68

7.1 Plastic Package.............................................................. I-68

7.2 Ceramic Package for Test Samples............................... I-69

CHAPTER 8 PAD LAYOUT .................................................................. I-70

8.1 Diagram of Pad Layout................................................... I-70

8.2 Pad Coordinates............................................................. I-71

S1C60N01 TECHNICAL HARDWARE EPSON I-1

CHAPTER 1: INTRODUCTION

INTRODUCTION

Each member of the S1C60N01 Series of single chip micro-

computers feature a 4-bit S1C6200B core CPU, 1,024 words

of ROM (12 bits per word), 80 words of RAM (4 bits per

word), an LCD driver, 4 bits for input ports (K00–K03), 2

bits for output ports (R00, R01), one 4-bit I/O port (P00–

P03) and one timer (clock timer).

Because of their low voltage operation and low power con-

sumption, the S1C60N01 Series are ideal for a wide range of

applications.

Configuration

The S1C60N01 Series are configured as follows, depending

on the supply voltage.

CHAPTER 1

1.1

Table 1.1.1

Configuration of the

S1C60N01 Series

Model Supply Voltage Oscillation Circuits

3.0 V

1.5 V

S1C60N01

S1C60L01

Crystal or CR

Supply Voltage Range

1.8–3.6 V

1.2–2.0 V

I-2 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 1: INTRODUCTION

Features

S1C6200B

Crystal or CR oscillation circuit, 32.768 kHz (typ.)

100 instructions

1,024 words ×12 bits

80 words × 4 bits

4 bits (Supplementary pull-down resistors may be used )

2 bits (Piezo buzzer and programmable frequency output

can be driven directry by mask option)

4 bits

20 segments × 4, 3 or 2 common duty

1 system: clock timer

Input port interrupt 1 system

Timer interrupt 1 system

1.5 V (1.2–2.0 V) S1C60L01

3.0 V (1.8–3.6 V) S1C60N01

1.0 µA

(Crystal oscillation CLK = 32.768 kHz, when halted)

2.5 µA

(Crystal oscillation CLK = 32.768 kHz, when executing)

QFP12-48pin (plastic) or chip

1.2

Core CPU

Built-in oscillation circuit

Instruction set

ROM capacity

RAM capacity (data RAM)

Input port

Output port

Input/output port

LCD driver

Timer

Interrupts:External interrupt

Internal interrupt

Supply voltage

Current consumption (typ.)

Supply form

S1C60N01 TECHNICAL HARDWARE EPSON I-3

CHAPTER 1: INTRODUCTION

1.3

Fig. 1.3.1

Block diagram

Power

Controller

LCD

Driver

RAM

80 × 4 Interrupt

Generator

I Port

Test Port

I/O Port

O Port

Timer

Core CPU S1C6200B

ROM

1,024 × 12 OSC System

Reset

Control

RESET

OSC1

COM0

COM3

SEG0

SEG19

VDD

VL1

VL3

VS1

VSS

K00~K03

TEST

P00~P03

R00, R01

OSC2

FOUT

BUZZER

(FOUT/BUZZER)

(BUZZER)

Block Diagram

I-4 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 1: INTRODUCTION

1.4

N.C. = No Connection

OSC2

N.C.

P00

P01

P02

P03

K00

K01

K02

K03

N.C.

R01

R00

SEG19

SEG18

SEG17

SEG16

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

TEST

RESET

SEG9

SEG8

SEG7

SEG6

SEG5

SEG4

SEG3

SEG2

SEG1

SEG0

COM0

COM1

COM2

COM3

OSC1

Pin No Pin Name Pin No Pin Name Pin No Pin No Pin NamePin Name

Fig. 1.4.1

Pin assignment

QFP12-48pin

2536

INDEX

121

Pin Layout Diagram

S1C60N01 TECHNICAL HARDWARE EPSON I-5

CHAPTER 1: INTRODUCTION

1.5

Table 1.5.1 Pin description

Terminal Name

CA, CB

OSC1

OSC2

K00–K03

P00–P03

R00, R01

SEG0–19

COM0–3

RESET

TEST

Pin No.

44, 45

8–11

4–7

14, 13

36–27

24–15

37–40

Input/Output

(I)

–

I/O

Function

Power source (+) terminal

Power source (-) terminal

Oscillation and internal logic system regulated

voltage output terminal

LCD system reducer output terminal (V

× 1/2)

/ LCD system reducer output terminal (V

× 1/3)

LCD system booster output terminal (V

× 2)

/ LCD system reducer output terminal (V

× 2/3)

LCD system booster output terminal (V

× 3)

/ LCD system booster output terminal (V

× 3/2)

Booster capacitor connecting terminal

Crystal or CR oscillation input terminal

Crystal or CR oscillation output terminal

Input terminal

I/O terminal

Output terminal

LCD segment output terminal

(convertible to DC output terminal by mask option)

LCD common output terminal

Initial setting input terminal

Test input terminal

Pin Description

I-6 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

POWER SUPPLY AND INITIAL RESETCHAPTER 2

2.1 Power Supply

With a single external power supply (*1) supplied to VDD

through VSS, the S1C60N01 Series generate the necessary

internal voltages with the regulated voltage circuit (<VS1> for

oscillators and internal circuit) and the voltage booster/

reducer (<VL2, VL3 or VL1, VL3> for LCDs).

When the S1C60N01 LCD power is selected for 4.5 V LCD

panel by mask option, the S1C60N01 short-circuits between

<VL2> and <VSS> in internally, and the voltage booster/

reducer generates <VL1> and <VL3>. When 3.0 V LCD panel

is selected, the S1C60N01 short-circuits between <VL3> and

<VSS>, and the voltage reducer generates <VL1> and <VL2>.

The S1C60L01 short-circuits between <VL1> and <VSS>, and

the voltage booster generates <VL2> and <VL3>.

The voltage <VS1> for the internal circuit that is generated

by the regulated voltage circuit is -1.2 V (VDD standard).

Figure 2.1.1 shows the power supply configuration of the

S1C60N01 Series in each condition.

*1 Supply voltage: S1C60N01.... 3.0 V

S1C60L01 .... 1.5 V

- External loads cannot be driven by the output voltage of the

regulated voltage circuit and the voltage booster/reducer.

- See Chapter 6, "ELECTRICAL CHARACTERISTICS", for

voltage values.

Note

S1C60N01 TECHNICAL HARDWARE EPSON I-7

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

• S1C60N01

4.5 V LCD panel

1/4, 1/3, 1/2 duty, 1/3 bias

Note: VL2 is shorted to VSS inside the IC.

3 V LCD panel 3 V LCD panel

1/4, 1/3, 1/2 duty, 1/3 bias 1/4, 1/3, 1/2 duty, 1/2 bias

• S1C60L01

4.5 V LCD panel 3 V LCD panel

1/4, 1/3, 1/2 duty, 1/3 bias 1/4, 1/3, 1/2 duty, 1/2 bias

Note: VL1 is shorted to VSS inside the IC.

Fig. 2.1.1 External element configuration of power system

Note: VL3 is shorted to VSS inside the IC.

VDD

VS1

VL1

VL2

VL3

VSS

3 V

VDD

VS1

VL1

VL2

VL3

VSS

3 V

VDD

VS1

VL1

VL2

VL3

VSS

3 V

VDD

VS1

VL1

VL2

VL3

VSS

1.5 V

VDD

VS1

VL1

VL2

VL3

VSS

1.5 V

I-8 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

Initial Reset

To initialize the S1C60N01 Series circuits, an initial reset

must be executed. There are three ways of doing this.

(1)Initial reset by the oscillation detection circuit (Note)

(2)External initial reset via the RESET pin

(3)External initial reset by simultaneous high input to pins

K00–K03 (depending on mask option)

Figure 2.2.1 shows the configuration of the initial reset

circuit.

Fig. 2.2.1

Configuration of

initial reset circuit

2.2

Vss

RESET

K03

K02

K01

K00

OSC2

OSC1

Oscillation

circuit

Vss

Oscillation

detection

circuit Noise

rejection

circuit

Initial

reset

Noise

rejection

circuit

Note Be sure to use reset function (2) or (3) at power-on because the

initial reset function by the oscillation detection circuit (1) may not

operate normally depending on the power-on procedure.

S1C60N01 TECHNICAL HARDWARE EPSON I-9

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

The oscillation detection circuit outputs the initial reset

signal at power-on until the crystal oscillation circuit starts

oscillating, or when the crystal oscillation circuit stops

oscillating for some reason.

However, use the following reset functions at power-on

because the initial reset function by the oscillation detection

circuit may not operate normally depending on the power-on

procedure.

An initial reset can be invoked externally by making the

reset pin high. This high level must be maintained for at

least 5 ms (when oscillating frequency, fosc = 32 kHz),

because the initial reset circuit contains a noise rejection

circuit. When the reset pin goes low the CPU begins to

operate.

Another way of invoking an initial reset externally is to input

a high signal simultaneously to the input ports (K00–K03)

selected with the mask option. The specified input port pins

must be kept high for at least 4 sec (when oscillating fre-

quency fosc = 32 kHz), because of the noise rejection circuit.

Table 2.2.1 shows the combinations of input ports (K00–

K03) that can be selected with the mask option.

ANot used

BK00*K01

CK00*K01*K02

DK00*K01*K02*K03

When, for instance, mask option D (K00*K01*K02*K03) is

selected, an initial reset is executed when the signals input

to the four ports K00–K03 are all high at the same time.

If you use this function, make sure that the specified ports

do not go high at the same time during normal operation.

Oscillation detection

circuit

Reset pin (RESET)

Simultaneous high

input to input ports

(K00–K03)

Table 2.2.1

Input port combinations

I-10 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

Internal register fol-

lowing initialization

Table 2.2.2

Initial values

2.3

An initial reset initializes the CPU as shown in the table

below.

CPU Core

Name

Program counter step

Program counter page

New page pointer

Stack pointer

Index register X

Index register Y

General register A

General register B

Interrupt flag

Decimal flag

Zero flag

Carry flag

Signal

PCS

PCP

NPP

Number of Bits

Setting Value

00H

Undefined

Peripheral Circuits

Name

RAM

Display memory

Other peripheral circuit

Number of Bits

80 × 4

20 × 4

–

Setting Value

Undefined

*1: See section 4.1, "Memory Map"

Test Pin (TEST)

This pin is used when IC is inspected for shipment.

During normal operation connect it to VSS.

S1C60N01 TECHNICAL HARDWARE EPSON I-11

CHAPTER 3: CPU, ROM, RAM

CPU, ROM, RAM

CPU

The S1C60N01 Series employs the S1C6200B core CPU, so

that register configuration, instructions, and so forth are

virtually identical to those in other processors in the family

using the S1C6200B. Refer to the "S1C6200/6200A Core

CPU Manual" for details of the S1C6200B.

Note the following points with regard to the S1C60N01

Series:

(1)The SLEEP operation is not provided, so the SLP instruc-

tion cannot be used.

(2)Because the ROM capacity is 1,024 words, 12 bits per

word, bank bits are unnecessary, and PCB and NBP are

not used.

(3)The RAM page is set to 0 only, so the page part (XP, YP)

of the index register that specifies addresses is invalid.

PUSH XP PUSH YP

POP XP POP YP

LD XP,r LD YP,r

LD r,XP LD r,YP

CHAPTER 3

3.1

I-12 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 3: CPU, ROM, RAM

3.2 ROM

The built-in ROM, a mask ROM for the program, has a

capacity of 1,024 × 12-bit steps. The program area is 4

pages (0–3), each consisting of 256 steps (00H–FFH). After

an initial reset, the program start address is page 1, step

00H. The interrupt vector is allocated to page l, steps 01H–

07H.

3.3

Fig. 3.2.1

ROM configuration

RAM

The RAM, a data memory for storing a variety of data, has a

capacity of 80 words, 4-bit words. When programming,

keep the following points in mind:

(1)Part of the data memory is used as stack area when

saving subroutine return addresses and registers, so be

careful not to overlap the data area and stack area.

(2)Subroutine calls and interrupts take up three words on

the stack.

(3)Data memory 000H–00FH is the memory area pointed by

the register pointer (RP).

00H step

07H step

08H step

FFH step

12 bits

Program start address

Interrupt vector area

Bank 0

Program area

0 page

1 page

2 page

3 page

01H step

S1C60N01 TECHNICAL HARDWARE EPSON I-13

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

PERIPHERAL CIRCUITS

AND OPERATION

Peripheral circuits (timer, I/O, and so on) of the S1C60N01

Series are memory mapped. Thus, all the peripheral circuits

can be controlled by using memory operations to access the

I/O memory. The following sections describe how the pe-

ripheral circuits operate.

CHAPTER 4

Memory Map

The data memory of the S1C60N01 Series has an address

space of 113 words, of which 32 words are allocated to

display memory and 13 words, to I/O memory. Figure 4.1.1

show the overall memory map for the S1C60N01 Series, and

Tables 4.1.1(a)–(d), the memory maps for the peripheral

circuits (I/O space).

4.1

Unused area

Fig. 4.1.1

Memory map

Note Memory is not mounted in unused area within the memory map

and in memory area not indicated in this chapter. For this reason,

normal operation cannot be assured for programs that have been

prepared with access to these areas.

Address

Page High

Low 0123456789ABCDEF

M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF

RAM area (000H–04FH)

80 words x 4 bits (R/W)

Display memory area (090H–0AFH)

32 words x 4 bits (Write only)

I/O memory area Tables 4.1.1(a)–(d)

I-14 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1(a) I/O memory map

* 1 Initial value following initial reset

* 2 Not set in the circuit

* 3 Undefined

* 4 Reset (0) immediately after being read

* 5 Constantly 0 when being read

* 6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name SR

0E0H

0E4H

0E8H

K03 K02 K01 K00

TM3 TM2 TM1 TM0

EIK03 EIK02 EIK01 EIK00

R/W

K03

K02

K01

K00

–

TM3

TM2

TM1

TM0

–

EIK03

EIK02

EIK01

EIK00

Enable

Mask

Timer data (clock timer 2 Hz)

Timer data (clock timer 4 Hz)

Timer data (clock timer 8 Hz)

Timer data (clock timer 16 Hz)

Input port (K00–K03)

High

Low

Interrupt mask register (K03)

Interrupt mask register (K02)

Interrupt mask register (K01)

Interrupt mask register (K00)

High

Low

0 EIT2 EIT8 EIT32 0

EIT2

EIT8

EIT32

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

Enable

Mask

0EBH

R R/W

S1C60N01 TECHNICAL HARDWARE EPSON I-15

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1(b) I/O memory map

* 1 Initial value following initial reset

* 2 Not set in the circuit

* 3 Undefined

* 4 Reset (0) immediately after being read

* 5 Constantly 0 when being read

* 6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name SR

0EDH

0EFH

0 0 0 IK0

0 IT2 IT8 IT32

IK0 0

IT2

IT8

IT32

Yes

Interrupt factor flag (K00–K03)

Interrupt factor flag (clock timer 2 Hz)

Interrupt factor flag (clock timer 8 Hz)

Interrupt factor flag (clock timer 32 Hz)

Yes No

0F6H

P03 P02 P01 P00 P03

P02

P01

P00

–

I/O port (P00–P03)

High

Low

R/W

0F3H

R01 R00 0

R01

BUZZER

R00

FOUT

High

Low

OFF

Low

OFF

R01 output port data

Buzzer ON/OFF control register

R00 output port data

Frequency output ON/OFF control register

R/WR

BUZZER FOUT

I-16 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1(c) I/O memory map

* 1 Initial value following initial reset

* 2 Not set in the circuit

* 3 Undefined

* 4 Reset (0) immediately after being read

* 5 Constantly 0 when being read

* 6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name SR *1 10

0F9H

0FAH

0 TMRST 0 0

HLMOD 0 0 0

TMRST

Reset

HLMOD

Clock timer reset

Heavy load protection mode register

Reset –

R/W

Heavy

load Normal

load

0FBH

0FCH

CSDC 0 0 0

00 0IOC

IOC 0

I/O port P00–P03 Input/Output

LCD drive switch

Static Dynamic

Output Input

R/W

CSDC

S1C60N01 TECHNICAL HARDWARE EPSON I-17

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1(d) I/O memory map

* 1 Initial value following initial reset

* 2 Not set in the circuit

* 3 Undefined

* 4 Reset (0) immediately after being read

* 5 Constantly 0 when being read

* 6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name SR

0FDH

XBZR 0 XFOUT1 XFOUT0

XBZR

XFOUT1

XFOUT0

Buzzer frequency control

2 kHz

High

4 kHz

Low

R/WR/W

FOUT frequency control:

XFOUT1(0), XFOUT0(0) -> F1

XFOUT1(0), XFOUT0(1) -> F2

XFOUT1(1), XFOUT0(0) -> F3

XFOUT1(1), XFOUT0(1) -> F4

I-18 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)

Oscillation Circuit

The S1C60N01 Series have a built-in crystal oscillation

circuit. This circuit generates the operating clock for the

CPU and peripheral circuit on connection to an external

crystal oscillator (typ. 32.768 kHz) and trimmer capacitor

(5–25 pF).

Figure 4.2.1 is the block diagram of the crystal oscillation

circuit.

4.2

Fig. 4.2.1

Crystal oscillation circuit

Crystal oscillation

circuit

As Figure 4.2.1 indicates, the crystal oscillation circuit can

be configured simply by connecting the crystal oscillator

(X'tal) between the OSC1 and OSC2 pins and the trimmer

capacitor (CG) between the OSC1 and VDD pins.

X'tal

OSC2

OSC1 To CPU and

peripheral circuits

The S1C60N01 Series

VDD

CDVDD

Note The OSC1 and OSC2 terminals on the board should be shielded

with the VDD (+ side)

S1C60N01 TECHNICAL HARDWARE EPSON I-19

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)

CR oscillation circuit For the S1C60N01 Series, CR oscillation circuit (typ. 65

kHz) may also be selected by a mask option. Figure 4.2.2 is

the block diagram of the CR oscillation circuit.

Fig. 4.2.2

CR oscillation circuit

As Figure 4.2.2 indicates, the CR oscillation circuit can be

configured simply by connecting the register (R) between

pins OSC1 and OSC2 since capacity (C) is built-in.

See Chapter 6, "ELECTRICAL CHARACTERISTICS" for R

value.

OSC2

OSC1

To CPU and

peripheral circuits

The S1C60N01 Series

I-20 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

Input Ports (K00–K03)

The S1C60N01 Series have a 4-bit general-purpose input

port. Each of the input port pins (K00–K03) has an internal

pull-down resistance. The pull-down resistance can be

selected for each bit with the mask option.

Figure 4.3.1 shows the configuration of input port.

Selecting "pull-down resistance enabled" with the mask

option allows input from a push button, key matrix, and so

forth. When "pull-down resistance disabled" is selected, the

port can be used for slide switch input and interfacing with

other LSIs.

4.3

Configuration of

input port

Fig. 4.3.1

Configuration of input port

All four input port bits (K00–K03) provide the interrupt

function. The conditions for issuing an interrupt can be set

by the software for the four bits. Also, whether to mask the

interrupt function can be selected individually for all four

bits by the software. Figure 4.3.2 shows the configuration of

K00–K03.

Interrupt function

Kxx

Mask option

Address

Interrupt

request

Data bus

S1C60N01 TECHNICAL HARDWARE EPSON I-21

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

Fig. 4.3.3

Input interrupt timing

Input interrupt programing related precautions

When the content of the mask register is rewritten, while

the port K input is in the active status. The input interrupt

factor flag is set at ➀.

The interrupt mask registers (EIK00–EIK03) enable the

interrupt mask to be selected individually for K00–K03. An

interrupt occurs when the input value which are not

masked change and the interrupt factor flag (IK0) is set to 1.

Fig. 4.3.2

Input interrupt circuit

configuration

(K00–K03)

When using an input interrupt, if you rewrite the content of

the mask register, when the value of the input terminal

which becomes the interrupt input is in the active status

(input terminal = high status), the factor flag for input

interrupt may be set.

For example, a factor flag is set with the timing of ➀ shown

in Figure 4.3.3. However, when clearing the content of the

mask register with the input terminal kept in the high

status and then setting it, the factor flag of the input inter-

rupt is again set at the timing that has been set.

Data bus

Address

Interrupt mask

Kxx

Mask option

(K00–K03)

Noise

rejector

One for each pin series

Interrupt factor

flag (IK)

Interrupt

request

Address

Port K input

Factor flag set Not set

Mask register

Active status

➀

I-22 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

Consequently, when the input terminal is in the active

status (high status), do not rewrite the mask register (clear-

ing, then setting the mask register), so that a factor flag will

only set at the rising edge in this case. When clearing, then

setting the mask register, set the mask register, when the

input terminal is not in the active status (low status).

The contents that can be selected with the input port mask

option are as follows:

(1) An internal pull-down resistance can be selected for each

of the four bits of the input ports (K00–K03). Having

selected "pull-down resistance disabled", take care that

the input does not float. Select "pull-down resistance

enabled" for input ports that are not being used.

(2) The input interrupt circuit contains a noise rejection

circuit to prevent interrupts form occurring through

noise. The mask option enables selection of the noise

rejection circuit for each separate pin series. When "use"

is selected, a maximum delay of 0.5 ms (fosc = 32 kHz)

occurs from the time an interrupt condition is established

until the interrupt factor flag (IK) is set to 1.

Mask option

S1C60N01 TECHNICAL HARDWARE EPSON I-23

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

Table 4.3.1 list the input port control bits and their ad-

dresses.

Table 4.3.1 Input port control bits

Control of input port

Address Comment

D3 D2 D1 D0 Name SR 1 0

0E0H

K03 K02 K01 K00

K03

K02

K01

K00

–

Input port (K00–K03)

High

Low

0E8H

EIK03 EIK02 EIK01 EIK00

R/W

EIK03

EIK02

EIK01

EIK00

Interrupt mask register (K03)

Interrupt mask register (K02)

Interrupt mask register (K01)

Interrupt mask register (K00)

Enable

Mask

0EDH

0 0 IK0

IK0 0

Interrupt factor flag (K00–K03)

Yes No

K00–K03 Input port data (0E0H)

The input data of the input port pins can be read with these

registers.

When 1 is read: High level

When 0 is read: Low level

Writing: Invalid

The value read is 1 when the pin voltage of the four bits of

the input port (K00–K03) goes high (VDD), and 0 when the

voltage goes low (VSS). These bits are reading, so writing

cannot be done.

I-24 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

Interrupt mask registers (0E8H)

Masking the interrupt of the input port pins can be done

with these registers.

When 1 is written: Enable

When 0 is written: Mask

Reading: Valid

With these registers, masking of the input port bits can be

done for each of the four bits. After an initial reset, these

registers are all set to 0.

EIK00–EIK03

IK0 Interrupt factor flag (0EDH)

This flag indicates the occurrence of an input interrupt.

When 1 is read: Interrupt has occurred

When 0 is read: Interrupt has not occurred

Writing: Invalid

The interrupt factor flag IK0 is associated with K00–K03.

From the status of this flag, the software can decide whether

an input interrupt has occurred.

This flag is reset when the software has read it.

Reading of interrupt factor flag is available at EI, but be

careful in the following cases.

If the interrupt mask register value corresponding to the

interrupt factor flag to be read is set to 1, an interrupt

request will be generated by the interrupt factor flag set

timing, or an interrupt request will not be generated.

After an initial reset, this flag is set to 0.

S1C60N01 TECHNICAL HARDWARE EPSON I-25

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

Output Ports (R00, R01)

The S1C60N01 Series have a 2-bit general output port (R00,

R01).

Output specification of the output port can be selected in a

bit unit with the mask option. Two kinds of output specifi-

cations are available: complementary output and Pch open

drain output. Also, the mask option enables the output

ports R00 and R01 to be used as special output ports.

Figure 4.4.1 shows the configuration of the output port.

Configuration of

output port

4.4

Fig. 4.4.1

Configuration of output port

Data bus

Address

Rxx

Complementary

Pch open drain

Mask option

I-26 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

The mask option enables the following output port selection.

(1)Output specification of output port

The output specifications for the output port (R00, R01)

may be either complementary output or Pch open drain

output for each of the two bits. However, even when Pch

open drain output is selected, a voltage exceeding the

source voltage must not be applied to the output port.

(2)Special output

In addition to the regular DC output, special output can

be selected for output ports R00 and R01, as shown in

Table 4.4.1. Figure 4.4.2 shows the structure of output

ports R00 and R01.

Mask option

Table 4.4.1

Special output

FOUT or BUZZER

BUZZER

R00

R01

Pin Name When Special Output is Selected

Fig. 4.4.2

Structure of output ports

R00, R01

Address

(0F3H)

Data bus

Mask option

R01

R00

(R01)

(R00)

FOUT

BUZZER

S1C60N01 TECHNICAL HARDWARE EPSON I-27

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

FOUT (R00) When output port R00 is set for FOUT output, this port will

generate fosc (CPU operating clock frequency) or clock

frequency divided into fosc. Clock frequency may be se-

lected individually for F1–F4, from among 5 types by mask

option; one among F1–F4 is selected by software and used.

The types of frequency which may be selected are shown in

Table 4.4.2.

Output ports R01 and R00 may be set to BUZZER output

and BUZZER output (BUZZER reverse output), respectively,

allowing for direct driving of the piezo-electric buzzer.

BUZZER output (R00) may only be set if R01 is set to

BUZZER output. In such case, whether ON/OFF of the

BUZZER output is done through R00 register or is con-

trolled through R01 simultaneously with BUZZER output is

also selected by mask option.

The frequency of buzzer output may be selected by software

to be either 2 kHz or 4 kHz.

Table 4.4.2

FOUT clock frequency

A hazard may occur when the FOUT signal is turned on or off.Note

(D1, D0) = (XFOUT1, XFOUT0)

Mask

Option

Sets

Clock Frequency (Hz)

Set 4

256

(fosc/128) 512

(fosc/64) 1,024

(fosc/32) 2,048

(fosc/16)

512

(fosc/64) 1,024

(fosc/32) 2,048

(fosc/16)

8,192

(fosc/4)

1,024

(fosc/32) 2,048

(fosc/16) 4,096

(fosc/8)

4,096

(fosc/8) 8,192

(fosc/4) 16,384

(fosc/2)

4,096

(fosc/8)

32,768

(fosc/1)

2,048

(fosc/16) 4,096

(fosc/8) 8,192

(fosc/4) 16,384

(fosc/2)

Set 1

Set 2

Set 3

Set 5

(D1,D0)=(0,0) (D1,D0)=(0,1) (D1,D0)=(1,0) (D1,D0)=(1,1)

F1 F2 F3 F4

fosc = 32.768 kHz

BUZZER, BUZZER

(R01, R00)

I-28 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

Output port data (0F3H D0, 0F3H D1)

Sets the output data for the output ports.

When 1 is written: High output

When 0 is written: Low output

Reading: Valid

The output port pins output the data written to the corre-

sponding registers (R00, R01) without changing it. When 1

is written to the register, the output port pin goes high

(VDD), and when 0 is written, the output port pin goes low

(VSS). After an initial reset, all the registers are set to 0.

R00, R01

Table 4.4.3 lists the output port control bits and their ad-

dresses.

Table 4.4.3 Control bits of output port

Control of output

port

Address Comment

D3 D2 D1 D0 Name SR 1 0

0F3H

R01 R00 0

R01

BUZZER

R00

FOUT

High

Low

OFF

Low

OFF

R01 output port data

Buzzer ON/OFF control register

R00 output port data

Frequency output ON/OFF control register

R/WR

BUZZER FOUT

0FDH

XBZR 0 XFOUT1 XFOUT0

XBZR

XFOUT1

XFOUT0

Buzzer frequency control

2 kHz

High

4 kHz

Low

R/WR/W

FOUT frequency control:

XFOUT1(0), XFOUT0(0) -> F1

XFOUT1(0), XFOUT0(1) -> F2

XFOUT1(1), XFOUT0(0) -> F3

XFOUT1(1), XFOUT0(1) -> F4

S1C60N01 TECHNICAL HARDWARE EPSON I-29

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

Special output port data (0F3H D0)

Controls the FOUT (clock) output.

When 1 is written: Clock output

When 0 is written: Low level (DC) output

Reading: Valid

FOUT output can be controlled by writing data to R00. After

an initial reset, this register is set to 0.

Figure 4.4.3 shows the output waveform for FOUT output.

R00 (when FOUT is

selected)

Fig. 4.4.3

FOUT output waveform

FOUT frequency control (0FDH D0, 0FDH D1)

Selects the output frequency when R00 port is set for FOUT

output.

XFOUT0, XFOUT1

Table 4.4.4

FOUT frequency selection

After an initial reset, these registers are set to 0.

XFOUT1

XFOUT0

Frequency Selection

R00 register

FOUT output

waveform

I-30 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

Special output port data (0F3H D0, 0F3H D1)

Controls the buzzer output.

When 1 is written: Buzzer output

When 0 is written: Low level (DC) output

Reading: Valid

BUZZER and BUZZER output can be controlled by writing

data to R00 and R01.

When BUZZER output by R01 register control is selected by

mask option, BUZZER output and BUZZER output can be

controlled simultaneously by writing data to R01 register.

After an initial reset, these registers are set to 0.

Figure 4.4.4 shows the output waveform for buzzer output.

R00, R01 (when BUZZER

and BUZZER is

selected)

Fig. 4.4.4

Buzzer output waveform

Buzzer frequency control (0FDH D3)

Selects the frequency of the buzzer signal.

When 1 is written: 2 kHz

When 0 is written: 4 kHz

Reading: Valid

When R00 and R01 port is set to buzzer output, the fre-

quency of the buzzer signal can be selected by this register.

When 1 is written to this register, the frequency is set in 2

kHz, and in 4 kHz when 0 is written.

After an initial reset, this register is set to 0.

XBZR

R01 (R00) register

BUZZER output

waveform

BUZZER output

waveform

S1C60N01 TECHNICAL HARDWARE EPSON I-31

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

I/O Ports (P00–P03)

The S1C60N01 Series have a 4-bit general-purpose I/O port.

Figure 4.5.1 shows the configuration of the I/O port. The

four bits of the I/O port P00–P03 can be set to either input

mode or output mode. The mode can be set by writing data

to the I/O control register (IOC).

4.5

Configuration of I/O

port

Fig. 4.5.1

Configuration of I/O port

Address

Input

control

I/O control

(IOC)

Data bus

Pxx

Vss

I-32 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

Input or output mode can be set for the four bits of I/O port

P00–P03 by writing data into I/O control register IOC.

To set the input mode, 0 is written to the I/O control regis-

ter. When an I/O port is set to input mode, its impedance

becomes high and it works as an input port. However, the

input line is pulled down when input data is read.

The output mode is set when 1 is written to the I/O control

as an output port, it outputs a high signal (VDD) when the

port output data is 1, and a low signal (VSS) when the port

output data is 0.

After an initial reset, the I/O control register is set to 0, and

the I/O port enters the input mode.

The output specification during output mode (IOC = 1) of the

I/O port can be set with the mask option for either comple-

mentary output or Pch open drain output. This setting can

be performed for each bit of the I/O port. However, when

Pch open drain output has been selected, voltage in excess

of the supply voltage must not be applied to the port.

Mask option

I/O control register

and I/O mode

S1C60N01 TECHNICAL HARDWARE EPSON I-33

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

Table 4.5.1 lists the I/O port control bits and their ad-

dresses.

Control of I/O port

Table 4.5.1 I/O port control bits

I/O port data (0F6H)

I/O port data can be read and output data can be written

through the port.

• When writing data

When 1 is written: High level

When 0 is written: Low level

When an I/O port is set to the output mode, the written

data is output from the I/O port pin unchanged. When 1

is written as the port data, the port pin goes high (VDD),

and when 0 is written, the level goes low (VSS). Port data

can also be written in the input mode.

• When reading data

When 1 is read: High level

When 0 is read: Low level

P00–P03

Address Comment

D3 D2 D1 D0 Name SR 1 0

0F6H

P03 P02 P01 P00 P03

P02

P01

P00

–

I/O port (P00–P03)

High

Low

R/W

0FCH

00 0IOC

IOC 0

I/O port P00–P03 Input/Output

Output Input

R/W

I-34 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

The pin voltage level of the I/O port is read. When the I/

O port is in the input mode the voltage level being input

to the port pin can be read; in the output mode the

output voltage level can be read. When the pin voltage is

high (VDD) the port data read is 1, and when the pin

voltage is low (VSS) the data is 0. Also, the built-in pull-

down resistance functions during reading, so the I/O port

pin is pulled down.

- When the I/O port is set to the output mode and a low-imped-

ance load is connected to the port pin, the data written to the

- When the I/O port is set to the input mode and a low-level

voltage (Vss) is input by the built-in pull-down resistance, an

erroneous input results if the time constant of the capacitive

load of the input line and the built- in pull-down resistance load

is greater than the read-out time. When the input data is being

read, the time that the input line is pulled down is equivalent to

0.5 cycles of the CPU system clock. Hence, the electric poten-

tial of the pins must settle within 0.5 cycles. If this condition

cannot be met, some measure must be devised, such as

arranging a pull-down resistance externally, or performing

multiple read-outs.

I/O control register (0FCH D0)

The input or output I/O port mode can be set with this

When 1 is written: Output mode

When 0 is written: Input mode

Reading: Valid

The input or output mode of the I/O port is set in units of

four bits. For instance, IOC sets the mode for P00–P03.

Writing 1 to the I/O control register makes the I/O port

enter the output mode, and writing 0, the input mode.

After an initial reset, the IOC register is set to 0, so the I/O

port is in the input mode.

Note

IOC

S1C60N01 TECHNICAL HARDWARE EPSON I-35

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

LCD Driver (COM0–COM3, SEG0–SEG19)

The S1C60N01 Series have four common pins and 20

(SEG0–SEG19) segment pins, so that an LCD with a maxi-

mum of 80 (20 × 4) segments can be driven. The power for

driving the LCD is generated by the CPU internal circuit, so

there is no need to supply power externally.

The driving method is 1/4 duty (or 1/3, 1/2 duty by mask

option) dynamic drive, adopting the four types of potential

(1/3 bias), VDD, VL1, VL2 and VL3. Moreover, the 1/2 bias

dynamic drive that uses three types of potential, VDD, VL1 =

VL2 and VL3, can be selected by setting the mask option

(drive duty can also be selected from 1/4, 1/3 or 1/2). 1/2

bias drive is effective when the LCD system regulated voltage

circuit is not used. The VL1 terminal and the VL2 terminal

should be connected outside of the IC.

The frame frequency is 32 Hz for 1/4 duty and 1/2 duty,

and 42.7 Hz for 1/3 duty (in the case of fosc = 32.768 kHz).

Figure 4.6.1 shows the drive waveform for 1/4 duty (1/3 bias),

Figure 4.6.2 shows the drive waveform for 1/3 duty (1/3 bias),

Figure 4.6.3 shows the drive waveform for 1/2 duty (1/3 bias),

Figure 4.6.4 shows the drive waveform for 1/4 duty (1/2 bias),

Figure 4.6.5 shows the drive waveform for 1/3 duty (1/2 bias)

and Figure 4.6.6 shows the drive waveform for 1/2 duty (1/2

bias).

fosc indicates the oscillation frequency of the oscillation circuit.

Configuration of LCD

driver

4.6

Note

I-36 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

Fig. 4.6.1

Drive waveform for

1/4 duty (1/3 bias)

LCD lighting status

COM0

COM1

COM2

COM3

Not lit

Lit

-VDD

-VL1

-VL2

-VL3

COM0

COM1

COM2

COM3

SEG

0–19

Frame frequency

SEG0–19

-VDD

-VL1

-VL2

-VL3

S1C60N01 TECHNICAL HARDWARE EPSON I-37

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

Fig. 4.6.2

Drive waveform for

1/3 duty (1/3 bias)

Frame frequency

SEG

0–19

COM3

COM2

COM1

COM0 -VDD

-VL1

-VL2

-VL3

Not lit

Lit

SEG0–19

LCD lighting status

COM0

COM1

COM2

-VDD

-VL1

-VL2

-VL3

I-38 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

Fig. 4.6.3

Drive waveform for

1/2 duty (1/3 bias)

COM0

COM1

COM2

COM3

SEG

0–19

Frame frequency

-VDD

-VL1

-VL2

-VL3

-VDD

-VL1

-VL2

-VL3

Not lit

Lit

SEG0–19

LCD lighting status

COM0

COM1

S1C60N01 TECHNICAL HARDWARE EPSON I-39

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

LCD lighting status

Not lit

Lit

SEG

0–19

SEG0–19

Frame frequency

COM0

COM1

COM2

COM3

COM0

COM1

COM2

COM3

-V

L1, L2

-V

L1, L2

-V

Fig. 4.6.4

Drive waveform for

1/4 duty (1/2 bias)

I-40 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

LCD lighting status

Not lit

Lit

SEG

0–19

Frame frequency

SEG0–19

COM0

COM1

COM2

COM0

COM1

COM2

COM3

-VDD

-VL1, L2

-VL3

-VDD

-VL1, L2

-VL3

COM0

COM1

COM0

COM1

COM2

COM3

-V

L1, L2

-V

L1, L2

-V

LCD lighting status

Not lit

Lit

SEG

0–19

Frame frequency

SEG0–19

Fig. 4.6.5

Drive waveform for

1/3 duty (1/2 bias)

Fig. 4.6.6

Drive waveform for

1/2 duty (1/2 bias)

S1C60N01 TECHNICAL HARDWARE EPSON I-41

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

Cadence adjust-

ment of oscillation

frequency

In the S1C60N01 Series, the LCD drive duty can be set to

1/1 duty by software. This function enables easy adjust-

ment (cadence adjustment) of the oscillation frequency of

the OSC circuit.

The procedure to set to 1/1 duty drive is as follows:

➀Write 1 to the CSDC register at address 0FBH D3.

➁Write the same value to all registers corresponding to

COMs 0 through 3 of the display memory.

The frame frequency is 32 Hz (fOSC1/1,024, when fOSC1 =

32.768 kHz).

- Even when l/3 or 1/2 duty is selected by the mask option, the

display data corresponding to all COM are valid during 1/1 duty

driving. Hence, for 1/1 duty drive, set the same value for all

display memory corresponding to COMs 0 through 3.

For cadence adjustment, set the display data corresponding to

COMs 0 through 3

, so that all the LCD segments go on.

Figure 4.6.7 shows the 1/1 duty drive waveform (1/3 bias).

Figure 4.6.8 shows the 1/1 duty drive waveform (1/2 bias).

Fig. 4.6.7

1/1 duty drive waveform

(1/3 bias)

Fig. 4.6.8

1/1 duty drive waveform

(1/2 bias)

Note

SEG

0–19

COM

0–3

Frame frequency

LCD lighting status

COM0

COM1

COM2

COM3

SEG0–19

-VDD

-VL1, VL2

-VL3

Not lit Lit

-VDD

-VL1, VL2

-VL3

-VDD

-VL1, VL2

-VL3

SEG

0–19

COM

0–3

Frame frequency

LCD lighting status

COM0

COM1

COM2

COM3

SEG0–19

-VDD

-VL1

-VL2

-VL3

-VDD

-VL1

-VL2

-VL3

-VDD

-VL1

-VL2

-VL3

Not lit Lit

I-42 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

(1)Segment allocation

As shown in Figure 4.l.1, the S1C60N01 Series display

data is decided by the display data written to the display

memory (write-only) at address 090H–0AFH.

The address and bits of the display memory can be made

to correspond to the segment pins (SEG0–SEG19) in any

combination through mask option. This simplifies design

by increasing the degree of freedom with which the liquid

crystal panel can be designed.

Figure 4.6.9 shows an example of the relationship be-

tween the LCD segments (on the panel) and the display

memory in the case of 1/3 duty.

Mask option

(segment allocation)

Fig. 4.6.9

Segment allocation

aa'

ff'

ee'

dd' p'

SEG10 SEG11 SEG12

Common 0

Common 1

Common 2

09AH

09BH

09CH

09DH

Address

Data

Display data memory allocation

SEG10

SEG11

SEG12

9A, D0

(a)

9A, D1

(b)

9D, D1

(f')

9B, D1

(f)

9B, D2

(g)

9A, D2

(c)

9B, D0

(e)

9A, D3

(d)

9B, D3

(p)

Pin address allocation

Common 0 Common 1 Common 2

S1C60N01 TECHNICAL HARDWARE EPSON I-43

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

(2)Drive duty

According to the mask option, either 1/4, 1/3 or 1/2

duty can be selected as the LCD drive duty.

Table 4.6.1 shows the differences in the number of seg-

ments according to the selected duty.

Pins Used Maximum Number Frame Frequency

in Common of Segments (when fosc = 32 kHz)

1/4 COM0–3 80 (20 × 4) 32 Hz

1/3 COM0–2 60 (20 × 3) 42.7 Hz

1/2 COM0–1 40 (20 × 2) 32 Hz

(3)Output specification

➀The segment pins (SEG0–SEG19) are selected by mask

option in pairs for either segment signal output or DC

output (VDD and VSS binary output). When DC output

is selected, the data corresponding to COM0 of each

segment pin is output.

➁When DC output is selected, either complementary

output or Pch open drain output can be selected for

each pin by mask option.

The pin pairs are the combination of SEG (2

n) and SEG (2

n +

1) (where n is an integer from 0 to 12).

(4)Drive bias

For the drive bias of the S1C60N01 or the S1C60L01,

either 1/3 bias or 1/2 bias can be selected by the mask

option.

Table 4.6.1

Differences according to

selected duty

Duty

Note

I-44 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

Table 4.6.2 shows the control bits of the LCD driver and

their addresses. Figure 4.6.10 shows the display memory

map.

Control of LCD

driver

CSDC

Display memory

Fig. 4.6.10

Display

memory map

Address 0123456789ABCDEF

090

0A0 Display memory (Write only)

32 words x 4 bits

Table 4.6.2 Control bits of LCD driver

LCD drive switch (0FBH D3)

The LCD drive format can be selected with this switch.

When 1 is written: Static drive

When 0 is written: Dynamic drive

Reading: Valid

After an initial reset, dynamic drive (CSDC = 0) is selected.

(090H–0AFH)

The LCD segments are turned on or off according to this

data.

When 1 is written: On

When 0 is written: Off

Reading: Invalid

By writing data into the display memory allocated to the

LCD segment (on the panel), the segment can be turned on

or off. After an initial reset, the contents of the display

memory are undefined.

Address Comment

D3 D2 D1 D0 Name SR 1 0

0FBH

CSDC 0 0 0

LCD drive switch

Static Dynamic

R/W

CSDC

S1C60N01 TECHNICAL HARDWARE EPSON I-45

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

Clock Timer

The S1C60N01 Series have a built-in clock timer driven by

the source oscillator. The clock timer is configured as a

seven-bit binary counter that serves as a frequency divider

taking a 256 Hz source clock from the dividing circuit. The

four high-order bits (16 Hz–2 Hz) can be read by the soft-

ware.

Figure 4.7.1 is the block diagram of the clock timer.

4.7

Configuration of

clock timer

Normally, this clock timer is used for all kinds of timing

purpose, such as clocks.

Fig. 4.7.1

Block diagram of

clock timer

128 Hz–32 Hz

Data bus

32 Hz, 8 Hz, 2 Hz

256 Hz

Clock timer reset signal

OSC

(oscillation circuit)

and

dividing circuit

Interrupt

request

Interrupt

control

16 Hz–2 Hz

I-46 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

The clock timer can interrupt on the falling edge of the 32

Hz, 8 Hz, and 2 Hz signals. The software can mask any of

these interrupt signals.

Figure 4.7.2 is the timing chart of the clock timer.

Interrupt function

Clock timer timing chartFrequency

bits

Address

0E4H

D0 16 Hz

8 Hz

4 Hz

2 Hz

Occurrence of

32 Hz interrupt request

Occurrence of

8 Hz interrupt request

Occurrence of

2 Hz interrupt request

As shown in Figure 4.7.2, an interrupt is generated on the

falling edge of the 32 Hz, 8 Hz, and 2 Hz frequencies. When

this happens, the corresponding interrupt event flag (IT32,

IT8, IT2) is set to 1. Masking the separate interrupts can be

done with the interrupt mask register (EIT32, EIT8, EIT2).

However, regardless of the interrupt mask register setting,

the interrupt event flags will be set to 1 on the falling edge of

their corresponding signal (e.g. the falling edge of the 2 Hz

signal sets the 2 Hz interrupt factor flag to 1).

Write to the interrupt mask register (EIT32, EIT8, EIT2) and read

the interrupt factor flags (IT32, IT8, IT2) only in the DI status

(interrupt flag = 0). Otherwise, it causes malfunction.

Note

Fig. 4.7.2 Timing chart of the clock timer

S1C60N01 TECHNICAL HARDWARE EPSON I-47

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

Table 4.7.1 shows the clock timer control bits and their

addresses.

Control of clock

timer

Table 4.7.1 Control bits of clock timer

TM0–TM3 Timer data (0E4H)

The l6 Hz to 2 Hz timer data of the clock timer can be read

from this register. These four bits are read-only, and write

operations are invalid.

After an initial reset, the timer data is initialized to 0H.

Address Comment

D3 D2 D1 D0 Name SR 1 0

0E4H

TM3 TM2 TM1 TM0

TM3

TM2

TM1

TM0

–

Timer data (clock timer 2 Hz)

Timer data (clock timer 4 Hz)

Timer data (clock timer 8 Hz)

Timer data (clock timer 16 Hz)

High

Low

0EBH

0 EIT2 EIT8 EIT32

EIT2

EIT8

EIT32

Enable

Mask

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

R/W

0EFH

0 IT2 IT8 IT32 0

IT2

IT8

IT32

Yes

Interrupt factor flag (clock timer 2 Hz)

Interrupt factor flag (clock timer 8 Hz)

Interrupt factor flag (clock timer 32 Hz)

0F9H

0 TMRST 0 0

TMRST

Reset

Clock timer reset

Reset –

I-48 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

Interrupt mask registers (0EBH D0–D2)

These registers are used to mask the clock timer interrupt.

When 1 is written: Enabled

When 0 is written: Masked

Reading: Valid

The interrupt mask register bits (EIT32, EIT8, EIT2) mask

the corresponding interrupt frequencies (32 Hz, 8 Hz, 2 Hz).

After an initial reset, these registers are all set to 0.

EIT32, EIT8, EIT2

IT32, IT8, IT2 Interrupt factor flags (0EFH D0–D2)

These flags indicate the status of the clock timer interrupt.

When 1 is read: Interrupt has occurred

When 0 is read: Interrupt has not occurred

Writing: Invalid

The interrupt factor flags (IT32, IT8, IT2) correspond to the

clock timer interrupts (32 Hz, 8 Hz, 2 Hz). The software can

determine from these flags whether there is a clock timer

interrupt. However, even if the interrupt is masked, the

flags are set to 1 on the falling edge of the signal. These

flags can be reset when the register is read by the software.

Reading of interrupt factor flags is available at EI, but be

careful in the following cases.

If the interrupt mask register value corresponding to the

interrupt factor flags to be read is set to 1, an interrupt

request will be generated by the interrupt factor flags set

timing, or an interrupt request will not be generated. Be

very careful when interrupt factor flags are in the same

address.

After an initial reset, these flags are set to 0.

Clock timer reset (0F9H D2)

This bit resets the clock timer.

When 1 is written: Clock timer reset

When 0 is written: No operation

Reading: Always 0

The clock timer is reset by writing 1 to TMRST. The clock

timer starts immediately after this. No operation results

when 0 is written to TMRST.

This bit is write-only, and so is always 0 when read.

TMRST

S1C60N01 TECHNICAL HARDWARE EPSON I-49

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Heavy Load Protection Function)

4.8 Heavy Load Protection Function

The S1C60N01 Series have a heavy load protection function

for when the battery load becomes heavy and the supply

voltage drops, such as when an external buzzer sounds or

an external lamp lights. This function works in the heavy

load protection mode.

The normal mode changes to the heavy load protection mode

in the following case:

• When the software changes the mode to the heavy load

protection mode (HLMOD = 1)

In the heavy load protection mode, the internally regulated

voltage is switched to the high-stability mode from the low

current consumption mode. Consequently, more current is

consumed in the heavy load protection mode than in the

normal mode. Unless necessary, do not select the heavy

load protection mode with the software.

Operation of heavy

load protection

function

I-50 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Heavy Load Protection Function)

Table 4.8.1 shows the control bits and their addresses for

the heavy load protection function.

Table 4.8.1 Control bits for heavy load protection function

Control of heavy

load protection

function

Heavy load protection mode on/off (0FAH D3)

When 1 is written: Heavy load protection mode on

When 0 is written: Heavy load protection mode off

Reading: Valid

When HLMOD is set to 1, the IC enters the heavy load

protection mode.

In the heavy load protection mode, the consumed current

becomes larger. Unless necessary, do not select the heavy

load protection mode with the software.

HLMOD

Address Comment

D3 D2 D1 D0 Name SR 1 0

0FAH

HLMOD 0 0 0 HLMOD

Heavy load protection mode register

RR/W

Heavy

load Normal

load

S1C60N01 TECHNICAL HARDWARE EPSON I-51

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

Interrupt and HALT

The S1C60N01 Series provide the following interrupt set-

tings, each of which is maskable.

External interrupt: Input interrupt (one)

Internal interrupt: Timer interrupt (one)

To enable interrupts, the interrupt flag must be set to 1 (EI)

and the necessary related interrupt mask registers must be

set to 1 (enable). When an interrupt occurs, the interrupt

flag is automatically reset to 0 (DI) and interrupts after that

are inhibited.

When a HALT instruction is input, the CPU operating clock

stops and the CPU enters the halt state. The CPU is reacti-

vated from the halt state when an interrupt request occurs.

Figure 4.9.1 shows the configuration of the interrupt circuit.

4.9

I-52 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

Fig. 4.9.1 Configuration of interrupt circuit

K00

EIK00

K01

EIK01

K02

EIK02

K03

EIK03

IT2

EIT2

IT8

EIT8

IT32

EIT32

IK0

(MSB)

(LSB)

Program counter of CPU

(three low-order bits)

Interrupt vector

Interrupt factor flag

Interrupt mask register

Interrupt flag

INT

(Interrupt request)

S1C60N01 TECHNICAL HARDWARE EPSON I-53

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

Table 4.9.1 shows the factors that generate interrupt re-

quests.

The interrupt factor flags are set to 1 depending on the

corresponding interrupt factors.

The CPU is interrupted when the following two conditions

occur and an interrupt factor flag is set to 1.

• The corresponding mask register is 1 (enabled)

• The interrupt flag is 1 (EI)

The interrupt factor flag is a read-only register, but can be

reset to 0 when the register data is read.

After an initial reset, the interrupt factor flags are reset to 0.

Interrupt factors

Reading of interrupt factor flags is available at EI, but be careful in

the following cases.

If the interrupt mask register value corresponding to the interrupt

factor flags to be read is set to 1, an interrupt request will be

generated by the interrupt factor flags set timing, or an interrupt

request will not be generated. Be very careful when interrupt factor

flags are in the same address.

Note

Table 4.9.1

Interrupt factors

Interrupt Factor

Colck timer 2 Hz falling edge

Colck timer 8 Hz falling edge

Colck timer 32 Hz falling edge

Input data (K00–K03) rising edge

Interrupt Factor Flag

IT2

IT8

IT32

IK0

(0EFH D2)

(0EFH D1)

(0EFH D0)

(0EDH D0)

I-54 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

When an interrupt request is input to the CPU, the CPU

begins interrupt processing. After the program being exe-

cuted is suspended, interrupt processing is executed in the

following order:

➀The address data (value of the program counter) of the

program step to be executed next is saved on the stack

(RAM).

➁The interrupt request causes the value of the interrupt

vector (page 1, 01H–07H) to be loaded into the program

counter.

➂The program at the specified address is executed (execu-

tion of interrupt processing routine).

The processing in steps 1 and 2, above, takes 12 cycles of the

CPU system clock.

Interrupt vectors

Note

The interrupt factor flags can be masked by the correspond-

ing interrupt mask registers. The interrupt mask registers

are read/write registers. They are enabled (interrupt en-

abled) when 1 is written to them, and masked (interrupt

disabled) when 0 is written to them. After an initial reset,

the interrupt mask register is set to 0.

Table 4.9.2 shows the correspondence between interrupt

mask registers and interrupt factor flags.

Specific masks and

factor flags for inter-

rupt

Table 4.9.2

Interrupt mask registers and

interrupt factor flags

* There is an interrupt mask register for each input port pin.

Interrupt Mask Register

EIT2

EIT8

EIT32

EIK03*

EIK02*

EIK01*

EIK00*

Interrupt Factor Flag

(0EBH D2)

(0EBH D1)

(0EBH D0)

(0E8H D3)

(0E8H D2)

(0E8H D1)

(0E8H D0)

IT2

IT8

IT32

(0EFH D2)

(0EFH D1)

(0EFH D0)

IK0 (0EDH D0)

S1C60N01 TECHNICAL HARDWARE EPSON I-55

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

Tables 4.9.3 shows the interrupt control bits and their

addresses.

Control of interrupt

Table 4.9.3 Interrupt control bits

Address Comment

D3 D2 D1 D0 Name SR 1 0

0E8H

0EBH

EIK03 EIK02 EIK01 EIK00

0 EIT2 EIT8 EIT32

R/W

EIK03

EIK02

EIK01

EIK00

EIT2

EIT8

EIT32

Enable

Mask

Interrupt mask register (K03)

Interrupt mask register (K02)

Interrupt mask register (K01)

Interrupt mask register (K00)

Enable

Mask

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

R/W

0EDH

00 IK00

IK0 0

Interrupt factor flag (K00–K03)

Yes No

0EFH

0 IT2 IT8 IT32 0

IT2

IT8

IT32

Enable

Mask

Interrupt factor flag (clock timer 2 Hz)

Interrupt factor flag (clock timer 8 Hz)

Interrupt factor flag (clock timer 32 Hz)

Interrupt mask registers (0EBH D0–D2)

Interrupt factor flags (0EFH D0–D2)

See 4.7, "Clock Timer".

Interrupt mask registers (0E8H)

Interrupt factor flag (0EDH D0)

See 4.3, "Input Ports".

EIT32, EIT8, EIT2

IT32, IT8, IT2

EIK00–EIK03

IK0

I-56 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM

BASIC EXTERNAL WIRING DIAGRAM

(1) Piezo Buzzer Single Terminal Driving

CHAPTER 5

X'tal

–C

Crystal oscillator

Trimmer capacitor

Capacitor

32.768 kHz CI(MAX) = 35 kΩ

5–25 pF

0.1 µF

3.3 µF

X'tal

1.5 V

3.0 V

Piezo

Buzzer

R01

K00

K03

P00

P03

R00

I/O

SEG0

SEG19

COM0

COM3

LCD

PANEL

Coil

OSC1

OSC2

RESET

TEST

Capacitors (C

–C

) are connected.

Connection depending on power supply

and LCD panel specification.

Please refer to page I-7.

S1C60N01 TECHNICAL HARDWARE EPSON I-57

CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM

(2) Piezo Buzzer Direct Driving

X'tal

I/O

SEG0

SEG19

COM0

COM3

LCD

PANEL

OSC1

OSC2

RESET

TEST

1.5 V

3.0 V

Piezo

Buzzer

R01

R00

K00

K03

P00

P03

Capacitors (C

–C

) are connected.

Connection depending on power supply

and LCD panel specification.

Please refer to page I-7.

X'tal

–C

Crystal oscillator

Trimmer capacitor

Capacitor

32.768 kHz CI(MAX) = 35 kΩ

5–25 pF

0.1 µF

3.3 µF

I-58 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 6: ELECTRICAL CHARACTERISTICS

CHAPTER 6 ELECTRICAL CHARACTERISTICS

6.1 Absolute Maximum Rating

Power voltage

Input voltage (1)

Input voltage (2)

Permissible total output current *1

Operating temperature

Storage temperature

Soldering temperature / Time

Allowable dissipation *2

IOSC

∑I

VSS

Topr

Tstg

Tsol

-5.0 to 0.5

Vss-0.3 to 0.5

-20 to 70

-65 to 150

260°C, 10sec (lead section)

250

°C

–

=0V)

Item Symbol Rated Value Unit

∗1 The permissible total output current is the sum total of the

current (average current) that simultaneously flows from the

output pins (or is draw in).

∗2 In case of QFP12-48pin plastic package

S1C60N01 TECHNICAL HARDWARE EPSON I-59

CHAPTER 6: ELECTRICAL CHARACTERISTICS

Recommended Operating Conditions

S1C60N01

6.2

S1C60L01

Item

Power voltage

Oscillation frequency

Booster capacitor

Capacitor between VDD and VL1

or VSS and VL1

Capacitor between VSS and VL2

Capacitor between VDD and VL3

Capacitor between VDD and VS1

Symbol

VSS

fOSC1

fOSC2

Condition

VDD=0V

Crystal oscillation

CR oscillation, R=470kΩ

Min

-3.6

0.1

Typ

-3.0

32.768

Unit

kHz

µF

Max

-1.8

(Ta=-20 to 70°C)

Item

Power voltage

Oscillation frequency

Booster capacitor

Capacitor between V

and V

Capacitor between V

and V

Capacitor between V

and V

Capacitor between V

and V

Symbol

OSC1

OSC2

Condition

=0V

Crystal oscillation

CR oscillation, R=470kΩ

Min

-2.0

0.1

Typ

-1.5

32.768

Unit

kHz

µF

Max

-1.2

(Ta=-20 to 70°C)

I-60 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 6: ELECTRICAL CHARACTERISTICS

6.3 DC Characteristics

S1C60N01

Unless otherwise specified

VDD=0 V, VSS=-3.0 V, fosc=32.768 kHz, Ta=25°C, VS1, VL1, VL2 and VL3 are internal

voltages, and C1=C2=C3=C4=C5=0.1 µF

Item

Symbol

VIH1

VIH2

VIL1

VIL2

IIH1

IIH2

IIH3

IIL

IOH1

IOH2

IOL1

IOL2

IOH3

IOL3

IOH4

IOL4

IOH5

IOL5

Condition Min

0.2•Vss

0.15•Vss

Vss

-0.5

3.0

300

Typ Unit

µA

Max

0.8•Vss

0.85•Vss

0.5

100

-1.0

-3

-300

K00–K03, P00–P03

RESET

K00–K03, P00–P03

RESET

K00–K03, P00–P03

K00–K03

P00–P03, RESET

K00–K03, P00–P03,

RESET, TEST

P00–P03

R00, R01

P00–P03

R00, R01

COM0–COM3

SEG0–SEG19

High level input voltage (1)

High level input voltage (2)

Low level input voltage (1)

Low level input voltage (2)

High level input current (1)

High level input current (2)

High level input current (3)

Low level input current

High level output current (1)

High level output current (2)

Low level output current (1)

Low level output current (2)

Common output current

Segment output current

(during LCD output)

Segment output current

(during DC output)

VIH1=0V

Without pull down resistor

VIH2=0V

With pull down resistor

VIH3=0V

With pull down resistor

VIL=VSS

VOH1=0.1•VSS

VOH2=0.1•VSS

(built-in protection resistance)

VOL1=0.9•VSS

VOL2=0.9•VSS

(built-in protection resistance)

VOH3=-0.05V

VOL3=VL3+0.05V

VOH4=-0.05V

VOL4=VL3+0.05V

VOH5=0.1•VSS

VOL5=0.9•VSS

S1C60N01 TECHNICAL HARDWARE EPSON I-61

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1C60L01

Unless otherwise specified

VDD=0 V, VSS=-1.5 V, fosc=32.768 kHz, Ta=25°C, VS1, VL1, VL2 and VL3 are internal

voltages, and C1=C2=C3=C4=C5=0.1 µF

Item Symbol

IH1

IH2

IL1

IL2

IH1

IH2

IH3

OH1

OH2

OL1

OL2

OH3

OL3

OH4

OL4

OH5

OL5

Condition Min

0.2•Vss

0.15•Vss

Vss

5.0

9.0

-0.5

700

130

Typ Unit

µA

Max

0.8•Vss

0.85•Vss

0.5

100

-200

-3

-100

K00–K03, P00–P03

RESET

K00–K03, P00–P03

RESET

K00–K03, P00–P03

K00–K03

P00–P03, RESET

K00–K03, P00–P03,

RESET, TEST

P00–P03

R00, R01

P00–P03

R00, R01

COM0–COM3

SEG0–SEG19

High level input voltage (1)

High level input voltage (2)

Low level input voltage (1)

Low level input voltage (2)

High level input current (1)

High level input current (2)

High level input current (3)

Low level input current

High level output current (1)

High level output current (2)

Low level output current (1)

Low level output current (2)

Common output current

Segment output current

(during LCD output)

Segment output current

(during DC output)

IH1

=0V

Without pull down resistor

IH2

=0V

With pull down resistor

IH3

=0V

With pull down resistor

OH1

=0.1•V

OH2

=0.1•V

(built-in protection resistance)

OL1

=0.9•V

OL2

=0.9•V

(built-in protection resistance)

OH3

=-0.05V

OL3

+0.05V

OH4

=-0.05V

OL4

+0.05V

OH5

=0.1•V

OL5

=0.9•V

I-62 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 6: ELECTRICAL CHARACTERISTICS

6.4 Analog Circuit Characteristics and Power Current Con-

sumption

S1C60N01 (Normal Operating Mode)

Unless otherwise specified

VDD=0 V, VSS=-3.0 V, fosc=32.768 kHz (crystal oscillation), Ta=25°C, CG=25 pF,

VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=0.1 µF

S1C60N01 (Heavy Load Protection Mode)

Unless otherwise specified

VDD=0 V, VSS=-3.0 V, fosc=32.768 kHz (crystal oscillation), Ta=25°C, CG=25 pF,

VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=0.1 µF

Item

Internal voltage

Power current

consumption

Symbol

Condition

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Min

1/2•V

-0.1

3/2•V

-0.1

Typ

1.0

2.5

Unit

µA

Max

1/2•V

0.9

3/2•V

0.9

2.5

5.0

During HALT

During execution Without panel load

Item

Internal voltage

Power current

consumption

Symbol

Condition

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Min

1/2•V

-0.1

3/2•V

-0.1

Typ

2.0

5.5

Unit

µA

Max

1/2•V

0.85

3/2•V

0.85

5.5

10.0

During HALT

During execution Without panel load

S1C60N01 TECHNICAL HARDWARE EPSON I-63

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1C60L01 (Normal Operating Mode)

Unless otherwise specified

VDD=0 V, VSS=-1.5 V, fosc=32.768 kHz (crystal oscillation), Ta=25°C, CG=25 pF,

VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=0.1 µF

S1C60L01 (Heavy Load Protection Mode)

Unless otherwise specified

VDD=0 V, VSS=-1.5 V, fosc=32.768 kHz (crystal oscillation), Ta=25°C, CG=25 pF,

VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=0.1 µF

Item

Internal voltage

Power current

consumption

Symbol

Condition

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Min

2•V

-0.1

3•V

-0.1

Typ

1.0

2.5

Unit

µA

Max

2•V

0.9

3•V

0.9

2.5

5.0

During HALT

During execution Without panel load

Item

Internal voltage

Power current

consumption

Symbol

Condition

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Min

2•V

-0.1

3•V

-0.1

Typ

2.0

5.5

Unit

µA

Max

2•V

0.85

3•V

0.85

5.5

10.0

During HALT

During execution Without panel load

I-64 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1C60N01 (CR, Normal Operating Mode)

Unless otherwise specified

VDD=0 V, VSS=-3.0 V, fosc=65 kHz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 and VL3 are

internal voltages, and C1=C2=C3=C4=C5=0.1 µF, Recommended external resistance

for CR oscillation=470 kΩ

S1C60N01 (CR, Heavy Load Protection Mode)

Unless otherwise specified

VDD=0 V, VSS=-3.0 V, fosc=65 kHz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 and VL3 are

internal voltages, and C1=C2=C3=C4=C5=0.1 µF, Recommended external resistance

for CR oscillation=470 kΩ

Item

Internal voltage

Power current

consumption

Symbol

Condition

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Min

1/2•V

-0.1

3/2•V

-0.1

Typ

8.0

15.0

Unit

µA

Max

1/2•V

0.9

3/2•V

0.9

15.0

20.0

During HALT

During execution Without panel load

Item

Internal voltage

Power current

consumption

Symbol

Condition

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Min

1/2•V

-0.1

3/2•V

-0.1

Typ

16.0

30.0

Unit

µA

Max

1/2•V

0.85

3/2•V

0.85

30.0

40.0

During HALT

During execution Without panel load

S1C60N01 TECHNICAL HARDWARE EPSON I-65

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1C60L01 (CR, Normal Operating Mode)

Unless otherwise specified

VDD=0 V, VSS=-1.5 V, fosc=65 kHz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 and VL3 are

internal voltages, and C1=C2=C3=C4=C5=0.1 µF, Recommended external resistance

for CR oscillation=470 kΩ

S1C60L01 (CR, Heavy Load Protection Mode)

Unless otherwise specified

VDD=0 V, VSS=-1.5 V, fosc=65 kHz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 and VL3 are

internal voltages, and C1=C2=C3=C4=C5=0.1 µF, Recommended external resistance

for CR oscillation=470 kΩ

Item

Internal voltage

Power current

consumption

Symbol

Condition

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Min

2•V

-0.1

3•V

-0.1

Typ

8.0

15.0

Unit

µA

Max

2•V

0.9

3•V

0.9

15.0

20.0

During HALT

During execution Without panel load

Item

Internal voltage

Power current

consumption

Symbol

Condition

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Min

2•V

-0.1

3•V

-0.1

Typ

16.0

30.0

Unit

µA

Max

2•V

0.85

3•V

0.85

30.0

40.0

During HALT

During execution Without panel load

I-66 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 6: ELECTRICAL CHARACTERISTICS

6.5 Oscillation Characteristics

Oscillation characteristics will vary according to different conditions. Use the

following characteristics are as reference values.

S1C60N01

Unless otherwise specified

VDD=0 V, VSS=-3.0 V, Crystal : Q13MC146, CG=25 pF, CD=built-in, Ta=25°C

S1C60L01

Unless otherwise specified

VDD=0 V, VSS=-1.5 V, Crystal : Q13MC146, CG=25 pF, CD=built-in, Ta=25°C

Item

Oscillation start

voltage

Oscillation stop

voltage

Built-in capacity (drain)

Frequency voltage deviation

Frequency IC deviation

Frequency adjustment range

Higher harmonic oscillation

start voltage

Allowable leak resistance

Symbol

Vsta

(Vss)

Vstp

(Vss)

f/V

f/I

f/C

hho

(Vss)

leak

Condition Min

-1.8

-10

200

Typ

Unit

ppm

MΩ

Max

-3.6

sta≤5sec

stp≤10sec

Including the parasitic capacity inside the IC

Vss=-1.8 to -3.6V

=5–25pF

=5pF

Between OSC1 and V

Item

Oscillation start

voltage

Oscillation stop

voltage

Built-in capacity (drain)

Frequency voltage deviation

Frequency IC deviation

Frequency adjustment range

Higher harmonic oscillation

start voltage

Allowable leak resistance

Symbol

Vsta

(Vss)

Vstp

(Vss)

f/V

f/I

f/C

hho

(Vss)

leak

Condition Min

-1.2

-10

200

Typ

Unit

ppm

MΩ

Max

-2.0

sta≤5sec

stp≤10sec

Including the parasitic capacity inside the IC

Vss=-1.2 to -2.0V

=5–25pF

=5pF

Between OSC1 and V

S1C60N01 TECHNICAL HARDWARE EPSON I-67

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1C60N01 (CR)

Unless otherwise specified

VDD=0 V, VSS=-3.0 V, RCR=470 kΩ, Ta=25°C

S1C60L01 (CR)

Unless otherwise specified

VDD=0 V, VSS=-1.5 V, RCR=470 kΩ, Ta=25°C

Item

Oscillation frequency dispersion

Oscillation start voltage

Oscillation start time

Oscillation stop voltage

Symbol

fosc

Vsta

sta

Vstp

Condition

Vss=-1.8 to -3.6V

Min

-20

-1.8

Typ

65kHz

Unit

Max

Item

Oscillation frequency dispersion

Oscillation start voltage

Oscillation start time

Oscillation stop voltage

Symbol

fosc

Vsta

sta

Vstp

Condition

Vss=-1.2 to -2.0V

Min

-20

-1.2

Typ

65kHz

Unit

Max

I-68 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 7: PACKAGE

CHAPTER 7 PACKAGE

7.1 Plastic Package

Plastic QFP12-48pin

±0.1

±0.4

2536

±0.1

±0.4

INDEX

0.18121

1.4

±0.1

0.1

1.7

max

0.5

±0.2

0°

10°

0.125

±0.05

0.5

+0.1

–0.05

S1C60N01 TECHNICAL HARDWARE EPSON I-69

CHAPTER 7: PACKAGE

7.2 Ceramic Package for Test Samples

DIP-64pin

Pin No.

Pin Name

N.C.

SEG5

SEG4

SEG3

SEG2

SEG1

SEG0

N.C.

COM0

COM1

COM2

COM3

VL3

VL2

Pin No.

Pin Name

VL1

VSS

VDD

OSC1

OSC2

N.C.

VS1

N.C.

P00

P01

P02

Pin No.

Pin Name

P03

K00

K01

K02

K03

N.C.

R01

R00

SEG19

SEG18

SEG17

SEG16

Pin No.

N.C. = No Connection

Pin Name

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

N.C.

TEST

RESET

SEG9

SEG8

SEG7

SEG6

N.C.

12Pin No. Index Mark 3132

64 63 3433

81.3

78.7

23.1

2.54

22.8

(Unit: mm)

I-70 EPSON S1C60N01 TECHNICAL HARDWARE

CHAPTER 8: PAD LAYOUT

CHAPTER 8

8.1

PAD LAYOUT

Diagram of Pad Layout

Chip size: 2,640 µm (X) x 2,180 µm (Y)

(0, 0)

1510

25 30 35

Die No.

S1C60N01 TECHNICAL HARDWARE EPSON I-71

CHAPTER 8: PAD LAYOUT

8.2 Pad Coordinates

(Unit: µm)

Pad No

Pad Name

R01

R00

SEG19

SEG18

SEG17

SEG16

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

TEST

RESET

SEG9

SEG8

SEG7

SEG6

SEG5

SEG4

SEG3

SEG2

SEG1

Pad Name

SEG0

COM0

COM1

COM2

COM3

VL3

VL2

VL1

VSS

VDD

OSC1

OSC2

VS1

P00

P01

P02

P03

K00

K01

K02

K03

759

629

401

271

141

-119

-249

-379

-509

-639

-769

-1,151

-1,126

-988

-858

-727

-597

-466

-336

-206

-76

570

700

835

987

1,140

1,151

923

789

657

526

396

266

136

-124

-254

-384

-514

-644

-923

-11

119

249

379

518

648

778

908

S1C60N01

II.

Technical Software

Software

S1C60N01 TECHNICAL SOFTWARE EPSON II-i

CONTENTS

CHAPTER 1 CONFIGURATION ........................................................... II-1

1.1 S1C60N01 Block Diagram ............................................. II-1

1.2 ROM Map ....................................................................... II-2

1.3 Interrupt Vectors............................................................. II-3

1.4 Data Memory Map.......................................................... II-4

CHAPTER 2 INITIAL RESET ................................................................... II-9

2.1 Internal Register Status on Initial Reset ......................... II-9

2.2 Initialize Program Example............................................ II-11

CHAPTER 3 PERIPHERAL CIRCUITS.................................................... II-13

3.1 Input Ports ..................................................................... II-13

Input port memory map .......................................... II-13

Control of the input port ......................................... II-14

Examples of input port control program .................. II-14

3.2 Output Ports .................................................................. II-16

Output port memory map........................................ II-16

Control of the output port ....................................... II-16

Examples of output port control program ................ II-17

3.3 Special Use Output Ports .............................................. II-19

Special use output port memory map ...................... II-19

Control of the special use output port ..................... II-20

Examples of special use output port

control program ...................................................... II-21

II-ii EPSON S1C60N01 TECHNICAL SOFTWARE

CONTENTS

3.4 I/O Ports ........................................................................ II-23

I/O port memory map ............................................. II-23

Control of the I/O port ............................................ II-24

Examples of I/O port control program ..................... II-25

3.5 LCD Driver..................................................................... II-28

LCD driver memory map ......................................... II-28

Control of the LCD driver ........................................ II-29

Examples of LCD driver control program ................. II-31

3.6 Timer ............................................................................. II-33

Timer memory map ................................................. II-33

Control of the timer................................................. II-34

Examples of timer control program.......................... II-35

3.7 Heavy Load Protection Function ................................... II-37

Heavy load protection function memory map ........... II-37

Heavy load protection function ................................ II-37

Examples of heavy load protection

function control program......................................... II-38

3.8 Interrupt and Halt........................................................... II-39

Interrupt memory map ............................................ II-39

Control of interrupts and halt ................................. II-40

Examples of interrupt and halt control program ...... II-48

CHAPTER 4 SUMMARY OF PROGRAMMING POINTS....................... II-50

APPENDIX A Table of Instructions ...................................................... II-54

B The S1C60N01 I/O Memory Map.................................. II-59

C Table of the ICE Commands ......................................... II-60

D Cross-assembler Pseudo-instruction List...................... II-62

S1C60N01 TECHNICAL SOFTWARE EPSON II-1

CHAPTER 1: CONFIGURATION

CHAPTER 1

1.1

CONFIGURATION

S1C60N01 Block Diagram

Power

Controller

LCD

Driver

RAM

80 × 4 Interrupt

Generator

I Port

Test Port

I/O Port

O Port

Timer

Core CPU S1C6200B

ROM

1,024 × 12 OSC System

Reset

Control

RESET

OSC1

COM0

COM3

SEG0

SEG19

K00~K03

TEST

P00~P03

R00, R01

OSC2

FOUT

BUZZER

(FOUT/BUZZER)

(BUZZER)

Fig. 1.1.1

S1C60N01 block diagram

II-2 EPSON S1C60N01 TECHNICAL SOFTWARE

CHAPTER 1: CONFIGURATION

ROM Map

The S1C60N01 has a built-in mask ROM with a capacity of

1,024 steps × 12 bits for program storage. The configuration

of the ROM is shown in Figure 1.2.1.

1.2

Fig. 1.2.1

Configuration of built-in ROM

00H step

07H step

08H step

FFH step

12 bits

Program start address

Interrupt vector area

Bank 0

Program area

0 page

1 page

2 page

3 page

01H step

S1C60N01 TECHNICAL SOFTWARE EPSON II-3

CHAPTER 1: CONFIGURATION

Interrupt Vectors

When an interrupt request is received by the CPU, the CPU

initiates the following interrupt processing after completing

the instruction being executed.

(1)The address of the next instruction to be executed (the

value of the program counter) is saved on the stack

(RAM).

(2)The interrupt vector address corresponding to the inter-

rupt request is loaded into the program counter.

(3)The branch instruction written in the vector is executed

to branch to the software interrupt processing routine.

Steps 1 and 2 require 12 cycles of the CPU system clock.

The interrupt vectors are shown in Table 1.3.1.

1.3

Note

Table 1.3.1

Interrupt requests and vectors

Addesses (start address of interrupt processing routines) to

jump to are written into the addresses available for interrupt

vector allocation.

Step Interrupt Vector

Initial reset

Clock timer interrupt

Input (K00–K03) interrupt

Input interrupt and clock timer interrupt

Page

00H

01H

04H

05H

II-4 EPSON S1C60N01 TECHNICAL SOFTWARE

CHAPTER 1: CONFIGURATION

Data Memory Map

The S1C60N01 built-in RAM has 80 words of data memory,

32 words of display memory for the LCD, and I/O memory

for controlling the peripheral circuit. When writing pro-

grams, note the following:

(1)Since the stack area is in the data memory area, take

care not to overwrite the stack with data. Subroutine

calls or interrupts use 3 words on the stack.

(2)Data memory addresses 000H–00FH are memory register

areas that are addressed with register pointer RP.

Fig. 1.4.1

Data memory map

1.4

Address

Page High

Low 0123456789ABCDEF

M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF

RAM (80 words x 4 bits)

R/W

Unused area

I/O memory

Display memory

Unused area

Memory is not mounted in unused area within the memory map

and in memory area not indicated in this chapter. For this reason,

normal operation cannot be assured for programs that have been

prepared with access to these areas.

Note

S1C60N01 TECHNICAL SOFTWARE EPSON II-5

CHAPTER 1: CONFIGURATION

Table 1.4.1(a) I/O memory map 1

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always 0 when being read

*6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name SR

0E0H

0E4H

0E8H

K03 K02 K01 K00

TM3 TM2 TM1 TM0

EIK03 EIK02 EIK01 EIK00

R/W

K03

K02

K01

K00

–

TM3

TM2

TM1

TM0

–

EIK03

EIK02

EIK01

EIK00

Enable

Mask

Timer data (clock timer 2 Hz)

Timer data (clock timer 4 Hz)

Timer data (clock timer 8 Hz)

Timer data (clock timer 16 Hz)

Input port (K00–K03)

High

Low

Interrupt mask register (K03)

Interrupt mask register (K02)

Interrupt mask register (K01)

Interrupt mask register (K00)

High

Low

0 EIT2 EIT8 EIT32 0

EIT2

EIT8

EIT32

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

Enable

Mask

0EBH

R R/W

II-6 EPSON S1C60N01 TECHNICAL SOFTWARE

CHAPTER 1: CONFIGURATION

Table 1.4.1(b) I/O memory map 2

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always 0 when being read

*6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name SR *1 10

0EDH

0EFH

00 0IK0

0 IT2 IT8 IT32

IK0 0

IT2

IT8

IT32

Yes

Interrupt factor flag (K00–K03)

Interrupt factor flag (clock timer 2 Hz)

Interrupt factor flag (clock timer 8 Hz)

Interrupt factor flag (clock timer 32 Hz)

Yes No

0F6H

P03 P02 P01 P00 P03

P02

P01

P00

–

I/O port (P00–P03)

High

Low

R/W

0F3H

R01 R00 0

R01

BUZZER

R00

FOUT

High

Low

OFF

Low

OFF

R01 output port data

Buzzer ON/OFF control register

R00 output port data

Frequency output ON/OFF control register

R/WR

BUZZER FOUT

S1C60N01 TECHNICAL SOFTWARE EPSON II-7

CHAPTER 1: CONFIGURATION

Table 1.4.1(c) I/O memory map 3

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always 0 when being read

*6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name SR *1 10

0F9H

0FAH

0 TMRST 0 0

HLMOD 0 0 0

TMRST

Reset

HLMOD

Clock timer reset

Heavy load protection mode register

Reset –

R/W

Heavy

load Normal

load

0FBH

0FCH

CSDC 0 0 0

00 0IOC

IOC 0

I/O port P00–P03 Input/Output

LCD drive switch

Static Dynamic

Output Input

R/W

CSDC

II-8 EPSON S1C60N01 TECHNICAL SOFTWARE

CHAPTER 1: CONFIGURATION

Table 1.4.1(d) I/O memory map 4

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always 0 when being read

*6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name SR

0FDH

XBZR 0 XFOUT1 XFOUT0

XBZR

XFOUT1

XFOUT0

Buzzer frequency control

2 kHz

High

4 kHz

Low

R/WR/W

FOUT frequency control:

XFOUT1(0), XFOUT0(0) -> F1

XFOUT1(0), XFOUT0(1) -> F2

XFOUT1(1), XFOUT0(0) -> F3

XFOUT1(1), XFOUT0(1) -> F4

S1C60N01 TECHNICAL SOFTWARE EPSON II-9

CHAPTER 2: INITIAL RESET

INITIAL RESET

Internal Register Status on Initial Reset

Following an initial reset, the internal registers and internal

data memory area are initialized to the values shown in

Tables 2.1.1 and 2.1.2.

Internal Register Bit Length Initial Value Following Reset

Program counter step PCS 8 00H

Program counter page PCP 4 1H

New page pointer NPP 4 1H

Stack pointer SP 8 Undefined

Index register X 8 Undefined

Index register Y 8 Undefined

General register A 4 Undefined

General register B 4 Undefined

Interrupt flag I 1 0

Decimal flag D 1 0

Zero flag Z 1 Undefined

Carry flag C 1 Undefined

Internal Data Initial Value

Memory Area Following Reset

RAM data 4 × 80 Undefined 000H–05FH

Display memory 4 × 20 Undefined 090H–0AFH

Internal I/O register See Tables 1.4.1(a)–1.4.1(d) 0E0H–0FDH

2.1

Table 2.1.1

Initial values of internal

registers

CHAPTER 2

Table 2.1.2

Initial values of internal data

memory area

Bit Length Address

II-10 EPSON S1C60N01 TECHNICAL SOFTWARE

CHAPTER 2: INITIAL RESET

After an initial reset, the program counter page (PCP) is

initialized to 1H, and the program counter step (PCS), to

00H. This is why the program is executed from step 00H of

the first page.

The initial values of some internal registers and internal

data memory area locations are undefined after a reset. Set

them as necessary to the proper initial values in the pro-

gram.

The peripheral I/O functions (memory-mapped I/O) are

assigned to internal data memory area addresses 0E0H to

0FDH. Each address represents a 4-bit internal I/O register,

allowing access to the peripheral functions in 1-word (4-bit)

read/write units.

S1C60N01 TECHNICAL SOFTWARE EPSON II-11

CHAPTER 2: INITIAL RESET

Initialize Program Example

The following is a program that clears the RAM and LCD,

resets the flags, registers and timer, and sets the stack

pointer immediately after resetting the system.

Label Mnemonic/operand Comment

ORG 100H

JP INIT ;Jump to "INIT"

;ORG 110H

INIT RST F,0011B ;Interrupt mask, decimal

;adjustment off

;LD X,0 ;

RAMCLR LDPX MX,0 ;

CP XH,5H ;

JP NZ,RAMCLR ;

LD X,90H ;

LCDCLR LDPX MX,0 ;

CP XH,0BH ;

JP NZ,LCDCLR ;

;LD A,0 ;

LD B,4 ;

LD SPL,A ;

LD SPH,B ;

;LD X,0F9H ;

OR MX,0100B ;

;LD X,0EBH ;

OR MX,0111B ;

;LD X,0E8H ;

OR MX,1111B ;

;LD X,0 ;

LD Y,0 ;

LD A,0 ;

LD B,0 ;

RST F,0 ;

EI ;Enable interrupt

Clear RAM (00H–4FH)

Enable timer interrupt

Enable input interrupt

(K03–K00)

Clear LCD (90H–AFH)

Reset timer

Set stack pointer to 40H

2.2

Reset register flags

II-12 EPSON S1C60N01 TECHNICAL SOFTWARE

CHAPTER 2: INITIAL RESET

The above program is a basic initialization program for the

S1C60N01. The setting data are all initialized as shown in

Table 2.1.1 by executing this program. When using this

program, add setting items necessary for each specific

application. (Figure 2.2.1 is the flow chart for this program.)

Fig. 2.2.1

Flow chart of the initialization

program

Initialization

Reset

I (Interrupt flag)

D (Decimal adjustment flag)

Clear RAM

Set SP

Reset timer

Enable timer interrupt

Enable input interrupt

Reset registers (X, Y, A, B)

flags (I, Z, D, C)

EI (enable interrupt)

I : Interrupt flag

D : Decimal adjustment flag

Clear data RAM (00H to 04FH)

Clear segment RAM (90H to 0AFH)

Set stack pointer to 40H

Enable K03–K00 input port interrupt

Enable timer interrupt 2 Hz, 8 Hz, 32 Hz

To next process

S1C60N01 TECHNICAL SOFTWARE EPSON II-13

CHAPTER 3: PERIPHERAL CIRCUITS (Input Ports)

PERIPHERAL CIRCUITS

Details on how to control the S1C60N01 peripheral circuit is

given in this chapter.

CHAPTER 3

3.1

Input port memory

map

Table 3.1.1 I/O memory map

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always 0 when being read

*6 Refer to main manual

Input Ports

Address Comment

D3 D2 D1 D0 Name SR

0E0H

K03 K02 K01 K00

K03

K02

K01

K00

–

Input port (K00–K03)

High

Low

0E8H

EIK03 EIK02 EIK01 EIK00

R/W

EIK03

EIK02

EIK01

EIK00

Interrupt mask register (K03)

Interrupt mask register (K02)

Interrupt mask register (K01)

Interrupt mask register (K00)

Enable

Mask

0EDH

00 IK0

IK0 0

Interrupt factor flag (K00–K03)

Yes No

II-14 EPSON S1C60N01 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Input Ports)

The S1C60N01 has one 4-bit input port (K00–K03). Input

port data can be read as a 4-bit unit (K00–K03).

The state of the input ports can be obtained by reading the

data (bits D3, D2, D1, D0) of address 0E0H. The input ports

can be used to send an interrupt request to the CPU via the

input interrupt condition flag. See Section 3.8 "Interrupt

and Halt", for details.

• Loading K00–K03 into the A register

Label Mnemonic/operand Comment

LD Y,0E0H ;Set address of port

LD A,MY ;A register ← K00–K03

As shown in Figure 3.1.1, the two instruction steps above

load the data of the input port into the A register.

Control of

the input port

Examples of input

port control

program

K03

K02

K01

K00

A register

The data of the input port can be loaded into the B register

or MX instead of the A register.

Fig. 3.1.1

Loading the A register

S1C60N01 TECHNICAL SOFTWARE EPSON II-15

CHAPTER 3: PERIPHERAL CIRCUITS (Input Ports)

• Bit-unit checking of input ports

Label Mnemonic/operand Comment

DI ;Disable interrupt

LD Y,0E0H ;Set address of port

INPUT1: FAN MY,0010B ;

JP NZ,INPUT1 ;Loop until K01 becomes "0"

INPUT2: FAN MY,0010B ;

JP Z,INPUT2 ;Loop until K01 becomes "1"

This program loopes until a rising edge is input to input port

K01.

The input port can be addressed using the X register instead

of the Y register.

When the input port is changed from high level to low level with a

pull-down resistor, the signal falls following a certain delay caused

by the time constants of the pull-down resistance and the input

gate capacitance. It is therefore necessary to observe a proper

wait time before the input port data is read.

Note

II-16 EPSON S1C60N01 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Output Ports)

Output Ports3.2

Output port

memory map

Table 3.2.1 I/O memory map

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always 0 when being read

*6 Refer to main manual

The S1C60N01 Series have 2 bits for general output ports

(R00, R01). R00 and R01 although can be use for special

use output port as shown in later of this section. The output

port is a read/write register, output pins provide the con-

tents of the register. The states of the output ports (R00,

R01) are decided by the data of address 0F3H. Output ports

can also be read, and output control is possible using the

operation instructions (AND, OR, etc.). The output ports are

all initialized to low level (0) after an initial reset.

Control of

the output port

Address Comment

D3 D2 D1 D0 Name 1 0

0F3H

R01 R00 0

R01

BUZZER

R00

FOUT

High

Low

OFF

Low

OFF

R01 output port data

Buzzer ON/OFF control register

R00 output port data

Frequency output ON/OFF control register

R/WR

BUZZER FOUT

S1C60N01 TECHNICAL SOFTWARE EPSON II-17

CHAPTER 3: PERIPHERAL CIRCUITS (Output Ports)

• Loading B register data into R00, R01

Label Mnemonic/operand Comment

LD Y,0F3H ;Set address of port

LD MY,B ;R00, R01 ← B register

As shown in Figure 3.2.1, the two instruction steps above

load the data of the B register into the output ports.

Examples of output

port control

program

D3 D2 D1 D0

Data register R00

Data register R01

B register

"0" when being read

Fig. 3.2.1

Control of the output port

The output data can be taken from the A register, MX, or

immediate data instead of the B register.

II-18 EPSON S1C60N01 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Output Ports)

• Bit-unit operation of output ports

Label Mnemonic/operand Comment

LD Y,0F3H ;Set address of port

OR MY,0010B ;Set R01 to 1

AND MY,1110B ;Set R00 to 0

The three instruction steps above cause the output port to

be set, as shown in Figure 3.2.2.

Fig. 3.2.2

Setting of the output port

0 0 R01 R00

Sets "0"

Sets "1"

Unused

Address 0F3H D3 D2 D1 D0

S1C60N01 TECHNICAL SOFTWARE EPSON II-19

CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports)

Special Use Output Ports3.3

Special use output

port memory map

Table 3.3.1 I/O memory map

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always 0 when being read

*6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name 1 0

0F3H

R01 R00 0

R01

BUZZER

R00

FOUT

High

Low

OFF

Low

OFF

R01 output port data

Buzzer ON/OFF control register

R00 output port data

Frequency output ON/OFF control register

R/WR

BUZZER FOUT

0FDH

XBZR 0 XFOUT1 XFOUT0

XBZR

XFOUT1

XFOUT0

Buzzer frequency control

2 kHz

High

4 kHz

Low

R/WR/W

FOUT frequency control:

XFOUT1(0), XFOUT0(0) -> F1

XFOUT1(0), XFOUT0(1) -> F2

XFOUT1(1), XFOUT0(0) -> F3

XFOUT1(1), XFOUT0(1) -> F4

SR *1

II-20 EPSON S1C60N01 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports)

In addition to the regular DC, special output can be selected

for output ports R00 and R01, as shown in Table 3.3.2.

Figure 3.3.1 shows the structure of output ports R00 and

R01.

Control of the spe-

cial use output port

Table 3.3.2

Special output

Fig. 3.3.1

Structure of output ports

R00, R01

FOUT or BUZZER

BUZZER

R00

R01

Pin Name When Special Output is Selected

Address

(0F3H)

Data bus

Mask option

R01

R00

(R01)

(R00)

FOUT

BUZZER

S1C60N01 TECHNICAL SOFTWARE EPSON II-21

CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports)

• Buzzer driver output (BUZZER)

When output port R01 is set for BUZZER and R00 is set for

BUZZER, it performs 2,048 Hz or 4,096 Hz selected by

Label Mnemonic/operand Comment

LD Y,0FDH ;Set address of BUZZER

;frequency control register

LD MY,1000B ;Select 2,048 Hz

LD Y,0F3H ;Set address of output port

OR MY,0010B ;Turn on BUZZER

: :

AND MY,1101B ;Turn off BUZZER

Examples of special

use output port

control program

II-22 EPSON S1C60N01 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports)

Table 3.3.3

Mask option and register

selection

• Internal divided frequency output (FOUT)

When output port R00 is set to FOUT output, fosc or clock

frequency divided into fosc is generated. Clock frequency

may be selected individually for F1–F4, from among 5 types

by mask option; a clock frequency is then selected from 4

types (i.e., F1–F4) through XFOUT0 and XFOUT1 (0FDH D0

and D1) registers and is generated.

The clock frequency types are shown in Table 3.3.3.

For example mask option is set to Set 4:

Label Mnemonic/operand Comment

LD Y,0FDH ;Set address of FOUT

;frequency control register

LD MY,0011B ;Select 16,384 Hz

LD Y,0F3H ;Set address of output port

OR MY,0001B ;Turn on FOUT

: :

AND MY,1110B ;Turn off FOUT

Mask

Option

Sets

Clock Frequency (Hz)

Set 4

256

(fosc/128) 512

(fosc/64) 1,024

(fosc/32) 2,048

(fosc/16)

512

(fosc/64) 1,024

(fosc/32) 2,048

(fosc/16)

8,192

(fosc/4)

1,024

(fosc/32) 2,048

(fosc/16) 4,096

(fosc/8)

4,096

(fosc/8) 8,192

(fosc/4) 16,384

(fosc/2)

4,096

(fosc/8)

32,768

(fosc/1)

2,048

(fosc/16) 4,096

(fosc/8) 8,192

(fosc/4) 16,384

(fosc/2)

Set 1

Set 2

Set 3

Set 5

(D1,D0)=(0,0) (D1,D0)=(0,1) (D1,D0)=(1,0) (D1,D0)=(1,1)

F1 F2 F3 F4

fosc = 32.768 kHz

S1C60N01 TECHNICAL SOFTWARE EPSON II-23

CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)

3.4 I/O Ports

I/O port memory

map

Table 3.4.1 I/O memory map

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always 0 when being read

*6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name SR

0F6H

P03 P02 P01 P00 P03

P02

P01

P00

–

I/O port (P00–P03)

High

Low

R/W

0FCH

00 0IOC

IOC 0

I/O port P00–P03 Input/Output

Output Input

R/W

II-24 EPSON S1C60N01 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)

The S1C60N01 contains a 4-bit general I/O port (4 bits × 1).

This port can be used as an input port or an output port,

according to I/O port control register IOC. When IOC is "0",

the port is set for input, when it is "1", the port is set for

output.

• How to set an input port

Set "0" in the I/O port control register (D0 of address 0FCH),

and the I/O port is set as an input port. The state of the I/O

port (P00–P03) is decided by the data of address 0F6H. (In

the input mode, the port level is read directly.)

• How to set an output port

Set "1" in the I/O port control register, and the I/O port is

set as an output port. The state of the I/O port is decided by

the data of address 0F6H. This data is held by the register,

and can be set regardless of the contents of the I/O control

input ports or output ports.)

The I/O control registers are cleared to "0" (input/output

ports are set as input ports), and the data registers are also

cleared to "0" after an initial reset.

Control of

the I/O port

S1C60N01 TECHNICAL SOFTWARE EPSON II-25

CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)

• Loading P00–P03 input data into A register

Label Mnemonic/operand Comment

LD Y,0FCH ;Set address of I/O control port

AND MY,1110B ;Set port as input port

LD Y,0F6H ;Set address of port

LD A,MY ;A register ← P00–P03

As shown in Figure 3.4.1, the four instruction steps above

load the data of the I/O ports into the A register.

P03

P02

P01

P00

A register

Examples of I/O port

control program

Fig. 3.4.1

Loading into the A register

II-26 EPSON S1C60N01 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)

• Loading P00–P03 output data into A register

Label Mnemonic/operand Comment

LD Y,0FCH ;Set the address of input/output

;port control register

OR MY,0001B ;Set as output port

LD Y,0F6H ;Set the address of port

LD A,MY ;A register ← P00–P03

As shown in Figure 3.4.2, the four instruction steps above

load the data of the I/O ports into the A register.

P03 P02 P01 P00

Data register P00

Data register P01

Data register P02

Data register P03

A register D3 D2 D1 D0

Fig. 3.4.2

Control of I/O port (input)

Data can be loaded from the I/O port into the B register or

MX instead of the A register.

S1C60N01 TECHNICAL SOFTWARE EPSON II-27

CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)

• Loading contents of B register into P00–P03

Label Mnemonic/operand Comment

LD Y,0FCH ;Set the address of input/output

;port control register

OR MY,0001B ;Set port as output port

LD Y,0F6H ;Set the address of port

LD MY,B ;P00–P03 ← B register

As shown in Figure 3.4.3, the four instruction steps above

load the data of the B register into the I/O ports.

D3 D2 D1 D0

Data register P00

Data register P01

Data register P02

Data register P03

B register

The output data can be taken from the A register, MX, or

immediate data instead of the B register.

Bit-unit operation for the I/O port is identical to that for the

input ports (K00–K03) or output ports (R00, R01).

Fig. 3.4.3

Control of the I/O port (output)

II-28 EPSON S1C60N01 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)

LCD Driver3.5

LCD driver memory

map

Fig. 3.5.1

Display memory map

Address 0123456789ABCDEF

090

0A0 Display memory (write only)

32 words x 4 bits

Table 3.5.1 I/O memory map

Address Comment

D3 D2 D1 D0 Name SR

0FBH

CSDC 0 0 0

LCD drive switch

Static Dynamic

R/W

CSDC

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always 0 when being read

*6 Refer to main manual

S1C60N01 TECHNICAL SOFTWARE EPSON II-29

CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)

The S1C60N01 contains 128 bits of display memory in

addresses 090H to 0AFH of the data memory. Each display

memory can be assigned to any 80 bits of the 128 bits for

the LCD driver (20 SEG × 4 COM), 60 bits of the 128 bits (20

SEG × 3 COM) or 40 bits of the 128 bits (20 SEG × 2 COM)

by using a mask option. The remaining 48 bits, 68 bits or 88

bits of display memory are not connected to the LCD driver,

and are not output even when data is written. An LCD

segment is on with "1" set in the display memory, and off

with "0" set in the display memory. Note that the display

memory is a write-only.

• LCD drive control register (CSDC)

The LCD drive control register (CSDC: address 0FBH, D3)

can set the 1/1 duty drive. Set "0" in CSDC for 1/4 duty, 1/3

duty or 1/1 duty drive. Set "1" in CSDC and the same value

in the registers corresponding to COMs 0 through 3 for 1/1

duty drive.

Figure 3.5.2 shows the 1/1 duty drive waveform (1/3 bias)

and Figure 3.5.3 shows an example of the 7-segment LCD

assignment.

See page I-41 for the 1/1 duty drive waveform (1/2 bias).

Control of the LCD

driver

II-30 EPSON S1C60N01 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)

Fig. 3.5.3

7-segment LCD assignment

In the assignment shown in Figure 3.5.3, the 7-segment

display pattern is controlled by writing data to display

memory addresses 090H and 091H.

g f e

091H

dcba

090H D3 D2 D1 D0

Address Register

SEG

0–19

COM

0–3

Frame frequency

LCD lighting status

COM0

COM1

COM2

COM3

SEG0–19

-VDD

-VL1

-VL2

-VL3

-VDD

-VL1

-VL2

-VL3

-VDD

-VL1

-VL2

-VL3

Not lit Lit

Fig. 3.5.2

1/1 duty drive control

(1/3 bias)

S1C60N01 TECHNICAL SOFTWARE EPSON II-31

CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)

• Displaying 7-segment

The LCD display routine using the assignment of Figure

3.5.3 can be programmed as follows.

Label Mnemonic/operand Comment

ORG 000H

RETD 3FH ;0 is displayed

RETD 06H ;1 is displayed

RETD 5BH ;2 is displayed

RETD 4FH ;3 is displayed

RETD 66H ;4 is displayed

RETD 6DH ;5 is displayed

RETD 7DH ;6 is displayed

RETD 27H ;7 is displayed

RETD 7FH ;8 is displayed

RETD 6FH ;9 is displayed

SEVENS: LD B,0 ;Set the address of jump

LD X,090H ;Set address of display memory

JPBA

When the above routine is called (by the CALL or CALZ

instruction) with any number from "0" to "9" set in the A

are displayed according to the contents of the A register.

The RETD instruction can be used to write data to the

display memory only if it is addressed using the X register.

(Addressing using the Y register is invalid.)

Note that the stack pointer must be set to a proper value

before the CALL (CALZ) instruction is executed.

Fig. 3.5.4

Data set in A register and

displayed patterns

Examples of

LCD driver control

program

DisplayA resister

II-32 EPSON S1C60N01 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)

• Bit-unit operation of the display memory

Label Mnemonic/operand Comment

LD X,SEGBUF ;Set address display

;memory buffer

LD Y,090H ;Set address display memory

LD MX,3 ;Set buffer data

LD MY,MX ;SEG-A, B ON (●●, ▲▲)

AND MX,1110B ;Change buffer data

LD MY,MX ;SEG-A OFF (●, ▲▲)

AND MX,1101B ;Change buffer data

LD MY,MX ;SEG-B OFF (●, ▲)

For manipulation of the display memory in bit-units for the

assignment of Figure 3.5.5, a buffer must be provided in

RAM to hold data. Note that, since the display memory is

write-only, data cannot be changed directly using an ALU

instruction (for example, AND or OR).

After manipulating the data in the buffer, write it into the

corresponding display memory using the transfer command.

Fig. 3.5.5

Example of segment

assignment

▲●

090H D3 D2 D1 D0

Address Data

▲

●: SEG-A

: SEG-B

S1C60N01 TECHNICAL SOFTWARE EPSON II-33

CHAPTER 3: PERIPHERAL CIRCUITS (Timer)

3.6 Timer

Timer memory map

Table 3.6.1 I/O memory map

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always 0 when being read

*6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name 1 0

0E4H

TM3 TM2 TM1 TM0

TM3

TM2

TM1

TM0

–

Timer data (clock timer 2 Hz)

Timer data (clock timer 4 Hz)

Timer data (clock timer 8 Hz)

Timer data (clock timer 16 Hz)

High

Low

0EBH

0 EIT2 EIT8 EIT32

EIT2

EIT8

EIT32

Enable

Mask

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

R/W

0EFH

0 IT2 IT8 IT32 0

IT2

IT8

IT32

Yes

Interrupt factor flag (clock timer 2 Hz)

Interrupt factor flag (clock timer 8 Hz)

Interrupt factor flag (clock timer 32 Hz)

0F9H

0 TMRST 0 0

TMRST

Reset

Clock timer reset

Reset –

SR *1

II-34 EPSON S1C60N01 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Timer)

The S1C60N01 contains a timer with a basic oscillation of

32.768 kHz (typical). This timer is a 4-bit binary counter,

and the counter data can be read as necessary. The counter

data of the 16 Hz clock can be read by reading TM3 to TM0

(address 0E4H, D3 to D0). ("1" to "0" are set in TM3 to TM0,

corresponding to the high-low levels of the 2 Hz, 4 Hz, 8 Hz,

and 16 Hz 50 % duty waveform. See Figure 3.6.1.) The timer

can also interrupt the CPU on the falling edges of the 32 Hz,

8 Hz, and 2 Hz signals. For details, see Section 3.8, "Inter-

rupt and Halt".

Control of the timer

The timer is reset by setting "1" in TMRST (address 0F9H,

D2).

The 128 Hz to 2 Hz of the internal divider is initialized by resetting

the timer

Fig. 3.6.1

Output waveform of

timer and interrupt timing

Note

Clock timer timing chart

Frequency

bit

Address

0E4H

D0 16 Hz

8 Hz

4 Hz

2 Hz

Occurrence of

32 Hz interrupt request

Occurrence of

8 Hz interrupt request

Occurrence of

2 Hz interrupt request

S1C60N01 TECHNICAL SOFTWARE EPSON II-35

CHAPTER 3: PERIPHERAL CIRCUITS (Timer)

• Initializing the timer

Label Mnemonic/operand Comment

LD Y,0F9H ;Set address of the timer

;reset register

OR MY,0100B ;Reset the timer

The two instruction steps above are used to reset (clear

TM0–TM3 to 0) and restart the timer. The TMRST register is

cleared to "0" by hardware 1 clock after it is set to "1".

• Loading the timer

Label Mnemonic/operand Comment

LD Y,0E4H ;Set address of

;the timer data (TM0 to TM3)

LD A,MY ;Load the data of

;TM0 to TM3 into A register

As shown in Table 3.6.2, the two instruction steps load the

data of TM0 to TM3 into the A register.

Table 3.6.2

Loading the timer data

Examples of timer

control program

TM3 (2 Hz)

TM2 (4 Hz)

TM1 (8 Hz)

TM0 (16 Hz)

A register

II-36 EPSON S1C60N01 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Timer)

• Checking timer edge

Label Mnemonic/operand Comment

LD X,TMSTAT ;Set address of the timer edge counter

CP MX,0 ;Check whether the timer edge

;counter is "0"

JP Z,RETURN ;Jump if "0" (Z-flag is "1")

LD Y,0E4H ;Set address of the timer

LD A,MY ;Read the data of TM0 to TM3

;into A register

LD Y,TMDTBF ;Set address of the timer data buffer

XOR MY,A ;Did the count on the timer

;change?

FAN MX,0100B ;Check bit D2 of the timer data buffer

LD MY,A ;Set the data of A register into

;the timer data buffer

JP Z,RETURN ;Jump, if the Z-flag is "1"

ADD MX,0FH ;Decrement the timer edge counter

;

RETURN: RET ;Return

This program takes a subroutine form. It is called at short

intervals, and decrements the data at address TMSTAT every

125 ms until the data reaches "0". The timing chart is

shown in Figure 3.6.2. The timer can be addressed using

the X register instead of the Y register.

TMSTAT and TMDTBF may be any address in RAM and not

involve a hardware function.

125 ms

Timer edge counter (TMSTAT) decrementing timing

TM2

Fig. 3.6.2

Timing of the timer

edge counter

Note

S1C60N01 TECHNICAL SOFTWARE EPSON II-37

CHAPTER 3: PERIPHERAL CIRCUITS (Heavy Load Protection Function)

Heavy Load Protection Function3.7

Heavy load protec-

tion function mem-

ory map

Table 3.7.1 I/O memory map

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always 0 when being read

*6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name 1 0

0FAH

HLMOD 0 0 0 HLMOD

Heavy load protection mode register

RR/W

Heavy

load Normal

load

SR *1

Heavy load protec-

tion function

The S1C60N01 has the heavy load protection function for

when the battery load becomes heavy and the source voltage

changes, such as when an external buzzer sounds or an

external lamp lights. The state where the heavy load protec-

tion function is in effect is called the heavy load protection

mode. Compared with the normal operation mode, this mode

can reduce the output voltage variation of the internal regu-

lated voltage and spend more power consumption.

The normal mode changes to the heavy load protection mode

in the following case:

• When the software changes the mode to the heavy load

protection mode (HLMOD = "1")

II-38 EPSON S1C60N01 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Heavy Load Protection Function)

Examples of heavy

load protection

function control

program

• Operation through the HLMOD register

This is a sample program when lamp is driven with the

R00 terminal during performance of heavy load protec-

tion.

Label Mnemonic/operand Comment

LD X,0FAH ;Sets the address of HLMOD

OR MX,1000B ;Sets to the heavy protection mode

LD Y,0F3H ;Sets the address of R0n port

OR MY,0001B ;Turns lamp ON

LD Y,0F3H ;Sets the R0n port address

AND MY,1110B ;Turns the lamp OFF

CALL WT1S ;1 second waiting time (software timer)

AND MX,0111B ;Cancels the heavy load protection mode

In the above program, the heavy load protection mode is

canceled after 1 sec waiting time provided as the time for

the battery voltage to stabilize after the lamp is turned

off; however, since this time varies according to the

nature of the battery, time setting must be done in accor-

dance with the actual application.

S1C60N01 TECHNICAL SOFTWARE EPSON II-39

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

3.8 Interrupt and Halt

Table 3.8.1 I/O memory map

Interrupt memory

map

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always 0 when being read

*6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name 1 0

0E8H

0EBH

EIK03 EIK02 EIK01 EIK00

0 EIT2 EIT8 EIT32

R/W

EIK03

EIK02

EIK01

EIK00

EIT2

EIT8

EIT32

Enable

Mask

Interrupt mask register (K03)

Interrupt mask register (K02)

Interrupt mask register (K01)

Interrupt mask register (K00)

Enable

Mask

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

R/W

0EDH

0 0 IK0

IK0 0

Interrupt factor flag (K00–K03)

Yes No

0EFH

0 IT2 IT8 IT32 0

IT2

IT8

IT32

Enable

Mask

Interrupt factor flag (clock timer 2 Hz)

Interrupt factor flag (clock timer 8 Hz)

Interrupt factor flag (clock timer 32 Hz)

SR *1

II-40 EPSON S1C60N01 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

The S1C60N01 supports two types of a total of 7 interrupts.

There are three timer interrupts (2 Hz, 8 Hz, 32 Hz) and four

input interrupts (K00–K03).

The 7 interrupts are individually enabled or masked (dis-

abled) by interrupt mask registers. The EI and DI instruc-

tions can be used to set or reset the interrupt flag (I), which

enables or disables all the interrupts at the same time.

When an interrupt is accepted, the interrupt flag (I) is reset,

and cannot accepts any other interrupts (DI state).

Restart from the halt state created by the HALT instruction,

is done by interrupt.

Control of interrupts

and halt

S1C60N01 TECHNICAL SOFTWARE EPSON II-41

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

• Interrupt factor flags

This flag is set when any of the K00 to K03 input interrupts

occurs. The interrupt factor flag (IK0) is set to "1" when the

contents of the input (K00–K03) become "1" and the data of

the corresponding interrupt mask register (EIK00–EIK03) is

"1".

The contents of the IK0 flag can be loaded by software to

determine whether the K00–K03 input interrupts have

occured.

The flag is reset when loaded by software. (See Figure

3.8.1.)

IK0

Fig. 3.8.1

K00–K03

Input interrupt circuit

Address 0E8H

Input interrupt mask register

(EIK00–EIK03)

Input interrupt factor

flag register (IK0)

INT

(Interrupt request)

Interrupt flag (I)

K03

K02

K01

K00

Address 0E0H

Data bus

II-42 EPSON S1C60N01 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

This flag is set to "1" when a falling edge is detected in the

timer TM1 (32 Hz) signal.

The contents of the IT32 flag can be loaded by software to

determine whether a 32 Hz timer interrupt has occured.

The flag is reset, when it is loaded by software. (See Figure

3.8.2.)

This flag is set to "1" when a falling edge is detected in the

timer TM1 (8 Hz) signal.

The contents of the IT8 flag can be loaded by software to

determine whether an 8 Hz timer interrupt has occured.

The flag is reset, when it is loaded by software. (See Figure

3.8.2.)

This flag is set to "1" when a falling edge is detected in the

timer TM1 (2 Hz) signal.

The contents of the IT2 flag can be loaded by software to

determine whether a 2 Hz timer interrupt has occured.

The flag is reset, when it is loaded by software. (See Figure

3.8.2.)

IT32

Fig. 3.8.2

Timer interrupt circuit

Address 0EFH

Address 0EBH

Timer interrupt

mask register (EIT)

Timer interrupt

factor flag (IT)

INT

(Interrupt request)

Interrupt flag (I)

Data bus

Data bus Basic clock counter

32 Hz

8 Hz

2 Hz

IT2

IT8

S1C60N01 TECHNICAL SOFTWARE EPSON II-43

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

• Interrupt mask registers

The interrupt mask registers are registers that individually

specify whether to enable or mask the timer interrupt (2 Hz,

8 Hz, 32 Hz) or input interrupt (K00–K03).

The following are descriptions of the interrupt mask regis-

ters.

EIK00 to EIK03 This register enables or masks the K00–K03 input interrupt.

The interrupt condition flag (IK0) is set to "1" when the

contents of the input (K00–K03) become "1" and the data of

the corresponding interrupt mask register (EIK00–EIK03) is

"1". The CPU is interrupted if it is in the EI state (interrupt

flag [I] = "1"). (See Figure 3.8.1.)

When using an input interrupt, if you rewrite the content of

the mask register, when the value of the input terminal

which becomes the interrupt input is in the active status

(input terminal = high status), the factor flag for input

interrupt may be set.

For example, a factor flag is set with the timing of ➀ shown

in Figure 3.8.3. However, when clearing the content of the

mask register with the input terminal kept in the high

status and then setting it, the factor flag of the input inter-

rupt is again set at the timing that has been set.

Consequently, when the input terminal is in the active

status (high status), do not rewrite the mask register (clear-

ing, then setting the mask register), so that a factor flag will

only set at the rising edge in this case. When clearing, then

setting the mask register, set the mask register, when the

input terminal is not in the active status (low status).

When the content of the mask register is rewritten, while

the port K input is in the active status. The input interrupt

factor flag is set at ➀.

Fig. 3.8.3

Input interrupt timing

Port K input

Factor flag set Not set

Mask register

Active status

➀

II-44 EPSON S1C60N01 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

EIT32 This register enables or masks the 32 Hz timer interrupt.

The CPU is interrupted if it is in the EI state when the

interrupt mask register (EIT32) is set to "1" and the inter-

rupt condition flag (IT32) is "1". (See Figure 3.8.2.)

EIT8 This register enables or masks the 8 Hz timer interrupt. The

CPU is interrupted if it is in the EI state when the interrupt

mask register (EIT8) is set to "1" and the interrupt condition

flag (IT8) is "1". (See Figure 3.8.2.)

This register enables or masks the 2 Hz timer interrupt. The

CPU is intterrupted if it is in the EI state when the interrupt

mask register (EIT2) is set to "1" and the interrupt condition

flag (IT2) is "1". (See Figure 3.8.2.)

EIT2

S1C60N01 TECHNICAL SOFTWARE EPSON II-45

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

• Interrupt vector address

The S1C60N01 interrupt vector address is made up of the

low-order 2 bits of the program counter (12 bits), each of

which is assigned a specific function as shown in Figure

3.8.4.

Note that all of the three timer interrupts have the same

vector address, and software must be used to judge whether

or not a given timer interrupt has occurred. For instance,

when the 32 Hz timer interrupt and the 8 Hz timer interrupt

are enabled at the same time, the accepted timer interrupt

must be identified by software. (Similarly, the K00–K03

input interrupts must be identified by software.)

When an interrupt is generated, the hardware resets the

interrupt flag (I) to enter the DI state. Execute the EI in-

struction as necessary to recover the EI state after interrupt

processing.

Set the EI state at the start of the interrupt processing

routine to allow nesting of the interrupts.

The interrupt factor flags must always be reset before set-

ting the EI status in the corresponding interrupt processing

routine. (The flag is reset when the interrupt condition flag

is read by software.)

Fig. 3.8.4

Assignment of the

interrupt vector

address

PCP3 0

PCP2 0

PCP1 1

PCP0 0

PCS7 0

PCS6 0

PCS5 0

PCS4 0

PCS3 ×

PCS2 0

PCS1 ×

PCS0

Input (K00–K03) interrupt

Clock timer interrupt

II-46 EPSON S1C60N01 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

If the EI instruction is executed without resetting the inter-

rupt factor flag after generating the timer interrupt, and if

the corresponding interrupt mask register is still "1", the

same interrupt is generated once more. (See Figure 3.8.5.)

If the EI state is set without resetting the interrupt factor

flag after generating the input interrupt (K00–K03), the same

interrupt is generated once more. (See Figure 3.8.5.)

The interrupt factor flag must always be read (reset) in the

DI state (interrupt flag [I] = "0"). There may be an operation

error if read in the EI state.

The timer interrupt factor flags (IT32, IT8, IT2) and the

stopwatch interrupt factor flags (ISW1, ISW0) are set

whether the corresponding interrupt mask register is set or

not.

The input interrupt factor flag (IK0) is allowed to be set in

the condition when the corresponding interrupt mask regis-

ter (EIK00–EIK03) is set to "1" (interrupt is enabled). (See

Figure 3.8.5.)

Table 3.8.2 shows the interrupt vector map.

Addesses (start address of interrupt processing routines) to

jump to are written into the addresses available for interrupt

vector allocation.

Table 3.8.2

Interrupt vector map

Step Interrupt Vector

Initial reset

Clock timer interrupt

Input (K00–K03) interrupt

Input interrupt and clock timer interrupt

Page

00H

01H

04H

05H

S1C60N01 TECHNICAL SOFTWARE EPSON II-47

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

Fig. 3.8.5

Internal interrupt circuit

K00

EIK00

K01

EIK01

K02

EIK02

K03

EIK03

IT2

EIT2

IT8

EIT8

IT32

EIT32

IK0

(MSB)

(LSB)

Program counter of CPU

(three low-order bits)

Interrupt vector

Interrupt factor flag

Interrupt mask register

Interrupt flag

INT

(Interrupt request)

II-48 EPSON S1C60N01 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

Interruption vector routine

Label Mnemonic/operand Comment

ORG 100H

JP INIT

JP INTR ;Timer interrupt is generated

JP INTR

JP INTR ;K00 to K03 interrupt is generated

JP INTR ;Timer interrupt, K00 to K03 interrupt

;are generated

;

INTR: LD X,0EFH ;Address of timer interrupt factor flag

LD Y,TMFSK ;

Address of timer interrupt factor flag buffer

LD MY,MX

FAN MY,0100B ;Check 2 Hz timer interrupt

JP Z,TI8RQ ;Jump if not 2 Hz timer interrupt

CALL TINT2 ;Call 2 Hz timer interrupt service routine

TI8RQ: LD Y,TMFSK ;Address of timer factor flag buffer

FAN MY,0010B ;Check 8 Hz timer interrupt

JP Z,TI32RQ ;Jump if not 8 Hz timer interrupt

CALL TINT8 ;Call 8 Hz timer interrupt service routine

• Restart from halt state by interrupt

Main routine

Label Mnemonic/operand Comment

LD X,0E8H ;Set address of K00 to K03

;interrupt mask register

OR MX,1111B ;Enable K00 to K03

;input interrupt

;LD X,0EBH ;Set address of timer interrupt

;mask register

OR MX,0111B ;Enable timer interrupt

;(32 Hz, 8 Hz, 2 Hz)

MAIN: EI ;Set interrupt flag (EI state is set)

HALT ;Halt mode

JP MAIN ;Jump to MAIN

Examples of interrupt

and halt control

program

S1C60N01 TECHNICAL SOFTWARE EPSON II-49

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

TI32RQ: LD Y,TMFSK ;Address of timer factor flag buffer

FAN MY,0001B ;Check 8 Hz timer interrupt

JP Z,IK0RQ ;Jump if not 32 Hz timer interrupt

CALL TINT32 ;Call 32 Hz timer interrupt service routine

IK0RQ: LD X,0EDH ;Address of K00 to K03 input interrupt flag

FAN MX,0001B ;Check K00 to K03 input interrupt

JP Z,INTEND ;Jump if not K00 to K03 input interrupt

CALL IK0INT ;Call K00 to K03 input interrupt service

;routine

INTEND: EI

RET

The above program is normally used to restart the CPU

when in the halt state by interrupt and to return it to the

halt state again after the interrupt processing is completed.

The processing proceeds by repeating the → halt interrupt

→ halt → interrupt cycle.

The interrupt factor flag is reset when load by the software.

Thus, when using interrupts which interrupt factor flags are

in the same address at the same time, flag check must be

done after storing the data. For example, store the 1 word

including the factor flag in the RAM. (If check is directly

done by the FAN instruction, the factor flags of the same

address are all reset.)

Reading of interrupt factor flags is available at EI, but be

careful in the following cases.

If the interrupt mask register value corresponding to the

interrupt factor flags to be read is set to "1", an interrupt

request will be generated by the interrupt factor flags set

timing, or an interrupt request will not be generated.

II-50 EPSON S1C60N01 TECHNICAL SOFTWARE

CHAPTER 4: SUMMARY OF PROGRAMMING POINTS

CHAPTER 4

• Core CPU

• Power Supply

SUMMARY OF PROGRAMMING

POINTS

After the system reset, only the program counter (PC),

new page pointer (NPP) and interrupt flag (I) are initial-

ized by the hardware. The other internal circuits whose

settings are undefined must be initialized with the pro-

gram.

External load driving through the output voltage of

constant voltage circuit or voltage booster/reducer is not

permitted.

• Data Memory – Since some portions of the RAM are also used as stack

area during sub-routine call or register saving, see to it

that the data area and the stack area do not overlap.

– The stack area consumes 3 words during a sub-routine

call or interrupt.

– Address 00H–0FH in the RAM is the memory register

area addressed by the register pointer RP.

– Memory is not mounted in unused area within the mem-

ory map and in memory area not indicated in this man-

ual. For this reason, normal operation cannot be assured

for programs that have been prepared with access to

these areas.

• Initial Reset – Maintain the initial reset circuit at high level for at least

4 seconds (in case of oscillation frequency fosc = 32 kHz)

because noise rejector is built-in.

– When utilizing the simultaneous high input reset func-

tion of the input ports (K00–K03), take care not to make

the ports specified during normal operation to go high

simultaneously.

S1C60N01 TECHNICAL SOFTWARE EPSON II-51

CHAPTER 4: SUMMARY OF PROGRAMMING POINTS

• Input Port – When modifying the input port from high level to low level

with pull-down resistance, a delay will occur at the rise of

the waveform due to time constant of the pull-down

resistance and input gate capacities. Provide appropriate

waiting time in the program when performing input port

reading.

– Input interrupt programing related precautions

When the content of the mask register is rewritten, while

the port K input is in the active status. The input interrupt

factor flag is set at ➀.

When using an input interrupt, if you rewrite the content

of the mask register, when the value of the input terminal

which becomes the interrupt input is in the active status

(input terminal = high status), the factor flag for input

interrupt may be set.

For example, a factor flag is set with the timing of ➀

shown in Figure 4.1. However, when clearing the content

of the mask register with the input terminal kept in the

high status and then setting it, the factor flag of the input

interrupt is again set at the timing that has been set.

Consequently, when the input terminal is in the active

status (high status), do not rewrite the mask register

(clearing, then setting the mask register), so that a factor

flag will only set at the rising edge in this case. When

clearing, then setting the mask register, set the mask

status (low status).

Fig. 4.1

Input interrupt timing

• Output Port The FOUT and BUZZER output signal may produce

hazards when the output ports R00 and R01 are turned

on or off.

Port K input

Factor flag set Not set

Mask register

Active status

➀

II-52 EPSON S1C60N01 TECHNICAL SOFTWARE

CHAPTER 4: SUMMARY OF PROGRAMMING POINTS

• Heavy Load Protec-

tion Function In the heavy load protection function (heavy load protec-

tion mode flag = "1"), the internal regulated voltage is

more stabler but spend more power current consump-

tion.

• I/O Port – When the I/O port is set to the output mode and a low-

impedance load is connected to the port pin, the data

written to the register may differ from the data read.

– When the I/O port is set to the input mode and a low-

level voltage (VSS) is input by the built-in pull-down

resistance, an erroneous input results if the time con-

stant of the capacitive load of the input line and the built-

in pull-down resistance load is greater than the read-out

time. When the input data is being read, the time that the

input line is pulled down is equivalent to 0.5 cycles of the

CPU system clock.

Hence, the electric potential of the pins must settle within

0.5 cycles. If this condition cannot be met, some measure

must be devised, such as arranging a pull-down resis-

tance externally, or performing multiple read-outs.

• LCD Driver – Because the display memory is for writing only, re-writing

the contents with computing instructions (e.g., AND, OR,

etc.) which come with read-out operations is not possible.

To perform bit operations, a buffer to hold the display

data is required on the RAM.

– Even when 1/2 duty is selected, the display data corre-

sponding to COM0, COM3 are valid for static drive.

Hence, for static drive set the same value to all display

memory corresponding COM0–COM3.

– Even when 1/3 duty is selected, the display data corre-

sponding to COM3 is valid for static drive. Hence, for

static drive set the same value to all display memory

corresponding COM0–COM3.

– For cadence adjustment, set the display data including

display data corresponding to COM3.

– fosc indicates the oscillation frequency of the oscillation

circuit.

S1C60N01 TECHNICAL SOFTWARE EPSON II-53

CHAPTER 4: SUMMARY OF PROGRAMMING POINTS

• Interrupt – Re-start from the HALT state is performed by the inter-

rupt. The return address after completion of the interrupt

processing in this case will be the address following the

HALT instruction.

– When interrupt occurs, the interrupt flag will be reset by

the hardware and it will become DI state. After comple-

tion of the interrupt processing, set to the EI state

through the software as needed.

Moreover, the nesting level may be set to be program-

mable by setting to the EI state at the beginning of the

interrupt processing routine.

– Be sure to reset the interrupt factor flag before setting to

the EI state on the interrupt processing routine. The

interrupt factor flag is reset by reading through the

software. Not resetting the interrupt factor flag and

interrupt mask register being "1", will cause the same

interrupt to occur again.

– The interrupt factor flag will be reset by reading through

the software. Because of this, when multiple interrupt

factor flags are to be assigned to the same address,

perform the flag check after the contents of the address

has been stored in the RAM. Direct checking with the

FAN instruction will cause all the interrupt factor flag to

be reset.

– Reading of interrupt factor flags is available at EI, but be

careful in the following cases.

If the interrupt mask register value corresponding to the

interrupt factor flags to be read is set to "1", an interrupt

request will be generated by the interrupt factor flags set

timing, or an interrupt request will not be generated.

• Vacant Register and

Read/Write Writing data into the addresses where read/write bits

and read only bits are mixed in 1 word (4 bits) does not

affect the read only bits.

II-54 EPSON S1C60N01 TECHNICAL SOFTWARE

APPENDIX A: TABLE OF INSTRUCTIONS

APPENDIX A Table of Instructions

C, s

NC, s

Z, s

NZ, s

X, x

Y, y

XH, r

XL, r

YH, r

YL, r

r, XH

r, XL

r, YH

r, YL

XH, i

XL, i

YH, i

YL, i

PSET

JPBA

CALL

CALZ

RET

RETS

RETD

NOP5

NOP7

HALT

INC

ADC

Branch

instructions

System

control

instructions

Index

operation

instructions

Classification Operand

IDZC

↑

Clock

Operation Code Flag

NBP p4, NPP p3~p0

PCB NBP, PCP NPP, PCS s7~s0

PCB NBP, PCP NPP, PCS s7~s0 if C=1

PCB NBP, PCP NPP, PCS s7~s0 if C=0

PCB NBP, PCP NPP, PCS s7~s0 if Z=1

PCB NBP, PCP NPP, PCS s7~s0 if Z=0

←

←←

←

PCB NBP, PCP NPP, PCSH B, PCSL A

M(SP-1) PCP, M(SP-2) PCSH, M(SP-3) PCSL+1

SP SP-3, PCP NPP, PCS s7~s0

M(SP-1) PCP, M(SP-2) PCSH, M(SP-3) PCSL+1

SP SP-3, PCP 0, PCS s7~s0

PCSL M(SP), PCSH M(SP+1), PCP M(SP+2)

SP SP+3

PCSL M(SP), PCSH M(SP+1), PCP M(SP+2)

SP SP+3, PC PC+1

PCSL M(SP), PCSH M(SP+1), PCP M(SP+2)

SP SP+3, M(X) i3~i0, M(X+1) l7~l4, X X+2

No operation (5 clock cycles)

No operation (7 clock cycles)

Halt (stop clock)

X X+1

Y Y+1

XH x7~x4, XL x3~x0

YH y7~y4, YL y3~y0

r XH

r XL

r YH

r YL

←←

←←←

←←← ←←←

←←←

←←← ←

←← ←← ←

←←←←

←

←←

←

←←

←

Mne-

monic Operation

XH+i3~i0+C

XL+i3~i0+C

YH+i3~i0+C

YL+i3~i0+C

↓

S1C60N01 TECHNICAL SOFTWARE EPSON II-55

APPENDIX A: TABLE OF INSTRUCTIONS

XH, i

XL, i

YH, i

YL, i

r, i

r, q

A, Mn

B, Mn

Mn, A

Mn, B

MX, i

r, q

MY, i

r, q

MX, l

F, i

LDPX

LDPY

LBPX

SET

RST

SCF

RCF

SZF

RZF

SDF

RDF

INC

DEC

PUSH

POP

Index

operation

instructions

Data

transfer

instructions

Flag

operation

instructions

Stack

operation

instructions

Classification Operand

IDZC

↑

↓

↑

↓

↑

↓

↑

↓

↑

↓

↑

↓

Clock

Operation Code Flag

XH-i3~i0

XL-i3~i0

YH-i3~i0

YL-i3~i0

r i3~i0

r q

M(n3~n0) A

M(n3~n0) B

M(X) i3~i0, X X+1

r q, X X+1

M(Y) i3~i0, Y Y+1

r q, Y Y+1

M(X) l3~l0, M(X+1) l7~l4, X X+2

←

←←

←

←← ←←

Mne-

monic Operation

↓

↑

↓

↑

↓

SP SP+1

SP SP-1

SP SP-1, M(SP) r

SP SP-1, M(SP) XH

SP SP-1, M(SP) XL

SP SP-1, M(SP) YH

SP SP-1, M(SP) YL

SP SP-1, M(SP) F

r M(SP), SP SP+1

←

M(n3~n0)

←

←←

←

F i3~i0

1 (Decimal Adjuster ON)

0 (Decimal Adjuster OFF)

1 (Enables Interrupt)

0 (Disables Interrupt)

←

←←

←

M(SP), SP SP+1

←

II-56 EPSON S1C60N01 TECHNICAL SOFTWARE

APPENDIX A: TABLE OF INSTRUCTIONS

d3 d2, d2 d1, d1 d0, d0 C, C d3

d3 C, d2 d3, d1 d2, d0 d1, C d0

M(n3~n0) M(n3~n0)+1

M(n3~n0) M(n3~n0)-1

↓

SPH, r

SPL, r

r, SPH

r, SPL

r, i

r, q

r, i

r, q

r, i

r, q

r, i

r, q

r, i

r, q

r, i

r, q

r, i

r, q

r, i

r, q

MX, r

MY, r

MX, r

MY, r

POP

ADD

ADC

SUB

SBC

AND

XOR

FAN

RLC

RRC

INC

DEC

ACPX

ACPY

SCPX

SCPY

NOT

Stack

operation

instructions

Arithmetic

instructions

Classification Operand

IDZC

↑↑

↑

Clock

Operation Code Flag

F M(SP), SP SP+1

SPH

SPL

r SPH

r SPL

←

Mne-

monic Operation

↓

↑

←

↓↓

★

r r+i3~i0

r r+q

r r+i3~i0+C

r r+q+C

r r-q

r r-i3~i0-C

r r-q-C

r r i3~i0

r r q

r r i3~i0

r r q

r r i3~i0

r r q

r-i3~i0

r-q

r i3~i0

r q

M(X) M(X)+r+C, X X+1

M(Y) M(Y)+r+C, Y Y+1

M(X) M(X)-r-C, X X+1

M(Y) M(Y)-r-C, Y Y+1

r r

M(SP), SP SP+1

←

←←

←

←←← ←

←← ← ←←

←

S1C60N01 TECHNICAL SOFTWARE EPSON II-57

APPENDIX A: TABLE OF INSTRUCTIONS

Abbreviations used in the explanations have the following

meanings.

A .............. A register

B .............. B register

X .............. XHL register (low order eight bits of index register

IX)

Y .............. YHL register (low order eight bits of index

XH ........... XH register (high order four bits of XHL register)

XL ............ XL register (low order four bits of XHL register)

YH............ YH register (high order four bits of YHL register)

YL ............ YL register (low order four bits of YHL register)

XP ............ XP register (high order four bits of index

YP ............ YP register (high order four bits of index

SP ............ Stack pointer SP

SPH.......... High-order four bits of stack pointer SP

SPL .......... Low-order four bits of stack pointer SP

MX, M(X) .. Data memory whose address is specified with

index register IX

MY, M(Y)... Data memory whose address is specified with

index register IY

Mn, M(n) .. Data memory address 000H–00FH (address

specified with immediate data n of 00H–0FH)

M(SP) ....... Data memory whose address is specified with

stack pointer SP

r, q ........... Two-bit register code

r, q is two-bit immediate data; according to the

contents of these bits, they indicate registers A,

B, and MX and MY (data memory whose ad-

dresses are specified with index registers IX and

IY) rq

r1 r0 q1 q0

0000 A

0101 B

1010 MX

1111 MY

Registers specified

Symbols associated with

registers and memory

II-58 EPSON S1C60N01 TECHNICAL SOFTWARE

APPENDIX A: TABLE OF INSTRUCTIONS

NBP..... New bank pointer

NPP ..... New page pointer

PCB..... Program counter bank

PCP ..... Program counter page

PCS ..... Program counter step

PCSH .. Four high order bits of PCS

PCSL ... Four low order bits of PCS

F ......... Flag register (I, D, Z, C)

C ......... Carry flag

Z ......... Zero flag

D......... Decimal flag

I .......... Interrupt flag

↓............. Flag reset

↑............. Flag set

↕......... Flag set or reset

p ......... Five-bit immediate data or label 00H–1FH

s.......... Eight-bit immediate data or label 00H–0FFH

l .......... Eight-bit immediate data 00H–0FFH

i .......... Four-bit immediate data 00H–0FH

+ ......... Add

- .......... Subtract

∧............. Logical AND

∨............. Logical OR

∀ ............ Exclusive-OR

★......... Add-subtract instruction for decimal operation

when the D flag is set

Symbols associated with

program counter

Symbols associated with

flags

Associated with

immediate data

Associated with

arithmetic and other

operations

S1C60N01 TECHNICAL SOFTWARE EPSON II-59

APPENDIX B: THE S1C60N01 I/O MEMORY MAP

APPENDIX B The S1C60N01 I/O Memory Map

K03

K02

K01

K00

–

HIGH

LOW

INPORT DATA K03

INPORT DATA K02

INPORT DATA K01

INPORT DATA K00

K00

K01

K02

K03

TM3

TM2

TM1

TM0

–

HIGH

LOW

CLOCK TIMER DATA 2 Hz

CLOCK TIMER DATA 4 Hz

CLOCK TIMER DATA 8 Hz

CLOCK TIMER DATA 16 Hz

TM0

TM1

TM2

TM3

EIK03

EIK02

EIK01

EIK00

ENABLE

MASK

K03 INTERRUPT MASK REGISTER

K02 INTERRUPT MASK REGISTER

K01 INTERRUPT MASK REGISTER

K00 INTERRUPT MASK REGISTER

EIK00

R/W

EIK01

R/W

EIK02

R/W

EIK03

R/W

EIT2

EIT8

EIT32

–

ENABLE

–

MASK

TIMER INTERRUPT MASK REGISTER 2 Hz

TIMER INTERRUPT MASK REGISTER 8 Hz

TIMER INTERRUPT MASK REGISTER 32 Hz

EIT32

R/W

EIT8

R/W

EIT2

R/W

IK0 K00–K03 INTERRUPT FACTOR FLAG

IK0

IT2

IT8

IT32

–

YES

–

TIMER INTERRUPT FACTOR FLAG 2 Hz

TIMER INTERRUPT FACTOR FLAG 8 Hz

TIMER INTERRUPT FACTOR FLAG 32 Hz

IT32

IT8

IT2

AD-

DRESS

D0D1D2D3 01SRNAME COMMENT

DATA

–

YES

–

R01

BUZZER

R00

FOUT

–

HIGH

–

LOW

OFF

LOW

OFF

R01 OUTPUT PORT DATA

BUZZER ON/OFF CONTROL REGISTER

R00 OUTPUT PORT DATA

FREQUENCY OUTPUT ON/OFF CONTROL REGISTER

R00

FOUT

R/W

R01

BUZZER

R/W

P03

P02

P01

P00

–

HIGH

LOW

P03 I/O PORT DATA

P02 I/O PORT DATA

P01 I/O PORT DATA

P00 I/O PORT DATA

P00

R/W

P01

R/W

P02

R/W

P03

R/W

TMRST

–

RESET

–

RESET

–

TIMER RESET

TMRST

HLMOD

–

HEAVY

–

NORMAL

–

HEAVY LOAD PROTECTION MODE0

HLMOD

R/W

CSDC

LCD DRIVER CONTROL REG.0

CSDC

R/W

IOC

–

OUT

–

IN I/O IN-OUT CONTROL REG.

IOC

R/W

–

STATIC

–

DYNAMIC

–

XBZR

XFOUT1

XFOUT0

–

2 kHz

–

HIGH

4 kHz

–

LOW

BUZZER FREQUENCY CONTROL

FOUT FREQUENCY CONTROL:

XFOUT1(0), XFOUT0(0) -> F1

XFOUT1(0), XFOUT0(1) -> F2

XFOUT1(1), XFOUT0(0) -> F3

XFOUT1(1), XFOUT0(1) -> F4

XFOUT0

R/W

XFOUT1

R/W

XBZR

R/W

II-60 EPSON S1C60N01 TECHNICAL SOFTWARE

APPENDIX C: TABLE OF THE ICE COMMANDS

APPENDIX C Table of the ICE Commands

Assemble

Disassemble

Dump

Fill

Set

Run Mode

Trace

Break

Move

Data Set

Change CPU

Internal

Registers

#A,a

#L,a1,a2

#DP,a1,a2

#DD,a1,a2

#FP,a1,a2,d

#FD,a1,a2,d

#G,a

#TIM

#OTF

#T,a,n

#U,a,n

#BA,a

#BAR,a

#BD

#BDR

#BR

#BRR

#BM

#BMR

#BRES

#BC

#BE

#BSYN

#BT

#BRKSEL,REM

#MP,a1,a2,a3

#MD,a1,a2,a3

#SP,a

#SD,a

#DR

#SR

#DXY

#SXY

Assemble command mnemonic code and store at address "a"

Contents of addresses a1 to a2 are disassembled and displayed

Contents of program area a1 to a2 are displayed

Content of data area a1 to a2 are displayed

Data d is set in addresses a1 to a2 (program area)

Data d is set in addresses a1 to a2 (data area)

Program is executed from the "a" address

Execution time and step counter selection

On-the-fly display selection

Executes program while displaying results of step instruction

from "a" address

Displays only the final step of #T,a,n

Sets Break at program address "a"

Breakpoint is canceled

Break condition is set for data RAM

Breakpoint is canceled

Break condition is set for Evaluation Board CPU internal registers

Breakpoint is canceled

Combined break conditions set for program data RAM address

and registers

Cancel combined break conditions for program data ROM

address and registers

All break conditions canceled

Break condition displayed

Enter break enable mode

Enter break disable mode

Set break stop/trace modes

Set BA condition clear/remain modes

Contents of program area addresses a1 to a2 are moved to

addresses a3 and after

Contents of data area addresses a1 to a2 are moved to addresses

a3 and after

Data from program area address "a" are written to memory

Data from data area address "a" are written to memory

Item No. Function Command Format Outline of Operation

Display Evaluation Board CPU internal registers

Set Evaluation Board CPU internal registers

Reset Evaluation Board CPU

Display X, Y, MX and MY

Set data for X and Y display and MX, MY

S1C60N01 TECHNICAL SOFTWARE EPSON II-61

APPENDIX C: TABLE OF THE ICE COMMANDS

History

File

Coverage

ROM Access

Terminate

ICE

Command

Display

Self

Diagnosis

#H,p1,p2

#HB

#HG

#HP

#HPS,a

#HC,S/C/E

#HA,a1,a2

#HAR,a1,a2

#HAD

#HS,a

#HSW,a

#HSR,a

#RF,file

#RFD,file

#VF,file

#VFD,file

#WF,file

#WFD,file

#CL,file

#CS,file

#CVD

#CVR

#RP

#VP

#ROM

#HELP

#CHK

Display history data for pointer 1 and pointer 2

Display upstream history data

Display 21 line history data

Display history pointer

Set history pointer

Sets up the history information acquisition before (S),

before/after (C) and after (E)

Sets up the history information acquisition from program area

a1 to a2

Sets up the prohibition of the history information acquisition

from program area a1 to a2

Indicates history acquisition program area

Retrieves and indicates the history information which executed

a program address "a"

Retrieves and indicates the history information which wrote or

read the data area address "a"

Save contents of memory to program file

Save contents of memory to data file

Load ICE set condition from file

Save ICE set condition to file

Terminate ICE and return to operating system control

Display ICE instruction

Report results of ICE self diagnostic test

Move program file to memory

Move data file to memory

Compare program file and contents of memory

Compare data file and contents of memory

Indicates coverage information

Clears coverage information

Move contents of ROM to program memory

Compare contents of ROM with contents of program memory

Set ROM type

Item No. Function Command Format Outline of Operation

means press the RETURN key.

II-62 EPSON S1C60N01 TECHNICAL SOFTWARE

APPENDIX D: CROSS-ASSEMBLER PSEUDO-INSTRUCTION LIST

APPENDIX D Cross-assembler Pseudo-instruction List

Item No. Pseudo-instruction Meaning Example of Use

EQU

(Equation)

ORG

(Origin)

SET

(Set)

(Define Word)

PAGE

(Page)

SECTION

(Section)

END

(End)

MACRO

(Macro)

LOCAL

(Local)

ENDM

(End Macro)

To allocate data to label

To define location counter

To allocate data to label

(data can be changed)

To define ROM data

To define boundary of page

To define boundary of section

To terminate assembly

To define macro

To make local specification of label

during macro definition

To end macro definition

ABC EQU 9

CHECK MACRO DATA

LOCAL LOOP

LOOP CP MX,DATA

JP NZ,LOOP

ENDM

CHECK 1

BCD EQU ABC+1

ORG 100H

ORG 256

ABC SET 0001H

ABC SET 0002H

ABC DW 'AB'

BCD DW 0FFBH

PAGE 1H

PAGE 3

SECTION

END

AMERICA

EPSON ELECTRONICS AMERICA, INC.

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Phone: +44-(0)1344-381700 Fax: +44-(0)1344-381701

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Telex: 65542 EPSCO HX

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SEIKO EPSON CORPORATION

ELECTRONIC DEVICES MARKETING DIVISION

Electronic Device Marketing Department

IC Marketing & Engineering Group

421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN

Phone: +81-(0)42-587-5816 Fax: +81-(0)42-587-5624

ED International Marketing Department Europe & U.S.A.

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Phone: +81-(0)42-587-5812 Fax: +81-(0)42-587-5564

ED International Marketing Department Asia

421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN

Phone: +81-(0)42-587-5814 Fax: +81-(0)42-587-5110

International Sales Operations

In pursuit of “Saving” Technology, Epson electronic devices.

Our lineup of semiconductors, liquid crystal displays and quartz devices

assists in creating the products of our customers’ dreams.

Epson IS energy savings.

http://www.epson.co.jp/device/

Technical Manual

S1C60N01

EPSON Electronic Devices Website

ELECTRONIC DEVICES MARKETING DIVISION

First issue February, 1997

Printed March, 2001 in Japan A