700 MHz to 4200 MHz, Tx DGA ADL5335 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS VPOS2 VPOS3 1 4 13 ADL5335 RFIN- 2 12dB 0dB TO -20dB RFIN+ 3 5 RF power control and calibration in wireless transmitters VPOS1 6 7 8 9 GND1 GND2 GND3 GND4 GND5 11 ENBL 10 RFOUT 16 CS 15 SCLK 14 SDIO 12 FA 16304-001 Differential input to single-ended output conversion Broad input frequency range: 700 MHz to 4200 MHz Maximum gain: 12.0 dB typical Gain range of 20 dB typical Gain step size: 0.5 dB typical Glitch free, thermometer-based digital step attenuator Fast attack, gain switching with programmable gain step Matched 50 inputs and output Figure 1. GENERAL DESCRIPTION The ADL5335 is a digital gain amplifier (DGA) optimized for use in wireless transmitters. A differential input and singleended output facilitates a balun free connection between the broadband integrated transceivers with differential outputs and the RF gain blocks and drivers amplifiers with single-ended inputs. The gain is programmable via a standard Analog Devices, Inc., serial peripheral interface (SPI) port from a maximum gain of 12.0 dB down to a minimum gain of -8.0 dB with a gain step Rev. 0 size of 0.5 dB. The ADL5335 also features a fast attack function where the gain can rapidly increase or decrease by the application of a single pulse. The use of a thermometer-based digital step attenuator (DSA) ensures that gain changes are fundamentally glitch free. The ADL5335 is packaged in a 4 mm x 4 mm, 16-lead LFCSP. A fully populated evaluation board and system demonstration platform (SDP)-based control software are available. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADL5335 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions..............................8 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................9 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 13 General Description ......................................................................... 1 Basic Structure ............................................................................ 13 Revision History ............................................................................... 2 Digital Interface Overview ........................................................ 13 Specifications..................................................................................... 3 Applications Information .............................................................. 15 Digital Logic Timing .................................................................... 6 Basic Connections ...................................................................... 15 Absolute Maximum Ratings ............................................................ 7 Outline Dimensions ....................................................................... 16 Thremal Resistance ...................................................................... 7 Ordering Guide .......................................................................... 16 ESD Caution .................................................................................. 7 REVISION HISTORY 12/2017--Revision 0: Initial Version Rev. 0 | Page 2 of 16 Data Sheet ADL5335 SPECIFICATIONS VPOS1, VPOS2, VPOS3 = 5 V, TA = 25C, impedance out (ZOUT) = 50 , and a differential input drive, unless otherwise noted. Table 1. Parameter OVERALL FUNCTION Input Frequency Range Impedance Input Output GAIN CONTROL Gain Range Maximum Gain Minimum Gain Gain Step Size BAND 8: 925 MHz TO 960 MHz Gain Range Maximum Gain Minimum Gain Gain Flatness Gain Step Error Group Delay Variation Output Third-Order Intercept (IP3) Output 1 dB Compression Point (P1dB) Noise Figure Return Loss Input Output Common-Mode Rejection Ratio (CMRR) BAND 3: 1805 MHz TO 1880 MHz Gain Range Maximum Gain Minimum Gain Gain Flatness Gain Step Error Group Delay Variation Output IP3 Output P1dB Noise Figure Return Loss Input Output CMRR Test Conditions/Comments Min Typ 700 Differential input drive Single-ended output Max Unit 4200 MHz 50 50 20 12.0 -8.0 0.5 dB dB dB dB 200 MHz, all gains All gain states Between any attenuation step Maximum gain, 4 dBm per tone Minimum gain, -18 dBm per tone Maximum gain Minimum gain Maximum gain Minimum gain 20 13.0 -7.0 0.3 0.2 50 34 13.6 18.0 -0.6 5.4 8.3 dB dB dB dB dB ps dBm dBm dBm dBm dB dB Minimum gain Maximum gain vs. frequency (200 MHz) -18 -17 -30 20 dB dB dB dB 200 MHz, all gains All gain states Between any attenuation step Maximum gain, 4 dBm per tone Minimum gain, -18 dBm per tone Maximum gain Minimum gain Maximum gain Minimum gain 20 12.8 -7.2 0.5 0.4 45 33 12 18.3 0 6.9 10.6 dB dB dB dB dB ps dBm dBm dBm dBm dB dB Minimum gain Maximum gain vs. frequency (200 MHz) -32 -23 -17 22 dB dB dB dB Rev. 0 | Page 3 of 16 ADL5335 Parameter BAND 1: 2110 MHz TO 2170 MHz Gain Range Maximum Gain Minimum Gain Gain Flatness Gain Step Error Group Delay Variation Output IP3 Output P1dB Noise Figure Return Loss Input Output CMRR BAND 7: 2620 MHz TO 2690 MHz Gain Range Maximum Gain Minimum Gain Gain Flatness Gain Step Error Group Delay Variation Output IP3 Output P1dB Noise Figure Return Loss Input Output CMRR BAND 42: 3400 MHz TO 3600 MHz Gain Range Maximum Gain Minimum Gain Gain Flatness Gain Step Error Group Delay Variation Output IP3 Output P1dB Noise Figure Data Sheet Test Conditions/Comments Min Typ Max Unit 200 MHz, all gains All gain states Between any attenuation step Maximum gain, 4 dBm per tone Minimum gain, -18 dBm per tone Maximum gain Minimum gain Maximum gain Minimum gain 20 12.5 -7.5 0.5 0.38 20 32 11.6 18.1 -0.2 6.9 10.4 dB dB dB dB dB ps dBm dBm dBm dBm dB dB Minimum gain Maximum gain vs. frequency (200 MHz) -32 -25 -19 25 dB dB dB dB 200 MHz, all gains All gain states Between any attenuation step Maximum gain, 4 dBm per tone Minimum gain, -18 dBm per tone Maximum gain Minimum gain Maximum gain Minimum gain 20 12.0 -8.0 0.7 0.37 30 32 13.1 17.8 -1.1 7.5 10.5 dB dB dB dB dB ps dBm dBm dBm dBm dB dB Minimum gain Maximum gain vs. frequency (200 MHz) -19 -24 -17 26 dB dB dB dB 200 MHz, all gains All gain states Between any attenuation step Maximum gain, 4 dBm per tone Minimum gain, -18 dBm per tone Maximum gain Minimum gain Maximum gain Minimum gain 20 10.2 -9.8 0.7 0.36 20 31 10.9 16.8 2.3 7.5 12.2 dB dB dB dB dB ps dBm dBm dBm dBm dB dB Rev. 0 | Page 4 of 16 Data Sheet Parameter Return Loss Input Output CMRR FREQUENCY = 4.2 GHz Gain Range Maximum Gain Minimum Gain Gain Flatness Gain Step Error Group Delay Variation Output IP3 Output P1dB Noise Figure Return Loss Input Output CMRR SPI PORT AND FAST ATTACK Logic Low Logic High Fast Attack Response Time ENABLE INTERFACE Voltage Level To Enable To Disable Time Enable Disable POWER SUPPLY INTERFACE Supply Voltage Quiescent Current Power Consumption ADL5335 Test Conditions/Comments Min Typ Max Unit Minimum gain Maximum gain vs. frequency (200 MHz) -19 -17 -11 28 dB dB dB dB 200 MHz, all gains All gain states Between any attenuation step Maximum gain, -4 dBm per tone Minimum gain, -18 dBm per tone Maximum gain Minimum gain Maximum gain Minimum gain 20 9.3 -10.7 0.9 0.49 25 29 11 15.8 -3.7 8.7 13.5 dB dB dB dB dB ps dBm dBm dBm dBm dB dB -24 -12 -11 29 dB dB dB dB Minimum gain Maximum gain SDIO, SCLK, CS, FA pins 1.62 0.18 1.8 V V ns 1.8 0.18 V V 20 ENBL pin ENBL voltage (VENBL) increasing Enable/disable voltage (VENBLDN) increasing 1.62 0 30 30 VPOSx pins Main supply Device enabled Device enabled Power-down mode Rev. 0 | Page 5 of 16 4.75 5 125 625 18.5 ns ns 5.25 V mA mW mW ADL5335 Data Sheet DIGITAL LOGIC TIMING Table 2. Parameter tCLK tHI tLO tS Description Maximum serial clock rate Minimum period that SCLK is in a logic high state Minimum period that SCLK is in a logic low state Setup time between falling edge of CS and SCLK Min tH tDS tDH tZ tACCESS Hold time between data and rising edge of SCLK Setup time between data and rising edge of SCLK SCLK to SDIO Hold Time Maximum time delay between CS deactivation and SDIO bus to return to high impedance Maximum time delay between falling edge of SCLK and out data valid for a read operation Typ 25 10 10 15 Max 5 15 10 5 5 Unit MHz ns ns ns ns ns ns ns ns SPI Timing Diagram tHI tDS tS tCLK tDH tH tACCESS tLO CS SCLK DON'T CARE tZ SDIO DON'T CARE R/W A14 A13 A12 A11 A10 A9 D7 D6 Figure 2. SPI Timing Rev. 0 | Page 6 of 16 D5 D4 D3 D2 D1 D0 DON'T CARE 16304-002 DON'T CARE Data Sheet ADL5335 ABSOLUTE MAXIMUM RATINGS THREMAL RESISTANCE Table 3. Parameter Supply Voltage, VPOS SCLK, SDIO, CS, FA Enable Voltage, ENBL Input Average RF Power Equivalent Voltage, Sine Wave Input1 Internal Power Dissipation Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 60 sec) 1 Rating 5.5 V 3.9 V 2.2 V 12 dBm 2.5 V p-p 725 mW 150C -40C to +85C -65C to +150C 300C Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Table 4 shows the thermal resistance from the die to ambient (JA) and die to lead (JC), respectively. Table 4. Thermal Resistance Package Type CP-16-39 ESD CAUTION If the common-mode voltage at the inputs (VCOM) is closer than 0.625 V from either rail voltage (VRAIL), the equivalent voltage reduces to (|VRAIL - VCOM|) x 4, where VRAIL is the rail closest to VCOM. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. 0 | Page 7 of 16 JA 58.7 JC 2.2 Unit C/W ADL5335 Data Sheet 13 VPOS3 14 SDIO 16 CS 15 SCLK PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VPOS1 1 12 FA RFIN- 2 ADL5335 RFIN+ 3 TOP VIEW (Not to Scale) 10 RFOUT NOTES 1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO A GROUND PLANE WITH A LOW THERMAL AND ELECTRICAL IMPEDANCE. 16304-003 GND4 8 GND3 7 GND2 6 9 GND5 GND1 5 VPOS2 4 11 ENBL Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1, 4, 13 2, 3 5 to 9 Mnemonic VPOS1, VPOS2, VPOS3 RFIN-, RFIN+ 10 11 GND1, GND2, GND3, GND4, GND5 RFOUT ENBL 12 FA 14 SDIO 15 SCLK 16 CS EP Description Power Supplies. Separately decouple each power supply pin using 100 pF and 0.1F capacitors. RF Negative and Positive Inputs. These pins have a 50 differential input pair and are internally accoupled. Ground. Connect these ground pins to a low impedance ground plane. RF Output. This pin has a 50 single-ended output and is internally ac-coupled. Enable. A logic high on this pin (1.8 V logic) enables operation and a logic low on this pin puts the device in a low power sleep mode. Fast Attack. A logic high on this pin (1.8 V logic) decreases the programmed gain by an additional 2 dB, 4 dB, 8 dB, or 16 dB. The fast attack attenuation step is defined by the last two bits of an 8-bit programming byte that is written to the device via the SPI. When FA returns to a logic low, the gain returns to its normal programmed level. When not using the fast attack function, tie the FA pin to ground. Serial Data Input/Output (SDIO), 1.8 V Logic. The gain and fast attack attenuation levels are programmed using eight bits (Register Address 0x100). The 24-bit write consists of an R/W bit, a 15-bit register address, and the eight bits of data. The first six bits of data set the gain and the last two bits set the fast attack attenuation (-2 dB, -4 dB, -8 dB, or -16 dB). Serial Clock (SCLK), 1.8 V Logic. The gain and fast attack attenuation levels are programmed using eight bits (Register Address 0x100). The 24-bit write consists of an R/W bit, a 15-bit register address, and the eight bits of data. The first six bits of data set the gain and the last two bits set the fast attack attenuation (-2 dB, -4 dB, -8 dB, or -16 dB). Chip Select Bar (CS), 1.8 V Logic. The gain and fast attack attenuation levels are programmed using eight bits (Register Address 0x100). The 24-bit write consists of an R/W bit, a 15-bit register address, and the eight bits of data. The first six bits of data set the gain and the last two bits set the fast attack attenuation (-2 dB, -4 dB, -8 dB, or -16 dB). Exposed Pad. Connect the exposed pad to a ground plane with a low thermal and electrical impedance. Rev. 0 | Page 8 of 16 Data Sheet ADL5335 25 127 20 125 123 121 119 5.25V 5V 4.75V 117 115 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (C) GAIN = +12dB 15 10 5 GAIN = -8dB 0 -5 +85C +25C -40C -10 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 FREQUENCY (GHz) Figure 4. Supply Current vs. Temperature for Various Power Supplies (VPOS) 16304-007 OUTPUT 1dB COMPRESSION (dBm) 129 16304-004 SUPPLY CURRENT (mA) TYPICAL PERFORMANCE CHARACTERISTICS Figure 7. Output 1dB Compression vs. Frequency for Various Temperatures and Gains, VPOS = 5 V 36 15 14 34 13 12 11 30 28 26 10 9 8 7 +12dB GAIN +10dB GAIN +8dB GAIN +6dB GAIN +4dB GAIN +2dB GAIN 0dB GAIN -2dB GAIN -4dB GAIN -6dB GAIN -8dB GAIN 6 5 4 24 3 +85C +25C -40C 5V 4.75V 5.25V 20 0.5 2 1 5 FREQUENCY (GHz) Figure 5. Output Third-Order Intercept (OIP3) vs. Frequency for Various VPOS and Temperatures, Maximum Gain = 12 dB, Output Tones = 4 dBm 11 20 10 18 9 NOISE FIGURE (dB) 12 22 14 12 10 8 2.0 2.5 3.0 3.5 4.0 4.5 8 7 6 5 4 3 0 0.5 2 5V 4.75V 5.25V +85C +25C -40C 1 5 FREQUENCY (GHz) Figure 6. OIP3 vs. Frequency for Various VPOS and Temperatures, Minimum Gain = -8 dB, Output Tones = -18 dBm 0 0.5 16304-006 +85C +25C -40C 1.0 1.5 2.0 2.5 3.0 FREQUENCY (GHz) 3.5 5V 4.75V 5.25V 4.0 4.5 16304-009 6 2 1.5 FREQUENCY (GHz) 24 4 1.0 Figure 8. Noise Figure vs. Frequency for Various Gain Steps at VPOS = 5 V 16 OIP3 (dBm) 0 0.5 16304-005 22 16304-008 NOISE FIGURE (dB) OIP3 (dBm) 32 Figure 9. Noise Figure vs. Frequency for Various Temperatures and VPOS at Maximum Gain = 12 dB Rev. 0 | Page 9 of 16 ADL5335 Data Sheet 0.5 16 0.4 15 14 13 0.2 12 0.1 GAIN (dB) 0 -0.1 11 10 9 8 -0.2 7 -0.3 6 +85C +25C -40C -0.5 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 GAIN SETTING (dB) +85C +25C -40C 5 5V 4.75V 5.25V 4 0.5 16304-010 -0.4 5 FREQUENCY (GHz) Figure 10. Gain Step Error vs. Gain Setting for Various Temperatures, VPOS = 5 V 16304-013 GAIN STEP ERROR (dB) 0.3 Figure 13. Gain vs. Frequency for Various Temperatures and VPOS 20 14 15 10 12 5 0 10 SSD21 (dB) GAIN (dB) -5 -10 -15 -20 8 6 -25 -30 4 -35 -40 2 0 0.5 16304-011 -50 0.5 5 FREQUENCY LOGARITHMIC RESPONSE (GHz) 1 1.5 2 2.5 3 3.5 4 4.5 5 FREQUENCY (GHz) Figure 11. Gain vs. Frequency Logarithmic Response with a Maximum Gain = +12 dB to a Minimum Gain = -8 dB in 1 dB Steps 16304-014 -45 Figure 14. Forward Transmission (SSD21) vs. Frequency, Gain = 12 dB 15 -24 -26 10 -28 SDS12 (dB) 0 -5 -30 -32 -34 -36 -10 1.8 2.4 3.0 3.6 4.2 FREQUENCY (GHz) Figure 12. Gain vs. Frequency for All Gain Steps (+12 dB to -8 dB, 0.5 dB Step Size), VPOS = 5 V, Temperature = 25C -40 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 FREQUENCY (GHz) Figure 15. Reverse Transmission (SDS12) vs. Frequency, Gain = 12 dB Rev. 0 | Page 10 of 16 16304-015 -15 0.6 -38 16304-012 GAIN (dB) 5 Data Sheet ADL5335 0 40 -5 35 -10 CMRR (dB) SSS22 (dB) 30 -15 -20 25 20 -25 2 2.5 3 3.5 4 4.5 5 FREQUENCY (GHz) Figure 16. Output Reflection Coefficient (SSS22) vs. Frequency, Gain = 12 dB -5 1.5 -10 1.0 VOLTAGE (DC) 2.0 -20 -25 -1.5 -40 0.5 -2.0 -40 2 2.5 3 3.5 4 4.5 5 1.5 1200 1.0 VOLTAGE (DC) 1400 -1.5 FREQUENCY (GHz) -10 0 10 20 30 40 30 40 -0.5 200 5 -20 0 -1.0 0 0.5 -30 0.5 400 16304-018 GROUP DELAY (ps) 2.0 600 FA RF Figure 20. Fast Attack Response, On at 16 dB 1600 800 3.5 4 4.5 5 TIME (ns) Figure 17. Input Reflection Coefficient (SDD11) vs. Frequency, Gain = 12 dB 1000 3 -0.5 -35 1.5 2.5 0 -1.0 FREQUENCY (GHz) 2 0.5 -30 1 1.5 Figure 19. Common-Mode Rejection Ratio (CMRR) vs. Frequency, Gain = 12 dB 0 -15 1 FREQUENCY (GHz) 16304-017 SDD11 (dB) 10 0.5 16304-020 1.5 Figure 18. Group Delay vs. Frequency, Gain = 12 dB -2.0 -40 FA RF -30 -20 -10 0 10 20 TIME (ns) Figure 21. Fast Attack Response, Off at 16 dB Rev. 0 | Page 11 of 16 16304-021 1 16304-016 -35 0.5 16304-019 15 -30 ADL5335 Data Sheet -30 ENBL RF -40 DISTORTION (dBc) -50 HD2 -60 -70 -80 HD3 100 200 300 400 500 TIME (ns) -100 0.5 16304-022 0 0dBm = POUT 2dBm = POUT 4dBm = POUT 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FREQUENCY (GHz) Figure 22. Enable/Disable Time Domain Response Figure 23. Distortion (HD2 and HD3) vs. Frequency for Various Output Powers (POUT) Rev. 0 | Page 12 of 16 4.5 16304-023 -90 Data Sheet ADL5335 THEORY OF OPERATION BASIC STRUCTURE The ADL5335 is an SPI controlled DGA. An integrated, on-chip balun converts a 50 differential RF input into a 50 singleended RF output. The RF inputs and the RF output utilize internal ac coupling capacitors. The DGA core consists of a fixed gain amplifier and digitally controlled attenuator. The amplifier has a gain of 12.0 dB. The attenuator has a range of 0 dB to -8.0 dB with +0.5 dB steps and uses a thermometer coding technique to eliminate transient glitches during gain changes. DIGITAL INTERFACE OVERVIEW The ADL5335 digital section includes an enable pin (ENBL), a fast attack pin (FA), and a SPI. Serial Peripheral Interface (SPI) The SPI uses the three following pins: the serial data input/output (SDIO), the serial clock (SCLK), and the chip select bar (CS). The SPI data register consists of three bytes: one read/write bit (R/W), 15 address bits (A14 to A0), two fast attack (FA) attenuation step size bits (D7 and D6), and six gain control bits (D5 to D0), as shown in Figure 24. The gain code and fast attack attenuation step size bits are controlled via Register Address 0x100. See Table 6 and Table 7, respectively, for their truth tables. Table 6. Gain Code Truth Table 6-Bit Binary Gain Code, Bits[D5:D0] 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 Gain (dB) +12.0 +11.5 +11.0 +10.5 +10.0 +9.5 +9.0 +8.5 +8.0 +7.5 +7.0 +6.5 +6.0 +5.5 +5.0 +4.5 6-Bit Binary Gain Code, Bits[D5:D0] 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 100011 to 111111 Gain (dB) +4.0 +3.5 +3.0 +2.5 +2.0 +1.5 +1.0 +0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 -5.5 -6.0 -6.5 -7.0 -7.5 -8.0 -8.0 Fast Attack (FA) The fast attack feature allows the gain to be reduced from its present setting by a predetermined step size. Four different attenuation step sizes are available (see Table 7). The FA pin controls fast attack mode. A logic high on the FA pin results in an attenuation that is selected by Bits[D7:D6] in the SPI register (Register Address 0x100). Table 7. Fast Attack Attenuation Step Size Truth Table 6-Bit Binary Gain Code, Bits[D7:D6] 00 01 10 11 Rev. 0 | Page 13 of 16 Step Size (dB) -2 -4 -8 -16 ADL5335 Data Sheet R/W DB1 0 1 REGISTER ADDRESS A14 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 1 A7 0 A6 0 FAST ATTACK A5 0 A4 0 A3 0 A2 0 READ/WRITE WRITE READ A1 0 A0 0 D7 0 0 1 1 D6 0 1 0 1 D7 D6 D4 D3 D2 D1 D0 D4 0 0 0 0 . . . 0 0 0 0 . . . 1 D3 0 0 0 0 . . . 0 0 1 1 . . . 1 D2 0 0 0 0 . . . 1 1 0 0 . . . 1 D1 0 0 1 1 . . . 1 1 0 0 . . . 1 D0 0 1 0 1 . . . 0 1 0 1 . . . 1 GAIN 12.0dB 11.5dB 11.0dB 10.5dB . . . -7.0dB -7.5dB -8.0dB -8.0dB . . . -8.0dB ATTENUATION -2dB -4dB -8dB -16dB D5 0 0 0 0 . . . 1 1 1 1 . . . 1 Figure 24. Gain and Fast Attack Programming via Register Address 0x100 Rev. 0 | Page 14 of 16 GAIN D5 16304-024 READ WRITE Data Sheet ADL5335 APPLICATIONS INFORMATION SDIO, and CS), fast attack (FA), and enable (ENBL) pins operate at an 1.8 V voltage. To enable the ADL5335, pull the ENBL pin high (1.8 V). A low on the ENBL pin sets the device to power-down mode, reducing the current to approximately 3.7 mA. BASIC CONNECTIONS Figure 25 shows the basic connections for operating the ADL5335. Apply a 5 V voltage to the supply pins (VPOS1, VPOS2, and VPOS3). Decouple each supply pin with at least one low inductance, surface-mount ceramic, 0.1 F capacitor placed as close to the device as possible. The balanced differential inputs are decoupled using 100 pF capacitors and so is the 50 load on the RF output. The serial peripheral interface pins (SCLK, For additional information on device operation, see the EV-ADL5335SD1Z User Guide. 0.1F SERIAL PERIPHERAL INTERFACE 2 BALANCED SOURCE 100pF 3 4 13 14 15 VPOS1 FA RFIN- ENBL ADL5335 RFIN+ RFOUT VPOS2 GND5 12 1.8V 11 10 100pF 9 GND4 50 LOAD 8 GND3 7 GND2 6 5 GND1 100pF 0.1F 1.8V NOTES 1. THE 100pF CAPACITORS ON THE RFIN- AND RFIN+ PINS ARE OPTIONAL BECAUSE THE DEVICE IS INTERNALLY AC-COUPLED. Figure 25. Basic Connections Rev. 0 | Page 15 of 16 16304-025 1 100pF VPOS3 100pF SDIO CS 0.1F SCLK 16 100pF ADL5335 Data Sheet OUTLINE DIMENSIONS DETAIL A (JEDEC 95) PIN 1 INDICATOR 0.32 0.30 0.25 0.65 BSC 13 PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 16 1 12 2.44 2.34 SQ 2.24 EXPOSED PAD 4 9 TOP VIEW 0.80 0.75 0.70 SIDE VIEW PKG-004901 SEATING PLANE 0.45 0.40 0.35 5 8 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGC-4. 08-04-2017-A 4.10 4.00 SQ 3.90 Figure 26. 16-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm x 4 mm Body and 0.75 mm Package Height (CP-16-39) Dimensions shown in millimeters ORDERING GUIDE Model1 ADL5335ACPZN ADL5335ACPZN-R7 EV-ADL5335SD1Z 1 Temperature Range -40C to +85C -40C to +85C Package Description 16-Lead Lead Frame Chip Scale Package [LFCSP] 16-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board Z = RoHS Compliant Part. (c)2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16304-0-12/17(0) Rev. 0 | Page 16 of 16 Package Option CP-16-39 CP-16-39