2003 Microchip Technology Inc. DS21685B-page 1
MMCP6021/2/3/4
Features
• Rail-to-Rail Input/Output
• Wide Bandwidth: 10 MHz (typ.)
• Low Noise: 8.7 nV/√Hz, at 10 kHz (typ.)
• Low Offset Voltage:
- Industrial Temperature: ±500 µV (max.)
- Extended Temperature: ±250 µV (max.)
• Mid-Supply VREF: MCP6021 and MCP6023
• Low Supply Current: 1 mA (typ.)
• Total Harmonic Distortion: 0.00053% (typ., G = 1)
• Unity Gain Stable
• Power Supply Range: 2.5V to 5.5V
• Temperature Range:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
Typical Applications
• Automotive
• Driving A/D Converters
• Multi-Pole Active Filters
• Barcode Scanners
• Audio Processing
• Communications
• DAC Buffer
• Test Equipment
• Medical Instrumentation
Available Tools
• SPICE Macro Model (at www.microchip.com)
• FilterLab® software (at www.microchip.com)
Description
The MCP6021, MCP6022, MCP6023 and MCP6024
from Microchip Technology Inc. are rail-to-rail input and
output op amps with high performance. Key
specifications include: wide bandwidth (10 MHz), low
noise (8.7 nV/√Hz), low input offset voltage and low
distortion (0.00053% THD+N). These features make
these op amps well suited for applications requiring
high performance and bandwidth. The MCP6023 also
offers a chip select pin (CS) that gives power savings
when the part is not in use.
The single MCP6021, single MCP6023 and dual
MCP6022 are available in standard 8-lead PDIP, SOIC
and TSSOP. The quad MCP6024 is offered in 14-lead
PDIP, SOIC and TSSOP packages.
The MCP6021/2/3/4 family is available in the Industrial
and Extended temperature ranges. It has a power
supply range of 2.5V to 5.5V.
PACKAGE TYPES
MCP6021
PDIP SOIC, TSSOP
1
2
3
4
8
7
6
5
NC
VDD
VOUT
VREF
NC
VIN–
VIN+
VSS
MCP6022
PDIP SOIC, TSSOP
1
2
3
4
8
7
6
5
CS
VDD
VOUT
VREF
NC
VIN–
VIN+
VSS
MCP6023
PDIP SOIC, TSSOP
1
2
3
4
8
7
6
5
VDD
VOUTB
VINB–
VINB+
VOUTA
VINA–
VINA+
VSS
MCP6024
PDIP SOIC, TSSOP
1
2
3
4
VOUTD
VIND–
VIND+
VSS
VOUTA
VINA–
VINA+
VDD
VINC+
VINC–
VOUTC
5
6
7
VINB+
VINB–
VOUTB
14
13
12
11
10
9
8
Rail-to-Rail Input/Output, 10 MHz Op Amps
MCP6021/2/3/4
DS21685B-page 2 2003 Microchip Technology Inc.
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD - VSS .........................................................................7.0V
All Inputs and Outputs ..................... VSS - 0.3V to VDD +0.3V
Difference Input Voltage ....................................... |VDD -V
SS|
Output Short Circuit Current ..................................continuous
Current at Input Pins ....................................................±2 mA
Current at Output and Supply Pins ............................±30 mA
Storage Temperature ....................................-65°C to +150°C
Junction Temperature.................................................. +150°C
ESD Protection on all pins (HBM/MM) ................≥ 2 kV / 200V
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied. Expo-
sure to maximum rating conditions for extended periods may
affect device reliability.
Pin Function Table
Name Function
VIN+, VINA+, VINB+, VINC+, VIND+ Non-inverting Inputs
VIN–, VINA–, VINB–, VINC–, VIND– Inverting Inputs
VDD Positive Power Supply
VSS Negative Power Supply
CS Chip Select
VREF Reference Voltage
VOUT
, VOUTA, VOUTB, VOUTC,
VOUTD
Outputs
NC No Internal Connection
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND,
VCM = VDD/2, VOUT ≈VDD/2 and RL =10kΩ to VDD/2.
Parameters Sym Min Typ Max Units Conditions
Input Offset
Input Offset Voltage:
Industrial Temperature Parts VOS -500 — +500 µV VCM = 0V
Extended Temperature Parts VOS -250 — +250 µV VCM = 0V, VDD = 5.0V
Extended Temperature Parts VOS -2.5 — +2.5 mV VCM = 0V, VDD = 5.0V
TA = -40°C to +125°C
Input Offset Voltage Temperature Drift ∆VOS/∆TA—±3.5—µV/°CT
A = -40°C to +125°C
Power Supply Rejection Ratio PSRR 74 90 — dB VCM = 0V
Input Current and Impedance
Input Bias Current IB—1—pA
Industrial Temperature Parts IB— 30 150 pA TA = +85°C
Extended Temperature Parts IB— 640 5,000 pA TA = +125°C
Input Offset Current IOS —±1—pA
Common-Mode Input Impedance ZCM —10
13||6 — Ω||pF
Differential Input Impedance ZDIFF —10
13||3 — Ω||pF
Common-Mode
Common-Mode Input Range VCMR VSS-0.3 — VDD+0.3 V
Common-Mode Rejection Ratio CMRR 74 90 — dB VDD = 5V, VCM = -0.3V to 5.3V
CMRR 70 85 — dB VDD = 5V, VCM = 3.0V to 5.3V
CMRR 74 90 — dB VDD = 5V, VCM = -0.3V to 3.0V
Voltage Reference (MCP6021 and MCP6023 only)
VREF Accuracy (VREF - VDD/2) ∆VREF -50 — +50 mV
VREF Temperature Drift ∆VREF/∆T
A
—±100—µV/°CT
A = -40°C to +125°C
Open Loop Gain
DC Open Loop Gain (Large Signal) AOL 90 110 — dB VCM = 0V,
VOUT = VSS+0.3V to VDD-0.3V
2003 Microchip Technology Inc. DS21685B-page 3
MCP6021/2/3/4
AC CHARACTERISTICS
MCP6023 CHIP SELECT (CS) CHARACTERISTICS
Output
Maximum Output Voltage Swing VOL, VOH VSS+15 — VDD-20 mV 0.5V output overdrive
Output Short Circuit Current ISC —±30—mA
Power Supply
Supply Voltage VS2.5 — 5.5 V
Quiescent Current per Amplifier IQ0.5 1.0 1.35 mA IO = 0
Electrical Specifications: Unless otherwise indicated, TA = 25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
RL =10kΩ to VDD/2 and CL = 60 pF.
Parameters Sym Min Typ Max Units Conditions
AC Response
Gain Bandwidth Product GBWP — 10 — MHz
Phase Margin at Unity-Gain PM — 65 — ° G = 1
Settling Time, 0.2% tSETTLE — 250 — ns G = 1, VOUT = 100 mVp-p
Slew Rate SR — 7.0 — V/µs
Total Harmonic Distortion Plus Noise
f = 1 kHz, G = 1 THD+N — 0.00053 — % VOUT = 0.25V + 3.25V, BW = 22 kHz
f = 1 kHz, G = 1, RL = 600Ω@1 KHz THD+N — 0.00064 — % VOUT = 0.25V + 3.25V, BW = 22 kHz
f = 1 kHz, G = +1 V/V THD+N — 0.0014 — % VOUT = 4VP-P
, VDD = 5.0V, BW = 22 kHz
f = 1 kHz, G = +10 V/V THD+N — 0.0009 — % VOUT = 4VP-P
, VDD = 5.0V, BW = 22 kHz
f = 1 kHz, G = +100 V/V THD+N — 0.005 — % VOUT = 4VP-P
, VDD = 5.0V, BW = 22 kHz
Noise
Input Voltage Noise Eni — 2.9 — µVp-p f = 0.1 Hz to 10 Hz
Input Voltage Noise Density eni —8.7 —nV/√Hz f = 10 kHz
Input Current Noise Density ini —3 —fA/√Hz f = 1 kHz
Electrical Specifications: Unless otherwise indicated, TA = 25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
RL =10kΩ to VDD/2 and CL = 60 pF.
Parameters Sym Min Typ Max Units Conditions
DC Characteristics
CS Logic Threshold, Low VIL 0 — 0.2VDD V
CS Input Current, Low ICSL -1.0 0.01 — µA CS = VSS
CS Logic Threshold, High VIH 0.8VDD —V
DD V
CS Input Current, High ICSH — 0.01 2.0 µA CS = VDD
CS Input High, GND Current ISS — 0.05 2.0 µA CS = VDD
Amplifier Output Leakage ——0.01—µACS = VDD
Timing
CS Low to Amplifier Output
Turn-on Time
tON — 2 10 µs G = 1, VIN = VSS,
CS = 0.2VDD to VOUT = 0.45VDD time
CS High to Amplifier Output
High-Z Turn-off Time
tOFF — 0.01 — µs G = 1, VIN = VSS,
CS = 0.8VDD to VOUT = 0.05VDD time
Hysteresis VHYST — 0.6 — V Internal Switch
DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND,
VCM = VDD/2, VOUT ≈VDD/2 and RL =10kΩ to VDD/2.
Parameters Sym Min Typ Max Units Conditions
MCP6021/2/3/4
DS21685B-page 4 2003 Microchip Technology Inc.
TEMPERATURE CHARACTERISTICS
FIGURE 1-1: Timing diagram for the CS
pin on the MCP6023.
Electrical Specifications: Unless otherwise indicated, VDD = +2.5V to +5.5V and VSS = GND.
Parameters Symbol Min Typ Max Units Conditions
Temperature Ranges
Industrial Temperature Range TA-40 — +85 °C
Extended Temperature Range TA-40 — +125 °C
Operating Temperature Range TA-40 — +125 °C Note 1
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 8L-PDIP θJA —85—°C/W
Thermal Resistance, 8L-SOIC θJA —163— °C/W
Thermal Resistance, 8L-TSSOP θJA —124— °C/W
Thermal Resistance, 14L-PDIP θJA —70—°C/W
Thermal Resistance, 14L-SOIC θJA —120— °C/W
Thermal Resistance, 14L-TSSOP θJA —100— °C/W
Note 1: The industrial temperature devices operate over this extended temperature range, but with reduced
performance. In any case, the internal junction temperature (TJ) must not exceed the absolute maximum
specification of 150°C.
Hi-Z
tON
CS
tOFF
VOUT
50 nA (typ.)
Hi-Z
ISS
ICS 10 nA (typ.) 10 nA (typ.) 10 nA (typ.)
50 nA (typ.)
1mA (typ.)
Amplifier On
2003 Microchip Technology Inc. DS21685B-page 5
MCP6021/2/3/4
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to +5.5V, VSS = GND, VCM =V
DD/2, RL=10kΩto VDD/2,
VOUT ≈VDD/2 and CL= 60 pF.
FIGURE 2-1: Input Offset Voltage,
(Industrial Temperature Parts).
FIGURE 2-2: Input Offset Voltage,
(Extended Temperature Parts).
FIGURE 2-3: Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 2.5V.
FIGURE 2-4: Input Offset Voltage Drift,
(Industrial Temperature Parts).
FIGURE 2-5: Input Offset Voltage Drift,
(Extended Temperature Parts).
FIGURE 2-6: Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 5.5V.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0%
2%
4%
6%
8%
10%
12%
14%
16%
-500
-400
-300
-200
-100
0
100
200
300
400
500
Input Offset Voltage (µV)
Percentage of Occurances
1192 Samples
TA = +25°C
I-Temp
Parts
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
20%
22%
24%
-200
-160
-120
-80
-40
0
40
80
120
160
200
Input Offset Voltage (µV)
Percentage of Occurances
438 Samples
VDD = 5.0V
VCM = 0V
TA = +25°C
E-Temp
Parts
-500
-400
-300
-200
-100
0
100
200
300
400
500
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
VDD = 2.5V -40°C
+25°C
+85°C
+125°C
0%
1%
2%
3%
4%
5%
6%
7%
8%
9%
10%
11%
12%
-12
-10
-8
-6
-4
-2
0
2
4
6
8
10
12
Input Offset Voltage Drift (µV/°C)
Percentage of Occurances
1192 Samples
TA = -40°C to +85°C I-Temp
Parts
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
20%
22%
24%
26%
-20
-16
-12
-8
-4
0
4
8
12
16
20
Input Offset Voltage Drift (µV/°C)
Percentage of Occurances
438 Samples
VCM = 0V
TA = -40°C to +125°C
E-Temp
Parts
-500
-400
-300
-200
-100
0
100
200
300
400
500
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
VDD = 5.5V -40°C
+25°C
+85°C
+125°C
MCP6021/2/3/4
DS21685B-page 6 2003 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to +5.5V, VSS = GND, VCM =V
DD/2, RL=10kΩto VDD/2,
VOUT ≈VDD/2 and CL= 60 pF.
FIGURE 2-7: Input Offset Voltage vs.
Temperature.
FIGURE 2-8: Input Noise Voltage Density
vs. Frequency.
FIGURE 2-9: Common Mode, Power
Supply Rejection Ratios vs. Frequency.
FIGURE 2-10: Input Offset Voltage vs.
Output Voltage.
FIGURE 2-11: Input Noise Voltage Density
vs. Common Mode Input Voltage.
FIGURE 2-12: Common Mode, Power
Supply Rejection Ratios vs. Temperature.
-300
-250
-200
-150
-100
-50
0
50
100
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Input Offset Voltage (µV)
VDD = 5.0V
VCM = 0V
1
10
100
1,000
1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06
Frequency (Hz)
Input Noise Voltage Density
(nV/Hz)
0.1 1 10 100 1k 10k 1M100k
20
30
40
50
60
70
80
90
100
1.E+02 1.E+03 1.E+04 1.E+05 1.E+06
Frequency (Hz)
CMRR, PSRR (dB)
PSRR-
PSRR+
CMRR
100 1k 10k 100k 1M
-200
-150
-100
-50
0
50
100
150
200
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Input Offset Voltage (µV)
VDD = 5.5V
VCM = VDD/2
VDD = 2.5V
0
2
4
6
8
10
12
14
16
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Common Mode Input Voltage (V)
Input Noise Voltage Density
(nV/Hz)
f = 1 kHz
VDD = 5.0V
70
75
80
85
90
95
100
105
110
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
PSRR, CMRR (dB)
PSRR (VCM = 0V)
CMRR
2003 Microchip Technology Inc. DS21685B-page 7
MCP6021/2/3/4
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to +5.5V, VSS = GND, VCM =V
DD/2, RL=10kΩto VDD/2,
VOUT ≈VDD/2 and CL= 60 pF.
FIGURE 2-13: Input Bias, Offset Currents
vs. Common Mode Input Voltage.
FIGURE 2-14: Quiescent Current vs.
Supply Voltage.
FIGURE 2-15: Output Short-Circuit Current
vs. Supply Voltage.
FIGURE 2-16: Input Bias, Offset Currents
vs. Temperature.
FIGURE 2-17: Quiescent Current vs.
Temperature.
FIGURE 2-18: Open-Loop Gain, Phase vs.
Frequency.
1
10
100
1,000
10,000
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
Input Bias, Offset Currents (pA)
IB, TA = +125°C
VDD = 5.5V
IOS, TA = +85°C
IOS, TA = +125°C
IB, TA = +85°C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Quiescent Current
(mA/amplifier)
+125°C
+85°C
+25°C
-40°C
0
5
10
15
20
25
30
35
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Supply Voltage (V)
Output Short Circuit Current
(mA)
+125°C
+85°C
+25°C
-40°C
1
10
100
1,000
10,000
25 35 45 55 65 75 85 95 105 115 125
Ambient Temperature (°C)
Input Bias, Offset Currents (pA)
IB
VCM = VDD
VDD = 5.5V
IOS
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Quiescent Current
(mA/amplifier)
VDD = 5.5V
VDD = 2.5V
VCM = VDD - 0.5V
-20
-10
0
10
20
30
40
50
60
70
80
90
100
110
120
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
Frequency (Hz)
Open-Loop Gain (dB)
-210
-195
-180
-165
-150
-135
-120
-105
-90
-75
-60
-45
-30
-15
0
Open-Loop Phase (°)
Gain
Phase
1 10010 1k 100k10k 1M 100M10M
MCP6021/2/3/4
DS21685B-page 8 2003 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to +5.5V, VSS = GND, VCM =V
DD/2, RL=10kΩto VDD/2,
VOUT ≈VDD/2 and CL= 60 pF.
FIGURE 2-19: DC Open-Loop Gain vs.
Load Resistance.
FIGURE 2-20: Small Signal DC Open-Loop
Gain vs. Output Voltage Headroom.
FIGURE 2-21: Gain Bandwidth Product,
Phase Margin vs. Temperature.
FIGURE 2-22: DC Open-Loop Gain vs.
Temperature.
FIGURE 2-23: Gain Bandwidth Product,
Phase Margin vs. Common Mode Input Voltage.
FIGURE 2-24: Gain Bandwidth Product,
Phase Margin vs. Output Voltage.
80
90
100
110
120
130
1.E+02 1.E+03 1.E+04 1.E+05
Load Resistance (:)
DC Open-Loop Gain (dB)
VDD = 5.5V
VDD = 2.5V
100 1k 10k 100k
70
80
90
100
110
120
0.00 0.05 0.10 0.15 0.20 0.25 0.30
Output Voltage Headroom (V);
VDD - VOH or VOL - VSS
DC Open-Loop Gain (dB)
VCM = VDD/2
VDD = 2.5V
VDD = 5.5V
0
1
2
3
4
5
6
7
8
9
10
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Gain Bandwidth Product
(MHz)
0
10
20
30
40
50
60
70
80
90
100
Phase Margin, G = +1 (°)
GBWP, VDD = 5.5V
GBWP, VDD = 2.5V
PM, VDD = 2.5V
PM, VDD = 5.5V
90
95
100
105
110
115
120
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
DC Open-Loop Gain (dB)
VDD = 5.5V
VDD = 2.5V
0
2
4
6
8
10
12
14
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Common Mode Input Voltage (V)
Gain Bandwidth Product
(MHz)
0
15
30
45
60
75
90
105
Phase Margin, G = +1 (°)
Gain Bandwidth Product
Phase Margin, G = +1
VDD = 5.0V
0
2
4
6
8
10
12
14
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Output Voltage (V)
Gain Bandwidth Product
(MHz)
0
15
30
45
60
75
90
105
Phase Margin, G = +1 (°)
Gain Bandwidth Product
Phase Margin, G = +1
VDD = 5.0V
VCM = VDD/2
2003 Microchip Technology Inc. DS21685B-page 9
MCP6021/2/3/4
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to +5.5V, VSS = GND, VCM =V
DD/2, RL=10kΩto VDD/2,
VOUT ≈VDD/2 and CL= 60 pF.
FIGURE 2-25: Slew Rate vs. Temperature.
FIGURE 2-26: Total Harmonic Distortion
plus Noise vs. Output Voltage with f = 1 kHz.
FIGURE 2-27: The MCP6021/2/3/4 family
shows no phase reversal under overdrive.
FIGURE 2-28: Maximum Output Voltage
Swing vs. Frequency.
FIGURE 2-29: Total Harmonic Distortion
plus Noise vs. Output Voltage with f = 20 kHz.
FIGURE 2-30: Channel-to-Channel
Separation vs. Frequency (MCP6022 and
MCP6024 only).
0
1
2
3
4
5
6
7
8
9
10
11
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Slew Rate (V/µs)
Falling, VDD = 2.5V
Rising, VDD = 2.5V
Falling, VDD = 5.5V
Rising, VDD = 5.5V
0.0001%
0.0010%
0.0100%
0.1000%
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Output Voltage (VP-P)
THD+N (%)
f = 1 kHz
BWMeas = 22 kHz
VDD = 5.0V
G = +1 V/V
G = +10 V/V
G = +100 V/V
-1
0
1
2
3
4
5
6
0.0E+00 1.0E-05 2.0E-05 3.0E-05 4.0E-05 5.0E-05 6.0E-05 7.0E-05 8.0E-05 9.0E-05 1.0E-04
Time (10 µs/div)
Input, Output Voltage (V)
VDD = 5V
G = +1 V/V
VIN
VOUT
0.1
1
10
1.E+04 1.E+05 1.E+06 1.E+07
Frequency (Hz)
Maximum Output Voltage
Swing (VP-P)
VDD = 5.5V
10k 100k 1M 10M
VDD = 2.5V
0.0001%
0.0010%
0.0100%
0.1000%
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Output Voltage (VP-P)
THD+N (%)
G = +10 V/V
f = 20 kHz
BWMeas = 80 kHz
VDD = 5.0V
G = +1 V/V
G = +100 V/V
105
110
115
120
125
130
135
1.E+03 1.E+04 1.E+05 1.E+06
Frequency (Hz)
Channel to Channel Separation
(dB)
1k 1M
100k
10k
G = +1 V/V
MCP6021/2/3/4
DS21685B-page 10 2003 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to +5.5V, VSS = GND, VCM =V
DD/2, RL=10kΩto VDD/2,
VOUT ≈VDD/2 and CL= 60 pF.
FIGURE 2-31: Output Voltage Headroom
vs. Output Current.
FIGURE 2-32: Small-Signal Non-inverting
Pulse Response.
FIGURE 2-33: Large-Signal Non-inverting
Pulse Response.
FIGURE 2-34: Output Voltage Headroom
vs. Temperature.
FIGURE 2-35: Small-Signal Inverting Pulse
Response.
FIGURE 2-36: Large-Signal Inverting Pulse
Response.
1
10
100
1,000
0.01 0.1 1 10
Output Current Magnitude (mA)
Output Voltage Headroom;
VDD-VOH or VOL-VSS (mV)
VDD - VOH
VOL - VSS
-6.E-02
-5.E-02
-4.E-02
-3.E-02
-2.E-02
-1.E-02
0.E+00
1.E-02
2.E-02
3.E-02
4.E-02
5.E-02
6.E-02
0.E+00 2.E-07 4.E-07 6.E-07 8.E-07 1.E-06 1.E-06 1.E-06 2.E-06 2.E-06 2.E-06
Time (200 ns/div)
Output Voltage (10 mV/div)
G = +1 V/V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.E+00 5.E-07 1.E-06 2.E-06 2.E-06 3.E-06 3.E-06 4.E-06 4.E-06 5.E-06 5.E-06
Time (500 ns/div)
Output Voltage (V)
G = +1 V/V
0
1
2
3
4
5
6
7
8
9
10
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Output Voltage Headroom
VDD-VOH or VOL-VSS (mV)
VDD - VOH
VOL - VSS
-6.E-02
-5.E-02
-4.E-02
-3.E-02
-2.E-02
-1.E-02
0.E+00
1.E-02
2.E-02
3.E-02
4.E-02
5.E-02
6.E-02
0.E+00 2.E-07 4.E-07 6.E-07 8.E-07 1.E-06 1.E-06 1.E-06 2.E-06 2.E-06 2.E-06
Time (200 ns/div)
Output Voltage (10 mV/div)
G = -1 V/V
RF = 1 k:
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.E+00 5.E-07 1.E-06 2.E-06 2.E-06 3.E-06 3.E-06 4.E-06 4.E-06 5.E-06 5.E-06
Time (500 ns/div)
Output Voltage (V)
G = -1 V/V
RF = 1 k:
2003 Microchip Technology Inc. DS21685B-page 11
MCP6021/2/3/4
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to +5.5V, VSS = GND, VCM =V
DD/2, RL=10kΩto VDD/2,
VOUT ≈VDD/2 and CL= 60 pF.
FIGURE 2-37: VREF Accuracy vs. Supply
Voltage (MCP6021 and MCP6023 only).
FIGURE 2-38: Chip Select (CS) Hysteresis
(MCP6023 only) with VDD = 2.5V.
FIGURE 2-39: Chip Select (CS) to
Amplifier Output Response Time (MCP6023
only).
FIGURE 2-40: VREF Accuracy vs.
Temperature (MCP6021 and MCP6023 only).
FIGURE 2-41: Chip Select (CS) Hysteresis
(MCP6023 only) with VDD = 5.5V.
-50
-40
-30
-20
-10
0
10
20
30
40
50
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
VREF Accuracy; VREF-VDD/2 (mV)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.0 0.5 1.0 1.5 2.0 2.5
Chip Select Voltage (V)
Quiescent Current
(mA/amplifier)
Op Amp
shuts off here
Op Amp
turns on here
Hysteresis
VDD = 2.5V
G = +1 V/V
VIN = 1.25V
CS swept
low to high
CS swept
high to low
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0.0E+00 5.0E-06 1.0E-05 1.5E-05 2.0E-05 2.5E-05 3.0E-05 3.5E-05
Time (5 µs/div)
Chip Select Voltage,
Output Voltage (V)
Output High-Z
VDD = 5.0V
G = +1 V/V
VIN = VSS
Output
on
Output
on
VOUT
CS Voltage
-50
-40
-30
-20
-10
0
10
20
30
40
50
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
VREF Accuracy; VREF-VDD/2 (mV)
VDD = 5.5V
VDD = 2.5V
Representative Part
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select Voltage (V)
Quiescent Current
(mA/amplifier)
Op Amp
shuts off here
Op Amp
turns on here
Hysteresis
CS swept
high to low CS swept
low to high
VDD = 5.5V
G = +1 V/V
VIN = 2.75V
MCP6021/2/3/4
DS21685B-page 12 2003 Microchip Technology Inc.
3.0 APPLICATIONS INFORMATION
The MCP6021/2/3/4 family of operational amplifiers
are fabricated on Microchip’s state-of-the-art CMOS
process. They are unity-gain stable and suitable for a
wide range of general-purpose applications.
3.1 Rail-to-Rail Input
The MCP6021/2/3/4 amplifier family is designed to not
exhibit phase inversion when the input pins exceed the
supply voltages. Figure 2-27 shows an input voltage
exceeding both supplies with no resulting phase
inversion.
The input stage of the MCP6021/2/3/4 family of devices
uses two differential input stages in parallel; one
operates at low common-mode input voltage (VCM),
while the other operates at high VCM. With this topology,
the device operates with VCM up to 0.3V past either
supply rail (VSS - 0.3V to VDD + 0.3V) at 25°C. The
amplifier input behaves linearly as long as VCM is kept
within the specified VCMR limits. The input offset voltage
is measured at both VCM =V
SS - 0.3V and VDD + 0.3V
to ensure proper operation.
Input voltages that exceed the input voltage range
(VCMR) can cause excessive current to flow in or out of
the input pins. Current beyond ±2 mA introduces
possible reliability problems. Thus, applications that
exceed this rating must externally limit the input current
with an input resistor (RIN), as shown in Figure 3-1.
FIGURE 3-1: RIN limits the current flow
into an input pin.
3.2 Rail-to-Rail Output
The Maximum Output Voltage Swing is the maximum
swing possible under a particular output load.
According to the specification table, the output can
reach within 20 mV of either supply rail when
RL=10kΩ. See Figure 2-31 and Figure 2-34 for more
information concerning typical performance.
3.3 MCP6023 Chip Select (CS)
The MCP6023 is a single amplifier with chip select
(CS). When CS is high, the supply current is less than
10 nA (typ) and travels from the CS pin to VSS, with the
amplifier output being put into a high-impedance state.
When CS is low, the amplifier is enabled. If CS is left
floating, the amplifier will not operate properly.
Figure 1-1 and Figure 2-39 show the output voltage
and supply current response to a CS pulse.
3.4 MCP6021 and MCP6023 Reference
Voltage
The single op amps (MCP6021 and MCP6023) have
an internal mid-supply reference voltage connected to
the VREF pin (see Figure 3-2). The MCP6021 has CS
internally tied to VSS, which always keeps the op amp
on and always provides a mid-supply reference. With
the MCP6023, taking the CS pin high conserves power
by shutting down both the op amp and the VREF
circuitry. Taking the CS pin low turns on the op amp and
VREF circuitry.
FIGURE 3-2: Simplified internal VREF
circuit (MCP6021 and MCP6023 only).
See Figure 3-3 for a non-inverting gain circuit using the
internal mid-supply reference. The DC-blocking
capacitor (CB) also reduces noise by coupling the op
amp input to the source.
FIGURE 3-3: Non-inverting gain circuit
using VREF (MCP6021 and MCP6023 only).
VIN
RIN VOUT
MCP602X
RIN ≥(Maximum expected VIN) - VDD
2mA
RIN ≥VSS - (Minimum expected VIN)
2mA
VDD
VSS
VREF
CS
50 kΩ
50 kΩ
(CS tied internally to VSS for MCP6021)
VIN
RGRF
VOUT
CBVREF
2003 Microchip Technology Inc. DS21685B-page 13
MCP6021/2/3/4
To use the internal mid-supply reference for an
inverting gain circuit, connect the VREF pin to the non-
inverting input, as shown in Figure 3-4. The capacitor
CB helps reduce power supply noise on the output.
FIGURE 3-4: Inverting gain circuit using
VREF (MCP6021 and MCP6023 only).
If you don’t need the mid-supply reference, leave the
VREF pin open.
3.5 Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases, and the closed loop bandwidth is
reduced. This produces gain-peaking in the frequency
response, with overshoot and ringing in the step
response.
When driving large capacitive loads with these op
amps (e.g., > 60 pF when G = +1), a small series
resistor at the output (RISO in Figure 3-5) improves the
feedback loop’s phase margin (stability) by making the
load resistive at higher frequencies. The bandwidth will
be generally lower than the bandwidth with no
capacitive load.
FIGURE 3-5: Output resistor RISO
stabilizes large capacitive loads.
Figure 3-6 gives recommended RISO values for
different capacitive laods and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
gain are equal. For inverting gains, GN is 1+|Gain| (e.g.,
-1 V/V gives GN = +2 V/V).
FIGURE 3-6: Recommended RISO values
for capacitive loads.
After selecting RISO for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Evaluation on the bench and
simulations with the MCP6021/2/3/4 Spice macro
model are very helpful. Modify RISO’s value until the
response is reasonable.
3.6 Supply Bypass
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good, high-frequency performance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
shared with other parts.
3.7 PCB Surface Leakage
In applications where low input bias current is critical,
PCB (printed circuit board) surface-leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference would
cause 5 pA of current to flow, which is greater than the
MCP6021/2/3/4 family’s bias current at 25°C (1 pA,
typ).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in Figure 3-7.
FIGURE 3-7: Example guard ring layout.
VIN
RGRF
VOUT
VREF
CB
VIN
MCP602X
RISO
VOUT
CL
10
100
1,000
10 100 1,000 10,000
Normalized Capacitance; CL/GN (pF)
Recommended RISO (:)
GN t +1
Guard Ring VIN–V
IN+
MCP6021/2/3/4
DS21685B-page 14 2003 Microchip Technology Inc.
1. Inverting (Figure 3-7) and Transimpedance
Gain Amplifiers (convert current to voltage, such
as photo detectors).
a. Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp’s input (e.g., VDD/2 or ground).
b. Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
2. Non-inverting Gain and Unity-Gain Buffer
a. Connect the guard ring to the inverting input
pin (VIN–); this biases the guard ring to the
common mode input voltage.
b. Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
3.8 High-Speed PCB Layout
Due to their speed capabilities, a little extra care in the
PCB (Printed Circuit Board) layout can make a
significant difference in the performance of these op
amps. Good PC board layout techniques will help you
achieve the performance shown in the Electrical
Characteristics and Typical Performance Curves, while
also helping you minimize EMC (Electro-Magnetic
Compatibility) issues.
Use a solid ground plane and connect the bypass local
capacitor(s) to this plane with minimal length traces.
This cuts down inductive and capacitive crosstalk.
Separate digital from analog, low-speed from high-
speed and low power from high power. This will reduce
interference.
Keep sensitive traces short and straight. Separating
them from interfering components and traces. This is
especially important for high-frequency (low rise-time)
signals.
Sometimes it helps to place guard traces next to victim
traces. They should be on both sides of the victim
trace, and as close as possible. Connect the guard
trace to ground plane at both ends, and in the middle
for long traces.
Use coax cables (or low inductance wiring) to route
signal and power to and from the PCB.
3.9 Typical Applications
3.9.1 A/D CONVERTER DRIVER AND
ANTI-ALIASING FILTER
Figure 3-8 shows a third-order Butterworth filter that
can be used as an A/D converter driver. It has a band-
width of 20 kHz and a reasonable step response. It will
work well for conversion rates of 80 ksps and greater (it
has 29 dB attenuation at 60 kHz).
FIGURE 3-8: A/D converter driver and
anti-aliasing filter with a 20 kHz cutoff frequency.
This filter can easily be adjusted to another bandwidth
by multiplying all capacitors by the same factor.
Alternatively, the resistors can all be scaled by another
common factor to adjust the bandwidth.
3.9.2 OPTICAL DETECTOR AMPLIFIER
Figure 3-9 shows the MCP6021 op amp used as a
transimpedance amplifier in a photo detector circuit.
The photo detector looks like a capacitive current
source, so the 100 kΩ resistor gains the input signal to
a reasonable level. The 5.6 pF capacitor stabilizes this
circuit and produces a flat frequency response with a
bandwidth of 370 kHz.
FIGURE 3-9: Transimpedance amplifier
for an optical detector.
14.7 kΩ33.2 kΩ
1.0 nF
100 pF
MCP602X
8.45 kΩ
1.2 nF
Photo
Detector
100 pF
5.6 pF
100 kΩ
VDD/2
MCP6021
2003 Microchip Technology Inc. DS21685B-page 15
MCP6021/2/3/4
4.0 DESIGN TOOLS
Microchip provides the basic design tools needed for
the MCP6021/2/3/4 family of op amps.
4.1 SPICE Macro Model
The latest SPICE macro model for the MCP6021/2/3/4
op amps is available on our web site
(www.microchip.com). This model is intended as an
initial design tool that works well in the op amp’s linear
region of operation at room temperature. See the
model file for information on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specs and plots.
4.2 FilterLab® Software
The FilterLab® software is an innovative tool that
simplifies analog active filter (using op amps) design.
Available at no cost from our web site (at www.micro-
chip.com), the FilterLab software active filter design
tool provides full schematic diagrams of the filter circuit
with component values. It also outputs the filter circuit
in SPICE format, which can be used with the Macro
Model to simulate actual filter performance.
MCP6021/2/3/4
DS21685B-page 16 2003 Microchip Technology Inc.
5.0 PACKAGING INFORMATION
5.1 Package Marking Information
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
8-Lead SOIC (150 mil) Example:
XXXXXXXX
XXXXYYWW
NNN
MCP6021
I/P256
0331
MCP6021
I/SN0331
256
8-Lead TSSOP Example:
XXXX
YWW
NNN
6021
E331
256
Legend: XX...X Customer specific information*
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*Standard device marking consists of Microchip part number, year code, week code, and traceability
code.
2003 Microchip Technology Inc. DS21685B-page 17
MCP6021/2/3/4
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP6024) Example:
14-Lead TSSOP (MCP6024) Example:
14-Lead SOIC (150 mil) (MCP6024) Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
XXXXXXXXXX
YYWWNNN
XXXXXX
YYWW
NNN
MCP6024-I/P
XXXXXXXXXXXXXX
0331256
6024E
0331
256
XXXXXXXXXX MCP6024ISL
0331256
XXXXXXXXXX
MCP6021/2/3/4
DS21685B-page 18 2003 Microchip Technology Inc.
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
B1
B
A1
A
L
A2
p
α
E
eB
β
c
E1
n
D
1
2
Units INCHES* MILLIMETERS
Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n88
Pitch p.100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .360 .373 .385 9.14 9.46 9.78
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c.008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top α51015 51015
Mold Draft Angle Bottom β51015 51015
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
JEDEC Equivalent: MS-001
Drawing No. C04-018
.010” (0.254mm) per side.
§ Significant Characteristic
2003 Microchip Technology Inc. DS21685B-page 19
MCP6021/2/3/4
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
Foot Angle φ048048
1512015120
β
Mold Draft Angle Bottom
1512015120
α
Mold Draft Angle Top
0.510.420.33.020.017.013BLead Width
0.250.230.20.010.009.008
c
Lead Thickness
0.760.620.48.030.025.019LFoot Length
0.510.380.25.020.015.010hChamfer Distance
5.004.904.80.197.193.189DOverall Length
3.993.913.71.157.154.146E1Molded Package Width
6.206.025.79.244.237.228EOverall Width
0.250.180.10.010.007.004A1Standoff §
1.551.421.32.061.056.052A2Molded Package Thickness
1.751.551.35.069.061.053AOverall Height
1.27.050
p
Pitch
88
n
Number of Pins
MAXNOMMINMAXNOMMINDimension Limits
MILLIMETERSINCHES*Units
2
1
D
n
p
B
E
E1
h
L
β
c
45°
φ
A2
α
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
§ Significant Characteristic
MCP6021/2/3/4
DS21685B-page 20 2003 Microchip Technology Inc.
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
10501050
β
Mold Draft Angle Bottom
10501050
α
Mold Draft Angle Top
0.300.250.19.012.010.007BLead Width
0.200.150.09.008.006.004
c
Lead Thickness
0.700.600.50.028.024.020LFoot Length
3.103.002.90.122.118.114DMolded Package Length
4.504.404.30.177.173.169E1Molded Package Width
6.506.386.25.256.251.246EOverall Width
0.150.100.05.006.004.002A1Standoff §
0.950.900.85.037.035.033A2Molded Package Thickness
1.10.043AOverall Height
0.65.026
p
Pitch
88
n
Number of Pins
MAXNOMMINMAXNOMMINDimension Limits
MILLIMETERS*INCHESUnits
α
A2
A
A1
L
c
β
φ
1
2
D
n
p
B
E
E1
Foot Angle φ048048
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-086
§ Significant Characteristic
2003 Microchip Technology Inc. DS21685B-page 21
MCP6021/2/3/4
14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
n
D
1
2
eB
β
E
c
A
A1
B
B1
L
A2
p
α
Units INCHES* MILLIMETERS
Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n14 14
Pitch p.100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .740 .750 .760 18.80 19.05 19.30
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c.008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top α5 10 15 5 10 15
β5 10 15 5 10 15
Mold Draft Angle Bottom
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-005
§ Significant Characteristic
MCP6021/2/3/4
DS21685B-page 22 2003 Microchip Technology Inc.
14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)
Foot Angle φ048048
1512015120
β
Mold Draft Angle Bottom
1512015120
α
Mold Draft Angle Top
0.510.420.36.020.017.014BLead Width
0.250.230.20.010.009.008
c
Lead Thickness
1.270.840.41.050.033.016LFoot Length
0.510.380.25.020.015.010hChamfer Distance
8.818.698.56.347.342.337DOverall Length
3.993.903.81.157.154.150E1Molded Package Width
6.205.995.79.244.236.228EOverall Width
0.250.180.10.010.007.004A1Standoff §
1.551.421.32.061.056.052A2Molded Package Thickness
1.751.551.35.069.061.053AOverall Height
1.27.050
p
Pitch
1414
n
Number of Pins
MAXNOMMINMAXNOMMINDimension Limits
MILLIMETERSINCHES*Units
2
1
D
p
n
B
E
E1
h
L
c
β
45°
φ
α
A2
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
§ Significant Characteristic
2003 Microchip Technology Inc. DS21685B-page 23
MCP6021/2/3/4
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
840840
φ
Foot Angle
10501050
β
Mold Draft Angle Bottom
10501050
α
Mold Draft Angle Top
0.300.250.19.012.010.007BLead Width
0.200.150.09.008.006.004
c
Lead Thickness
0.700.600.50.028.024.020LFoot Length
5.105.004.90.201.197.193DMolded Package Length
4.504.404.30.177.173.169E1Molded Package Width
6.506.386.25.256.251.246EOverall Width
0.150.100.05.006.004.002A1Standoff §
0.950.900.85.037.035.033A2Molded Package Thickness
1.10.043AOverall Height
0.65.026
p
Pitch
1414
n
Number of Pins
MAXNOMMINMAXNOMMINDimension Limits
MILLIMETERS*INCHESUnits
L
β
c
φ
2
1
D
n
B
p
E1
E
α
A2A1
A
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-087
§ Significant Characteristic
MCP6021/2/3/4
DS21685B-page 24 2003 Microchip Technology Inc.
NOTES:
2003 Microchip Technology Inc. DS21685B-page 25
MCP6021/2/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Sales and Support
PART NO. X/XX
PackageTemperature
Range
Device
Device: MCP6021 CMOS Single Op Amp
MCP6021T CMOS Single Op Amp
(Tape and Reel for SOIC, TSSOP)
MCP6022 CMOS Dual Op Amp
MCP6022T CMOS Dual Op Amp
(Tape and Reel for SOIC and TSSOP)
MCP6023 CMOS Single Op Amp w/ CS Function
MCP6023T CMOS Single Op Amp w/ CS Function
(Tape and Reel for SOIC and TSSOP)
MCP6024 CMOS Quad Op Amp
MCP6024T CMOS Quad Op Amp
(Tape and Reel for SOIC and TSSOP)
Temperature Range: I = -40°C to +85°C
E = -40×C to +125×C
Package: P = Plastic DIP (300 mil Body), 8-lead, 14-lead
SN = Plastic SOIC (150mil Body), 8-lead
SL = Plastic SOIC (150 mil Body), 14-lead
ST = Plastic TSSOP, 8-lead, 14-lead
Examples:
a) MCP6021-I/P: Industrial temperature,
PDIP package.
b) MCP6021-E/P: Extended temperature,
PDIP package.
c) MCP6021-E/SN: Extended temperature,
SOIC package.
a) MCP6022-I/P: Industrial temperature,
PDIP package.
b) MCP6022-E/P: Extended temperature,
PDIP package.
c) MCP6022T-E/ST: Tape and Reel,
Extended temperature,
TSSOP package.
a) MCP6023-I/P: Industrial temperature,
PDIP package.
b) MCP6023-E/P: Extended temperature,
PDIP package.
c) MCP6023-E/SN: Extended temperature,
SOIC package.
a) MCP6024-I/SL: Industrial temperature,
SOIC package.
b) MCP6024-E/SL: Extended temperature,
SOIC package.
c) MCP6024T-E/ST: Tape and Reel,
Extended temperature,
TSSOP package.
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
MCP6021/2/3/4
DS21685B-page 26 2003 Microchip Technology Inc.
NOTES:
2003 Microchip Technology Inc. DS21685B-page 27
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE and PowerSmart are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER,
SEEVAL and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Application Maestro, dsPICDEM, dsPICDEM.net, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
DS21685B-page 28 2003 Microchip Technology Inc.
M
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07/28/03
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