PIC32MX1XX/2XX/5XX 64/100-PIN 32-bit Microcontrollers (up to 512 KB Flash and 64 KB SRAM) with Audio/Graphics/Touch (HMI), CAN, USB, and Advanced Analog Operating Conditions Timers/Output Compare/Input Capture * 2.3V to 3.6V, -40C to +105C (DC to 40 MHz), -40C to +85C (DC to 50 MHz) (R) * Five General Purpose Timers: - Five 16-bit and up to two 32-bit Timers/Counters * Five Output Compare (OC) modules * Five Input Capture (IC) modules * Peripheral Pin Select (PPS) to allow function remap * Real-Time Clock and Calendar (RTCC) module Core: 50 MHz/83 DMIPS MIPS32 M4K(R) * MIPS16e(R) mode for up to 40% smaller code size * Code-efficient (C and Assembly) architecture * Single-cycle (MAC) 32x16 and two-cycle 32x32 multiply Communication Interfaces Clock Management * * * * * 0.9% internal oscillator Programmable PLLs and oscillator clock sources Fail-Safe Clock Monitor (FSCM) Independent Watchdog Timer Fast wake-up and start-up Power Management * Low-power management modes (Sleep and Idle) * Integrated Power-on Reset, Brown-out Reset, and High Voltage Detect * 0.5 mA/MHz dynamic current (typical) * 44 A IPD current (typical) Audio/Graphics/Touch HMI Features * * * * External graphics interface with up to 34 PMP pins Audio data communication: I2S, LJ, RJ, USB Audio data control interface: SPI and I2C Audio data master clock: - Generation of fractional clock frequencies - Can be synchronized with USB clock - Can be tuned in run-time * Charge Time Measurement Unit (CTMU): - Supports mTouch(R) capacitive touch sensing - Provides high-resolution time measurement (1 ns) * USB 2.0-compliant Full-speed OTG controller * Up to five UART modules (12.5 Mbps): - LIN 1.2 protocols and IrDA(R) support * Four 4-wire SPI modules (25 Mbps) * Two I2C modules (up to 1 Mbaud) with SMBus support * PPS to allow function remap * Parallel Master Port (PMP) with dual read/write buffers * Controller Area Network (CAN) 2.0B Compliant with DeviceNetTM addressing support Direct Memory Access (DMA) * Four channels of hardware DMA with automatic data size detection * 32-bit Programmable Cyclic Redundancy Check (CRC) * Two additional channels dedicated to USB * Two additional channels dedicated to CAN Input/Output * 10 mA or 15 mA source/sink for standard VOH/VOL and up to 22 mA for non-standard VOH1 * 5V-tolerant pins * Selectable open drain, pull-ups, and pull-downs * External interrupts on all I/O pins Qualification and Class B Support Advanced Analog Features * ADC Module: - 10-bit 1 Msps rate with one Sample and Hold (S&H) - Up to 48 analog inputs - Can operate during Sleep mode * Flexible and independent ADC trigger sources * On-chip temperature measurement capability * Comparators: - Three dual-input Comparator modules - Programmable reference with 32 voltage points * AEC-Q100 REVG (Grade 2 -40C to +105C) * Class B Safety Library, IEC 60730 Debugger Development Support * * * * In-circuit and in-application programming 4-wire MIPS(R) Enhanced JTAG interface Unlimited program and six complex data breakpoints IEEE 1149.2-compatible (JTAG) boundary scan Packages Note Type QFN Pin Count I/O Pins (up to) 64 53 64 53 100 85 100 85 100 85 Contact/Lead Pitch Dimensions 0.50 mm 9x9x0.9 mm 0.50 mm 10x10x1 mm 0.40 mm 12x12x1 mm 0.50 mm 14x14x1 mm 0.65 mm 7x7x1.2 mm 1: TQFP TFBGA (see Note 1) Please contact your local Microchip Sales Office for information regarding the availability of devices in the 100-pin TFBGA package. 2014-2017 Microchip Technology Inc. DS60001290E-page 1 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY Packages(4) Program Memory (KB)(1) Data Memory (KB) Remappable Pins Timers/Capture/Compare(2) UART SPI/I2S External Interrupts(3) 10-bit 1 Msps ADC (Channels) Analog Comparators USB On-The-Go (OTG) CAN CTMU I2C PMP RTCC DMA Channels (Programmable/Dedicated) I/O Pins JTAG PIC32MX1XX/2XX/5XX 64/100-PIN CONTROLLER FAMILY FEATURES Pins TABLE 1: PIC32MX120F064H 64 QFN, TQFP 64+3 8 37 5/5/5 4 3 5 28 3 N 0 Y 2 Y Y 4/0 53 Y PIC32MX130F128H 64 QFN, TQFP 128+3 16 37 5/5/5 4 3 5 28 3 N 0 Y 2 Y Y 4/0 53 Y 128+3 16 54 5/5/5 5 4 5 48 3 N 0 Y 2 Y Y 4/0 85 Y 128+3 16 37 5/5/5 4 3 5 28 3 Y 0 Y 2 Y Y 4/2 49 Y 128+3 16 54 5/5/5 5 4 5 48 3 Y 0 Y 2 Y Y 81 Y 128+3 16 37 5/5/5 4 3 5 28 3 Y 1 Y 2 Y Y 4/4 49 Y 128+3 16 54 5/5/5 5 4 5 48 3 Y 1 Y 2 Y Y 4/4 81 Y 256+3 32 37 5/5/5 4 3 5 28 3 N 0 Y 2 Y Y 4/0 53 Y 256+3 32 54 5/5/5 5 4 5 48 3 N 0 Y 2 Y Y 4/0 85 Y 256+3 32 37 5/5/5 4 3 5 28 3 Y 0 Y 2 Y Y 4/2 49 Y 256+3 32 54 5/5/5 5 4 5 48 3 Y 0 Y 2 Y Y 4/2 81 Y 256+3 32 37 5/5/5 4 3 5 28 3 Y 1 Y 2 Y Y 4/4 49 Y 256+3 32 54 5/5/5 5 4 5 48 3 Y 1 Y 2 Y Y 4/4 81 Y 512+3 64 37 5/5/5 4 3 5 28 3 N 0 Y 2 Y Y 4/0 53 Y 512+3 64 54 5/5/5 5 4 5 48 3 N 0 Y 2 Y Y 4/0 85 Y 512+3 64 37 5/5/5 4 3 5 28 3 Y 0 Y 2 Y Y 4/2 49 Y 512+3 64 54 5/5/5 5 4 5 48 3 Y 0 Y 2 Y Y 4/2 81 Y 512+3 64 37 5/5/5 4 3 5 28 3 Y 1 Y 2 Y Y 4/4 49 Y 512+3 64 54 5/5/5 5 4 5 48 3 Y 1 Y 2 Y Y 4/4 81 Y Device Remappable Peripherals PIC32MX130F128L PIC32MX230F128H PIC32MX230F128L PIC32MX530F128H PIC32MX530F128L PIC32MX150F256H PIC32MX150F256L PIC32MX250F256H PIC32MX250F256L PIC32MX550F256H PIC32MX550F256L PIC32MX170F512H PIC32MX170F512L PIC32MX270F512H PIC32MX270F512L PIC32MX570F512H PIC32MX570F512L Note 1: 2: 3: 4: 100 TQFP 100 TFBGA 64 QFN, TQFP 100 TQFP 100 TFBGA 64 QFN, TQFP 100 TQFP 100 TFBGA 64 QFN, TQFP 100 TQFP 100 TFBGA 64 QFN, TQFP 100 TQFP 100 TFBGA 64 QFN, TQFP 100 TQFP 100 TFBGA 64 QFN, TQFP 100 TQFP 100 TFBGA 64 QFN, TQFP 100 TQFP 100 TFBGA 64 QFN, TQFP 100 TQFP 100 TFBGA 4/2 All devices feature 3 KB of Boot Flash memory. Four out of five timers are remappable. Four out of five external interrupts are remappable. Please contact your local Microchip Sales Office for information regarding the availability of devices in the 100-pin TFBGA package. DS60001290E-page 2 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY Device Pin Tables TABLE 2: PIN NAMES FOR 64-PIN GENERAL PURPOSE DEVICES 64-PIN QFN(4) AND TQFP (TOP VIEW) PIC32MX120F064H PIC32MX130F128H PIC32MX150F256H PIC32MX170F512H 64 1 64 QFN(4) Pin # Full Pin Name Pin # Full Pin Name 1 AN22/RPE5/PMD5/RE5 33 RPF3/RF3 2 AN23/PMD6/RE6 34 RPF2/RF2 3 AN27/PMD7/RE7 35 RPF6/SCK1/INT0/RF6 4 AN16/C1IND/RPG6/SCK2/PMA5/RG6 36 SDA1/RG3 5 AN17/C1INC/RPG7/PMA4/RG7 37 SCL1/RG2 6 AN18/C2IND/RPG8/PMA3/RG8 38 VDD 7 MCLR 39 OSC1/CLKI/RC12 8 AN19/C2INC/RPG9/PMA2/RG9 40 OSC2/CLKO/RC15 9 VSS 41 VSS 10 VDD 42 RPD8/RTCC/RD8 11 AN5/C1INA/RPB5/RB5 43 RPD9/RD9 12 AN4/C1INB/RB4 44 RPD10/PMA15/RD10 13 PGED3/AN3/C2INA/RPB3/RB3 45 RPD11/PMA14/RD11 14 PGEC3/AN2/CTCMP/C2INB/RPB2/CTED13/RB2 46 RPD0/RD0 15 PGEC1/VREF-/AN1/RPB1/CTED12/RB1 47 SOSCI/RPC13/RC13 16 PGED1/VREF+/AN0/RPB0/PMA6/RB0 48 SOSCO/RPC14/T1CK/RC14 17 PGEC2/AN6/RPB6/RB6 49 AN24/RPD1/RD1 18 PGED2/AN7/RPB7/CTED3/RB7 50 AN25/RPD2/RD2 19 AVDD 51 AN26/C3IND/RPD3/RD3 20 AVSS 52 RPD4/PMWR/RD4 21 AN8/RPB8/CTED10/RB8 53 RPD5/PMRD/RD5 22 AN9/RPB9/CTED4/PMA7/RB9 54 C3INC/RD6 23 TMS/CVREFOUT/AN10/RPB10/CTED11/PMA13/RB10 55 C3INB/RD7 24 TDO/AN11/PMA12/RB11 56 VCAP 25 VSS 57 VDD 26 VDD 58 C3INA/RPF0/RF0 27 TCK/AN12/PMA11/RB12 59 RPF1/RF1 28 TDI/AN13/PMA10/RB13 60 PMD0/RE0 29 AN14/RPB14/SCK3/CTED5/PMA1/RB14 61 PMD1/RE1 30 AN15/RPB15/OCFB/CTED6/PMA0/RB15 62 AN20/PMD2/RE2 31 RPF4/SDA2/PMA9/RF4 63 RPE3/CTPLS/PMD3/RE3 32 RPF5/SCL2/PMA8/RF5 64 AN21/PMD4/RE4 Note 1: 2: 3: 4: 1 TQFP The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 "Peripheral Pin Select" for restrictions. Every I/O port pin (RBx-RGx) can be used as a change notification pin (CNBx-CNGx). See Section 11.0 "I/O Ports" for more information. Shaded pins are 5V tolerant. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 2014-2017 Microchip Technology Inc. DS60001290E-page 3 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 3: PIN NAMES FOR 64-PIN USB DEVICES 64-PIN QFN(4) AND TQFP (TOP VIEW) PIC32MX230F128H PIC32MX530F128H PIC32MX250F256H PIC32MX550F256H PIC32MX270F512H PIC32MX570F512H 64 1 64 QFN Pin # Full Pin Name (4) Pin # Full Pin Name 1 AN22/RPE5/PMD5/RE5 33 USBID/RPF3/RF3 2 AN23/PMD6/RE6 34 VBUS 3 AN27/PMD7/RE7 35 VUSB3V3 4 AN16/C1IND/RPG6/SCK2/PMA5/RG6 36 D- 5 AN17/C1INC/RPG7/PMA4/RG7 37 D+ 6 AN18/C2IND/RPG8/PMA3/RG8 38 VDD 7 MCLR 39 OSC1/CLKI/RC12 8 AN19/C2INC/RPG9/PMA2/RG9 40 OSC2/CLKO/RC15 9 VSS 41 VSS 10 VDD 42 RPD8/RTCC/RD8 11 AN5/C1INA/RPB5/VBUSON/RB5 43 RPD9/SDA1/RD9 12 AN4/C1INB/RB4 44 RPD10/SCL1/PMA15/RD10 13 PGED3/AN3/C2INA/RPB3/RB3 45 RPD11/PMA14/RD11 14 PGEC3/AN2/CTCMP/C2INB/RPB2/CTED13/RB2 46 RPD0/INT0/RD0 15 PGEC1/VREF-/AN1/RPB1/CTED12/RB1 47 SOSCI/RPC13/RC13 16 PGED1/VREF+/AN0/RPB0/PMA6/RB0 48 SOSCO/RPC14/T1CK/RC14 17 PGEC2/AN6/RPB6/RB6 49 AN24/RPD1/RD1 18 PGED2/AN7/RPB7/CTED3/RB7 50 AN25/RPD2/SCK1/RD2 19 AVDD 51 AN26/C3IND/RPD3/RD3 20 AVSS 52 RPD4/PMWR/RD4 21 AN8/RPB8/CTED10/RB8 53 RPD5/PMRD/RD5 22 AN9/RPB9/CTED4/PMA7/RB9 54 C3INC/RD6 23 TMS/CVREFOUT/AN10/RPB10/CTED11/PMA13/RB10 55 C3INB/RD7 24 TDO/AN11/PMA12/RB11 56 VCAP 25 VSS 57 VDD 26 VDD 58 C3INA/RPF0/RF0 27 TCK/AN12/PMA11/RB12 59 RPF1/RF1 28 TDI/AN13/PMA10/RB13 60 PMD0/RE0 29 AN14/RPB14/SCK3/CTED5/PMA1/RB14 61 PMD1/RE1 30 AN15/RPB15/OCFB/CTED6/PMA0/RB15 62 AN20/PMD2/RE2 31 RPF4/SDA2/PMA9/RF4 63 RPE3/CTPLS/PMD3/RE3 32 RPF5/SCL2/PMA8/RF5 64 AN21/PMD4/RE4 Note 1: 2: 3: 4: 1 TQFP The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 "Peripheral Pin Select" for restrictions. Every I/O port pin (RBx-RGx) can be used as a change notification pin (CNBx-CNGx). See Section 11.0 "I/O Ports" for more information. Shaded pins are 5V tolerant. The metal plane at the bottom of the QFN device is not connected to any pins and is recommended to be connected to VSS externally. DS60001290E-page 4 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 4: PIN NAMES FOR 100-PIN GENERAL PURPOSE DEVICES 100-PIN TQFP (TOP VIEW) PIC32MX130F128L PIC32MX150F256L PIC32MX170F512L 100 1 Pin # Full Pin Name Pin # Full Pin Name 1 AN28/RG15 36 VSS 2 VDD 37 VDD 3 AN22/RPE5/PMD5/RE5 38 TCK/CTED2/RA1 4 AN23/PMD6/RE6 39 AN34/RPF13/SCK3/RF13 5 AN27/PMD7/RE7 40 AN35/RPF12/RF12 6 AN29/RPC1/RC1 41 AN12/PMA11/RB12 7 AN30/RPC2/RC2 42 AN13/PMA10/RB13 8 AN31/RPC3/RC3 43 AN14/RPB14/CTED5/PMA1/RB14 AN15/RPB15/OCFB/CTED6/PMA0/RB15 9 RPC4/CTED7/RC4 44 10 AN16/C1IND/RPG6/SCK2/PMA5/RG6 45 VSS 11 AN17/C1INC/RPG7/PMA4/RG7 46 VDD 12 AN18/C2IND/RPG8/PMA3/RG8 47 AN36/RPD14/RD14 13 MCLR 48 AN37/RPD15/SCK4/RD15 14 AN19/C2INC/RPG9/PMA2/RG9 49 RPF4/PMA9/RF4 15 VSS 50 RPF5/PMA8/RF5 16 VDD 51 RPF3/RF3 17 TMS/CTED1/RA0 52 AN38/RPF2/RF2 18 AN32/RPE8/RE8 53 AN39/RPF8/RF8 19 AN33/RPE9/RE9 54 RPF7/RF7 RPF6/SCK1/INT0/RF6 20 AN5/C1INA/RPB5/RB5 55 21 AN4/C1INB/RB4 56 SDA1/RG3 22 PGED3/AN3/C2INA/RPB3/RB3 57 SCL1/RG2 23 PGEC3/AN2/CTCMP/C2INB/RPB2/CTED13/RB2 58 SCL2/RA2 24 PGEC1/AN1/RPB1/CTED12/RB1 59 SDA2/RA3 25 PGED1/AN0/RPB0/RB0 60 TDI/CTED9/RA4 26 PGEC2/AN6/RPB6/RB6 61 TDO/RA5 27 PGED2/AN7/RPB7/CTED3/RB7 62 VDD 28 VREF-/PMA7/RA9 63 OSC1/CLKI/RC12 29 VREF+/PMA6/RA10 64 OSC2/CLKO/RC15 30 AVDD 65 VSS 31 AVSS 66 RPA14/RA14 32 AN8/RPB8/CTED10/RB8 67 RPA15/RA15 33 AN9/RPB9/CTED4/RB9 68 RPD8/RTCC/RD8 34 CVREFOUT/AN10/RPB10/CTED11/PMA13/RB10 69 RPD9/RD9 35 AN11/PMA12/RB11 70 RPD10/PMA15/RD10 Note 1: 2: 3: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 "Peripheral Pin Select" for restrictions. Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See Section 11.0 "I/O Ports" for more information. Shaded pins are 5V tolerant. 2014-2017 Microchip Technology Inc. DS60001290E-page 5 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 4: PIN NAMES FOR 100-PIN GENERAL PURPOSE DEVICES (CONTINUED) 100-PIN TQFP (TOP VIEW) PIC32MX130F128L PIC32MX150F256L PIC32MX170F512L 100 1 Pin # Full Pin Name Pin # 86 Full Pin Name 71 RPD11/PMA14/RD11 VDD 72 RPD0/RD0 87 AN44/C3INA/RPF0/PMD11/RF0 73 SOSCI/RPC13/RC13 88 AN45/RPF1/PMD10/RF1 74 SOSCO/RPC14/T1CK/RC14 89 RPG1/PMD9/RG1 75 VSS 90 RPG0/PMD8/RG0 76 AN24/RPD1/RD1 91 RA6 77 AN25/RPD2/RD2 92 CTED8/RA7 78 AN26/C3IND/RPD3/RD3 93 AN46/PMD0/RE0 79 AN40/RPD12/PMD12/RD12 94 AN47/PMD1/RE1 80 AN41/PMD13/RD13 95 RG14 81 RPD4/PMWR/RD4 96 RG12 82 RPD5/PMRD/RD5 97 RG13 83 AN42/C3INC/PMD14/RD6 98 AN20/PMD2/RE2 84 AN43/C3INB/PMD15/RD7 99 RPE3/CTPLS/PMD3/RE3 85 VCAP 100 AN21/PMD4/RE4 Note 1: 2: 3: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 "Peripheral Pin Select" for restrictions. Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See Section 11.0 "I/O Ports" for more information. Shaded pins are 5V tolerant. DS60001290E-page 6 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 5: PIN NAMES FOR 100-PIN USB DEVICES 100-PIN TQFP (TOP VIEW) PIC32MX230F128L PIC32MX530F128L PIC32MX250F256L PIC32MX550F256L PIC32MX270F512L PIC32MX570F512L 100 1 Pin # Full Pin Name Pin # Full Pin Name 1 AN28/RG15 36 VSS 2 VDD 37 VDD 3 AN22/RPE5/PMD5/RE5 38 TCK/CTED2/RA1 4 AN23/PMD6/RE6 39 AN34/RPF13/SCK3/RF13 5 AN27/PMD7/RE7 40 AN35/RPF12/RF12 6 AN29/RPC1/RC1 41 AN12/PMA11/RB12 7 AN30/RPC2/RC2 42 AN13/PMA10/RB13 8 AN31/RPC3/RC3 43 AN14/RPB14/CTED5/PMA1/RB14 AN15/RPB15/OCFB/CTED6/PMA0/RB15 9 RPC4/CTED7/RC4 44 10 AN16/C1IND/RPG6/SCK2/PMA5/RG6 45 VSS 11 AN17/C1INC/RPG7/PMA4/RG7 46 VDD 12 AN18/C2IND/RPG8/PMA3/RG8 47 AN36/RPD14/RD14 13 MCLR 48 AN37/RPD15/SCK4/RD15 14 AN19/C2INC/RPG9/PMA2/RG9 49 RPF4/PMA9/RF4 15 VSS 50 RPF5/PMA8/RF5 16 VDD 51 USBID/RPF3/RF3 17 TMS/CTED1/RA0 52 AN38/RPF2/RF2 18 AN32/RPE8/RE8 53 AN39/RPF8/RF8 19 AN33/RPE9/RE9 54 VBUS 20 AN5/C1INA/RPB5/VBUSON/RB5 55 VUSB3V3 21 AN4/C1INB/RB4 56 D- 22 PGED3/AN3/C2INA/RPB3/RB3 57 D+ 23 PGEC3/AN2/CTCMP/C2INB/RPB2/CTED13/RB2 58 SCL2/RA2 24 PGEC1/AN1/RPB1/CTED12/RB1 59 SDA2/RA3 25 PGED1/AN0/RPB0/RB0 60 TDI/CTED9/RA4 26 PGEC2/AN6/RPB6/RB6 61 TDO/RA5 27 PGED2/AN7/RPB7/CTED3/RB7 62 VDD 28 VREF-/PMA7/RA9 63 OSC1/CLKI/RC12 29 VREF+/PMA6/RA10 64 OSC2/CLKO/RC15 30 AVDD 65 VSS 31 AVSS 66 RPA14/SCL1/RA14 32 AN8/RPB8/CTED10/RB8 67 RPA15/SDA1/RA15 33 AN9/RPB9/CTED4/RB9 68 RPD8/RTCC/RD8 34 CVREFOUT/AN10/RPB10/CTED11/PMA13/RB10 69 RPD9/RD9 35 AN11/PMA12/RB11 70 RPD10/SCK1/PMA15/RD10 Note 1: 2: 3: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 "Peripheral Pin Select" for restrictions. Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See Section 11.0 "I/O Ports" for more information. Shaded pins are 5V tolerant. 2014-2017 Microchip Technology Inc. DS60001290E-page 7 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 5: PIN NAMES FOR 100-PIN USB DEVICES (CONTINUED) 100-PIN TQFP (TOP VIEW) PIC32MX230F128L PIC32MX530F128L PIC32MX250F256L PIC32MX550F256L PIC32MX270F512L PIC32MX570F512L 100 1 Pin # Full Pin Name Pin # 86 Full Pin Name 71 RPD11/PMA14/RD11 VDD 72 RPD0/INT0/RD0 87 AN44/C3INA/RPF0/PMD11/RF0 73 SOSCI/RPC13/RC13 88 AN45/RPF1/PMD10/RF1 74 SOSCO/RPC14/T1CK/RC14 89 RPG1/PMD9/RG1 75 VSS 90 RPG0/PMD8/RG0 76 AN24/RPD1/RD1 91 RA6 77 AN25/RPD2/RD2 92 CTED8/RA7 78 AN26/C3IND/RPD3/RD3 93 AN46/PMD0/RE0 79 AN40/RPD12/PMD12/RD12 94 AN47/PMD1/RE1 80 AN41/PMD13/RD13 95 RG14 81 RPD4/PMWR/RD4 96 RG12 82 RPD5/PMRD/RD5 97 RG13 83 AN42/C3INC/PMD14/RD6 98 AN20/PMD2/RE2 84 AN43/C3INB/PMD15/RD7 99 RPE3/CTPLS/PMD3/RE3 85 VCAP 100 AN21/PMD4/RE4 Note 1: 2: 3: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 "Peripheral Pin Select" for restrictions. Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See Section 11.0 "I/O Ports" for more information. Shaded pins are 5V tolerant. DS60001290E-page 8 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 13 2.0 Guidelines for Getting Started with 32-bit MCUs........................................................................................................................ 25 3.0 CPU............................................................................................................................................................................................ 35 4.0 Memory Organization ................................................................................................................................................................. 39 5.0 Interrupt Controller ..................................................................................................................................................................... 53 6.0 Flash Program Memory.............................................................................................................................................................. 63 7.0 Resets ........................................................................................................................................................................................ 69 8.0 Oscillator Configuration .............................................................................................................................................................. 73 9.0 Direct Memory Access (DMA) Controller ................................................................................................................................... 85 10.0 USB On-The-Go (OTG)............................................................................................................................................................ 105 11.0 I/O Ports ................................................................................................................................................................................... 129 12.0 Timer1 ...................................................................................................................................................................................... 159 13.0 Timer2/3, Timer4/5 ................................................................................................................................................................... 163 14.0 Watchdog Timer (WDT) ........................................................................................................................................................... 169 15.0 Input Capture............................................................................................................................................................................ 173 16.0 Output Compare....................................................................................................................................................................... 177 17.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 181 18.0 Inter-Integrated Circuit (I2C) ..................................................................................................................................................... 191 19.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 199 20.0 Parallel Master Port (PMP)....................................................................................................................................................... 207 21.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 221 22.0 10-bit Analog-to-Digital Converter (ADC) ................................................................................................................................. 231 23.0 Controller Area Network (CAN) ................................................................................................................................................ 243 24.0 Comparator .............................................................................................................................................................................. 271 25.0 Comparator Voltage Reference (CVREF) ................................................................................................................................. 275 26.0 Charge Time Measurement Unit (CTMU) ............................................................................................................................... 279 27.0 Power-Saving Features ........................................................................................................................................................... 285 28.0 Special Features ...................................................................................................................................................................... 291 29.0 Instruction Set .......................................................................................................................................................................... 303 30.0 Development Support............................................................................................................................................................... 305 31.0 40 MHz Electrical Characteristics............................................................................................................................................. 309 32.0 50 MHz Electrical Characteristics............................................................................................................................................. 353 33.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 359 34.0 Packaging Information.............................................................................................................................................................. 361 The Microchip Web Site ..................................................................................................................................................................... 379 Customer Change Notification Service .............................................................................................................................................. 379 Customer Support .............................................................................................................................................................................. 379 Product Identification System ............................................................................................................................................................ 380 2014-2017 Microchip Technology Inc. DS60001290E-page 9 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS60001290E-page 10 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY Referenced Sources This device data sheet is based on the following individual sections of the "PIC32 Family Reference Manual". These documents should be considered as the general reference for the operation of a particular module or device feature. Note: * * * * * * * * * * * * * * * * * * * * * * * * * * * To access the documents listed below, browse to the documentation section of the Microchip web site (www.microchip.com). Section 1. "Introduction" (DS60001127) Section 2. "CPU" (DS60001113) Section 3. "Memory Organization" (DS60001115) Section 5. "Flash Program Memory" (DS60001121) Section 6. "Oscillator Configuration" (DS60001112) Section 7. "Resets" (DS60001118) Section 8. "Interrupt Controller" (DS60001108) Section 9. "Watchdog Timer and Power-up Timer" (DS60001114) Section 10. "Power-Saving Features" (DS60001130) Section 12. "I/O Ports" (DS60001120) Section 13. "Parallel Master Port (PMP)" (DS60001128) Section 14. "Timers" (DS60001105) Section 15. "Input Capture" (DS60001122) Section 16. "Output Compare" (DS60001111) Section 17. "10-bit Analog-to-Digital Converter (ADC)" (DS60001104) Section 19. "Comparator" (DS60001110) Section 20. "Comparator Voltage Reference (CVREF)" (DS60001109) Section 21. "Universal Asynchronous Receiver Transmitter (UART)" (DS60001107) Section 23. "Serial Peripheral Interface (SPI)" (DS60001106) Section 24. "Inter-Integrated Circuit (I2C)" (DS60001116) Section 27. "USB On-The-Go (OTG)" (DS60001126) Section 29. "Real-Time Clock and Calendar (RTCC)" (DS60001125) Section 31. "Direct Memory Access (DMA) Controller" (DS60001117) Section 32. "Configuration" (DS60001124) Section 33. "Programming and Diagnostics" (DS60001129) Section 34. "Controller Area Network (CAN)" (DS60001123) Section 37. "Charge Time Measurement Unit (CTMU)" (DS60001167) 2014-2017 Microchip Technology Inc. DS60001290E-page 11 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY NOTES: DS60001290E-page 12 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 1.0 This document contains device-specific information for PIC32MX1XX/2XX/5XX 64/100-pin devices. DEVICE OVERVIEW Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX/5XX 64/100pin family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). FIGURE 1-1: Figure 1-1 illustrates a general block diagram of the core and peripheral modules in the PIC32MX1XX/2XX/ 5XX 64/100-pin family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. PIC32MX1XX/2XX/5XX 64/100-PIN BLOCK DIAGRAM VCAP OSC2/CLKO OSC1/CLKI OSC/SOSC Oscillators Power-up Timer FRC/LPRC Oscillators Oscillator Start-up Timer Voltage Regulator PLL PLL-USB Watchdog Timer USBCLK SYSCLK Timing Generation MCLR Power-on Reset Precision Band Gap Reference DIVIDERS VDD, VSS Brown-out Reset PBCLK Peripheral Bus Clocked by SYSCLK CTMU PORTA/CNA Timer1-5 Priority Interrupt Controller USB EJTAG PORTC/CNC MIPS32(R) PORTD/CND DMAC CPU Core DS 32 PORTE/CNE CAN INT M4K(R) IS 32 ICD 32 32 32 32 32 Bus Matrix PORTF/CNF 32 32 32 PORTG/CNG 32 Peripheral Bus Clocked by PBCLK JTAG BSCAN PORTB/CNB PWM OC1-5 IC1-5 32 SPI1-4 I2C1,2 PMP 10-bit ADC Data RAM Peripheral Bridge UART1-5 Remappable Pins 32-bit wide Program Flash Memory Flash Controller RTCC Comparators 1-3 Note: Not all features are available on all devices. Refer to TABLE 1: "PIC32MX1XX/2XX/5XX 64/100-pin Controller Family Features" for the list of features by device. 2014-2017 Microchip Technology Inc. DS60001290E-page 13 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Number Pin Type Buffer Type 25 I Analog 24 I Analog 14 23 I Analog 13 22 I Analog AN4 12 21 I Analog AN5 11 20 I Analog AN6 17 26 I Analog AN7 18 27 I Analog AN8 21 32 I Analog AN9 22 33 I Analog AN10 23 34 I Analog AN11 24 35 I Analog AN12 27 41 I Analog AN13 28 42 I Analog AN14 29 43 I Analog AN15 30 44 I Analog AN16 4 10 I Analog AN17 5 11 I Analog AN18 6 12 I Analog AN19 8 14 I Analog 64-pin QFN/ TQFP 100-pin TQFP AN0 16 AN1 15 AN2 AN3 Pin Name AN20 62 98 I Analog AN21 64 100 I Analog AN22 1 3 I Analog AN23 2 4 I Analog AN24 49 76 I Analog AN25 50 77 I Analog AN26 51 78 I Analog AN27 3 5 I Analog AN28 -- 1 I Analog AN29 -- 6 I Analog AN30 -- 7 I Analog AN31 -- 8 I Analog AN32 -- 18 I Analog AN33 -- 19 I Analog AN34 -- 39 I Analog AN35 -- 40 I Analog Description Analog input channels. Legend: CMOS = CMOS compatible input or output Analog = Analog input ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer Note 1: This pin is only available on devices without a USB module. 2: This pin is only available on devices with a USB module. 3: This pin is not available on 64-pin devices with a USB module. 4: This pin is only available on 100-pin devices without a USB module. 2014-2017 Microchip Technology Inc. I = Input P = Power O = Output DS60001290E-page 14 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Type Buffer Type 47 I Analog -- 48 I Analog AN38 -- 52 I Analog AN39 -- 53 I Analog AN40 -- 79 I Analog AN41 -- 80 I Analog AN42 -- 83 I Analog AN43 -- 84 I Analog AN44 -- 87 I Analog AN45 -- 88 I Analog AN46 -- 93 I Analog AN47 -- 94 I Analog CLKI 39 63 I ST/CMOS External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with the OSC2 pin function. 64-pin QFN/ TQFP 100-pin TQFP AN36 -- AN37 Pin Name Description Analog input channels. CLKO 40 64 O -- OSC1 39 63 I ST/CMOS OSC2 40 64 O -- SOSCI 47 73 I ST/CMOS SOSCO 48 74 O -- IC1 PPS PPS I ST IC2 PPS PPS I ST IC3 PPS PPS I ST IC4 PPS PPS I ST IC5 PPS PPS I ST OC1 PPS PPS O ST Output Compare Output 1 OC2 PPS PPS O ST Output Compare Output 2 OC3 PPS PPS O ST Output Compare Output 3 OC4 PPS PPS O ST Output Compare Output 4 OC5 PPS PPS O ST Output Compare Output 5 OCFA PPS PPS I ST Output Compare Fault A Input OCFB 30 44 I ST Output Compare Fault B Input Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. 32.768 kHz low-power oscillator crystal input; CMOS otherwise. 32.768 kHz low-power oscillator crystal output. Capture Input 1-5 Legend: CMOS = CMOS compatible input or output Analog = Analog input ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer Note 1: This pin is only available on devices without a USB module. 2: This pin is only available on devices with a USB module. 3: This pin is not available on 64-pin devices with a USB module. 4: This pin is only available on 100-pin devices without a USB module. 2014-2017 Microchip Technology Inc. I = Input P = Power O = Output DS60001290E-page 15 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name INT0 64-pin QFN/ TQFP 100-pin TQFP 35(1), 46(2) 55(1), 72(2) Pin Type Buffer Type I ST External Interrupt 0 Description INT1 PPS PPS I ST External Interrupt 1 INT2 PPS PPS I ST External Interrupt 2 INT3 PPS PPS I ST External Interrupt 3 INT4 PPS PPS I ST External Interrupt 4 RA0 -- 17 I/O ST RA1 -- 38 I/O ST RA2 -- 58 I/O ST RA3 -- 59 I/O ST RA4 -- 60 I/O ST RA5 -- 61 I/O ST RA6 -- 91 I/O ST RA7 -- 92 I/O ST RA9 -- 28 I/O ST RA10 -- 29 I/O ST RA14 -- 66 I/O ST RA15 -- 67 I/O ST RB0 16 25 I/O ST RB1 15 24 I/O ST RB2 14 23 I/O ST RB3 13 22 I/O ST RB4 12 21 I/O ST RB5 11 20 I/O ST RB6 17 26 I/O ST RB7 18 27 I/O ST RB8 21 32 I/O ST RB9 22 33 I/O ST RB10 23 34 I/O ST RB11 24 35 I/O ST RB12 27 41 I/O ST RB13 28 42 I/O ST RB14 29 43 I/O ST RB15 30 44 I/O ST PORTA is a bidirectional I/O port PORTB is a bidirectional I/O port Legend: CMOS = CMOS compatible input or output Analog = Analog input ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer Note 1: This pin is only available on devices without a USB module. 2: This pin is only available on devices with a USB module. 3: This pin is not available on 64-pin devices with a USB module. 4: This pin is only available on 100-pin devices without a USB module. 2014-2017 Microchip Technology Inc. I = Input P = Power O = Output DS60001290E-page 16 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Type Buffer Type 6 I/O ST -- 7 I/O ST RC3 -- 8 I/O ST RC4 -- 9 I/O ST RC12 39 63 I/O ST RC13 47 73 I/O ST RC14 48 74 I/O ST RC15 40 64 I/O ST RD0 46 72 I/O ST RD1 49 76 I/O ST RD2 50 77 I/O ST RD3 51 78 I/O ST RD4 52 81 I/O ST RD5 53 82 I/O ST RD6 54 83 I/O ST RD7 55 84 I/O ST RD8 42 68 I/O ST 64-pin QFN/ TQFP 100-pin TQFP RC1 -- RC2 Pin Name RD9 43 69 I/O ST RD10 44 70 I/O ST RD11 45 71 I/O ST RD12 -- 79 I/O ST RD13 -- 80 I/O ST RD14 -- 47 I/O ST RD15 -- 48 I/O ST RE0 60 93 I/O ST RE1 61 94 I/O ST RE2 62 98 I/O ST RE3 63 99 I/O ST RE4 64 100 I/O ST RE5 1 3 I/O ST RE6 2 4 I/O ST RE7 3 5 I/O ST RE8 -- 18 I/O ST RE9 -- 19 I/O ST Description PORTC is a bidirectional I/O port PORTD is a bidirectional I/O port PORTE is a bidirectional I/O port Legend: CMOS = CMOS compatible input or output Analog = Analog input ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer Note 1: This pin is only available on devices without a USB module. 2: This pin is only available on devices with a USB module. 3: This pin is not available on 64-pin devices with a USB module. 4: This pin is only available on 100-pin devices without a USB module. 2014-2017 Microchip Technology Inc. I = Input P = Power O = Output DS60001290E-page 17 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Type Buffer Type 87 I/O ST 88 I/O ST 64-pin QFN/ TQFP 100-pin TQFP RF0 58 RF1 59 Pin Name RF2 34 (3) 52 I/O ST RF3 33 51 I/O ST RF4 31 49 I/O ST RF5 32 50 I/O ST RF6 35(1) 55(1) I/O ST RF7 -- 54(4) I/O ST RF8 -- 53 I/O ST RF12 -- 40 I/O ST RF13 -- 39 I/O ST RG0 -- 90 I/O ST RG1 -- 89 I/O ST RG2 37 (1) 57(1) I/O ST RG3 36(1) 56(1) I/O ST RG6 4 10 I/O ST RG7 5 11 I/O ST RG8 6 12 I/O ST RG9 8 14 I/O ST RG12 -- 96 I/O ST RG13 -- 97 I/O ST RG14 -- 95 I/O ST Description PORTF is a bidirectional I/O port PORTG is a bidirectional I/O port RG15 -- 1 I/O ST T1CK 48 74 I ST Timer1 External Clock Input T2CK PPS PPS I ST Timer2 External Clock Input T3CK PPS PPS I ST Timer3 External Clock Input T4CK PPS PPS I ST Timer4 External Clock Input T5CK PPS PPS I ST Timer5 External Clock Input U1CTS PPS PPS I ST UART1 Clear to Send U1RTS PPS PPS O -- UART1 Ready to Send U1RX PPS PPS I ST UART1 Receive U1TX PPS PPS O -- UART1 Transmit U2CTS PPS PPS I ST UART2 Clear to Send U2RTS PPS PPS O -- UART2 Ready to Send U2RX PPS PPS I ST UART2 Receive U2TX PPS PPS O -- UART2 Transmit Legend: CMOS = CMOS compatible input or output Analog = Analog input ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer Note 1: This pin is only available on devices without a USB module. 2: This pin is only available on devices with a USB module. 3: This pin is not available on 64-pin devices with a USB module. 4: This pin is only available on 100-pin devices without a USB module. 2014-2017 Microchip Technology Inc. I = Input P = Power O = Output DS60001290E-page 18 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Type Buffer Type PPS I ST UART3 Clear to Send PPS O -- UART3 Ready to Send 64-pin QFN/ TQFP 100-pin TQFP U3CTS PPS U3RTS PPS Pin Name Description U3RX PPS PPS I ST UART3 Receive U3TX PPS PPS O -- UART3 Transmit U4CTS PPS PPS I ST UART4 Clear to Send U4RTS PPS PPS O -- UART4 Ready to Send U4RX PPS PPS I ST UART4 Receive U4TX PPS PPS O -- UART4 Transmit U5CTS -- PPS I ST UART5 Clear to Send U5RTS -- PPS O -- UART5 Ready to Send UART5 Receive U5RX -- PPS I ST U5TX -- PPS O -- UART5 Transmit I/O ST Synchronous Serial Clock Input/Output for SPI1 I -- SPI1 Data In SCK1 SDI1 35(1), 50(2) 55(1), 70(2) PPS PPS SDO1 PPS PPS O ST SPI1 Data Out SS1 PPS PPS I/O -- SPI1 Slave Synchronization for Frame Pulse I/O Synchronous Serial Clock Input/Output for SPI2 SCK2 4 10 I/O ST SDI2 PPS PPS I -- SPI2 Data In SDO2 PPS PPS O ST SPI2 Data Out SS2 PPS PPS I/O -- SPI2 Slave Synchronization for Frame Pulse I/O SCK3 29 39 I/O ST Synchronous Serial Clock Input/Output for SPI3 SDI3 PPS PPS I -- SPI3 Data In SDO3 PPS PPS O ST SPI3 Data Out SS3 PPS PPS I/O -- SPI3 Slave Synchronization for Frame Pulse I/O SCK4 -- 48 I/O ST Synchronous Serial Clock Input/Output for SPI4 SDI4 -- PPS I -- SPI4 Data In SDO4 -- PPS O ST SPI4 Data Out SS4 -- PPS I/O -- SPI4 Slave Synchronization for Frame Pulse I/O SCL1 37(1), 44(2) 57(1), 66(2) I/O ST Synchronous Serial Clock Input/Output for I2C1 SDA1 36(1), 43(2) 56(1), 67(2) I/O ST Synchronous Serial Data Input/Output for I2C1 SCL2 32 58 I/O ST Synchronous Serial Clock Input/Output for I2C2 SDA2 31 59 I/O ST Synchronous Serial Data Input/Output for I2C2 TMS 23 17 I ST JTAG Test Mode Select Pin TCK 27 38 I ST JTAG Test Clock Input Pin TDI 28 60 I -- JTAG Test Clock Input Pin TDO 24 61 O -- JTAG Test Clock Output Pin Legend: CMOS = CMOS compatible input or output Analog = Analog input ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer Note 1: This pin is only available on devices without a USB module. 2: This pin is only available on devices with a USB module. 3: This pin is not available on 64-pin devices with a USB module. 4: This pin is only available on 100-pin devices without a USB module. 2014-2017 Microchip Technology Inc. I = Input P = Power O = Output DS60001290E-page 19 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Type Buffer Type 68 O -- 23 34 O Analog C1INA 11 20 I Analog C1INB 12 21 I Analog C1INC 5 11 I Analog C1IND 4 10 I Analog C2INA 13 22 I Analog C2INB 14 23 I Analog C2INC 8 14 I Analog C2IND 6 12 I Analog C3INA 58 87 I Analog C3INB 55 84 I Analog C3INC 54 83 I Analog C3IND 51 78 I Analog C1OUT PPS PPS O -- Comparator 1 Output C2OUT PPS PPS O -- Comparator 2 Output C3OUT PPS PPS O -- PMALL 30 44 O TTL/ST Parallel Master Port Address Latch Enable Low Byte PMALH 29 43 O TTL/ST Parallel Master Port Address Latch Enable High Byte PMA0 30 44 O TTL/ST Parallel Master Port Address bit 0 Input (Buffered Slave modes) and Output (Master modes) PMA1 29 43 O TTL/ST Parallel Master Port Address bit 0 Input (Buffered Slave modes) and Output (Master modes) 64-pin QFN/ TQFP 100-pin TQFP RTCC 42 CVREFOUT Pin Name Description Real-Time Clock Alarm Output Comparator Voltage Reference (Output) Comparator 1 Inputs Comparator 2 Inputs Comparator 3 Inputs Comparator 3 Output Legend: CMOS = CMOS compatible input or output Analog = Analog input ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer Note 1: This pin is only available on devices without a USB module. 2: This pin is only available on devices with a USB module. 3: This pin is not available on 64-pin devices with a USB module. 4: This pin is only available on 100-pin devices without a USB module. 2014-2017 Microchip Technology Inc. I = Input P = Power O = Output DS60001290E-page 20 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Type Buffer Type 14 O TTL/ST 12 O TTL/ST 64-pin QFN/ TQFP 100-pin TQFP PMA2 8 PMA3 6 PMA4 5 11 O TTL/ST PMA5 4 10 O TTL/ST PMA6 16 29 O TTL/ST PMA7 22 28 O TTL/ST PMA8 32 50 O TTL/ST PMA9 31 49 O TTL/ST PMA10 28 42 O TTL/ST PMA11 27 41 O TTL/ST PMA12 24 35 O TTL/ST PMA13 23 34 O TTL/ST PMA14 45 71 O TTL/ST PMA15 44 70 O TTL/ST Pin Name PMCS1 45 71 O TTL/ST PMCS2 44 70 O TTL/ST PMD0 60 93 I/O TTL/ST PMD1 61 94 I/O TTL/ST PMD2 62 98 I/O TTL/ST PMD3 63 99 I/O TTL/ST PMD4 64 100 I/O TTL/ST PMD5 1 3 I/O TTL/ST PMD6 2 4 I/O TTL/ST PMD7 3 5 I/O TTL/ST PMD8 -- 90 I/O TTL/ST PMD9 -- 89 I/O TTL/ST PMD10 -- 88 I/O TTL/ST PMD11 -- 87 I/O TTL/ST PMD12 -- 79 I/O TTL/ST PMD13 -- 80 I/O TTL/ST PMD14 -- 83 I/O TTL/ST PMD15 -- 84 I/O TTL/ST Description Parallel Master Port data (Demultiplexed Master mode) or Address/Data (Multiplexed Master modes) Parallel Master Port data (Demultiplexed Master mode) or Address/Data (Multiplexed Master modes) PMRD 53 82 O -- Parallel Master Port Read Strobe PMWR 52 81 O -- Parallel Master Port Write Strobe VBUS(2) 34 54 I Analog USB Bus Power Monitor Legend: CMOS = CMOS compatible input or output Analog = Analog input ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer Note 1: This pin is only available on devices without a USB module. 2: This pin is only available on devices with a USB module. 3: This pin is not available on 64-pin devices with a USB module. 4: This pin is only available on 100-pin devices without a USB module. 2014-2017 Microchip Technology Inc. I = Input P = Power O = Output DS60001290E-page 21 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name 64-pin QFN/ TQFP 100-pin TQFP VUSB3V3(2) 35 55 Pin Type Buffer Type P -- Description USB internal transceiver supply. If the USB module is not used, this pin must be connected to VDD. VBUSON(2) 11 20 O -- D+(2) 37 57 I/O Analog USB D+ D-(2) 36 56 I/O Analog USB D- USBID(2) 33 51 I ST USB OTG ID Detect PGED1 16 25 I/O ST Data I/O pin for Programming/Debugging Communication Channel 1 PGEC1 15 24 I ST Clock Input pin for Programming/Debugging Communication Channel 1 PGED2 18 27 I/O ST Data I/O Pin for Programming/Debugging Communication Channel 2 PGEC2 17 26 I ST Clock Input Pin for Programming/Debugging Communication Channel 2 PGED3 13 22 I/O ST Data I/O Pin for Programming/Debugging Communication Channel 3 PGEC3 14 23 I ST Clock Input Pin for Programming/Debugging Communication Channel 3 CTED1 -- 17 I ST CTMU External Edge Input 1 CTED2 -- 38 I ST CTMU External Edge Input 2 CTED3 18 27 I ST CTMU External Edge Input 3 CTED4 22 33 I ST CTMU External Edge Input 4 CTED5 29 43 I ST CTMU External Edge Input 5 CTED6 30 44 I ST CTMU External Edge Input 6 CTED7 -- 9 I ST CTMU External Edge Input 7 CTED8 -- 92 I ST CTMU External Edge Input 8 CTED9 -- 60 I ST CTMU External Edge Input 9 CTED10 21 32 I ST CTMU External Edge Input 10 CTED11 23 34 I ST CTMU External Edge Input 11 CTED12 15 24 I ST CTMU External Edge Input 12 CTED13 14 23 I ST CTMU External Edge Input 13 C1RX PPS PPS I ST Enhanced CAN Receive C1TX PPS PPS O ST Enhanced CAN Transmit USB Host and OTG bus power control Output Legend: CMOS = CMOS compatible input or output Analog = Analog input ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer Note 1: This pin is only available on devices without a USB module. 2: This pin is only available on devices with a USB module. 3: This pin is not available on 64-pin devices with a USB module. 4: This pin is only available on 100-pin devices without a USB module. 2014-2017 Microchip Technology Inc. I = Input P = Power O = Output DS60001290E-page 22 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Type Buffer Type Description 13 I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. 19 30 P P Positive supply for analog modules. This pin must be connected at all times. 20 31 P P Ground reference for analog modules P -- Positive supply for peripheral logic and I/O pins 64-pin QFN/ TQFP 100-pin TQFP MCLR 7 AVDD AVSS Pin Name VDD VCAP 10, 26, 38, 2, 16, 37, 57 46, 62, 86 56 85 P -- Capacitor for Internal Voltage Regulator 9, 25, 41 15, 36, 45, 65, 75 P -- Ground reference for logic and I/O pins VREF+ 16 29 P Analog Analog Voltage Reference (High) Input VREF- 15 28 P Analog Analog Voltage Reference (Low) Input VSS Legend: CMOS = CMOS compatible input or output Analog = Analog input ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer Note 1: This pin is only available on devices without a USB module. 2: This pin is only available on devices with a USB module. 3: This pin is not available on 64-pin devices with a USB module. 4: This pin is only available on 100-pin devices without a USB module. 2014-2017 Microchip Technology Inc. I = Input P = Power O = Output DS60001290E-page 23 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY NOTES: 2014-2017 Microchip Technology Inc. DS60001290E-page 24 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 2.0 Note: 2.1 GUIDELINES FOR GETTING STARTED WITH 32-BIT MCUS This data sheet summarizes the features of the PIC32MX1XX/2XX/5XX 64/100-pin family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). Basic Connection Requirements Getting started with the PIC32MX1XX/2XX/5XX 64/ 100-pin family of 32-bit Microcontrollers (MCUs) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: * All VDD and VSS pins (see 2.2 "Decoupling Capacitors") * All AVDD and AVSS pins, even if the ADC module is not used (see 2.2 "Decoupling Capacitors") * VCAP pin (see 2.3 "Capacitor on Internal Voltage Regulator (VCAP)") * MCLR pin (see 2.4 "Master Clear (MCLR) Pin") * PGECx/PGEDx pins, used for In-Circuit Serial Programming (ICSPTM) and debugging purposes (see 2.5 "ICSP Pins") * OSC1 and OSC2 pins, when external oscillator source is used (see 2.7 "External Oscillator Pins") The following pins may be required: VREF+/VREF- pins, used when external voltage reference for the ADC module is implemented. Note: The AVDD and AVSS pins must be connected, regardless of ADC use and the ADC voltage reference source. 2014-2017 Microchip Technology Inc. 2.2 Decoupling Capacitors The use of decoupling capacitors on power supply pins, such as VDD, VSS, AVDD and AVSS is required. See Figure 2-1. Consider the following criteria when using decoupling capacitors: * Value and type of capacitor: A value of 0.1 F (100 nF), 10-20V is recommended. The capacitor should be a low Equivalent Series Resistance (low-ESR) capacitor and have resonance frequency in the range of 20 MHz and higher. It is further recommended that ceramic capacitors be used. * Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended that the capacitors be placed on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within onequarter inch (6 mm) in length. * Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 F in parallel with 0.001 F. * Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing PCB track inductance. DS60001290E-page 25 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY RECOMMENDED MINIMUM CONNECTION Tantalum or ceramic 10 F ESR 3(3) MCLR 1K C 0.1 F VSS VDD 10K R1 VCAP VUSB3V3(1) PIC32 VDD VSS Connect(2) VDD 0.1 F Ceramic AVSS VDD AVDD VSS 0.1 F Ceramic 0.1 F Ceramic VSS VDD 0.1 F Ceramic 0.1 F Ceramic L1(2) Note 1: If the USB module is not used, this pin must be connected to VDD. 2: As an option, instead of a hard-wired connection, an inductor (L1) can be substituted between VDD and AVDD to improve ADC noise rejection. The inductor impedance should be less than 3 and the inductor capacity greater than 10 mA. Where: f f L 2: 2.2.1 F CNV -------------2 1 ---------------------- 2 LC (i.e., ADC conversion rate/2) 1 - -------------------- 2f C 2.3.1 Master Clear (MCLR) Pin The MCLR functions: pin provides two specific device * Device Reset * Device programming and debugging Pulling The MCLR pin low generates a device Reset. Figure 2-2 illustrates a typical MCLR circuit. During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements. For example, as illustrated in Figure 2-2, it is recommended that the capacitor C, be isolated from the MCLR pin during programming and debugging operations. Place the components illustrated in Figure 2-2 within one-quarter inch (6 mm) from the MCLR pin. FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS VDD R 0.1 F(2) 10k C R1(1) 1 k MCLR PIC32 2 Aluminum or electrolytic capacitors should not be used. ESR 3 from -40C to 125C @ SYSCLK frequency (i.e., MIPS). Note 1 5 4 2 3 6 Capacitor on Internal Voltage Regulator (VCAP) VDD VSS NC PGECx(3) PGEDx(3) 1: 470 R1 1 will limit any current flowing into MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met without interfering with the Debug/Programmer tools. 2: The capacitor can be sized to prevent unintentional Resets from brief glitches or to extend the device Reset period during POR. 3: No pull-ups or bypass capacitors are allowed on active debug/program PGECx/PGEDx pins. BULK CAPACITORS The use of a bulk capacitor is recommended to improve power supply stability. Typical values range from 4.7 F to 47 F. This capacitor should be located as close to the device as possible. 2.3 2.4 ICSPTM FIGURE 2-1: INTERNAL REGULATOR MODE A low-ESR (3 ohm) capacitor is required on the VCAP pin, which is used to stabilize the internal voltage regulator output. The VCAP pin must not be connected to VDD, and must have a CEFC capacitor, with at least a 6V rating, connected to ground. The type can be ceramic or tantalum. Refer to Section 31.0 "40 MHz Electrical Characteristics" for additional information on CEFC specifications. DS60001290E-page 26 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 2.5 ICSP Pins The PGECx and PGEDx pins are used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input voltage low (VIL) requirements. Ensure that the "Communication Channel Select" (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to MPLAB(R) ICD 3 or MPLAB REAL ICETM. For more information on MPLAB ICD 3 and MPLAB REAL ICE connection requirements, refer to the following documents that are available on the Microchip web site. * "Using MPLAB(R) ICD 3" (poster) DS50001765 * "MPLAB(R) ICD 3 Design Advisory" DS50001764 * "MPLAB(R) REAL ICETM In-Circuit Debugger User's Guide" DS50001616 * "Using MPLAB(R) REAL ICETM Emulator" (poster) DS50001749 2.6 2.7 External Oscillator Pins Many MCUs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 "Oscillator Configuration" for details). The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is illustrated in Figure 2-3. FIGURE 2-3: SUGGESTED OSCILLATOR CIRCUIT PLACEMENT Oscillator Secondary Guard Trace Guard Ring Main Oscillator JTAG The TMS, TDO, TDI and TCK pins are used for testing and debugging according to the Joint Test Action Group (JTAG) standard. It is recommended to keep the trace length between the JTAG connector and the JTAG pins on the device as short as possible. If the JTAG connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes and capacitors on the TMS, TDO, TDI and TCK pins are not recommended as they will interfere with the programmer or debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input voltage low (VIL) requirements 2014-2017 Microchip Technology Inc. DS60001290E-page 27 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY FIGURE 2-4: The following examples are used to calculate the Primary Oscillator loading capacitor values: Circuit A Typical XT (4-10 MHz) C1 * CIN = PIC32_OSC2_Pin Capacitance = ~4-5 pF * COUT = PIC32_OSC1_Pin Capacitance = ~4-5 pF * C1 and C2 = XTAL manufacturing recommended loading capacitance * Estimated PCB stray capacitance, (i.e.,12 mm length) = 2.5 pF 1M OSC2 EXAMPLE 2-1: CRYSTAL LOAD CAPACITOR CALCULATION Typical HS (10-25 MHz) Therefore: = {( [20][20]) / [40] } + 2.5 C1 = {( [CIN + C1] * [COUT + C2] ) / [CIN + C1 + C2 + COUT] } + estimated oscillator PCB stray capacitance = {( [5 + 15][5 + 15] ) / [5 + 15 + 15 + 5] } + 2.5 pF OSC1 Circuit B Crystal manufacturer recommended: C1 = C2 = 15 pF CLOAD PRIMARY CRYSTAL OSCILLATOR CIRCUIT RECOMMENDATIONS C2 CRYSTAL OSCILLATOR DESIGN CONSIDERATION C2 2.7.1 = 10 + 2.5 = 12.5 pF Rounded to the nearest standard value or 13 pF in this example for Primary Oscillator crystals "C1" and "C2". OSC2 The following tips are used to increase oscillator gain, (i.e., to increase peak-to-peak oscillator signal): Note: 2.7.1.1 Do not add excessive gain such that the oscillator signal is clipped, flat on top of the sine wave. If so, you need to reduce the gain or add a series resistor, RS, as shown in circuit "C" in Figure 2-4. Failure to do so will stress and age the crystal, which can result in an early failure. Adjust the gain to trim the max peak-to-peak to ~VDD-0.6V. When measuring the oscillator signal you must use a FET scope probe or a probe with 1.5 pF or the scope probe itself will unduly change the gain and peak-to-peak levels. Circuit C C2 Typical XT/HS (4-25 MHz) C1 * Select a crystal with a lower "minimum" power drive rating * Select an crystal oscillator with a lower XTAL manufacturing "ESR" rating. * Add a parallel resistor across the crystal. The smaller the resistor value the greater the gain. It is recommended to stay in the range of 600k to 1M * C1 and C2 values also affect the gain of the oscillator. The lower the values, the higher the gain. * C2/C1 ratio also affects gain. To increase the gain, make C1 slightly smaller than C2, which will also help start-up performance. OSC1 Rs 1M OSC2 OSC1 Circuit D Not Recommended 1M Rs OSC1 OSC2 Circuit E Not Recommended Additional Microchip References * AN588 "PICmicro(R) Microcontroller Oscillator Design Guide" * AN826 "Crystal Oscillator Basics and Crystal Selection for rfPICTM and PICmicro(R) Devices" * AN849 "Basic PICmicro(R) Oscillator Design" OSC2 DS60001290E-page 28 2014-2017 Microchip Technology Inc. Rs 1M OSC1 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 2.8 Unused I/Os Unused I/O pins should not be allowed to float as inputs. They can be configured as outputs and driven to a logic-low state. Alternatively, inputs can be reserved by connecting the pin to VSS through a 1k to 10k resistor and configuring the pin as an input. 2014-2017 Microchip Technology Inc. DS60001290E-page 29 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 2.9 Considerations When Interfacing to Remotely Powered Circuits 2.9.1 NON-5V TOLERANT INPUT PINS A quick review of the absolute maximum rating section in 31.0 "40 MHz Electrical Characteristics" will indicate that the voltage on any non-5v tolerant pin may not exceed AVDD/VDD + 0.3V. Figure 2-5 shows an example of a remote circuit using an independent power source, which is powered while connected to a PIC32 non-5V tolerant circuit that is not powered. FIGURE 2-5: Note: PIC32 NON-5V TOLERANT CIRCUIT EXAMPLE When VDD power is OFF. PIC32 Non-5V Tolerant Pin Architecture On/Off VDD ANSEL I/O IN AN2/RB0 I/O OUT Remote GND TRIS CPU LOGIC Remote 0.3V dVIH d 3.6V PIC32 POWER SUPPLY Current Flow VSS DS60001290E-page 30 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY FIGURE 2-6: Opto Coupling Analog/Digital Switch EXAMPLES OF DIGITAL/ ANALOG ISOLATORS WITH OPTIONAL LEVEL TRANSLATION Capacitive Coupling TABLE 2-1: Inductive Coupling Without proper signal isolation, on non-5V tolerant pins, the remote signal can power the PIC32 device through the high side ESD protection diodes. Besides violating the absolute maximum rating specification when VDD of the PIC32 device is restored and ramping up or ramping down, it can also negatively affect the internal Power-on Reset (POR) and Brown-out Reset (BOR) circuits, which can lead to improper initialization of internal PIC32 logic circuits. In these cases, it is recommended to implement digital or analog signal isolation as depicted in Figure 2-6, as appropriate. This is indicative of all industry microcontrollers and not just Microchip products. X -- -- -- ADuM7241 / 40 CRZ (25 Mbps) X -- -- -- ISO721 -- X -- -- LTV-829S (2 Channel) -- -- X -- LTV-849S (4 Channel) -- -- X -- FSA266 / NC7WB66 -- -- -- X Example Digital/Analog Signal Isolation Circuits ADuM7241 / 40 ARZ (1 Mbps) DIGITAL/ANALOG SIGNAL ISOLATION CIRCUITS Conn PIC32 VDD Digital Isolator External VDD IN REMOTE_IN PIC32 PIC32 VDD Digital Isolator External VDD REMOTE_IN IN1 REMOTE_OUT OUT1 PIC32 VSS VSS PIC32 VDD Opto Digital ISOLATOR External VDD PIC32 VDD Analog / Digital Isolator Conn IN1 ENB Analog_OUT2 PIC32 External_VDD1 ENB PIC32 S Analog_IN1 REMOTE_IN Analog_IN2 Analog Switch VSS VSS 2014-2017 Microchip Technology Inc. DS60001290E-page 31 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 2.9.2 5V TOLERANT INPUT PINS The internal high side diode on 5V tolerant pins are bussed to an internal floating node, rather than being connected to VDD, as shown in Figure 2-7. Voltages on these pins, if VDD < 2.3V, should not exceed roughly 3.2V relative to VSS of the PIC32 device. Voltage of 3.6V or higher will violate the absolute maximum specification, and will stress the oxide layer separating the high side floating node, which impacts device reliability. If a remotely powered "digital-only" signal can be guaranteed to always be 3.2V relative to Vss on the PIC32 device side, a 5V tolerant pin could be used without the need for a digital isolator. This is assuming there is not a ground loop issue, logic ground of the two circuits not at the same absolute level, and a remote logic low input is not less than VSS - 0.3V. FIGURE 2-7: PIC32 5V TOLERANT PIN ARCHITECTURE EXAMPLE PIC32 5V Tolerant Pin Architecture Floating Bus Oxide BV = 3.6V if VDD < 2.3V OXIDE On/Off VDD ANSEL I/O IN RG10 I/O OUT Remote GND TRIS CPU LOGIC Remote VIH = 2.5V PIC32 POWER SUPPLY VSS DS60001290E-page 32 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 2.10 Typical Application Connection Examples Examples of typical application connections are shown in Figure 2-8, Figure 2-9, and Figure 2-10. FIGURE 2-8: CAPACITIVE TOUCH SENSING WITH GRAPHICS APPLICATION PIC32MX1XX/2XX/5XX Current Source To AN6 To AN7 To AN8 To AN9 To AN11 To AN0 CTMU AN0 AN1 ADC R1 R1 R1 R1 C1 C2 C3 C4 C5 To AN1 Read the Touch Sensors Microchip mTouch (R) Library R1 R2 R2 R2 R2 R2 C1 C2 C3 C4 C5 R3 R3 R3 R3 R3 C1 C2 C3 C4 C5 AN9 To AN5 Process Samples AN11 User Application Display Data Microchip Graphics Library FIGURE 2-9: USB Host Parallel Master Port LCD Controller PMD<7:0> Display Controller Frame Buffer PMWR LCD Panel AUDIO PLAYBACK APPLICATION PMD<7:0> USB PMP Display PMWR PIC32MX1XX/2XX/5XX I2S SPI Stereo Headphones 3 REFCLKO 3 Audio Codec Speaker 3 MMC SD SDI 2014-2017 Microchip Technology Inc. DS60001290E-page 33 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY FIGURE 2-10: LOW-COST CONTROLLERLESS (LCC) GRAPHICS APPLICATION WITH PROJECTED CAPACITIVE TOUCH PIC32MX1XX/2XX/5XX CTMU ADC ANx Microchip mTouch(R) GFX Libraries DMA LCD Display Projected Capacitive Touch Overlay PMP SRAM DS60001290E-page 34 External Frame Buffer 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 3.0 Note: CPU This data sheet summarizes the features of the PIC32MX1XX/2XX/5XX 64/100-pin family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 2. "CPU" (DS60001113) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). Resources for the MIPS32(R) M4K(R) Processor Core are available at http://www.imgtec.com. The the MIPS32(R) M4K(R) Processor Core is the heart of the PIC32MX1XX/2XX/5XX 64/100-pin device processor. The CPU fetches instructions, decodes each instruction, fetches source operands, executes each instruction and writes the results of instruction execution to the proper destinations. 3.1 Features * 5-stage pipeline * 32-bit address and data paths * MIPS32(R) Enhanced Architecture (Release 2): - Multiply-accumulate and multiply-subtract instructions - Targeted multiply instruction - Zero/One detect instructions - WAIT instruction - Conditional move instructions (MOVN, MOVZ) - Vectored interrupts - Programmable exception vector base - Atomic interrupt enable/disable - Bit field manipulation instructions FIGURE 3-1: * MIPS16e(R) Code Compression: - 16-bit encoding of 32-bit instructions to improve code density - Special PC-relative instructions for efficient loading of addresses and constants - SAVE and RESTORE macro instructions for setting up and tearing down stack frames within subroutines - Improved support for handling 8 and 16-bit data types * Simple Fixed Mapping Translation (FMT) Mechanism: * Simple Dual Bus Interface: - Independent 32-bit address and data buses - Transactions can be aborted to improve interrupt latency * Autonomous Multiply/Divide Unit (MDU): - Maximum issue rate of one 32x16 multiply per clock - Maximum issue rate of one 32x32 multiply every other clock - Early-in iterative divide. Minimum 11 and maximum 33 clock latency (dividend (rs) sign extension-dependent) * Power Control: - Minimum frequency: 0 MHz - Low-Power mode (triggered by WAIT instruction) - Extensive use of local gated clocks * EJTAG Debug: - Support for single stepping - Virtual instruction and data address/value - Breakpoints MIPS32(R) M4K(R) PROCESSOR CORE BLOCK DIAGRAM CPU EJTAG MDU TAP Execution Core (RF/ALU/Shift) System Co-processor 2014-2017 Microchip Technology Inc. FMT Bus Interface Off-chip Debug Interface Dual Bus Interface Bus Matrix Power Management DS60001290E-page 35 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 3.2 3.2.2 Architecture Overview The MIPS32(R) M4K(R) processor core contains several logic blocks working together in parallel, providing an efficient high-performance computing engine. The following blocks are included with the core: * * * * * * * * Execution Unit Multiply/Divide Unit (MDU) System Control Coprocessor (CP0) Fixed Mapping Translation (FMT) Dual Internal Bus interfaces Power Management MIPS16e(R) Support Enhanced JTAG (EJTAG) Controller 3.2.1 EXECUTION UNIT The MIPS32(R) M4K(R) processor core execution unit implements a load/store architecture with single-cycle ALU operations (logical, shift, add, subtract) and an autonomous multiply/divide unit. The core contains thirty-two 32-bit General Purpose Registers (GPRs) used for integer operations and address calculation. The execution unit includes: * 32-bit adder used for calculating the data address * Address unit for calculating the next instruction address * Logic for branch determination and branch target address calculation * Load aligner * Bypass multiplexers used to avoid stalls when executing instruction streams where data producing instructions are followed closely by consumers of their results * Leading Zero/One detect unit for implementing the CLZ and CLO instructions * Arithmetic Logic Unit (ALU) for performing bitwise logical operations * Shifter and store aligner TABLE 3-1: MULTIPLY/DIVIDE UNIT (MDU) The MIPS32(R) M4K(R) processor core includes a Multiply/Divide Unit (MDU) that contains a separate pipeline for multiply and divide operations. This pipeline operates in parallel with the Integer Unit (IU) pipeline and does not stall when the IU pipeline stalls. This allows MDU operations to be partially masked by system stalls and/or other integer unit instructions. The high-performance MDU consists of a 32x16 booth recoded multiplier, result/accumulation registers (HI and LO), a divide state machine, and the necessary multiplexers and control logic. The first number shown (`32' of 32x16) represents the rs operand. The second number (`16' of 32x16) represents the rt operand. The PIC32 core only checks the value of the latter (rt) operand to determine how many times the operation must pass through the multiplier. The 16x16 and 32x16 operations pass through the multiplier once. A 32x32 operation passes through the multiplier twice. The MDU supports execution of one 16x16 or 32x16 multiply operation every clock cycle; 32x32 multiply operations can be issued every other clock cycle. Appropriate interlocks are implemented to stall the issuance of back-to-back 32x32 multiply operations. The multiply operand size is automatically determined by logic built into the MDU. Divide operations are implemented with a simple 1 bit per clock iterative algorithm. An early-in detection checks the sign extension of the dividend (rs) operand. If rs is 8 bits wide, 23 iterations are skipped. For a 16-bit wide rs, 15 iterations are skipped and for a 24-bit wide rs, 7 iterations are skipped. Any attempt to issue a subsequent MDU instruction while a divide is still active causes an IU pipeline stall until the divide operation is completed. Table 3-1 lists the repeat rate (peak issue rate of cycles until the operation can be reissued) and latency (number of cycles until a result is available) for the PIC32 core multiply and divide instructions. The approximate latency and repeat rates are listed in terms of pipeline clocks. MIPS32(R) M4K(R) PROCESSOR CORE HIGH-PERFORMANCE INTEGER MULTIPLY/ DIVIDE UNIT LATENCIES AND REPEAT RATES Op code MULT/MULTU, MADD/MADDU, MSUB/MSUBU MUL DIV/DIVU DS60001290E-page 36 Operand Size (mul rt) (div rs) Latency Repeat Rate 16 bits 32 bits 16 bits 32 bits 8 bits 16 bits 24 bits 32 bits 1 2 2 3 12 19 26 33 1 2 1 2 11 18 25 32 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY The MIPS architecture defines that the result of a multiply or divide operation be placed in the HI and LO registers. Using the Move-From-HI (MFHI) and MoveFrom-LO (MFLO) instructions, these values can be transferred to the General Purpose Register file. In addition to the HI/LO targeted operations, the MIPS32(R) architecture also defines a multiply instruction, MUL, which places the least significant results in the primary register file instead of the HI/LO register pair. By avoiding the explicit MFLO instruction required when using the LO register, and by supporting multiple destination registers, the throughput of multiply-intensive operations is increased. SYSTEM CONTROL COPROCESSOR (CP0) 3.2.3 In the MIPS architecture, CP0 is responsible for the virtual-to-physical address translation, the exception control system, the processor's diagnostics capability, the operating modes (Kernel, User and Debug) and whether interrupts are enabled or disabled. Configuration information, such as presence of options like MIPS16e(R), is also available by accessing the CP0 registers, listed in Table 3-2. Two other instructions, Multiply-Add (MADD) and Multiply-Subtract (MSUB), are used to perform the multiply-accumulate and multiply-subtract operations. The MADD instruction multiplies two numbers and then adds the product to the current contents of the HI and LO registers. Similarly, the MSUB instruction multiplies two operands and then subtracts the product from the HI and LO registers. The MADD and MSUB operations are commonly used in DSP algorithms. TABLE 3-2: Register Number 0-6 COPROCESSOR 0 REGISTERS Register Name Function Reserved Reserved in the PIC32MX1XX/2XX/5XX 64/100-pin family core. 7 8 HWREna BadVAddr(1) Enables access via the RDHWR instruction to selected hardware registers. Reports the address for the most recent address-related exception. 9 10 Count(1) Reserved Processor cycle count. Reserved in the PIC32MX1XX/2XX/5XX 64/100-pin family core. 11 12 Compare(1) Status(1) Timer interrupt control. Processor status and control. 12 13 IntCtl(1) Cause(1) Interrupt system status and control. Cause of last general exception. 14 15 EPC(1) PRId Program counter at last exception. Processor identification and revision. 15 16 EBASE Config Exception vector base register. Configuration register. 16 16 Config1 Config2 Configuration register 1. Configuration register 2. 16 17-22 Config3 Reserved Configuration register 3. Reserved in the PIC32MX1XX/2XX/5XX 64/100-pin family core. 23 24 Debug(2) DEPC(2) Debug control and exception status. Program counter at last debug exception. Reserved ErrorEPC(1) Reserved in the PIC32MX1XX/2XX/5XX 64/100-pin family core. Program counter at last error. 25-29 30 31 Note 1: 2: DESAVE(2) Debug handler scratchpad register. Registers used in exception processing. Registers used during debug. 2014-2017 Microchip Technology Inc. DS60001290E-page 37 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY Coprocessor 0 also contains the logic for identifying and managing exceptions. Exceptions can be caused by a variety of sources, including alignment errors in data, external events or program errors. Table 3-3 lists the exception types in order of priority. TABLE 3-3: MIPS32(R) M4K(R) PROCESSOR CORE EXCEPTION TYPES Exception Description Reset Assertion MCLR or a Power-on Reset (POR). DSS DINT NMI EJTAG debug single step. EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the EjtagBrk bit in the ECR register. Assertion of NMI signal. Interrupt DIB Assertion of unmasked hardware or software interrupt signal. EJTAG debug hardware instruction break matched. AdEL IBE Fetch address alignment error. Fetch reference to protected address. Instruction fetch bus error. DBp Sys EJTAG breakpoint (execution of SDBBP instruction). Execution of SYSCALL instruction. Bp RI Execution of BREAK instruction. Execution of a reserved instruction. CpU CEU Execution of a coprocessor instruction for a coprocessor that is not enabled. Execution of a CorExtend instruction when CorExtend is not enabled. Ov Tr Execution of an arithmetic instruction that overflowed. Execution of a trap (when trap condition is true). DDBL/DDBS AdEL EJTAG Data Address Break (address only) or EJTAG data value break on store (address + value). Load address alignment error. Load reference to protected address. AdES DBE Store address alignment error. Store to protected address. Load or store bus error. DDBL EJTAG data hardware breakpoint matched in load data compare. 3.3 Power Management (R) The MIPS M4K(R) processor core offers a number of power management features, including low-power design, active power management and power-down modes of operation. The core is a static design that supports slowing or Halting the clocks, which reduces system power consumption during Idle periods. 3.3.1 INSTRUCTION-CONTROLLED POWER MANAGEMENT The mechanism for invoking Power-Down mode is through execution of the WAIT instruction. For more information on power management, see Section 27.0 "Power-Saving Features". 3.3.2 LOCAL CLOCK GATING The majority of the power consumed by the PIC32MX1XX/2XX/5XX 64/100-pin family core is in the clock tree and clocking registers. The PIC32MX family uses extensive use of local gated-clocks to reduce this dynamic power consumption. DS60001290E-page 38 3.4 EJTAG Debug Support The MIPS(R) M4K(R) processor core provides for an Enhanced JTAG (EJTAG) interface for use in the software debug of application and kernel code. In addition to standard User mode and Kernel modes of operation, the M4K(R) core provides a Debug mode that is entered after a debug exception (derived from a hardware breakpoint, single-step exception, etc.) is taken and continues until a Debug Exception Return (DERET) instruction is executed. During this time, the processor executes the debug exception handler routine. The EJTAG interface operates through the Test Access Port (TAP), a serial communication port used for transferring test data in and out of the core. In addition to the standard JTAG instructions, special instructions defined in the EJTAG specification define which registers are selected and how they are used. 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 4.0 Note: MEMORY ORGANIZATION This data sheet summarizes the features of the PIC32MX1XX/2XX/5XX 64/100-pin family of devices. It is not intended to be a comprehensive reference source.For detailed information, refer to Section 3. "Memory Organization" (DS60001115) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). PIC32MX1XX/2XX/5XX 64/100-pin microcontrollers provide 4 GB of unified virtual memory address space. All memory regions, including program, data memory, SFRs and Configuration registers, reside in this address space at their respective unique addresses. The program and data memories can be optionally partitioned into user and kernel memories. In addition, the data memory can be made executable, allowing PIC32MX1XX/2XX/5XX 64/100-pin devices to execute from data memory. 4.1 Memory Layout PIC32MX1XX/2XX/5XX 64/100-pin microcontrollers implement two address schemes: virtual and physical. All hardware resources, such as program memory, data memory and peripherals, are located at their respective physical addresses. Virtual addresses are exclusively used by the CPU to fetch and execute instructions as well as access peripherals. Physical addresses are used by bus master peripherals, such as DMA and the Flash controller, that access memory independently of the CPU. The memory maps for the PIC32MX1XX/2XX/5XX 64/ 100-pin devices are illustrated in Figure 4-1 through Figure 4-4. The key features include: * 32-bit native data width * Separate User (KUSEG) and Kernel (KSEG0/ KSEG1) mode address space * Flexible program Flash memory partitioning * Flexible data RAM partitioning for data and program space * Separate boot Flash memory for protected code * Robust bus exception handling to intercept runaway code * Simple memory mapping with Fixed Mapping Translation (FMT) unit 2014-2017 Microchip Technology Inc. DS60001290E-page 39 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY FIGURE 4-1: MEMORY MAP FOR DEVICES WITH 64 KB OF PROGRAM MEMORY + 8 KB RAM Virtual Memory Map(1) 0xFFFFFFFF 0xBFC00C00 0xBFC00BFF 0xBFC00BF0 Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC00BEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD010000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD00FFFF Program Flash(2) 0xBD000000 0xA0002000 Reserved 0xA0001FFF RAM(2) 0xA0000000 0x9FC00C00 0x9FC00BFF 0x9FC00BF0 0x1FC00C00 Device Configuration Registers Reserved Device Configuration Registers 0x1FC00BFF 0x1FC00BF0 0x1FC00BEF Boot Flash 0x1FC00000 0x9FC00BEF Boot Flash Reserved 0x9FC00000 0x1F900000 Reserved 0x9D010000 0x9D00FFFF KSEG0 0x1F8FFFFF Program Flash(2) SFRs 0x1F800000 Reserved 0x9D000000 0x80002000 0x1D010000 Reserved 0x1D00FFFF Program Flash(2) 0x1D000000 0x80001FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: DS60001290E-page 40 Reserved Reserved RAM(2) 0x00002000 0x00001FFF 0x00000000 Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS60001115) in the "PIC32 Family Reference Manual") and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information). 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY FIGURE 4-2: MEMORY MAP FOR DEVICES WITH 128 KB OF PROGRAM MEMORY + 16 KB RAM Virtual Memory Map(1) 0xFFFFFFFF 0xBFC00C00 0xBFC00BFF 0xBFC00BF0 Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC00BEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD020000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD01FFFF Program Flash(2) 0xBD000000 0xA0004000 Reserved 0xA0003FFF RAM(2) 0xA0000000 0x9FC00C00 0x9FC00BFF 0x9FC00BF0 0x1FC00C00 Device Configuration Registers Reserved Device Configuration Registers 0x1FC00BFF 0x1FC00BF0 0x1FC00BEF Boot Flash 0x9FC00BEF 0x1FC00000 Boot Flash Reserved 0x9FC00000 0x1F900000 Reserved 0x9D020000 0x9D01FFFF KSEG0 0x1F8FFFFF Program Flash(2) SFRs 0x1F800000 Reserved 0x9D000000 0x80004000 0x1D020000 Reserved 0x1D01FFFF Program Flash(2) 0x1D000000 0x80003FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM(2) 0x00004000 0x00003FFF 0x00000000 Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS60001115) in the "PIC32 Family Reference Manual") and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information). 2014-2017 Microchip Technology Inc. DS60001290E-page 41 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY FIGURE 4-3: MEMORY MAP FOR DEVICES WITH 256 KB OF PROGRAM MEMORY + 32 KB RAM Virtual Memory Map(1) 0xFFFFFFFF 0xBFC00C00 0xBFC00BFF 0xBFC00BF0 Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC00BEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD040000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD03FFFF Program Flash(2) 0xBD000000 0xA0008000 Reserved 0xA0007FFF RAM(2) 0xA0000000 0x9FC00C00 0x9FC00BFF 0x9FC00BF0 0x1FC00C00 Device Configuration Registers Reserved Device Configuration Registers 0x1FC00BFF 0x1FC00BF0 0x1FC00BEF Boot Flash 0x1FC00000 0x9FC00BEF Boot Flash Reserved 0x9FC00000 0x1F900000 Reserved 0x9D040000 0x9D03FFFF KSEG0 0x1F8FFFFF Program Flash(2) SFRs 0x1F800000 Reserved 0x9D000000 0x80008000 0x1D040000 Reserved 0x1D03FFFF Program Flash(2) 0x1D000000 0x80007FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: DS60001290E-page 42 Reserved Reserved RAM(2) 0x00008000 0x00007FFF 0x00000000 Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS60001115) in the "PIC32 Family Reference Manual") and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information). 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY FIGURE 4-4: MEMORY MAP FOR DEVICES WITH 512 KB OF PROGRAM MEMORY + 64 KB RAM Virtual Memory Map(1) 0xFFFFFFFF 0xBFC00C00 0xBFC00BFF 0xBFC00BF0 Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC00BEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD080000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD07FFFF Program Flash(2) 0xBD000000 0xA0010000 Reserved 0xA000FFFF RAM(2) 0xA0000000 0x9FC00C00 0x9FC00BFF 0x9FC00BF0 0x1FC00C00 Device Configuration Registers Reserved Device Configuration Registers 0x1FC00BFF 0x1FC00BF0 0x1FC00BEF Boot Flash 0x9FC00BEF 0x1FC00000 Boot Flash Reserved 0x9FC00000 0x1F900000 Reserved 0x9D080000 0x9D07FFFF KSEG0 0x1F8FFFFF Program Flash(2) SFRs 0x1F800000 Reserved 0x9D000000 0x80010000 0x1D080000 Reserved 0x1D07FFFF Program Flash(2) 0x1D000000 0x8000FFFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM(2) 0x00010000 0x0000FFFF 0x00000000 Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS60001115) in the "PIC32 Family Reference Manual") and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information). 2014-2017 Microchip Technology Inc. DS60001290E-page 43 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 4-1: SFR MEMORY MAP Virtual Address Peripheral Base Offset Start Interrupt Controller 0x1000 Bus Matrix 0x2000 DMA USB 0xBF88 0x3000 0x5000 PORTA-PORTG 0x6000 CAN1 0xB000 Watchdog Timer 0x0000 RTCC 0x0200 Timer1-Timer5 0x0600 IC1-IC5 0x2000 OC1-OC5 0x3000 I2C1-I2C2 0x5000 SPI1-SPI4 0x5800 UART1-UART5 PMP 0xBF80 0x6000 0x7000 ADC1 0x9000 DAC 0x9800 Comparator 1, 2, 3 0xA000 Oscillator 0xF000 Device and Revision ID 0xF200 Flash Controller 0xF400 PPS 0xFA00 Configuration 0x0BF0 DS60001290E-page 44 0xBFC0 2014-2017 Microchip Technology Inc. Special Function Register Maps BMXCON(1) 2010 BMXDKPBA(1) 2020 BMXDUDBA(1) 2030 BMXDUPBA(1) 2040 BMXDRMSZ 2050 BMXPUPBA(1) 2060 BMXPFMSZ 2070 BMXBOOTSZ Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 31:16 -- -- -- -- -- BMXCHEDMA -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 31:16 15:0 18/2 17/1 -- -- -- -- BMXWSDRM -- 16/0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 041F BMXARB<2:0> -- -- 0047 -- -- 0000 0000 0000 0000 0000 0000 xxxx BMXDRMSZ<31:0> 15:0 31:16 19/3 BMXDUPBA<15:0> 31:16 15:0 20/4 BMXDUDBA<15:0> 15:0 31:16 21/5 BMXDKPBA<15:0> 15:0 31:16 22/6 All Resets Register Name 2000 BUS MATRIX REGISTER MAP Bit Range Virtual Address (BF88_#) TABLE 4-2: xxxx -- -- -- -- -- -- -- -- -- -- BMXPUPBA<15:0> BMXPFMSZ<31:0> -- -- BMXPUPBA<19:16> 0000 0000 xxxx xxxx BMXBOOTSZ<31:0> 0000 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. DS60001290E-page 45 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 2014-2017 Microchip Technology Inc. 4.2 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 4.3 Control Registers Register 4-1 through Register 4-8 are used for setting the RAM and Flash memory partitions for data and code. REGISTER 4-1: Bit Range BMXCON: BUS MATRIX CONFIGURATION REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- -- BMX ERRIXI BMX ERRICD BMX ERRDMA BMX ERRDS BMX ERRIS U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 R/W-1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-1 -- BMX WSDRM -- -- -- 31:24 23:16 15:8 7:0 Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set BMXARB<2:0> U = Unimplemented bit, read as `0' `0' = Bit is cleared bit 31-21 Unimplemented: Read as `0' bit 20 BMXERRIXI: Enable Bus Error from IXI bit 1 = Enable bus error exceptions for unmapped address accesses initiated from IXI shared bus 0 = Disable bus error exceptions for unmapped address accesses initiated from IXI shared bus bit 19 BMXERRICD: Enable Bus Error from ICD Debug Unit bit 1 = Enable bus error exceptions for unmapped address accesses initiated from ICD 0 = Disable bus error exceptions for unmapped address accesses initiated from ICD bit 18 BMXERRDMA: Bus Error from DMA bit 1 = Enable bus error exceptions for unmapped address accesses initiated from DMA 0 = Disable bus error exceptions for unmapped address accesses initiated from DMA bit 17 BMXERRDS: Bus Error from CPU Data Access bit (disabled in Debug mode) 1 = Enable bus error exceptions for unmapped address accesses initiated from CPU data access 0 = Disable bus error exceptions for unmapped address accesses initiated from CPU data access bit 16 BMXERRIS: Bus Error from CPU Instruction Access bit (disabled in Debug mode) 1 = Enable bus error exceptions for unmapped address accesses initiated from CPU instruction access 0 = Disable bus error exceptions for unmapped address accesses initiated from CPU instruction access bit 15-7 Unimplemented: Read as `0' bit 6 BMXWSDRM: CPU Instruction or Data Access from Data RAM Wait State bit 1 = Data RAM accesses from CPU have one wait state for address setup 0 = Data RAM accesses from CPU have zero wait states for address setup bit 5-3 Unimplemented: Read as `0' bit 2-0 BMXARB<2:0>: Bus Matrix Arbitration Mode bits 111 = Reserved (using these configuration modes will produce undefined behavior) * * * 011 = Reserved (using these configuration modes will produce undefined behavior) 010 = Arbitration Mode 2 001 = Arbitration Mode 1 (default) 000 = Arbitration Mode 0 DS60001290E-page 46 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 4-2: Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 -- -- -- R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 BMXDKPBA<15:8> R-0 7:0 BMXDKPBA: DATA RAM KERNEL PROGRAM BASE ADDRESS REGISTER R-0 R-0 R-0 R-0 BMXDKPBA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-10 BMXDKPBA<15:10>: DRM Kernel Program Base Address bits When non-zero, this value selects the relative base address for kernel program space in RAM bit 9-0 BMXDKPBA<9:0>: Read-Only bits Value is always `0', which forces 1 KB increments Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernel mode data usage. The value in this register must be less than or equal to BMXDRMSZ. 2: 2014-2017 Microchip Technology Inc. DS60001290E-page 47 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 4-3: Bit Range 31:24 23:16 15:8 7:0 BMXDUDBA: DATA RAM USER DATA BASE ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 BMXDUDBA<15:8> R-0 R-0 BMXDUDBA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-10 BMXDUDBA<15:10>: DRM User Data Base Address bits When non-zero, the value selects the relative base address for User mode data space in RAM, the value must be greater than BMXDKPBA. bit 9-0 BMXDUDBA<9:0>: Read-Only bits Value is always `0', which forces 1 KB increments Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernel mode data usage. The value in this register must be less than or equal to BMXDRMSZ. 2: DS60001290E-page 48 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 4-4: Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 -- -- -- R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 BMXDUPBA<15:8> R-0 7:0 BMXDUPBA: DATA RAM USER PROGRAM BASE ADDRESS REGISTER R-0 R-0 R-0 R-0 BMXDUPBA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-10 BMXDUPBA<15:10>: DRM User Program Base Address bits When non-zero, the value selects the relative base address for User mode program space in RAM, BMXDUPBA must be greater than BMXDUDBA. bit 9-0 BMXDUPBA<9:0>: Read-Only bits Value is always `0', which forces 1 KB increments Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernel mode data usage. The value in this register must be less than or equal to BMXDRMSZ. 2: 2014-2017 Microchip Technology Inc. DS60001290E-page 49 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 4-5: Bit Range 31:24 23:16 15:8 7:0 BMXDRMSZ: DATA RAM SIZE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R R R R R R Bit Bit 28/20/12/4 27/19/11/3 R Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R R R R R R R R R R R R R BMXDRMSZ<31:24> R R BMXDRMSZ<23:16> R R R R R R R R BMXDRMSZ<15:8> R R BMXDRMSZ<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-0 BMXDRMSZ<31:0>: Data RAM Memory (DRM) Size bits Static value that indicates the size of the Data RAM in bytes: 0x00002000 = Device has 8 KB RAM 0x00004000 = Device has 16 KB RAM 0x00008000 = Device has 32 KB RAM 0x00010000 = Device has 64 KB RAM REGISTER 4-6: Bit Range 31:24 23:16 15:8 7:0 x = Bit is unknown BMXPUPBA: PROGRAM FLASH (PFM) USER PROGRAM BASE ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 BMXPUPBA<19:16> R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 BMXPUPBA<15:8> R-0 R-0 BMXPUPBA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-20 Unimplemented: Read as `0' bit 19-11 BMXPUPBA<19:11>: Program Flash (PFM) User Program Base Address bits bit 10-0 BMXPUPBA<10:0>: Read-Only bits Value is always `0', which forces 2 KB increments Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernel mode data usage. The value in this register must be less than or equal to BMXPFMSZ. 2: DS60001290E-page 50 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 4-7: Bit Range 31:24 23:16 15:8 7:0 BMXPFMSZ: PROGRAM FLASH (PFM) SIZE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R R R Bit Bit 28/20/12/4 27/19/11/3 R Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R R R R R R R R R R R R R BMXPFMSZ<31:24> R R R R R BMXPFMSZ<23:16> R R R R R BMXPFMSZ<15:8> R R R R R BMXPFMSZ<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-0 BMXPFMSZ<31:0>: Program Flash Memory (PFM) Size bits Static value that indicates the size of the PFM in bytes: 0x00010000 = Device has 64 KB Flash 0x00020000 = Device has 128 KB Flash 0x00040000 = Device has 256 KB Flash 0x00080000 = Device has 512 KB Flash REGISTER 4-8: Bit Range 31:24 23:16 15:8 7:0 x = Bit is unknown BMXBOOTSZ: BOOT FLASH (IFM) SIZE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R R R Bit Bit 28/20/12/4 27/19/11/3 R Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R R R R R R R R R R R R R BMXBOOTSZ<31:24> R R R R R R R R BMXBOOTSZ<23:16> R R BMXBOOTSZ<15:8> R R R R R BMXBOOTSZ<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-0 x = Bit is unknown BMXBOOTSZ<31:0>: Boot Flash Memory (BFM) Size bits Static value that indicates the size of the Boot PFM in bytes: 0x00000C00 = Device has 3 KB Boot Flash 2014-2017 Microchip Technology Inc. DS60001290E-page 51 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY NOTES: DS60001290E-page 52 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 5.0 Note: INTERRUPT CONTROLLER This data sheet summarizes the features of the PIC32MX1XX/2XX/5XX 64/100-pin family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8. "Interrupt Controller" (DS60001108) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). PIC32MX1XX/2XX/5XX 64/100-pin devices generate interrupt requests in response to interrupt events from peripheral modules. The interrupt control module exists externally to the CPU logic and prioritizes the interrupt events before presenting them to the CPU. * * * * * * * * * * interrupt Up to 76 interrupt sources Up to 46 interrupt vectors Single and multi-vector mode operations Five external interrupts with edge polarity control Interrupt proximity timer Seven user-selectable priority levels for each vector Four user-selectable subpriority levels within each priority Software can generate any interrupt User-configurable interrupt vector table location User-configurable interrupt vector spacing Note: The dedicated shadow register set is not available on these devices. INTERRUPT CONTROLLER MODULE BLOCK DIAGRAM Interrupt Requests FIGURE 5-1: The PIC32MX1XX/2XX/5XX 64/100-pin module includes the following features: Vector Number Interrupt Controller 2014-2017 Microchip Technology Inc. Priority Level CPU Core DS60001290E-page 53 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 5-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION Interrupt Source(1) IRQ # Vector # Interrupt Bit Location Flag Enable Priority Sub-priority Persistent Interrupt Highest Natural Order Priority CT - Core Timer Interrupt 0 0 IFS0<0> IEC0<0> IPC0<4:2> IPC0<1:0> No CS0 - Core Software Interrupt 0 1 1 IFS0<1> IEC0<1> IPC0<12:10> IPC0<9:8> No CS1 - Core Software Interrupt 1 2 2 IFS0<2> IEC0<2> IPC0<20:18> IPC0<17:16> No INT0 - External Interrupt 3 3 IFS0<3> IEC0<3> IPC0<28:26> IPC0<25:24> No T1 - Timer1 4 4 IFS0<4> IEC0<4> IPC1<4:2> IPC1<1:0> No IC1E - Input Capture 1 Error 5 5 IFS0<5> IEC0<5> IPC1<12:10> IPC1<9:8> Yes IC1 - Input Capture 1 6 5 IFS0<6> IEC0<6> IPC1<12:10> IPC1<9:8> Yes OC1 - Output Compare 1 7 6 IFS0<7> IEC0<7> IPC1<20:18> IPC1<17:16> No INT1 - External Interrupt 1 8 7 IFS0<8> IEC0<8> IPC1<28:26> IPC1<25:24> No T2 - Timer2 9 8 IFS0<9> IEC0<9> IPC2<4:2> IPC2<1:0> No IC2E - Input Capture 2 10 9 IFS0<10> IEC0<10> IPC2<12:10> IPC2<9:8> Yes Yes IC2 - Input Capture 2 11 9 IFS0<11> IEC0<11> IPC2<12:10> IPC2<9:8> OC2 - Output Compare 2 12 10 IFS0<12> IEC0<12> IPC2<20:18> IPC2<17:16> No INT2 - External Interrupt 2 13 11 IFS0<13> IEC0<13> IPC2<28:26> IPC2<25:24> No T3 - Timer3 14 12 IFS0<14> IEC0<14> IPC3<4:2> IPC3<1:0> No IC3E - Input Capture 3 15 13 IFS0<15> IEC0<15> IPC3<12:10> IPC3<9:8> Yes Yes IC3 - Input Capture 3 16 13 IFS0<16> IEC0<16> IPC3<12:10> IPC3<9:8> OC3 - Output Compare 3 17 14 IFS0<17> IEC0<17> IPC3<20:18> IPC3<17:16> No INT3 - External Interrupt 3 18 15 IFS0<18> IEC0<18> IPC3<28:26> IPC3<25:24> No T4 - Timer4 19 16 IFS0<19> IEC0<19> IPC4<4:2> IPC4<1:0> No IC4E - Input Capture 4 Error 20 17 IFS0<20> IEC0<20> IPC4<12:10> IPC4<9:8> Yes IC4 - Input Capture 4 21 17 IFS0<21> IEC0<21> IPC4<12:10> IPC4<9:8> Yes OC4 - Output Compare 4 22 18 IFS0<22> IEC0<22> IPC4<20:18> IPC4<17:16> No INT4 - External Interrupt 4 23 19 IFS0<23> IEC0<23> IPC4<28:26> IPC4<25:24> No T5 - Timer5 24 20 IFS0<24> IEC0<24> IPC5<4:2> IPC5<1:0> No IC5E - Input Capture 5 Error 25 21 IFS0<25> IEC0<25> IPC5<12:10> IPC5<9:8> Yes IC5 - Input Capture 5 26 21 IFS0<26> IEC0<26> IPC5<12:10> IPC5<9:8> Yes OC5 - Output Compare 5 27 22 IFS0<27> IEC0<27> IPC5<20:18> IPC5<17:16> No AD1 - ADC1 Convert done 28 23 IFS0<28> IEC0<28> IPC5<28:26> IPC5<25:24> Yes FSCM - Fail-Safe Clock Monitor 29 24 IFS0<29> IEC0<29> IPC6<4:2> IPC6<1:0> No RTCC - Real-Time Clock and Calendar 30 25 IFS0<30> IEC0<30> IPC6<12:10> IPC6<9:8> No FCE - Flash Control Event 31 26 IFS0<31> IEC0<31> IPC6<20:18> IPC6<17:16> No CMP1 - Comparator Interrupt 32 27 IFS1<0> IEC1<0> IPC6<28:26> IPC6<25:24> No CMP2 - Comparator Interrupt 33 28 IFS1<1> IEC1<1> IPC7<4:2> IPC7<1:0> No USB - USB Interrupts 34 29 IFS1<2> IEC1<2> IPC7<12:10> IPC7<9:8> Yes Yes SPI1E - SPI1 Fault 35 30 IFS1<3> IEC1<3> IPC7<20:18> IPC7<17:16> SPI1RX - SPI1 Receive Done 36 30 IFS1<4> IEC1<4> IPC7<20:18> IPC7<17:16> Yes SPI1TX - SPI1 Transfer Done 37 30 IFS1<5> IEC1<5> IPC7<20:18> IPC7<17:16> Yes Yes U1E - UART1 Fault 38 31 IFS1<6> IEC1<6> IPC7<28:26> IPC7<25:24> U1RX - UART1 Receive Done 39 31 IFS1<7> IEC1<7> IPC7<28:26> IPC7<25:24> Yes U1TX - UART1 Transfer Done 40 31 IFS1<8> IEC1<8> IPC7<28:26> IPC7<25:24> Yes I2C1B - I2C1 Bus Collision Event 41 32 IFS1<9> IEC1<9> IPC8<4:2> IPC8<1:0> Yes I2C1S - I2C1 Slave Event 42 32 IFS1<10> IEC1<10> IPC8<4:2> IPC8<1:0> Yes I2C1M - I2C1 Master Event 43 32 IFS1<11> IEC1<11> IPC8<4:2> IPC8<1:0> Yes Note 1: 2: Not all interrupt sources are available on all devices. See TABLE 1: "PIC32MX1XX/2XX/5XX 64/100-pin Controller Family Features" for the list of available peripherals. This interrupt source is not available on 64-pin devices. DS60001290E-page 54 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 5-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED) Interrupt Source(1) IRQ # Vector # Interrupt Bit Location Flag Enable Priority Sub-priority Persistent Interrupt CNA - PORTA Input Change Interrupt 44 33 IFS1<12> IEC1<12> IPC8<12:10> IPC8<9:8> Yes CNB - PORTB Input Change Interrupt 45 33 IFS1<13> IEC1<13> IPC8<12:10> IPC8<9:8> Yes CNC - PORTC Input Change Interrupt 46 33 IFS1<14> IEC1<14> IPC8<12:10> IPC8<9:8> Yes CND - PORTD Input Change Interrupt 47 33 IFS1<15> IEC1<15> IPC8<12:10> IPC8<9:8> Yes CNE - PORTE Input Change Interrupt 48 33 IFS1<16> IEC1<16> IPC8<12:10> IPC8<9:8> Yes CNF - PORTF Input Change Interrupt 49 33 IFS1<17> IEC1<17> IPC8<12:10> IPC8<9:8> Yes CNG - PORTG Input Change Interrupt 50 33 IFS1<18> IEC1<18> IPC8<12:10> IPC8<9:8> Yes PMP - Parallel Master Port 51 34 IFS1<19> IEC1<19> IPC8<20:18> IPC8<17:16> Yes PMPE - Parallel Master Port Error 52 34 IFS1<20> IEC1<20> IPC8<20:18> IPC8<17:16> Yes SPI2E - SPI2 Fault 53 35 IFS1<21> IEC1<21> IPC8<28:26> IPC8<25:24> Yes SPI2RX - SPI2 Receive Done 54 35 IFS1<22> IEC1<22> IPC8<28:26> IPC8<25:24> Yes SPI2TX - SPI2 Transfer Done 55 35 IFS1<23> IEC1<23> IPC8<28:26> IPC8<25:24> Yes U2E - UART2 Error 56 36 IFS1<24> IEC1<24> IPC9<4:2> IPC9<1:0> Yes U2RX - UART2 Receiver 57 36 IFS1<25> IEC1<25> IPC9<4:2> IPC9<1:0> Yes U2TX - UART2 Transmitter 58 36 IFS1<26> IEC1<26> IPC9<4:2> IPC9<1:0> Yes I2C2B - I2C2 Bus Collision Event 59 37 IFS1<27> IEC1<27> IPC9<12:10> IPC9<9:8> Yes I2C2S - I2C2 Slave Event 60 37 IFS1<28> IEC1<28> IPC9<12:10> IPC9<9:8> Yes I2C2M - I2C2 Master Event 61 37 IFS1<29> IEC1<29> IPC9<12:10> IPC9<9:8> Yes U3E - UART3 Error 62 38 IFS1<30> IEC1<30> IPC9<20:18> IPC9<17:16> Yes U3RX - UART3 Receiver 63 38 IFS1<31> IEC1<31> IPC9<20:18> IPC9<17:16> Yes U3TX - UART3 Transmitter 64 38 IFS2<0> IEC2<0> IPC9<20:18> IPC9<17:16> Yes U4E - UART4 Error 65 39 IFS2<1> IEC2<1> IPC9<28:26> IPC9<25:24> Yes U4RX - UART4 Receiver 66 39 IFS2<2> IEC2<2> IPC9<28:26> IPC9<25:24> Yes U4TX - UART4 Transmitter 67 39 IFS2<3> IEC2<3> IPC9<28:26> IPC9<25:24> Yes U5E - UART5 Error(2) 68 40 IFS2<4> IEC2<4> IPC10<4:2> IPC10<1:0> Yes U5RX - UART5 Receiver(2) 69 40 IFS2<5> IEC2<5> IPC10<4:2> IPC10<1:0> Yes U5TX - UART5 Transmitter(2) 70 40 IFS2<6> IEC2<6> IPC10<4:2> IPC10<1:0> Yes Event(2) 71 41 IFS2<7> IEC2<7> IPC10<12:10> IPC10<9:8> Yes DMA0 - DMA Channel 0 72 42 IFS2<8> IEC2<8> IPC10<20:18> IPC10<17:16> No DMA1 - DMA Channel 1 73 43 IFS2<9> IEC2<9> IPC10<28:26> IPC10<25:24> No CTMU - CTMU DMA2 - DMA Channel 2 74 44 IFS2<10> IEC2<10> IPC11<4:2> IPC11<1:0> No DMA3 - DMA Channel 3 75 45 IFS2<11> IEC2<11> IPC11<12:10> IPC11<9:8> No CMP3 - Comparator 3 Interrupt 76 46 IFS2<12> IEC2<12> IPC11<20:18> IPC11<17:16> No CAN1 - CAN1 Event 77 47 IFS2<13> IEC2<13> IPC11<28:26> IPC11<25:24> Yes SPI3E - SPI3 Fault 78 48 IFS2<14> IEC2<14> IPC12<4:2> IPC12<1:0> Yes SPI3RX - SPI3 Receive Done 79 48 IFS2<15> IEC2<15> IPC12<4:2> IPC12<1:0> Yes SPI3TX - SPI3 Transfer Done 80 48 IFS2<16> IEC2<16> IPC12<4:2> IPC12<1:0> Yes (2) 81 49 IFS2<17> IEC2<17> IPC12<12:10> IPC12<9:8> Yes SPI4RX - SPI4 Receive Done(2) 82 49 IFS2<18> IEC2<18> IPC12<12:10> IPC12<9:8> Yes SPI4TX - SPI4 Transfer Done(2) 83 49 IFS2<19> IEC2<19> IPC12<12:10> IPC12<9:8> Yes SPI4E - SPI4 Fault Lowest Natural Order Priority Note 1: 2: Not all interrupt sources are available on all devices. See TABLE 1: "PIC32MX1XX/2XX/5XX 64/100-pin Controller Family Features" for the list of available peripherals. This interrupt source is not available on 64-pin devices. 2014-2017 Microchip Technology Inc. DS60001290E-page 55 Interrupts Control Registers Virtual Address (BF88_#) Register Name(3) TABLE 5-2: 1000 INTCON INTERRUPT REGISTER MAP (4) 1010 INTSTAT 1020 IPTMR 1030 IFS0 1040 IFS1 1050 IFS2 1060 IEC0 1070 IEC1 1080 IEC2 1090 IPC0 10A0 IPC1 2014-2017 Microchip Technology Inc. 10B0 IPC2 10C0 IPC3 10D0 IPC4 31/15 30/14 29/13 28/12 27/11 26/10 31:16 -- -- 15:0 -- -- -- -- -- -- -- MVEC -- 31:16 -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 0000 INT0EP 0000 -- 0000 23/7 22/6 21/5 -- -- -- -- -- -- -- -- -- -- -- INT4EP INT3EP INT2EP -- -- -- -- -- -- -- -- -- -- SRIPL<2:0> 31:16 18/2 INT1EP 24/8 -- 19/3 16/0 25/9 TPC<2:0> 20/4 All Resets Bit Range Bits 17/1 VEC<5:0> 0000 0000 IPTMR<31:0> 15:0 31:16 FCEIF 15:0 IC3EIF RTCCIF FSCMIF 0000 AD1IF OC5IF IC5IF IC5EIF T5IF INT4IF OC4IF IC4IF IC4EIF T4IF INT3IF OC3IF IC3IF 0000 T3IF INT2IF OC2IF IC2IF IC2EIF T2IF INT1IF OC1IF IC1IF IC1EIF T1IF INT0IF CS1IF CS0IF CTIF 0000 31:16 U3RXIF U3EIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF SPI2TXIF SPI2RXIF SPI2EIF PMPEIF PMPIF CNGIF CNFIF CNEIF 0000 15:0 CNDIF CNCIF CNBIF CNAIF U1RXIF U1EIF SPI1TXIF SPI1RXIF SPI1EIF USBIF(2) CMP2IF 31:16 -- -- 15:0 SPI3RXIF SPI3EIF 31:16 FCEIE 15:0 IC3EIE I2C1MIF I2C1SIF I2C1BIF U1TXIF -- -- CANIF CMP3IF RTCCIE FSCMIE -- -- -- -- DMA3IF DMA2IF DMA1IF DMA0IF -- -- -- -- CTMUIF U5TXIF(1) U5RXIF(1) U5EIF(1) CMP1IF 0000 SPI4TXIF(1) SPI4RXIF(1) SPI4EIF(1) SPI3TXIF 0000 U4TXIF U4RXIF U4EIF U3TXIF 0000 AD1IE OC5IE IC5IE IC5EIE T5IE INT4IE OC4IE IC4IE IC4EIE T4IE INT3IE OC3IE IC3IE 0000 IC2IE IC2EIE T2IE INT1IE OC1IE IC1IE IC1EIE T1IE INT0IE CS1IE CS0IE CTIE 0000 U2EIE SPI2TXIE SPI2RXIE SPI2EIE PMPEIE PMPIE CNGIE CNFIE CNEIE 0000 U1RXIE U1EIE SPI1TXIE SPI1RXIE SPI1EIE USBIE(2) CMP2IE T3IE INT2IE OC2IE 31:16 U3RXIE U3EIE I2C2MIE I2C2SIE 15:0 CNDIE CNCIE CNBIE CNAIE 31:16 -- -- -- -- 15:0 -- -- -- -- 31:16 -- -- -- INT0IP<2:0> 15:0 -- -- -- 31:16 -- -- 15:0 -- 31:16 I2C2BIE U2TXIE U2RXIE I2C1MIE I2C1SIE I2C1BIE U1TXIE -- -- -- -- CMP1IE 0000 -- -- -- -- -- -- -- -- 0000 CTMUIE U5TXIE(1) U5RXIE(1) U5EIE(1) U4TXIE U4RXIE U4EIE U3TXIE 0000 INT0IS<1:0> -- -- -- CS1IP<2:0> CS1IS<1:0> 0000 CS0IP<2:0> CS0IS<1:0> -- -- -- CTIP<2:0> CTIS<1:0> 0000 -- INT1IP<2:0> INT1IS<1:0> -- -- -- OC1IP<2:0> OC1IS<1:0> 0000 -- -- IC1IP<2:0> IC1IS<1:0> -- -- -- T1IP<2:0> T1IS<1:0> 0000 -- -- -- INT2IP<2:0> INT2IS<1:0> -- -- -- OC2IP<2:0> OC2IS<1:0> 0000 15:0 -- -- -- IC2IP<2:0> IC2IS<1:0> -- -- -- T2IP<2:0> T2IS<1:0> 0000 31:16 -- -- -- INT3IP<2:0> INT3IS<1:0> -- -- -- OC3IP<2:0> OC3IS<1:0> 0000 15:0 -- -- -- IC3IP<2:0> IC3IS<1:0> -- -- -- T3IP<2:0> T3IS<1:0> 0000 31:16 -- -- -- INT4IP<2:0> INT4IS<1:0> -- -- -- OC4IP<2:0> OC4IS<1:0> 0000 15:0 -- -- -- IC4IP<2:0> IC4IS<1:0> -- -- -- T4IP<2:0> T4IS<1:0> 0000 DMA3IE DMA2IE DMA1IE DMA0IE Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note This bit is only available on 100-pin devices. This bit is only implemented on devices with a USB module. With the exception of those noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. This register does not have associated CLR, SET, and INV registers. This bit is only implemented on devices with a CAN module. 1: 2: 3: 4: 5: PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 56 5.1 Virtual Address (BF88_#) Register Name(3) 10E0 IPC5 INTERRUPT REGISTER MAP (CONTINUED) 10F0 IPC6 1100 IPC7 1110 IPC8 1120 IPC9 1130 IPC10 1140 IPC11 1150 IPC12 31/15 30/14 29/13 28/12 23/7 22/6 21/5 31:16 -- -- -- AD1IP<2:0> 15:0 -- -- -- IC5IP<2:0> AD1IS<1:0> -- -- -- OC5IP<2:0> OC5IS<1:0> 0000 IC5IS<1:0> -- -- -- T5IP<2:0> T5IS<1:0> 31:16 -- -- -- 0000 CMP1IP<2:0> CMP1IS<1:0> -- -- -- FCEIP<2:0> FCEIS<1:0> 15:0 -- -- 0000 -- RTCCIP<2:0> RTCCIS<1:0> -- -- -- FSCMIP<2:0> FSCMIS<1:0> 31:16 -- 0000 -- -- U1IP<2:0> U1IS<1:0> -- -- -- SPI1IP<2:0> SPI1IS<1:0> 15:0 0000 -- -- -- USBIP<2:0>(2) USBIS<1:0>(2) -- -- -- CMP2IP<2:0> CMP2IS<1:0> 0000 31:16 -- -- -- SPI2IP<2:0> SPI2IS<1:0> -- -- -- PMPIP<2:0> PMPIS<1:0> 0000 15:0 -- -- -- CNIP<2:0> CNIS<1:0> -- -- -- I2C1IP<2:0> I2C1IS<1:0> 0000 31:16 -- -- -- U4IP<2:0> U4IS<1:0> -- -- -- U3IP<2:0> U3IS<1:0> 0000 15:0 -- -- -- I2C2IP<2:0> I2C2IS<1:0> -- -- -- U2IP<2:0> U2IS<1:0> 0000 31:16 -- -- -- DMA1IP<2:0> DMA1IS<1:0> -- -- -- DMA0IP<2:0> DMA0IS<1:0> 0000 15:0 -- -- -- CTMUIP<2:0> CTMUIS<1:0> -- -- -- U5IP<2:0> U5IS<1:0> 0000 31:16 -- -- -- CANIP<2:0>(5) CANIS<1:0>(5) -- -- -- CMP3IP<2:0> CMP3IS<1:0> 0000 15:0 -- -- -- DMA3IP<2:0> DMA3IS<1:0> -- -- -- DMA2IP<2:0> DMA2IS<1:0> 0000 31:16 -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- 27/11 -- SPI4P<2:0>(1) 26/10 -- 25/9 -- 24/8 -- SPI4S<1:0>(1) 20/4 -- 19/3 -- SPI3P<2:0> 18/2 -- 17/1 16/0 All Resets Bit Range Bits -- SPI3S<1:0> 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note This bit is only available on 100-pin devices. This bit is only implemented on devices with a USB module. With the exception of those noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. This register does not have associated CLR, SET, and INV registers. This bit is only implemented on devices with a CAN module. 1: 2: 3: 4: 5: DS60001290E-page 57 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 2014-2017 Microchip Technology Inc. TABLE 5-2: PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 5-1: Bit Range 31:24 23:16 15:8 7:0 INTCON: INTERRUPT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 -- -- -- MVEC -- U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 TPC<2:0> R/W-0 R/W-0 -- -- -- INT4EP INT3EP INT2EP INT1EP INT0EP Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-13 Unimplemented: Read as `0' bit 12 MVEC: Multi Vector Configuration bit 1 = Interrupt controller configured for multi vectored mode 0 = Interrupt controller configured for single vectored mode bit 11 bit 10-8 Unimplemented: Read as `0' TPC<2:0>: Interrupt Proximity Timer Control bits 111 = Interrupts of group priority 7 or lower start the Interrupt Proximity timer 110 = Interrupts of group priority 6 or lower start the Interrupt Proximity timer 101 = Interrupts of group priority 5 or lower start the Interrupt Proximity timer 100 = Interrupts of group priority 4 or lower start the Interrupt Proximity timer 011 = Interrupts of group priority 3 or lower start the Interrupt Proximity timer 010 = Interrupts of group priority 2 or lower start the Interrupt Proximity timer 001 = Interrupts of group priority 1 start the Interrupt Proximity timer 000 = Disables Interrupt Proximity timer bit 7-5 bit 4 Unimplemented: Read as `0' INT4EP: External Interrupt 4 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge bit 3 INT3EP: External Interrupt 3 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge INT2EP: External Interrupt 2 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge bit 2 bit 1 bit 0 INT1EP: External Interrupt 1 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge INT0EP: External Interrupt 0 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge DS60001290E-page 58 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 5-2: Bit Range 31:24 23:16 15:8 7:0 INTSTAT: INTERRUPT STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 -- -- -- -- -- U-0 U-0 R/W-0 R/W-0 R/W-0 -- -- SRIPL<2:0>(1) R/W-0 R/W-0 R/W-0 VEC<5:0>(1) Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-11 Unimplemented: Read as `0' bit 10-8 SRIPL<2:0>: Requested Priority Level bits(1) 111-000 = The priority level of the latest interrupt presented to the CPU bit 7-6 bit 5-0 Unimplemented: Read as `0' VEC<5:0>: Interrupt Vector bits(1) 11111-00000 = The interrupt vector that is presented to the CPU Note 1: This value should only be used when the interrupt controller is configured for Single Vector mode. REGISTER 5-3: Bit Range 31:24 23:16 15:8 7:0 IPTMR: INTERRUPT PROXIMITY TIMER REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IPTMR<31:24> R/W-0 IPTMR<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IPTMR<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IPTMR<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-0 x = Bit is unknown IPTMR<31:0>: Interrupt Proximity Timer Reload bits Used by the Interrupt Proximity Timer as a reload value when the Interrupt Proximity timer is triggered by an interrupt event. 2014-2017 Microchip Technology Inc. DS60001290E-page 59 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 5-4: Bit Range 31:24 23:16 15:8 7:0 IFSx: INTERRUPT FLAG STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFS31 IFS30 IFS29 R/W-0 R/W-0 R/W-0 IFS28 IFS27 IFS26 IFS25 IFS24 R/W-0 R/W-0 R/W-0 R/W-0 IFS23 IFS22 IFS21 R/W-0 IFS20 IFS19 IFS18 IFS17 IFS16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFS15 IFS14 IFS13 IFS12 IFS11 IFS10 IFS9 IFS8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFS7 IFS6 IFS5 IFS4 IFS3 IFS2 IFS1 IFS0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-0 Note: IFS31-IFS0: Interrupt Flag Status bits 1 = Interrupt request has occurred 0 = No interrupt request has occurred This register represents a generic definition of the IFSx register. Refer to Table 5-1 for the exact bit definitions. REGISTER 5-5: Bit Range 31:24 23:16 15:8 7:0 x = Bit is unknown Bit 31/23/15/7 IECx: INTERRUPT ENABLE CONTROL REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IEC31 IEC30 IEC29 IEC28 IEC27 IEC26 IEC25 IEC24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IEC23 IEC22 IEC21 IEC20 IEC19 IEC18 IEC17 IEC16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IEC15 IEC14 IEC13 IEC12 IEC11 IEC10 IEC9 IEC8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IEC7 IEC6 IEC5 IEC4 IEC3 IEC2 IEC1 IEC0 Legend: R = Readable bit -n = Value at POR bit 31-0 Note: W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown IEC31-IEC0: Interrupt Enable bits 1 = Interrupt is enabled 0 = Interrupt is disabled This register represents a generic definition of the IECx register. Refer to Table 5-1 for the exact bit definitions. DS60001290E-page 60 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 5-6: Bit Range IPCx: INTERRUPT PRIORITY CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 -- -- -- U-0 U-0 U-0 -- -- -- U-0 U-0 U-0 -- -- -- U-0 U-0 U-0 -- -- -- 31:24 23:16 15:8 7:0 Legend: R = Readable bit -n = Value at POR Bit Bit 28/20/12/4 27/19/11/3 W = Writable bit `1' = Bit is set R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 IP3<2:0> R/W-0 R/W-0 IS3<1:0> R/W-0 IP2<2:0> R/W-0 R/W-0 R/W-0 IP0<2:0> R/W-0 IS2<1:0> R/W-0 IP1<2:0> R/W-0 R/W-0 R/W-0 R/W-0 IS1<1:0> R/W-0 R/W-0 R/W-0 IS0<1:0> U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-29 Unimplemented: Read as `0' bit 28-26 IP3<2:0>: Interrupt Priority bits 111 = Interrupt priority is 7 * * * 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 25-24 IS3<1:0>: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 23-21 Unimplemented: Read as `0' bit 20-18 IP2<2:0>: Interrupt Priority bits 111 = Interrupt priority is 7 * * * 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 17-16 IS2<1:0>: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 15-13 Unimplemented: Read as `0' bit 12-10 IP1<2:0>: Interrupt Priority bits 111 = Interrupt priority is 7 * * * 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled Note: This register represents a generic definition of the IPCx register. Refer to Table 5-1 for the exact bit definitions. 2014-2017 Microchip Technology Inc. DS60001290E-page 61 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 5-6: bit 9-8 bit 7-5 bit 4-2 IPCx: INTERRUPT PRIORITY CONTROL REGISTER (CONTINUED) IS1<1:0>: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented: Read as `0' IP0<2:0>: Interrupt Priority bits 111 = Interrupt priority is 7 * * * bit 1-0 Note: 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled IS0<1:0>: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 This register represents a generic definition of the IPCx register. Refer to Table 5-1 for the exact bit definitions. DS60001290E-page 62 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 6.0 Note: FLASH PROGRAM MEMORY This data sheet summarizes the features of the PIC32MX1XX/2XX/5XX 64/100-pin family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 5. "Flash Program Memory" (DS60001121) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). PIC32MX1XX/2XX/5XX 64/100-pin devices contain an internal Flash program memory for executing user code. There are three methods by which the user can program this memory: * Run-Time Self-Programming (RTSP) * EJTAG Programming * In-Circuit Serial ProgrammingTM (ICSPTM) RTSP is performed by software executing from either Flash or RAM memory. Information about RTSP techniques is available in Section 5. "Flash Program Memory" (DS60001121) in the "PIC32 Family Reference Manual". EJTAG is performed using the EJTAG port of the device and an EJTAG capable programmer. ICSP is performed using a serial data connection to the device and allows much faster programming times than RTSP. The EJTAG and ICSP methods are described in the "PIC32 Flash Programming Specification" (DS60001145), which can be downloaded from the Microchip web site. Note: 2014-2017 Microchip Technology Inc. On PIC32MX1XX/2XX/5XX 64/100-pin devices, the Flash page size is 1 KB and the row size is 128 bytes (256 IW and 32 IW, respectively). DS60001290E-page 63 Control Registers Virtual Address (BF80_#) TABLE 6-1: FLASH CONTROLLER REGISTER MAP F400 NVMCON(1) F410 NVMKEY F420 NVMADDR(1) F430 NVMDATA F440 NVMSRC ADDR Legend: Note 1: 31/15 30/14 29/13 31:16 -- -- -- 15:0 31:16 WR WREN WRERR 15:0 31:16 15:0 31:16 15:0 31:16 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- LVDERR LVDSTAT 18/2 17/1 16/0 -- -- -- NVMOP<3:0> NVMKEY<31:0> NVMADDR<31:0> NVMDATA<31:0> NVMSRCADDR<31:0> 15:0 x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. All Resets Bit Range Register Name Bits 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 64 6.1 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 6-1: Bit Range NVMCON: PROGRAMMING CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 23:16 -- R/W-0 15:8 WR 7:0 -- R/W-0 (1) WREN -- -- -- -- -- -- R-0 R-0 R-0 U-0 U-0 U-0 WRERR(2) LVDERR(2) LVDSTAT(2) U-0 U-0 U-0 U-0 -- -- -- -- Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set R/W-0 -- -- -- R/W-0 R/W-0 R/W-0 NVMOP<3:0> U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 WR: Write Control bit This bit is writable when WREN = 1 and the unlock sequence is followed. 1 = Initiate a Flash operation. Hardware clears this bit when the operation completes 0 = Flash operation complete or inactive bit 14 WREN: Write Enable bit(1) 1 = Enable writes to WR bit and enables LVD circuit 0 = Disable writes to WR bit and disables LVD circuit This is the only bit in this register reset by a device Reset. bit 13 WRERR: Write Error bit(2) This bit is read-only and is automatically set by hardware. 1 = Program or erase sequence did not complete successfully 0 = Program or erase sequence completed normally bit 12 LVDERR: Low-Voltage Detect Error bit (LVD circuit must be enabled)(2) This bit is read-only and is automatically set by hardware. 1 = Low-voltage detected (possible data corruption, if WRERR is set) 0 = Voltage level is acceptable for programming bit 11 LVDSTAT: Low-Voltage Detect Status bit (LVD circuit must be enabled)(2) This bit is read-only and is automatically set, and cleared, by hardware. 1 = Low-voltage event active 0 = Low-voltage event NOT active bit 10-4 Unimplemented: Read as `0' bit 3-0 NVMOP<3:0>: NVM Operation bits These bits are writable when WREN = 0. 1111 =Reserved * * * 0111 = Reserved 0110 =No operation 0101 =Program Flash (PFM) erase operation: erases PFM, if all pages are not write-protected 0100 =Page erase operation: erases page selected by NVMADDR, if it is not write-protected 0011 =Row program operation: programs row selected by NVMADDR, if it is not write-protected 0010 =No operation 0001 =Word program operation: programs word selected by NVMADDR, if it is not write-protected 0000 = No operation Note 1: 2: This bit is cleared by any reset (i.e., POR, BOR, WDT, MCLR, SWR). This bit is only cleared by setting NVMOP = 0000, and initiating a Flash WR operation or a POR. Any other kind of reset (i.e., BOR, WDT, MCLR) does not clear this bit. 2014-2017 Microchip Technology Inc. DS60001290E-page 65 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 6-2: Bit Range 31:24 23:16 15:8 7:0 NVMKEY: PROGRAMMING UNLOCK REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 W-0 W-0 W-0 Bit Bit 28/20/12/4 27/19/11/3 W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<31:24> W-0 W-0 W-0 W-0 W-0 NVMKEY<23:16> W-0 W-0 W-0 W-0 W-0 NVMKEY<15:8> W-0 W-0 W-0 W-0 W-0 NVMKEY<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-0 Note: NVMKEY<31:0>: Unlock Register bits These bits are write-only, and read as `0' on any read. This register is used as part of the unlock sequence to prevent inadvertent writes to the PFM. REGISTER 6-3: Bit Range 31:24 23:16 15:8 7:0 x = Bit is unknown NVMADDR: FLASH ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMADDR<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMADDR<23:16> R/W-0 NVMADDR<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMADDR<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-0 x = Bit is unknown NVMADDR<31:0>: Flash Address bits Bulk/Chip/PFM Erase: Address is ignored Page Erase: Address identifies the page to erase Row Program: Address identifies the row to program Word Program: Address identifies the word to program DS60001290E-page 66 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 6-4: Bit Range 31:24 23:16 15:8 7:0 NVMDATA: FLASH PROGRAM DATA REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATA<31:24> R/W-0 NVMDATA<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATA<15:8> R/W-0 NVMDATA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-0 Note: NVMDATA<31:0>: Flash Programming Data bits The bits in this register are only reset by a Power-on Reset (POR). REGISTER 6-5: Bit Range 31:24 23:16 15:8 7:0 x = Bit is unknown NVMSRCADDR: SOURCE DATA ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMSRCADDR<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMSRCADDR<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMSRCADDR<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMSRCADDR<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-0 x = Bit is unknown NVMSRCADDR<31:0>: Source Data Address bits The system physical address of the data to be programmed into the Flash when the NVMOP<3:0> bits (NVMCON<3:0>) are set to perform row programming. 2014-2017 Microchip Technology Inc. DS60001290E-page 67 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY NOTES: DS60001290E-page 68 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 7.0 Note: RESETS This data sheet summarizes the features of the PIC32MX1XX/2XX/5XX 64/100-pin family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 7. "Resets" (DS60001118) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). FIGURE 7-1: The Reset module combines all Reset sources and controls the device Master Reset signal, SYSRST. The following is a list of device Reset sources: * * * * * * * POR: Power-on Reset MCLR: Master Clear Reset pin SWR: Software Reset WDTR: Watchdog Timer Reset BOR: Brown-out Reset CMR: Configuration Mismatch Reset HVDR: High Voltage Detect Reset A simplified block diagram of the Reset module is illustrated in Figure 7-1. SYSTEM RESET BLOCK DIAGRAM MCLR Glitch Filter Sleep or Idle WDTR WDT Time-out Voltage Regulator Enabled Power-up Timer VDD MCLR POR SYSRST VDD Rise Detect Configuration Mismatch Reset Brown-out Reset Brown-out Reset Software Reset BOR CMR SWR VCAP HVD Detect and Reset 2014-2017 Microchip Technology Inc. HVDR DS60001290E-page 69 Control Registers Virtual Address (BF80_#) Register Name(1) TABLE 7-1: F600 RCON F610 RSWRST RESET SFR SUMMARY 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 -- -- HVDR -- -- -- -- -- 15:0 -- -- -- -- -- -- CMR VREGS 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- Legend: -- = unimplemented, read as `0'. Address offset values are shown in hexadecimal. Note 1: The Reset value is dependent on the DEVCFGx Configuration bits and the type of reset. 23/7 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Bits 22/6 21/5 -- -- -- -- -- -- -- -- EXTR SWR -- WDTO SLEEP IDLE BOR POR -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- SWRST 0000 0000 xxxx(1) 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 70 7.1 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 7-1: Bit Range 31:24 23:16 15:8 7:0 RCON: RESET CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 R/W-0, HS U-0 -- -- HVDR -- U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS R/W-0 -- -- -- -- -- -- CMR VREGS R/W-0, HS R/W-0, HS U-0 R/W-0, HS R/W-0, HS R/W-0, HS EXTR SWR -- WDTO SLEEP IDLE R/W-1, HS (1) R/W-1, HS (1) Legend: R = Readable bit -n = Value at POR HS = Set by hardware W = Writable bit `1' = Bit is set BOR POR U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-30 Unimplemented: Read as `0' bit 29 HVDR: High Voltage Detect Reset Flag bit 1 = High Voltage Detect (HVD) Reset has occurred, voltage on VCAP > 2.5V 0 = HVD Reset has not occurred bit 28-10 Unimplemented: Read as `0' bit 9 CMR: Configuration Mismatch Reset Flag bit 1 = Configuration mismatch Reset has occurred 0 = Configuration mismatch Reset has not occurred bit 8 VREGS: Voltage Regulator Standby Enable bit 1 = Regulator is enabled and is on during Sleep mode 0 = Regulator is disabled and is off during Sleep mode bit 7 EXTR: External Reset (MCLR) Pin Flag bit 1 = Master Clear (pin) Reset has occurred 0 = Master Clear (pin) Reset has not occurred bit 6 SWR: Software Reset Flag bit 1 = Software Reset was executed 0 = Software Reset as not executed bit 5 Unimplemented: Read as `0' bit 4 WDTO: Watchdog Timer Time-out Flag bit 1 = WDT Time-out has occurred 0 = WDT Time-out has not occurred bit 3 SLEEP: Wake From Sleep Flag bit 1 = Device was in Sleep mode 0 = Device was not in Sleep mode bit 2 IDLE: Wake From Idle Flag bit 1 = Device was in Idle mode 0 = Device was not in Idle mode bit 1 BOR: Brown-out Reset Flag bit(1) 1 = Brown-out Reset has occurred 0 = Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit(1) 1 = Power-on Reset has occurred 0 = Power-on Reset has not occurred Note 1: User software must clear this bit to view next detection. 2014-2017 Microchip Technology Inc. DS60001290E-page 71 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 7-2: Bit Range 31:24 23:16 15:8 7:0 RSWRST: SOFTWARE RESET REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- U-0 U-0 U-0 -- U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- Legend: HC = Cleared by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared -- W-0, HC (1) SWRST x = Bit is unknown bit 31-1 Unimplemented: Read as `0' bit 0 SWRST: Software Reset Trigger bit(1) 1 = Enable software Reset event 0 = No effect Note 1: The system unlock sequence must be performed before the SWRST bit can be written. Refer to Section 6. "Oscillator" (DS60001112) in the "PIC32 Family Reference Manual" for details. DS60001290E-page 72 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 8.0 Note: OSCILLATOR CONFIGURATION This data sheet summarizes the features of the PIC32MX1XX/2XX/5XX 64/100-pin family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 6. "Oscillator Configuration" (DS60001112) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). The PIC32MX1XX/2XX/5XX 64/100-pin oscillator system has the following modules and features: * A Total of four external and internal oscillator options as clock sources * On-Chip PLL with user-selectable input divider, multiplier and output divider to boost operating frequency on select internal and external oscillator sources * On-Chip user-selectable divisor postscaler on select oscillator sources * Software-controllable switching between various clock sources * A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown * Dedicated On-Chip PLL for USB peripheral A block diagram of the oscillator system is provided in Figure 8-1. 2014-2017 Microchip Technology Inc. DS60001290E-page 73 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY FIGURE 8-1: PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY CLOCK DIAGRAM USB PLL(5) USB Clock (48 MHz) div x UFIN div 2 PLL x24 UFRCEN UPLLEN 96 MHz UFIN 4 MHz UPLLIDIV<2:0> ROTRIM<8:0> (M) REFCLKI POSC FRC LPRC SOSC PBCLK SYSCLK FVCO System PLL 4 MHz FIN 5 MHz FIN div x PLL PLLMULT<2:0> XTPLL, HSPLL, ECPLL, FRCPLL PLLODIV<2:0> Primary Oscillator (POSC) OSC1 RF(2) XTAL RP(1) C2(3) OSC2 POSC (XT, HS, EC) To Internal Logic Enable RS(1) To SPI ROSEL<3:0> div y C1(3) REFCLKO M 2 N + --------512 RODIV<14:0> (N) FPLLIDIV<2:0> COSC<2:0> OE FRC div 16 (4) div 2 CPU and Select Peripherals Postscaler SYSCLK FRCDIV FRCDIV<2:0> TUN<5:0> LPRC Oscillator PBDIV<1:0> FRC/16 To ADC FRC Oscillator 8 MHz typical Postscaler Peripherals div x PBCLK (TPB) 31.25 kHz typical LPRC Secondary Oscillator (SOSC) SOSCO 32.768 kHz SOSC SOSCEN and FSOSCEN Clock Control Logic Fail-Safe Clock Monitor SOSCI FSCM INT FSCM Event NOSC<2:0> COSC<2:0> FSCMEN<1:0> OSWEN WDT, PWRT Timer1, RTCC Notes: 1. 2. 3. 4. 5. A series resistor, RS, may be required for AT strip cut crystals or eliminate clipping. Alternately, to increase oscillator circuit gain, add a parallel resistor, RP, with a value of 1 M The internal feedback resistor, RF, is typically in the range of 2 M to 10 M Refer to Section 6. "Oscillator Configuration" (DS60001112) in the "PIC32 Family Reference Manual" for determining the best oscillator components. PBCLK out is available on the OSC2 pin in certain clock modes. USB PLL is available on PIC32MX2XX/5XX devices only. DS60001290E-page 74 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY FIGURE 8-2: PIC32MX1XX/2XX/5XX PLL BLOCK DIAGRAM (1) (1) FIN: FSYS: 3.92 MHz FIN z 60 MHz FSYS z (Crystal, External Clock Or Internal RC) FPLLIDIV X VCO (1) SYSCLK: 234,375 Hz SYSCLK 50 MHz FPLLODIV SYSCLK FPLLMULT Divide By: 1,2,3,4,5,6,10,12 Divide By: 1,2,4,8,16,32,64,256 Multiply By: 15,16,17,18,19, 20,21,22,23,24 Note 1: This frequency range must be satisfied at all times if the PLL is enabled and software is updating the corresponding bits in the OSCON register. 2014-2017 Microchip Technology Inc. DS60001290E-page 75 Control Registers Virtual Address (BF80_#) Register Name(1) TABLE 8-1: F000 OSCCON F010 OSCILLATOR CONFIGURATION REGISTER MAP OSCTUN F020 REFOCON F030 REFOTRIM 31:16 31/15 30/14 -- -- 29/13 28/12 27/11 26/10 PLLODIV<2:0> COSC<2:0> 25/9 24/8 FRCDIV<2:0> -- 23/7 -- 21/5 SOSCRDY PBDIVRDY 20/4 19/3 17/1 16/0 x1xx(2) PLLMULT<2:0> 15:0 -- CLKLOCK ULOCK SLOCK SLPEN CF -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- 31:16 -- 15:0 ON UFRCEN -- (3) SOSCEN OSWEN xxxx(2) -- -- 0000 TUN<5:0> 0000 RODIV<14:0> -- SIDL OE 31:16 RSLP -- DIVSWEN ACTIVE -- ROTRIM<8:0> -- 18/2 PBDIV<1:0> 31:16 15:0 NOSC<2:0> 22/6 -- -- -- -- -- -- -- -- All Resets Bit Range Bits 0000 -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 ROSEL<3:0> 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note With the exception of those noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. Reset values are dependent on the DEVCFGx Configuration bits and the type of reset. This bit is only available on devices with a USB module. 1: 2: 3: DS60001290E-page 76 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 2014-2017 Microchip Technology Inc. 8.1 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 8-1: Bit Range 31:24 23:16 15:8 7:0 OSCCON: OSCILLATOR CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 R/W-y -- -- U-0 -- U-0 R-0 R/W-y R-0 Bit 26/18/10/2 R/W-y R/W-0 PLLODIV<2:0> R-1 SOSCRDY PBDIVRDY -- Bit Bit 28/20/12/4 27/19/11/3 R-0 R/W-y R-0 Bit 24/16/8/0 R/W-0 R/W-1 FRCDIV<2:0> R/W-y R/W-y PBDIV<1:0> COSC<2:0> Bit 25/17/9/1 R/W-y R/W-y PLLMULT<2:0> U-0 R/W-y -- R/W-y R/W-y NOSC<2:0> R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-y R/W-0 CLKLOCK ULOCK(1) SLOCK SLPEN CF UFRCEN(1) SOSCEN OSWEN Legend: R = Readable bit -n = Value at POR y = Value set from Configuration bits on POR W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-30 Unimplemented: Read as `0' bit 29-27 PLLODIV<2:0>: Output Divider for PLL 111 = PLL output divided by 256 110 = PLL output divided by 64 101 = PLL output divided by 32 100 = PLL output divided by 16 011 = PLL output divided by 8 010 = PLL output divided by 4 001 = PLL output divided by 2 000 = PLL output divided by 1 bit 26-24 FRCDIV<2:0>: Internal Fast RC (FRC) Oscillator Clock Divider bits 111 = FRC divided by 256 110 = FRC divided by 64 101 = FRC divided by 32 100 = FRC divided by 16 011 = FRC divided by 8 010 = FRC divided by 4 001 = FRC divided by 2 (default setting) 000 = FRC divided by 1 bit 23 Unimplemented: Read as `0' bit 22 SOSCRDY: Secondary Oscillator (SOSC) Ready Indicator bit 1 = Indicates that the Secondary Oscillator is running and is stable 0 = Secondary Oscillator is still warming up or is turned off bit 21 PBDIVRDY: Peripheral Bus Clock (PBCLK) Divisor Ready bit 1 = PBDIV<1:0> bits can be written 0 = PBDIV<1:0> bits cannot be written bit 20-19 PBDIV<1:0>: Peripheral Bus Clock (PBCLK) Divisor bits 11 = PBCLK is SYSCLK divided by 8 (default) 10 = PBCLK is SYSCLK divided by 4 01 = PBCLK is SYSCLK divided by 2 00 = PBCLK is SYSCLK divided by 1 Note 1: Note: This bit is available on PIC32MX2XX/5XX devices only. Writes to this register require an unlock sequence. Refer to Section 6. "Oscillator" (DS60001112) in the "PIC32 Family Reference Manual" for details. 2014-2017 Microchip Technology Inc. DS60001290E-page 77 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 18-16 PLLMULT<2:0>: Phase-Locked Loop (PLL) Multiplier bits 111 = Clock is multiplied by 24 110 = Clock is multiplied by 21 101 = Clock is multiplied by 20 100 = Clock is multiplied by 19 011 = Clock is multiplied by 18 010 = Clock is multiplied by 17 001 = Clock is multiplied by 16 000 = Clock is multiplied by 15 bit 15 Unimplemented: Read as `0' bit 14-12 COSC<2:0>: Current Oscillator Selection bits 111 = Internal Fast RC (FRC) Oscillator divided by OSCCON<FRCDIV> bits 110 = Internal Fast RC (FRC) Oscillator divided by 16 101 = Internal Low-Power RC (LPRC) Oscillator 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator (POSC) with PLL module (XTPLL, HSPLL or ECPLL) 010 = Primary Oscillator (POSC) (XT, HS or EC) 001 = Internal Fast RC Oscillator with PLL module via Postscaler (FRCPLL) 000 = Internal Fast RC (FRC) Oscillator bit 11 Unimplemented: Read as `0' bit 10-8 NOSC<2:0>: New Oscillator Selection bits 111 = Internal Fast RC Oscillator (FRC) divided by OSCCON<FRCDIV> bits 110 = Internal Fast RC Oscillator (FRC) divided by 16 101 = Internal Low-Power RC (LPRC) Oscillator 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL or ECPLL) 010 = Primary Oscillator (XT, HS or EC) 001 = Internal Fast Internal RC Oscillator with PLL module via Postscaler (FRCPLL) 000 = Internal Fast Internal RC Oscillator (FRC) On Reset, these bits are set to the value of the FNOSC Configuration bits (DEVCFG1<2:0>). CLKLOCK: Clock Selection Lock Enable bit If clock switching and monitoring is disabled (FCKSM<1:0> = 1x): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified bit 7 bit 6 bit 5 bit 4 bit 3 Note If clock switching and monitoring is enabled (FCKSM<1:0> = 0x): Clock and PLL selections are never locked and may be modified. ULOCK: USB PLL Lock Status bit(1) 1 = Indicates that the USB PLL module is in lock or USB PLL module start-up timer is satisfied 0 = Indicates that the USB PLL module is out of lock or USB PLL module start-up timer is in progress or USB PLL is disabled SLOCK: PLL Lock Status bit 1 = PLL module is in lock or PLL module start-up timer is satisfied 0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled SLPEN: Sleep Mode Enable bit 1 = Device will enter Sleep mode when a WAIT instruction is executed 0 = Device will enter Idle mode when a WAIT instruction is executed CF: Clock Fail Detect bit 1 = FSCM has detected a clock failure 0 = No clock failure has been detected 1: This bit is available on PIC32MX2XX/5XX devices only. Note: Writes to this register require an unlock sequence. Refer to Section 6. "Oscillator" (DS60001112) in the "PIC32 Family Reference Manual" for details. DS60001290E-page 78 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 8-1: bit 2 bit 1 bit 0 Note 1: Note: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) UFRCEN: USB FRC Clock Enable bit(1) 1 = Enable FRC as the clock source for the USB clock source 0 = Use the Primary Oscillator or USB PLL as the USB clock source SOSCEN: Secondary Oscillator (SOSC) Enable bit 1 = Enable Secondary Oscillator 0 = Disable Secondary Oscillator OSWEN: Oscillator Switch Enable bit 1 = Initiate an oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete This bit is available on PIC32MX2XX/5XX devices only. Writes to this register require an unlock sequence. Refer to Section 6. "Oscillator" (DS60001112) in the "PIC32 Family Reference Manual" for details. 2014-2017 Microchip Technology Inc. DS60001290E-page 79 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 8-2: Bit Range 31:24 23:16 15:8 7:0 OSCTUN: FRC TUNING REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- R/W-0 (1) TUN<5:0> Legend: y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-6 Unimplemented: Read as `0' bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1) 100000 = Center frequency -12.5% 100001 = * * * 111111 = 000000 = Center frequency. Oscillator runs at minimal frequency (8 MHz) 000001 = * * * 011110 = 011111 = Center frequency +12.5% x = Bit is unknown Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation, and is neither characterized, nor tested. Note: Writes to this register require an unlock sequence. Refer to Section 6. "Oscillator" (DS60001112) in the "PIC32 Family Reference Manual" for details. DS60001290E-page 80 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 8-3: Bit Range 31:24 23:16 15:8 7:0 REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 U-0 R/W-0 R/W-0 R/W-0 R/W-0 -- R/W-0 RODIV<14:8> R/W-0 R/W-0 R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R-0, HS, HC -- DIVSWEN ACTIVE R/W-0 R/W-0 R/W-0 (1) RODIV<7:0>(3) R/W-0 U-0 R/W-0 R/W-0 ON -- SIDL OE U-0 U-0 U-0 U-0 -- -- -- -- R/W-0 RSLP (2) R/W-0 ROSEL<3:0>(1) Legend: HC = Hardware Clearable HS = Hardware Settable R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set bit 31 U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' bit 30-16 RODIV<14:0>: Reference Clock Divider bits(1) This value selects the Reference Clock Divider bits. See Figure 8-1 for more information. bit 15 ON: Output Enable bit 1 = Reference Oscillator Module enabled 0 = Reference Oscillator Module disabled Unimplemented: Read as `0' bit 14 bit 13 SIDL: Peripheral Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode OE: Reference Clock Output Enable bit 1 = Reference clock is driven out on REFCLKO pin 0 = Reference clock is not driven out on REFCLKO pin bit 12 RSLP: Reference Oscillator Module Run in Sleep bit(2) 1 = Reference Oscillator Module output continues to run in Sleep 0 = Reference Oscillator Module output is disabled in Sleep Unimplemented: Read as `0' bit 11 bit 10 bit 9 DIVSWEN: Divider Switch Enable bit 1 = Divider switch is in progress 0 = Divider switch is complete ACTIVE: Reference Clock Request Status bit 1 = Reference clock request is active 0 = Reference clock request is not active bit 8 bit 7-4 Unimplemented: Read as `0' Note 1: The ROSEL and RODIV bits should not be written while the ACTIVE bit is `1', as undefined behavior may result. This bit is ignored when the ROSEL<3:0> bits = 0000 or 0001. While the ON bit is set to `1', writes to these bits do not take effect until the DIVSWEN bit is also set to `1'. 2: 3: 2014-2017 Microchip Technology Inc. DS60001290E-page 81 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 8-3: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER (CONTINUED) bit 3-0 ROSEL<3:0>: Reference Clock Source Select bits(1) 1111 = Reserved; do not use * * * 1001 = Reserved; do not use 1000 = REFCLKI 0111 = System PLL output 0110 = USB PLL output 0101 = SOSC 0100 = LPRC 0011 = FRC 0010 = POSC 0001 = PBCLK 0000 = SYSCLK Note 1: The ROSEL and RODIV bits should not be written while the ACTIVE bit is `1', as undefined behavior may result. This bit is ignored when the ROSEL<3:0> bits = 0000 or 0001. While the ON bit is set to `1', writes to these bits do not take effect until the DIVSWEN bit is also set to `1'. 2: 3: DS60001290E-page 82 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 8-4: Bit Range 31:24 23:16 15:8 7:0 REFOTRIM: REFERENCE OSCILLATOR TRIM REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 ROTRIM<8:1> R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 ROTRIM<0> -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- Legend: y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-23 ROTRIM<8:0>: Reference Oscillator Trim bits 111111111 = 511/512 divisor added to RODIV value 111111110 = 510/512 divisor added to RODIV value * * * 100000000 = 256/512 divisor added to RODIV value * * * 000000010 = 2/512 divisor added to RODIV value 000000001 = 1/512 divisor added to RODIV value 000000000 = 0/512 divisor added to RODIV value bit 22-0 Note: Unimplemented: Read as `0' While the ON bit (REFOCON<15>) is `1', writes to this register do not take effect until the DIVSWEN bit is also set to `1'. 2014-2017 Microchip Technology Inc. DS60001290E-page 83 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY NOTES: DS60001290E-page 84 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 9.0 DIRECT MEMORY ACCESS (DMA) CONTROLLER Note: This data sheet summarizes the features of the PIC32MX1XX/2XX/5XX 64/100-pin family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 31. "Direct Memory Access (DMA) Controller" (DS60001117) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). The PIC32 Direct Memory Access (DMA) controller is a bus master module useful for data transfers between different devices without CPU intervention. The source and destination of a DMA transfer can be any of the memory mapped modules existent in the PIC32 (such as Peripheral Bus (PBUS) devices: SPI, UART, PMP, etc.) or memory itself. The following are some of the key features of the DMA controller module: * Four identical channels, each featuring: - Auto-increment source and destination address registers - Source and destination pointers - Memory to memory and memory to peripheral transfers * Automatic word-size detection: - Transfer granularity, down to byte level - Bytes need not be word-aligned at source and destination FIGURE 9-1: INT Controller Peripheral Bus * Fixed priority channel arbitration * Flexible DMA channel operating modes: - Manual (software) or automatic (interrupt) DMA requests - One-Shot or Auto-Repeat Block Transfer modes - Channel-to-channel chaining * Flexible DMA requests: - A DMA request can be selected from any of the peripheral interrupt sources - Each channel can select any (appropriate) observable interrupt as its DMA request source - A DMA transfer abort can be selected from any of the peripheral interrupt sources - Pattern (data) match transfer termination * Multiple DMA channel status interrupts: - DMA channel block transfer complete - Source empty or half empty - Destination full or half full - DMA transfer aborted due to an external event - Invalid DMA address generated * DMA debug support features: - Most recent address accessed by a DMA channel - Most recent DMA channel to transfer data * CRC Generation module: - CRC module can be assigned to any of the available channels - CRC module is highly configurable DMA BLOCK DIAGRAM System IRQ Address Decoder SE Channel 0 Control I0 Channel 1 Control I1 L Y Bus Interface Device Bus + Bus Arbitration I2 Global Control (DMACON) Channel n Control In L SE Channel Priority Arbitration 2014-2017 Microchip Technology Inc. DS60001290E-page 85 Control Registers 3000 DMACON 3010 DMASTAT 3020 DMAADDR 31:16 -- -- -- 15:0 31:16 ON -- -- -- -- -- 15:0 31:16 -- -- -- All Resets Bit Range 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 -- -- -- -- -- -- -- RDWR SUSPEND DMABUSY -- -- -- -- DMACH<2:0> 0000 0000 DMAADDR<31:0> 15:0 x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. 0000 All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. TABLE 9-2: DMA CRC REGISTER MAP Bits Register Name(1) Virtual Address (BF88_#) 30/14 31/15 30/14 -- -- -- -- 29/13 28/12 26/10 25/9 24/8 23/7 WBO -- PLEN<4:0> -- BITO -- CRCEN 22/6 21/5 -- -- CRCAPP CRCTYP 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- -- CRCCH<2:0> -- 2014-2017 Microchip Technology Inc. 3030 DCRCCON 31:16 15:0 3040 DCRCDATA 31:16 15:0 DCRCDATA<31:0> 0000 0000 3050 DCRCXOR 31:16 15:0 DCRCXOR<31:0> 0000 0000 Legend: Note 1: BYTO<1:0> -- 27/11 All Resets Note 1: 31/15 Bit Range Legend: DMA GLOBAL REGISTER MAP Bits Register Name(1) Virtual Address (BF88_#) TABLE 9-1: 0000 0000 x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 86 9.1 Virtual Address (BF88_#) 3070 DCH0ECON DCH0INT 3090 DCH0SSA 30A0 DCH0DSA 30B0 DCH0SSIZ 30C0 DCH0DSIZ 30D0 DCH0SPTR 30E0 DCH0DPTR 30F0 DCH0CSIZ 3100 DCH0CPTR 3110 DCH0DAT 3120 DCH1CON 3130 DCH1ECON 3140 DCH1INT DS60001290E-page 87 3150 DCH1SSA 3160 DCH1DSA Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CHCHNS -- CHEN CHAED CHCHN CHAEN -- CHAIRQ<7:0> CHEDET -- -- -- 31:16 -- -- -- CHSIRQ<7:0> -- -- -- -- -- CFORCE CABORT CHSDIE CHSHIE PATEN CHDDIE SIRQEN CHDHIE AIRQEN CHBCIE -- CHCCIE -- CHTAIE -- FFF8 CHERIE 0000 15:0 -- -- -- -- -- -- -- CHSDIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 0000 31:16 15:0 CHBUSY 31:16 15:0 -- 31:16 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 17/1 16/0 -- -- -- 0000 CHPRI<1:0> 0000 00FF 0000 0000 -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 CHPDAT<7:0> -- -- -- 0000 0000 0000 -- 0000 -- 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- CHCHNS -- 31:16 -- -- -- CHSIRQ<7:0> -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- 0000 CHCPTR<15:0> 15:0 -- -- 0000 0000 CHCSIZ<15:0> 15:0 CHBUSY 15:0 31:16 -- 18/2 CHDPTR<15:0> -- 31:16 19/3 CHSPTR<15:0> -- 31:16 20/4 CHDSIZ<15:0> -- 31:16 CHSHIF 21/5 CHSSIZ<15:0> 15:0 31:16 15:0 22/6 CHDSA<31:0> 15:0 31:16 15:0 31:16 23/7 CHSSA<31:0> 15:0 15:0 31:16 24/8 All Resets Bit Range Register Name(1) Bits 3060 DCH0CON 3080 DMA CHANNEL 0 THROUGH CHANNEL 3 REGISTER MAP 0000 -- -- -- CHEN CHAED CHCHN CHAEN -- CHAIRQ<7:0> CHEDET CFORCE CABORT CHSDIE CHSHIE PATEN CHDDIE SIRQEN CHDHIE AIRQEN CHBCIE -- CHCCIE -- CHTAIE -- FFF8 CHERIE 0000 CHSDIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 0000 CHSSA<31:0> CHDSA<31:0> 15:0 x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. CHSHIF -- -- CHPRI<1:0> 0000 00FF 0000 0000 0000 All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 2014-2017 Microchip Technology Inc. TABLE 9-3: Virtual Address (BF88_#) 3180 DCH1DSIZ 3190 DCH1SPTR 31A0 DCH1DPTR 31B0 DCH1CSIZ 31C0 DCH1CPTR 31D0 DCH1DAT 31E0 DCH2CON 31F0 DCH2ECON DCH2INT 3210 DCH2SSA 3220 DCH2DSA 2014-2017 Microchip Technology Inc. 3230 DCH2SSIZ 3240 DCH2DSIZ 3250 DCH2SPTR 3260 DCH2DPTR 3270 DCH2CSIZ 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 31:16 15:0 31:16 -- -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- 15:0 31:16 15:0 31:16 24/8 -- -- CHSSIZ<15:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CHCHNS -- 31:16 -- -- -- CHSIRQ<7:0> -- -- -- -- -- 15:0 -- -- -- -- -- -- -- 15:0 18/2 17/1 16/0 -- -- -- -- -- -- -- 0000 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 CHPDAT<7:0> -- -- -- 0000 0000 0000 -- 0000 -- -- -- 15:0 -- 31:16 -- 0000 0000 -- -- -- CHEN CHAED CHCHN CHAEN -- CHAIRQ<7:0> CHEDET CFORCE CABORT CHSDIE CHSHIE PATEN CHDDIE SIRQEN CHDHIE AIRQEN CHBCIE -- CHCCIE -- CHTAIE -- FFF8 CHERIE 0000 CHSDIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 0000 CHSHIF -- -- CHPRI<1:0> CHSSA<31:0> 15:0 31:16 -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- CHSSIZ<15:0> -- -- 0000 CHDSIZ<15:0> -- -- 0000 CHSPTR<15:0> -- -- 0000 CHDPTR<15:0> -- -- -- -- -- -- -- -- -- CHCSIZ<15:0> 0000 00FF 0000 0000 CHDSA<31:0> -- 0000 0000 CHCPTR<15:0> 15:0 CHBUSY 15:0 19/3 CHCSIZ<15:0> -- 15:0 31:16 20/4 CHDPTR<15:0> -- 15:0 31:16 21/5 CHSPTR<15:0> -- 31:16 -- 22/6 CHDSIZ<15:0> -- 31:16 23/7 All Resets Bit Range Register Name(1) Bits 3170 DCH1SSIZ 3200 DMA CHANNEL 0 THROUGH CHANNEL 3 REGISTER MAP (CONTINUED) 0000 0000 0000 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 88 TABLE 9-3: Virtual Address (BF88_#) 3290 DCH2DAT 32A0 DCH3CON 32B0 DCH3ECON DCH3INT 32D0 DCH3SSA 32E0 DCH3DSA 32F0 DCH3SSIZ 3300 DCH3DSIZ 3310 DCH3SPTR 3320 DCH3DPTR 3330 DCH3CSIZ 3340 DCH3CPTR 3350 DCH3DAT Legend: DS60001290E-page 89 Note 1: 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 -- -- -- -- -- -- -- 15:0 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CHCPTR<15:0> All Resets Bit Range Register Name(1) Bits 3280 DCH2CPTR 32C0 DMA CHANNEL 0 THROUGH CHANNEL 3 REGISTER MAP (CONTINUED) 0000 0000 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CHCHNS -- CHEN CHAED CHCHN CHAEN -- CHAIRQ<7:0> CHEDET -- -- -- 31:16 -- -- -- CHSIRQ<7:0> -- -- -- -- -- CFORCE CABORT CHSDIE CHSHIE PATEN CHDDIE SIRQEN CHDHIE AIRQEN CHBCIE -- CHCCIE -- CHTAIE -- FFF8 CHERIE 0000 15:0 -- -- -- -- -- -- -- CHSDIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 0000 15:0 CHBUSY 31:16 15:0 -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- 0000 CHPRI<1:0> 0000 00FF 0000 0000 -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- CHSSIZ<15:0> -- -- 0000 CHDSIZ<15:0> -- -- 0000 CHSPTR<15:0> -- -- 0000 CHDPTR<15:0> -- -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- 15:0 CHSHIF -- -- -- -- 0000 CHCPTR<15:0> -- -- -- -- -- -- -- -- -- x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. -- 0000 0000 CHCSIZ<15:0> -- 0000 0000 CHDSA<31:0> 15:0 31:16 15:0 31:16 CHPDAT<7:0> CHSSA<31:0> 15:0 31:16 15:0 31:16 -- 0000 CHPDAT<7:0> 0000 0000 All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 2014-2017 Microchip Technology Inc. TABLE 9-3: PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 9-1: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 DMACON: DMA CONTROLLER CONTROL REGISTER Bit Bit 30/22/14/6 29/21/13/5 U-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 (1) U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- ON SUSPEND DMABUSY(1) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: DMA On bit(1) 1 = DMA module is enabled 0 = DMA module is disabled bit 14-13 Unimplemented: Read as `0' bit 12 SUSPEND: DMA Suspend bit 1 = DMA transfers are suspended to allow CPU uninterrupted access to data bus 0 = DMA operates normally bit 11 DMABUSY: DMA Module Busy bit(1) 1 = DMA module is active 0 = DMA module is disabled and not actively transferring data bit 10-0 Unimplemented: Read as `0' Note 1: When using 1:1 PBCLK divisor, the user's software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. DS60001290E-page 90 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 9-2: Bit Range 31:24 23:16 15:8 7:0 DMASTAT: DMA STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 -- -- -- -- RDWR DMACH<2:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-4 Unimplemented: Read as `0' bit 3 RDWR: Read/Write Status bit 1 = Last DMA bus access was a read 0 = Last DMA bus access was a write bit 2-0 DMACH<2:0>: DMA Channel bits These bits contain the value of the most recent active DMA channel. REGISTER 9-3: Bit Range 31:24 23:16 15:8 7:0 DMAADDR: DMA ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R-0 R-0 R-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DMAADDR<31:24> R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DMAADDR<23:16> R-0 R-0 DMAADDR<15:8> R-0 R-0 R-0 R-0 R-0 DMAADDR<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 DMAADDR<31:0>: DMA Module Address bits These bits contain the address of the most recent DMA access. 2014-2017 Microchip Technology Inc. DS60001290E-page 91 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 9-4: Bit Range 31:24 23:16 15:8 7:0 DCRCCON: DMA CRC CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 U-0 U-0 R/W-0 R/W-0 BYTO<1:0> Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 R/W-0 R/W-0 (1) -- -- WBO -- -- BITO U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- R/W-0 R/W-0 R/W-0 U-0 U-0 PLEN<4:0> CRCEN CRCAPP(1) CRCTYP -- -- R/W-0 CRCCH<2:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-30 Unimplemented: Read as `0' bit 29-28 BYTO<1:0>: CRC Byte Order Selection bits 11 = Endian byte swap on half-word boundaries (i.e., source half-word order with reverse source byte order per half-word) 10 = Swap half-words on word boundaries (i.e., reverse source half-word order with source byte order per half-word) 01 = Endian byte swap on word boundaries (i.e., reverse source byte order) 00 = No swapping (i.e., source byte order) bit 27 WBO: CRC Write Byte Order Selection bit(1) 1 = Source data is written to the destination re-ordered as defined by BYTO<1:0> 0 = Source data is written to the destination unaltered bit 26-25 Unimplemented: Read as `0' bit 24 BITO: CRC Bit Order Selection bit(1 When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode): 1 = The IP header checksum is calculated Least Significant bit (LSb) first (i.e., reflected) 0 = The IP header checksum is calculated Most Significant bit (MSb) first (i.e., not reflected) When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode): 1 = The LFSR CRC is calculated Least Significant bit first (i.e., reflected) 0 = The LFSR CRC is calculated Most Significant bit first (i.e., not reflected) bit 23-13 Unimplemented: Read as `0' bit 12-8 PLEN<4:0>: Polynomial Length bits(1) When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode): These bits are unused. When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode): Denotes the length of the polynomial - 1. bit 7 CRCEN: CRC Enable bit 1 = CRC module is enabled and channel transfers are routed through the CRC module 0 = CRC module is disabled and channel transfers proceed normally Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set. DS60001290E-page 92 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 9-4: DCRCCON: DMA CRC CONTROL REGISTER (CONTINUED) bit 6 CRCAPP: CRC Append Mode bit(1) 1 = The DMA transfers data from the source into the CRC but NOT to the destination. When a block transfer completes the DMA writes the calculated CRC value to the location given by CHxDSA 0 = The DMA transfers data from the source through the CRC obeying WBO as it writes the data to the destination bit 5 CRCTYP: CRC Type Selection bit 1 = The CRC module will calculate an IP header checksum 0 = The CRC module will calculate a LFSR CRC bit 4-3 Unimplemented: Read as `0' bit 2-0 CRCCH<2:0>: CRC Channel Select bits 111 = CRC is assigned to Channel 7 110 = CRC is assigned to Channel 6 101 = CRC is assigned to Channel 5 100 = CRC is assigned to Channel 4 011 = CRC is assigned to Channel 3 010 = CRC is assigned to Channel 2 001 = CRC is assigned to Channel 1 000 = CRC is assigned to Channel 0 Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set. 2014-2017 Microchip Technology Inc. DS60001290E-page 93 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 9-5: Bit Range 31:24 23:16 15:8 7:0 DCRCDATA: DMA CRC DATA REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 DCRCDATA<31:0>: CRC Data Register bits Writing to this register will seed the CRC generator. Reading from this register will return the current value of the CRC. Bits greater than PLEN will return `0' on any read. When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode): Only the lower 16 bits contain IP header checksum information. The upper 16 bits are always `0'. Data written to this register is converted and read back in 1's complement form (i.e., current IP header checksum value). When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode): Bits greater than PLEN will return `0' on any read. REGISTER 9-6: Bit Range 31:24 23:16 15:8 7:0 DCRCXOR: DMA CRCXOR ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCXOR<31:24> R/W-0 R/W-0 DCRCXOR<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCXOR<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCXOR<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 DCRCXOR<31:0>: CRC XOR Register bits When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode): This register is unused. When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode): 1 = Enable the XOR input to the Shift register 0 = Disable the XOR input to the Shift register; data is shifted in directly from the previous stage in the register DS60001290E-page 94 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 9-7: Bit Range 31:24 23:16 15:8 7:0 DCHxCON: DMA CHANNEL `x' CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 CHBUSY -- -- -- -- -- -- CHCHNS(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R-0 CHEN(2) CHAED CHCHN CHAEN -- CHEDET CHPRI<1:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 CHBUSY: Channel Busy bit 1 = Channel is active or has been enabled 0 = Channel is inactive or has been disabled bit 14-9 Unimplemented: Read as `0' bit 8 CHCHNS: Chain Channel Selection bit(1) 1 = Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete) 0 = Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete) bit 7 CHEN: Channel Enable bit(2) 1 = Channel is enabled 0 = Channel is disabled bit 6 CHAED: Channel Allow Events If Disabled bit 1 = Channel start/abort events will be registered, even if the channel is disabled 0 = Channel start/abort events will be ignored if the channel is disabled bit CHCHN: Channel Chain Enable bit 1 = Allow channel to be chained 0 = Do not allow channel to be chained bit 4 CHAEN: Channel Automatic Enable bit 1 = Channel is continuously enabled, and not automatically disabled after a block transfer is complete 0 = Channel is disabled on block transfer complete bit 3 Unimplemented: Read as `0' bit 2 CHEDET: Channel Event Detected bit 1 = An event has been detected 0 = No events have been detected bit 1-0 CHPRI<1:0>: Channel Priority bits 11 = Channel has priority 3 (highest) 10 = Channel has priority 2 01 = Channel has priority 1 00 = Channel has priority 0 Note 1: 2: The chain selection bit takes effect when chaining is enabled (i.e., CHCHN = 1). When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if available on the device variant) to see when the channel is suspended, as it may take some clock cycles to complete a current transaction before the channel is suspended. 2014-2017 Microchip Technology Inc. DS60001290E-page 95 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 9-8: Bit Range 31:24 23:16 DCHxECON: DMA CHANNEL `x' EVENT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 (1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CHAIRQ<7:0> 15:8 R/W-1 CHSIRQ<7:0>(1) 7:0 S-0 S-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 CFORCE CABORT PATEN SIRQEN AIRQEN -- -- -- Legend: R = Readable bit -n = Value at POR S = Settable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as `0' bit 23-16 CHAIRQ<7:0>: Channel Transfer Abort IRQ bits(1) 11111111 = Interrupt 255 will abort any transfers in progress and set CHAIF flag * * * bit 15-8 00000001 = Interrupt 1 will abort any transfers in progress and set CHAIF flag 00000000 = Interrupt 0 will abort any transfers in progress and set CHAIF flag CHSIRQ<7:0>: Channel Transfer Start IRQ bits(1) 11111111 = Interrupt 255 will initiate a DMA transfer * * * bit 2-0 00000001 = Interrupt 1 will initiate a DMA transfer 00000000 = Interrupt 0 will initiate a DMA transfer CFORCE: DMA Forced Transfer bit 1 = A DMA transfer is forced to begin when this bit is written to a `1' 0 = This bit always reads `0' CABORT: DMA Abort Transfer bit 1 = A DMA transfer is aborted when this bit is written to a `1' 0 = This bit always reads `0' PATEN: Channel Pattern Match Abort Enable bit 1 = Abort transfer and clear CHEN on pattern match 0 = Pattern match is disabled SIRQEN: Channel Start IRQ Enable bit 1 = Start channel cell transfer if an interrupt matching CHSIRQ occurs 0 = Interrupt number CHSIRQ is ignored and does not start a transfer AIRQEN: Channel Abort IRQ Enable bit 1 = Channel transfer is aborted if an interrupt matching CHAIRQ occurs 0 = Interrupt number CHAIRQ is ignored and does not terminate a transfer Unimplemented: Read as `0' Note 1: See Table 5-1: "Interrupt IRQ, Vector and Bit Location" for the list of available interrupt IRQ sources. bit 7 bit 6 bit 5 bit 4 bit 3 DS60001290E-page 96 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 9-9: Bit Range 31:24 23:16 15:8 7:0 DCHxINT: DMA CHANNEL `x' INTERRUPT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as `0' bit 23 CHSDIE: Channel Source Done Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 22 CHSHIE: Channel Source Half Empty Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 21 CHDDIE: Channel Destination Done Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 20 CHDHIE: Channel Destination Half Full Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 19 CHBCIE: Channel Block Transfer Complete Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 18 CHCCIE: Channel Cell Transfer Complete Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 17 CHTAIE: Channel Transfer Abort Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 16 CHERIE: Channel Address Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 15-8 Unimplemented: Read as `0' bit 7 CHSDIF: Channel Source Done Interrupt Flag bit 1 = Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ) 0 = No interrupt is pending bit 6 CHSHIF: Channel Source Half Empty Interrupt Flag bit 1 = Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2) 0 = No interrupt is pending bit 5 CHDDIF: Channel Destination Done Interrupt Flag bit 1 = Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ) 0 = No interrupt is pending 2014-2017 Microchip Technology Inc. DS60001290E-page 97 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 9-9: DCHxINT: DMA CHANNEL `x' INTERRUPT CONTROL REGISTER (CONTINUED) bit 4 CHDHIF: Channel Destination Half Full Interrupt Flag bit 1 = Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2) 0 = No interrupt is pending bit 3 CHBCIF: Channel Block Transfer Complete Interrupt Flag bit 1 = A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred), or a pattern match event occurs 0 = No interrupt is pending bit 2 CHCCIF: Channel Cell Transfer Complete Interrupt Flag bit 1 = A cell transfer has been completed (CHCSIZ bytes have been transferred) 0 = No interrupt is pending bit 1 CHTAIF: Channel Transfer Abort Interrupt Flag bit 1 = An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted 0 = No interrupt is pending bit 0 CHERIF: Channel Address Error Interrupt Flag bit 1 = A channel address error has been detected Either the source or the destination address is invalid. 0 = No interrupt is pending DS60001290E-page 98 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 9-10: Bit Range DCHxSSA: DMA CHANNEL `x' SOURCE START ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 R/W-0 R/W-0 31:24 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 R/W-0 R/W-0 R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA<31:24> R/W-0 23:16 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA<23:16> R/W-0 15:8 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA<15:8> R/W-0 7:0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-0 x = Bit is unknown CHSSA<31:0> Channel Source Start Address bits Channel source start address. Note: This must be the physical address of the source. REGISTER 9-11: Bit Range 31:24 23:16 15:8 7:0 DCHxDSA: DMA CHANNEL `x' DESTINATION START ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHDSA<31:24> R/W-0 R/W-0 CHDSA<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHDSA<15:8> R/W-0 CHDSA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 CHDSA<31:0>: Channel Destination Start Address bits Channel destination start address. Note: This must be the physical address of the destination. 2014-2017 Microchip Technology Inc. DS60001290E-page 99 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 9-12: Bit Range 31:24 23:16 15:8 DCHxSSIZ: DMA CHANNEL `x' SOURCE SIZE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSIZ<15:8> 7:0 R/W-0 CHSSIZ<7:0> Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 CHSSIZ<15:0>: Channel Source Size bits 1111111111111111 = 65,535 byte source size * * * 0000000000000010 = 2 byte source size 0000000000000001 = 1 byte source size 0000000000000000 = 65,536 byte source size REGISTER 9-13: Bit Range 31:24 23:16 15:8 DCHxDSIZ: DMA CHANNEL `x' DESTINATION SIZE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHDSIZ<15:8> 7:0 R/W-0 CHDSIZ<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 CHDSIZ<15:0>: Channel Destination Size bits 1111111111111111 = 65,535 byte destination size * * * 0000000000000010 = 2 byte destination size 0000000000000001 = 1 byte destination size 0000000000000000 = 65,536 byte destination size DS60001290E-page 100 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 9-14: Bit Range 31:24 23:16 15:8 DCHxSPTR: DMA CHANNEL `x' SOURCE POINTER REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CHSPTR<15:8> 7:0 R-0 R-0 CHSPTR<7:0> Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 CHSPTR<15:0>: Channel Source Pointer bits 1111111111111111 = Points to byte 65,535 of the source * * * 0000000000000001 = Points to byte 1 of the source 0000000000000000 = Points to byte 0 of the source When in Pattern Detect mode, this register is reset on a pattern detect. Note: REGISTER 9-15: Bit Range 31:24 23:16 15:8 DCHxDPTR: DMA CHANNEL `x' DESTINATION POINTER REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CHDPTR<15:8> 7:0 R-0 R-0 CHDPTR<7:0> Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 CHDPTR<15:0>: Channel Destination Pointer bits 1111111111111111 = Points to byte 65,535 of the destination * * * 0000000000000001 = Points to byte 1 of the destination 0000000000000000 = Points to byte 0 of the destination 2014-2017 Microchip Technology Inc. DS60001290E-page 101 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 9-16: Bit Range 31:24 23:16 15:8 DCHxCSIZ: DMA CHANNEL `x' CELL-SIZE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHCSIZ<15:8> 7:0 R/W-0 CHCSIZ<7:0> Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 CHCSIZ<15:0>: Channel Cell-Size bits 1111111111111111 = 65,535 bytes transferred on an event * * * 0000000000000010 = 2 bytes transferred on an event 0000000000000001= 1 byte transferred on an event 0000000000000000 = 65,536 bytes transferred on an event REGISTER 9-17: Bit Range 31:24 23:16 15:8 DCHxCPTR: DMA CHANNEL `x' CELL POINTER REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CHCPTR<15:8> 7:0 R-0 R-0 CHCPTR<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 CHCPTR<7:0>: Channel Cell Progress Pointer bits 1111111111111111 = 65,535 bytes have been transferred since the last event * * * 0000000000000001 = 1 byte has been transferred since the last event 0000000000000000 = 0 bytes have been transferred since the last event Note: When in Pattern Detect mode, this register is reset on a pattern detect. DS60001290E-page 102 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 9-18: Bit Range 31:24 23:16 15:8 7:0 DCHxDAT: DMA CHANNEL `x' PATTERN DATA REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHPDAT<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7-0 CHPDAT<7:0>: Channel Data Register bits Pattern Terminate mode: Data to be matched must be stored in this register to allow terminate on match. All other modes: Unused. 2014-2017 Microchip Technology Inc. DS60001290E-page 103 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY NOTES: DS60001290E-page 104 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 10.0 Note: USB ON-THE-GO (OTG) This data sheet summarizes the features of the PIC32MX1XX/2XX/5XX 64/100-pin family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 27. "USB OnThe-Go (OTG)" (DS60001126) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). The Universal Serial Bus (USB) module contains analog and digital components to provide a USB 2.0 full-speed and low-speed embedded host, full-speed device or OTG implementation with a minimum of external components. This module in Host mode is intended for use as an embedded host and therefore does not implement a UHCI or OHCI controller. The USB module consists of the clock generator, the USB voltage comparators, the transceiver, the Serial Interface Engine (SIE), a dedicated USB DMA controller, pull-up and pull-down resistors, and the register interface. A block diagram of the PIC32 USB OTG module is presented in Figure 10-1. The clock generator provides the 48 MHz clock required for USB full-speed and low-speed communication. The voltage comparators monitor the voltage on the VBUS pin to determine the state of the bus. The transceiver provides the analog translation between the USB bus and the digital logic. The SIE is a state machine that transfers data to and from the endpoint buffers and generates the hardware protocol for data transfers. The USB DMA controller transfers data between the data buffers in RAM and the SIE. The integrated pull-up and pull-down resistors eliminate the need for external signaling components. The register interface allows the CPU to configure and communicate with the module. The PIC32 USB module includes the following features: * * * * * * * * * USB Full-speed support for host and device Low-speed host support USB OTG support Integrated signaling resistors Integrated analog comparators for VBUS monitoring Integrated USB transceiver Transaction handshaking performed by hardware Endpoint buffering anywhere in system RAM Integrated DMA to access system RAM and Flash Note: 2014-2017 Microchip Technology Inc. The implementation and use of the USB specifications, and other third party specifications or technologies, may require licensing; including, but not limited to, USB Implementers Forum, Inc. (also referred to as USB-IF). The user is fully responsible for investigating and satisfying any applicable licensing obligations. DS60001290E-page 105 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY FIGURE 10-1: PIC32MX1XX/2XX/5XX USB INTERFACE DIAGRAM USBEN FRC Oscillator 8 MHz Typical USB Suspend CPU Clock Not POSC Sleep TUN<5:0>(3) Primary Oscillator (POSC) Div x OSC1 UPLLIDIV USB Suspend OSC2 (PB Out)(1) UFIN(4) PLL Div 2 UPLLEN(5) (5) UFRCEN(2) To Clock Generator for Core and Peripherals Sleep or Idle USB Module Nominal +5V VBUS SRP Charge SRP Discharge USB Voltage Comparators 48 MHz USB Clock(6) Full Speed Pull-up D+ Registers and Control Interface Host Pull-down SIE Transceiver Low Speed Pull-up DDMA System RAM Host Pull-down ID Pull-up USBID(7) VBUSON(7) Transceiver Power 3.3V VUSB3V3 Note 1: 2: 3: 4: 5: 6: 7: PB clock is only available on this pin for select EC modes. This bit field is contained in the OSCCON register. This bit field is contained in the OSCTRM register. USB PLL UFIN requirements: 4 MHz. This bit field is contained in the DEVCFG2 register. A 48 MHz clock is required for proper USB operation. Pins can be used as GPIO when the USB module is disabled or if the USB is enabled but DEVCFG3<31:30> = `0b00. DS60001290E-page 106 2014-2017 Microchip Technology Inc. Control Registers Virtual Address (BF88_#) Register Name(1) TABLE 10-1: 5040 U1OTGIR(2) 5050 U1OTGIE 5060 U1OTGSTAT(3) 5070 U1OTGCON 5080 U1PWRC 5200 U1IR(2) 5210 U1IE U1EIR(2) 5230 U1EIE U1STAT(3) 23/7 22/6 21/5 -- -- 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 -- -- -- -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- IDIF -- T1MSECIF LSTATEIF -- -- ACTVIF -- SESVDIF SESENDIF -- -- -- -- VBUSVDIF 0000 -- 0000 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- IDIE -- T1MSECIE LSTATEIE -- -- ACTVIE -- SESVDIE SESENDIE -- -- -- -- VBUSVDIE 0000 -- 0000 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ID -- 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- UACTPND(4) -- 15:0 -- -- -- -- -- -- -- -- STALLIF 31:16 -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- STALLIE 31:16 -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- BTSEF 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 19/3 18/2 17/1 -- -- -- SESVD -- DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON -- -- -- -- -- -- -- -- -- 0000 0000 OTGEN -- VBUSCHG -- VBUSDIS -- 0000 0000 USUSPEND USBPWR -- -- 0000 0000 -- -- DS60001290E-page 107 SOFIF UERRIF -- -- -- -- IDLEIE TRNIE SOFIE UERRIE -- -- -- -- -- BMXEF DMAEF BTOEF -- -- -- -- -- BTSEE BMXEE DMAEE BTOEE -- -- -- -- -- -- -- -- EOFEE -- -- -- -- -- -- -- -- ENDPT<3:0> -- -- -- DIR -- PPBI -- -- -- -- -- JSTATE SE0 PKTDIS TOKBUSY USBRST -- ATTACHIE RESUMEIE 5260 U1ADDR 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- LSPDEN -- -- 5270 U1BDTP1 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DFN8EF CRC16EF -- -- DFN8EE CRC16EE -- CRC5EF EOFEF -- CRC5EE URSTIF 0000 DETACHIF 0000 -- URSTIE 0000 0000 DETACHIE 0000 -- 0000 PIDEF 0000 0000 -- 0000 0000 PIDEE -- 0000 0000 -- -- -- -- 0000 0000 PPBRST USBEN SOFEN 0000 0000 -- -- -- 0000 0000 -- -- -- -- 0000 0000 HOSTEN RESUME -- DEVADDR<6:0> -- BDTPTRL<15:9> 0000 VBUSVD -- TRNIF -- -- -- -- IDLEIF -- 16/0 SESEND -- USLPGRD USBBUSY -- -- ATTACHIF RESUMEIF U1CON 2: 3: 4: -- LSTATE -- 5250 Legend: Note 1: 20/4 All Resets Bit Range Bits 5220 5240 USB REGISTER MAP x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. With the exception of those noted, all registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. This register does not have associated SET and INV registers. This register does not have associated CLR, SET and INV registers. Reset value for this bit is undefined. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 2014-2017 Microchip Technology Inc. 10.1 Virtual Address (BF88_#) Register Name(1) Bit Range USB REGISTER MAP (CONTINUED) 5280 U1FRML(3) 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FRML<7:0> -- -- -- 0000 0000 5290 U1FRMH(3) 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FRMH<2:0> -- 0000 0000 52A0 U1TOK 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PID<3:0> -- -- -- -- EP<3:0> -- 0000 0000 52B0 U1SOF 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CNT<7:0> -- -- -- -- -- 0000 0000 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BDTPTRH<23:16> -- -- -- -- -- 0000 0000 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BDTPTRU<31:24> -- -- -- -- -- 0000 0000 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- UTEYE -- -- -- -- -- USBSIDL -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- LSPD -- RETRYDIS -- -- -- EPCONDIS EPRXEN -- -- EPTXEN -- EPSTALL -- EPHSHK -- 0000 0000 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN -- -- EPTXEN -- EPSTALL -- EPHSHK -- 0000 0000 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN -- -- EPTXEN -- EPSTALL -- EPHSHK -- 0000 0000 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN -- -- EPTXEN -- EPSTALL -- EPHSHK -- 0000 0000 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN -- -- EPTXEN -- EPSTALL -- EPHSHK -- 0000 0000 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN -- -- EPTXEN -- EPSTALL -- EPHSHK -- 0000 0000 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN -- -- EPTXEN -- EPSTALL -- EPHSHK -- 0000 0000 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN -- -- EPTXEN -- EPSTALL -- EPHSHK -- 0000 0000 52C0 52D0 U1BDTP2 U1BDTP3 2014-2017 Microchip Technology Inc. 52E0 U1CNFG1 5300 U1EP0 5310 U1EP1 5320 U1EP2 5330 U1EP3 5340 U1EP4 5350 U1EP5 5360 U1EP6 5370 U1EP7 5380 U1EP8 Legend: Note 1: 2: 3: 4: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 LSDEV -- 18/2 17/1 16/0 All Resets Bits UASUSPND 0000 -- 0000 15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. With the exception of those noted, all registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. This register does not have associated SET and INV registers. This register does not have associated CLR, SET and INV registers. Reset value for this bit is undefined. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 108 TABLE 10-1: Virtual Address (BF88_#) Register Name(1) Bit Range USB REGISTER MAP (CONTINUED) 5390 U1EP9 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN -- EPTXEN -- EPSTALL -- EPHSHK 0000 0000 53A0 U1EP10 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN -- EPTXEN -- EPSTALL -- EPHSHK 0000 0000 53B0 U1EP11 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN -- EPTXEN -- EPSTALL -- EPHSHK 0000 0000 53C0 U1EP12 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN -- EPTXEN -- EPSTALL -- EPHSHK 0000 0000 53D0 U1EP13 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN -- EPTXEN -- EPSTALL -- EPHSHK 0000 0000 53E0 U1EP14 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 53F0 U1EP15 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN -- -- EPTXEN -- EPSTALL -- EPHSHK -- 0000 0000 15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 Legend: Note 1: 2: 3: 4: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 -- 19/3 -- 18/2 17/1 16/0 All Resets Bits x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. With the exception of those noted, all registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. This register does not have associated SET and INV registers. This register does not have associated CLR, SET and INV registers. Reset value for this bit is undefined. DS60001290E-page 109 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 2014-2017 Microchip Technology Inc. TABLE 10-1: PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 10-1: Bit Range 31:24 23:16 15:8 7:0 U1OTGIR: USB OTG INTERRUPT STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS U-0 R/WC-0, HS IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF -- VBUSVDIF Legend: WC = Write `1' to clear HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 IDIF: ID State Change Indicator bit 1 = Change in ID state detected 0 = No change in ID state detected bit 6 T1MSECIF: 1 Millisecond Timer bit 1 = 1 millisecond timer has expired 0 = 1 millisecond timer has not expired bit 5 LSTATEIF: Line State Stable Indicator bit 1 = USB line state has been stable for 1millisecond, but different from last time 0 = USB line state has not been stable for 1 millisecond bit 4 ACTVIF: Bus Activity Indicator bit 1 = Activity on the D+, D-, ID or VBUS pins has caused the device to wake-up 0 = Activity has not been detected bit 3 SESVDIF: Session Valid Change Indicator bit 1 = VBUS voltage has dropped below the session end level 0 = VBUS voltage has not dropped below the session end level bit 2 SESENDIF: B-Device VBUS Change Indicator bit 1 = A change on the session end input was detected 0 = No change on the session end input was detected bit 1 Unimplemented: Read as `0' bit 0 VBUSVDIF: A-Device VBUS Change Indicator bit 1 = Change on the session valid input detected 0 = No change on the session valid input detected DS60001290E-page 110 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 10-2: Bit Range 31:24 23:16 15:8 7:0 U1OTGIE: USB OTG INTERRUPT ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE -- VBUSVDIE Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 IDIE: ID Interrupt Enable bit 1 = ID interrupt enabled 0 = ID interrupt disabled bit 6 T1MSECIE: 1 Millisecond Timer Interrupt Enable bit 1 = 1 millisecond timer interrupt enabled 0 = 1 millisecond timer interrupt disabled bit 5 LSTATEIE: Line State Interrupt Enable bit 1 = Line state interrupt enabled 0 = Line state interrupt disabled bit 4 ACTVIE: Bus Activity Interrupt Enable bit 1 = ACTIVITY interrupt enabled 0 = ACTIVITY interrupt disabled bit 3 SESVDIE: Session Valid Interrupt Enable bit 1 = Session valid interrupt enabled 0 = Session valid interrupt disabled bit 2 SESENDIE: B-Session End Interrupt Enable bit 1 = B-session end interrupt enabled 0 = B-session end interrupt disabled bit 1 Unimplemented: Read as `0' bit 0 VBUSVDIE: A-VBUS Valid Interrupt Enable bit 1 = A-VBUS valid interrupt enabled 0 = A-VBUS valid interrupt disabled 2014-2017 Microchip Technology Inc. DS60001290E-page 111 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 10-3: Bit Range 31:24 23:16 15:8 7:0 U1OTGSTAT: USB OTG STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-0 U-0 R-0 U-0 R-0 R-0 U-0 R-0 ID -- LSTATE -- SESVD SESEND -- VBUSVD Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 ID: ID Pin State Indicator bit 1 = No cable is attached or a Type-B cable has been plugged into the USB receptacle 0 = A Type-A cable has been plugged into the USB receptacle bit 6 Unimplemented: Read as `0' bit 5 LSTATE: Line State Stable Indicator bit 1 = USB line state (U1CON<SE0> and U1CON<JSTATE>) has been stable for the previous 1 ms 0 = USB line state (U1CON<SE0> and U1CON<JSTATE>) has not been stable for the previous 1 ms bit 4 Unimplemented: Read as `0' bit 3 SESVD: Session Valid Indicator bit 1 = VBUS voltage is above Session Valid on the A or B device 0 = VBUS voltage is below Session Valid on the A or B device bit 2 SESEND: B-Device Session End Indicator bit 1 = VBUS voltage is below Session Valid on the B device 0 = VBUS voltage is above Session Valid on the B device bit 1 Unimplemented: Read as `0' bit 0 VBUSVD: A-Device VBUS Valid Indicator bit 1 = VBUS voltage is above Session Valid on the A device 0 = VBUS voltage is below Session Valid on the A device DS60001290E-page 112 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 10-4: Bit Range 31:24 23:16 15:8 7:0 U1OTGCON: USB OTG CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VBUSON OTGEN VBUSCHG VBUSDIS DPPULUP DMPULUP DPPULDWN DMPULDWN Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 DPPULUP: D+ Pull-Up Enable bit 1 = D+ data line pull-up resistor is enabled 0 = D+ data line pull-up resistor is disabled bit 6 DMPULUP: D- Pull-Up Enable bit 1 = D- data line pull-up resistor is enabled 0 = D- data line pull-up resistor is disabled bit 5 DPPULDWN: D+ Pull-Down Enable bit 1 = D+ data line pull-down resistor is enabled 0 = D+ data line pull-down resistor is disabled bit 4 DMPULDWN: D- Pull-Down Enable bit 1 = D- data line pull-down resistor is enabled 0 = D- data line pull-down resistor is disabled bit 3 VBUSON: VBUS Power-on bit 1 = VBUS line is powered 0 = VBUS line is not powered bit 2 OTGEN: OTG Functionality Enable bit 1 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under software control 0 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under USB hardware control bit 1 VBUSCHG: VBUS Charge Enable bit 1 = VBUS line is charged through a pull-up resistor 0 = VBUS line is not charged through a resistor bit 0 VBUSDIS: VBUS Discharge Enable bit 1 = VBUS line is discharged through a pull-down resistor 0 = VBUS line is not discharged through a resistor 2014-2017 Microchip Technology Inc. DS60001290E-page 113 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 10-5: U1PWRC: USB POWER CONTROL REGISTER Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 U-0 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 UACTPND -- -- USLPGRD USBBUSY -- USUSPEND USBPWR Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 UACTPND: USB Activity Pending bit 1 = USB bus activity has been detected; but an interrupt is pending, it has not been generated yet 0 = An interrupt is not pending bit 6-5 Unimplemented: Read as `0' bit 4 USLPGRD: USB Sleep Entry Guard bit 1 = Sleep entry is blocked if USB bus activity is detected or if a notification is pending 0 = USB module does not block Sleep entry bit 3 USBBUSY: USB Module Busy bit(1) 1 = USB module is active or disabled, but not ready to be enabled 0 = USB module is not active and is ready to be enabled Note: When USBPWR = 0 and USBBUSY = 1, status from all other registers is invalid and writes to all USB module registers produce undefined results. bit 2 Unimplemented: Read as `0' bit 1 USUSPEND: USB Suspend Mode bit 1 = USB module is placed in Suspend mode (The 48 MHz USB clock will be gated off. The transceiver is placed in a low-power state.) 0 = USB module operates normally bit 0 USBPWR: USB Operation Enable bit 1 = USB module is turned on 0 = USB module is disabled (Outputs held inactive, device pins not used by USB, analog features are shut down to reduce power consumption.) DS60001290E-page 114 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 10-6: Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 U1IR: USB INTERRUPT REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit Bit 28/20/12/4 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 -- -- -- U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R-0 R/WC-0, HS (5) IDLEIF TRNIF(3) SOFIF UERRIF(4) STALLIF ATTACHIF(1) RESUMEIF(2) Legend: R = Readable bit -n = Value at POR WC = Write `1' to clear W = Writable bit `1' = Bit is set URSTIF DETACHIF(6) HS = Hardware Settable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 STALLIF: STALL Handshake Interrupt bit 1 = In Host mode, a STALL handshake was received during the handshake phase of the transaction In Device mode, a STALL handshake was transmitted during the handshake phase of the transaction 0 = STALL handshake has not been sent ATTACHIF: Peripheral Attach Interrupt bit(1) 1 = Peripheral attachment was detected by the USB module 0 = Peripheral attachment was not detected RESUMEIF: Resume Interrupt bit(2) 1 = K-State is observed on the D+ or D- pin for 2.5 s 0 = K-State is not observed IDLEIF: Idle Detect Interrupt bit 1 = Idle condition detected (constant Idle state of 3 ms or more) 0 = No Idle condition detected TRNIF: Token Processing Complete Interrupt bit(3) 1 = Processing of current token is complete; a read of the U1STAT register will provide endpoint information 0 = Processing of current token not complete SOFIF: SOF Token Interrupt bit 1 = SOF token received by the peripheral or the SOF threshold reached by the host 0 = SOF token was not received nor threshold reached UERRIF: USB Error Condition Interrupt bit(4) 1 = Unmasked error condition has occurred 0 = Unmasked error condition has not occurred URSTIF: USB Reset Interrupt bit (Device mode)(5) 1 = Valid USB Reset has occurred 0 = No USB Reset has occurred DETACHIF: USB Detach Interrupt bit (Host mode)(6) 1 = Peripheral detachment was detected by the USB module 0 = Peripheral detachment was not detected bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 Note 1: 2: 3: 4: 5: 6: This bit is valid only if the HOSTEN bit is set (see Register 10-11), there is no activity on the USB for 2.5 s, and the current bus state is not SE0. When not in Suspend mode, this interrupt should be disabled. Clearing this bit will cause the STAT FIFO to advance. Only error conditions enabled through the U1EIE register will set this bit. Device mode. Host mode. 2014-2017 Microchip Technology Inc. DS60001290E-page 115 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 10-7: Bit Range 31:24 23:16 15:8 7:0 U1IE: USB INTERRUPT ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STALLIE ATTACHIE RESUMEIE IDLEIE TRNIE SOFIE UERRIE(1) R/W-0 URSTIE(2) DETACHIE(3) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 STALLIE: STALL Handshake Interrupt Enable bit 1 = STALL interrupt enabled 0 = STALL interrupt disabled bit 6 ATTACHIE: ATTACH Interrupt Enable bit 1 = ATTACH interrupt enabled 0 = ATTACH interrupt disabled bit 5 RESUMEIE: RESUME Interrupt Enable bit 1 = RESUME interrupt enabled 0 = RESUME interrupt disabled bit 4 IDLEIE: Idle Detect Interrupt Enable bit 1 = Idle interrupt enabled 0 = Idle interrupt disabled bit 3 TRNIE: Token Processing Complete Interrupt Enable bit 1 = TRNIF interrupt enabled 0 = TRNIF interrupt disabled bit 2 SOFIE: SOF Token Interrupt Enable bit 1 = SOFIF interrupt enabled 0 = SOFIF interrupt disabled bit 1 UERRIE: USB Error Interrupt Enable bit(1) 1 = USB Error interrupt enabled 0 = USB Error interrupt disabled bit 0 URSTIE: USB Reset Interrupt Enable bit(2) 1 = URSTIF interrupt enabled 0 = URSTIF interrupt disabled DETACHIE: USB Detach Interrupt Enable bit(3) 1 = DATTCHIF interrupt enabled 0 = DATTCHIF interrupt disabled Note 1: 2: 3: For an interrupt to propagate USBIF, the UERRIE bit (U1IE<1>) must be set. Device mode. Host mode. DS60001290E-page 116 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 10-8: Bit Range 31:24 23:16 15:8 7:0 U1EIR: USB ERROR INTERRUPT STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS BTSEF BMXEF DMAEF(1) BTOEF(2) DFN8EF CRC16EF CRC5EF(4) EOFEF(3,5) Legend: WC = Write `1' to clear HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared PIDEF x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 BTSEF: Bit Stuff Error Flag bit 1 = Packet rejected due to bit stuff error 0 = Packet accepted bit 6 BMXEF: Bus Matrix Error Flag bit 1 = The base address, of the BDT, or the address of an individual buffer pointed to by a BDT entry, is invalid. 0 = No address error bit 5 DMAEF: DMA Error Flag bit(1) 1 = USB DMA error condition detected 0 = No DMA error bit 4 BTOEF: Bus Turnaround Time-Out Error Flag bit(2) 1 = Bus turnaround time-out has occurred 0 = No bus turnaround time-out bit 3 DFN8EF: Data Field Size Error Flag bit 1 = Data field received is not an integral number of bytes 0 = Data field received is an integral number of bytes bit 2 CRC16EF: CRC16 Failure Flag bit 1 = Data packet rejected due to CRC16 error 0 = Data packet accepted Note 1: 2: 3: 4: 5: This type of error occurs when the module's request for the DMA bus is not granted in time to service the module's demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer size is not sufficient to store the received data packet causing it to be truncated. This type of error occurs when more than 16-bit-times of Idle from the previous End-of-Packet (EOP) has elapsed. This type of error occurs when the module is transmitting or receiving data and the SOF counter has reached zero. Device mode. Host mode. 2014-2017 Microchip Technology Inc. DS60001290E-page 117 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 10-8: U1EIR: USB ERROR INTERRUPT STATUS REGISTER (CONTINUED) bit 1 CRC5EF: CRC5 Host Error Flag bit(4) 1 = Token packet rejected due to CRC5 error 0 = Token packet accepted EOFEF: EOF Error Flag bit(3,5) 1 = EOF error condition detected 0 = No EOF error condition bit 0 PIDEF: PID Check Failure Flag bit 1 = PID check failed 0 = PID check passed Note 1: 2: 3: 4: 5: This type of error occurs when the module's request for the DMA bus is not granted in time to service the module's demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer size is not sufficient to store the received data packet causing it to be truncated. This type of error occurs when more than 16-bit-times of Idle from the previous End-of-Packet (EOP) has elapsed. This type of error occurs when the module is transmitting or receiving data and the SOF counter has reached zero. Device mode. Host mode. DS60001290E-page 118 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 10-9: Bit Range 31:24 23:16 15:8 7:0 U1EIE: USB ERROR INTERRUPT ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BTSEE BMXEE DMAEE BTOEE DFN8EE CRC16EE CRC5EE(1) EOFEE(2) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared PIDEE x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit 1 = BTSEF interrupt enabled 0 = BTSEF interrupt disabled bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: Note: BMXEE: Bus Matrix Error Interrupt Enable bit 1 = BMXEF interrupt enabled 0 = BMXEF interrupt disabled DMAEE: DMA Error Interrupt Enable bit 1 = DMAEF interrupt enabled 0 = DMAEF interrupt disabled BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit 1 = BTOEF interrupt enabled 0 = BTOEF interrupt disabled DFN8EE: Data Field Size Error Interrupt Enable bit 1 = DFN8EF interrupt enabled 0 = DFN8EF interrupt disabled CRC16EE: CRC16 Failure Interrupt Enable bit 1 = CRC16EF interrupt enabled 0 = CRC16EF interrupt disabled CRC5EE: CRC5 Host Error Interrupt Enable bit(1) 1 = CRC5EF interrupt enabled 0 = CRC5EF interrupt disabled EOFEE: EOF Error Interrupt Enable bit(2) 1 = EOF interrupt enabled 0 = EOF interrupt disabled PIDEE: PID Check Failure Interrupt Enable bit 1 = PIDEF interrupt enabled 0 = PIDEF interrupt disabled Device mode. Host mode. For an interrupt to propagate USBIF, the UERRIE bit (U1IE<1>) must be set. 2014-2017 Microchip Technology Inc. DS60001290E-page 119 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 10-10: U1STAT: USB STATUS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-x R-x R-x R-x R-x R-x U-0 U-0 DIR PPBI -- -- ENDPT<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7-4 ENDPT<3:0>: Encoded Number of Last Endpoint Activity bits (Represents the number of the BDT, updated by the last USB transfer.) 1111 = Endpoint 15 1110 = Endpoint 14 * * * 0001 = Endpoint 1 0000 = Endpoint 0 bit 3 DIR: Last BD Direction Indicator bit 1 = Last transaction was a transmit transfer (TX) 0 = Last transaction was a receive transfer (RX) bit 2 PPBI: Ping-Pong BD Pointer Indicator bit 1 = The last transaction was to the ODD BD bank 0 = The last transaction was to the EVEN BD bank bit 1-0 Unimplemented: Read as `0' Note: The U1STAT register is a window into a 4-byte FIFO maintained by the USB module. U1STAT value is only valid when the TRNIF bit (U1IR<3>) is active. Clearing the TRNIF bit advances the FIFO. Data in register is invalid when the TRNIF bit = 0. DS60001290E-page 120 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 10-11: U1CON: USB CONTROL REGISTER Bit Bit Bit Range 31/23/15/7 30/22/14/6 31:24 23:16 15:8 7:0 U-0 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-x R-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 JSTATE SE0 PKTDIS(4) TOKBUSY(1,5) USBRST HOSTEN(2) RESUME(3) PPBRST USBEN(4) SOFEN(5) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 JSTATE: Live Differential Receiver JSTATE flag bit 1 = JSTATE detected on the USB 0 = No JSTATE detected bit 6 SE0: Live Single-Ended Zero flag bit 1 = Single Ended Zero detected on the USB 0 = No Single Ended Zero detected bit 5 PKTDIS: Packet Transfer Disable bit(4) 1 = Token and packet processing disabled (set upon SETUP token received) 0 = Token and packet processing enabled TOKBUSY: Token Busy Indicator bit(1,5) 1 = Token being executed by the USB module 0 = No token being executed bit 4 USBRST: Module Reset bit(5) 1 = USB reset generated 0 = USB reset terminated bit 3 HOSTEN: Host Mode Enable bit(2) 1 = USB host capability enabled 0 = USB host capability disabled bit 2 RESUME: RESUME Signaling Enable bit(3) 1 = RESUME signaling activated 0 = RESUME signaling disabled Note 1: 2: 3: 4: 5: Software is required to check this bit before issuing another token command to the U1TOK register (see Register 10-15). All host control logic is reset any time that the value of this bit is toggled. Software must set the RESUME bit for 10 ms if the part is a function, or for 25 ms if the part is a host, and then clear it to enable remote wake-up. In Host mode, the USB module will append a low-speed EOP to the RESUME signaling when this bit is cleared. Device mode. Host mode. 2014-2017 Microchip Technology Inc. DS60001290E-page 121 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 10-11: U1CON: USB CONTROL REGISTER (CONTINUED) bit 1 PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Even/Odd buffer pointers to the EVEN BD banks 0 = Even/Odd buffer pointers not being Reset bit 0 USBEN: USB Module Enable bit(4) 1 = USB module and supporting circuitry enabled 0 = USB module and supporting circuitry disabled SOFEN: SOF Enable bit(5) 1 = SOF token sent every 1 ms 0 = SOF token disabled Note 1: 2: 3: 4: 5: Software is required to check this bit before issuing another token command to the U1TOK register (see Register 10-15). All host control logic is reset any time that the value of this bit is toggled. Software must set the RESUME bit for 10 ms if the part is a function, or for 25 ms if the part is a host, and then clear it to enable remote wake-up. In Host mode, the USB module will append a low-speed EOP to the RESUME signaling when this bit is cleared. Device mode. Host mode. DS60001290E-page 122 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 10-12: U1ADDR: USB ADDRESS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LSPDEN DEVADDR<6:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 LSPDEN: Low Speed Enable Indicator bit 1 = Next token command to be executed at Low Speed 0 = Next token command to be executed at Full Speed bit 6-0 DEVADDR<6:0>: 7-bit USB Device Address bits REGISTER 10-13: U1FRML: USB FRAME NUMBER LOW REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 FRML<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7-0 FRML<7:0>: The 11-bit Frame Number Lower bits The register bits are updated with the current frame number whenever a SOF TOKEN is received. 2014-2017 Microchip Technology Inc. DS60001290E-page 123 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 10-14: U1FRMH: USB FRAME NUMBER HIGH REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 -- -- -- -- -- FRMH<2:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-3 Unimplemented: Read as `0' bit 2-0 FRMH<2:0>: The Upper 3 bits of the Frame Numbers bits The register bits are updated with the current frame number whenever a SOF TOKEN is received. REGISTER 10-15: U1TOK: USB TOKEN REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 (1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PID<3:0> EP<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7-4 PID<3:0>: Token Type Indicator bits(1) 0001 = OUT (TX) token type transaction 1001 = IN (RX) token type transaction 1101 = SETUP (TX) token type transaction Note: All other values are reserved and must not be used. bit 3-0 EP<3:0>: Token Command Endpoint Address bits The four bit value must specify a valid endpoint. Note 1: All other values are reserved and must not be used. DS60001290E-page 124 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 10-16: U1SOF: USB SOF THRESHOLD REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CNT<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7-0 CNT<7:0>: SOF Threshold Value bits Typical values of the threshold are: 01001010 = 64-byte packet 00101010 = 32-byte packet 00011010 =16-byte packet 00010010 =8-byte packet REGISTER 10-17: U1BDTP1: USB BDT PAGE 1 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 BDTPTRL<15:9> -- Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7-1 BDTPTRL<15:9>: BDT Base Address bits This 7-bit value provides address bits 15 through 9 of the BDT base address, which defines the starting location of the BDT in system memory. The 32-bit BDT base address is 512-byte aligned. bit 0 Unimplemented: Read as `0' 2014-2017 Microchip Technology Inc. DS60001290E-page 125 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 10-18: U1BDTP2: USB BDT PAGE 2 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BDTPTRH<23:16> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7-0 BDTPTRH<23:16>: BDT Base Address bits This 8-bit value provides address bits 23 through 16 of the BDT base address, which defines the starting location of the BDT in system memory. The 32-bit BDT base address is 512-byte aligned. REGISTER 10-19: U1BDTP3: USB BDT PAGE 3 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BDTPTRU<31:24> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7-0 BDTPTRU<31:24>: BDT Base Address bits This 8-bit value provides address bits 31 through 24 of the BDT base address, defines the starting location of the BDT in system memory. The 32-bit BDT base address is 512-byte aligned. DS60001290E-page 126 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 10-20: U1CNFG1: USB CONFIGURATION 1 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 UTEYE -- -- USBSIDL USBSIDL -- -- UASUSPND Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 UTEYE: USB Eye-Pattern Test Enable bit 1 = Eye-Pattern Test enabled 0 = Eye-Pattern Test disabled bit 6-5 Unimplemented: Read as `0' bit 4 USBSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 3 LSDEV: Low-Speed Device Enable bit 1 = USB module operates in Low-Speed Device mode only 0 = USB module operates in OTG, Host, or Full-Speed Device mode bit 2-1 Unimplemented: Read as `0' bit 0 UASUSPND: Automatic Suspend Enable bit 1 = USB module automatically suspends upon entry to Sleep mode. See the USUSPEND bit (U1PWRC<1>) in Register 10-5. 0 = USB module does not automatically suspend upon entry to Sleep mode. Software must use the USUSPEND bit (U1PWRC<1>) to suspend the module, including the USB 48 MHz clock 2014-2017 Microchip Technology Inc. DS60001290E-page 127 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 10-21: U1EP0-U1EP15: USB ENDPOINT CONTROL REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LSPD RETRYDIS -- EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 LSPD: Low-Speed Direct Connection Enable bit (Host mode and U1EP0 only) 1 = Direct connection to a low-speed device enabled 0 = Direct connection to a low-speed device disabled; hub required with PRE_PID bit 6 RETRYDIS: Retry Disable bit (Host mode and U1EP0 only) 1 = Retry NAKed transactions disabled 0 = Retry NAKed transactions enabled; retry done in hardware bit 5 Unimplemented: Read as `0' bit 4 EPCONDIS: Bidirectional Endpoint Control bit If EPTXEN = 1 and EPRXEN = 1: 1 = Disable Endpoint n from Control transfers; only TX and RX transfers allowed 0 = Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed Otherwise, this bit is ignored. bit 3 EPRXEN: Endpoint Receive Enable bit 1 = Endpoint n receive enabled 0 = Endpoint n receive disabled bit 2 EPTXEN: Endpoint Transmit Enable bit 1 = Endpoint n transmit enabled 0 = Endpoint n transmit disabled bit 1 EPSTALL: Endpoint Stall Status bit 1 = Endpoint n was stalled 0 = Endpoint n was not stalled bit 0 EPHSHK: Endpoint Handshake Enable bit 1 = Endpoint Handshake enabled 0 = Endpoint Handshake disabled (typically used for isochronous endpoints) DS60001290E-page 128 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 11.0 General purpose I/O pins are the simplest of peripherals. They allow the PIC(R) MCU to monitor and control other devices. To add flexibility and functionality, some pins are multiplexed with alternate functions. These functions depend on which peripheral features are on the device. In general, when a peripheral is functioning, that pin may not be used as a general purpose I/O pin. I/O PORTS Note: This data sheet summarizes the features of the PIC32MX1XX/2XX/5XX 64/100-pin family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 12. "I/O Ports" (DS60001120) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). FIGURE 11-1: The following are the key features of this module: * Individual output pin open-drain enable or disable * Individual input pin weak pull-up and pull-down * Monitor selective inputs and generate interrupt when change in pin state is detected * Operation during CPU Sleep and Idle modes * Fast bit manipulation using CLR, SET and INV registers Figure 11-1 illustrates a block diagram of a typical multiplexed I/O port. BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE Peripheral Module Peripheral Module Enable Peripheral Output Enable Peripheral Output Data PIO Module RD ODC Data Bus D SYSCLK Q ODC CK EN Q WR ODC 1 RD TRIS 0 I/O Cell 0 1 D Q 1 TRIS CK EN Q 0 WR TRIS Output Multiplexers D Q I/O Pin LAT CK EN Q WR LAT WR PORT RD LAT 1 RD PORT 0 Sleep Q Q D CK Q Q D CK SYSCLK Synchronization Peripheral Input Legend: Note: R Peripheral Input Buffer R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details. This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure for any specific port/peripheral combination may be different than shown here. 2014-2017 Microchip Technology Inc. DS60001290E-page 129 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 11.1 Parallel I/O (PIO) Ports All port pins have ten registers directly associated with their operation as digital I/O. The data direction register (TRISx) determines whether the pin is an input or an output. If the data direction bit is a `1', then the pin is an input. All port pins are defined as inputs after a Reset. Reads from the latch (LATx) read the latch. Writes to the latch write the latch. Reads from the port (PORTx) read the port pins, while writes to the port pins write the latch. 11.1.1 OPEN-DRAIN CONFIGURATION In addition to the PORTx, LATx, and TRISx registers for data control, some port pins can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin, regardless of the output function including PPS remapped output functions to act as an open-drain output. The only exception is the I2C pins that are open drain by default. The open-drain feature allows the presence of outputs higher than VDD (e.g., 5V) on any desired 5V-tolerant pins by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification. See the "Device Pin Tables" section for the available pins and their functionality. 11.1.2 CONFIGURING ANALOG AND DIGITAL PORT PINS The ANSELx register controls the operation of the analog port pins. The port pins that are to function as analog inputs must have their corresponding ANSEL and TRIS bits set. In order to use port pins for I/O functionality with digital modules, such as Timers, UARTs, etc., the corresponding ANSELx bit must be cleared. The ANSELx register has a default value of 0xFFFF; therefore, all pins that share analog functions are analog (not digital) by default. The ANSELx register bit, when cleared, disables the corresponding digital input buffer pin(s). If the TRIS bit is cleared (output) while the ANSELx bit is set, the digital output level (VOH or VOL) is converted by an analog peripheral, such as the ADC module or Comparator module. The TRISx bits only control the corresponding digital output buffer pin(s). When the PORT register is read, all pins configured as analog input channels are read as cleared (a low level; i.e., when ANSELx = 1; TRISx = x). Analog levels on any pin defined as a digital input (including the ANx pins) can cause the input buffer to consume current that exceeds the device specifications. DS60001290E-page 130 11.1.3 I/O PORT WRITE/READ TIMING One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically, this instruction would be an NOP. 11.1.4 INPUT CHANGE NOTIFICATION The input Change Notification (CN) function of the I/O ports allows the PIC32MX1XX/2XX/5XX 64/100-pin devices to generate interrupt requests to the processor in response to a change-of-state on selected input pins. This feature can detect input change-of-states even in Sleep mode, when the clocks are disabled. Every I/O port pin can be selected (enabled) for generating an interrupt request on a change-of-state. Five control registers are associated with the CN functionality of each I/O port. The CNENx registers contain the CN interrupt enable control bits for each of the input pins. Setting any of these bits enables a CN interrupt for the corresponding pins. The CNSTATx register indicates whether a change occurred on the corresponding pin since the last read of the PORTx bit. 11.1.5 INTERNALLY SELECTABLE PULLUPS AND PULL-DOWNS Each I/O pin also has a weak pull-up and every I/O pin has a weak pull-down connected to it, which are independent of any other I/O pin functionality (i.e., PPS, Open Drain, or CN). The pull-ups act as a current source or sink source connected to the pin, and eliminate the need for external resistors when push-button or keypad devices are connected. The pull-ups and pull-downs are enabled separately using the CNPUx and the CNPDx registers, which contain the control bits for each of the pins. Setting any of the control bits enables the weak pull-ups and/or pulldowns for the corresponding pins. Note: Pull-ups and pull-downs on change notification pins should always be disabled when the port pin is configured as a digital output. They should also be disabled on 5V tolerant pins when the pin voltage can exceed VDD. An additional control register (CNCONx) is shown in Register 11-3. 11.2 CLR, SET, and INV Registers Every I/O module register has a corresponding CLR (clear), SET (set) and INV (invert) register designed to provide fast atomic bit manipulations. As the name of the register implies, a value written to a SET, CLR or INV register effectively performs the implied operation, but only on the corresponding base register and only bits specified as `1' are modified. Bits specified as `0' are not modified. Reading SET, CLR and INV registers returns undefined values. To see the affects of a write operation to a SET, CLR or INV register, the base register must be read. 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 11.3 Peripheral Pin Select A major challenge in general purpose devices is providing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins. The challenge is even greater on low pin count devices. In an application where more than one peripheral needs to be assigned to a single pin, inconvenient workarounds in application code or a complete redesign may be the only options. Peripheral pin select configuration provides an alternative to these choices by enabling peripheral set selection and their placement on a wide range of I/O pins. By increasing the pinout options available on a particular device, users can better tailor the device to their entire application, rather than trimming the application to fit the device. The peripheral pin select configuration feature operates over a fixed subset of digital I/O pins. Users may independently map the input and/or output of most digital peripherals to these I/O pins. Peripheral pin select is performed in software and generally does not require the device to be reprogrammed. Hardware safeguards are included that prevent accidental or spurious changes to the peripheral mapping once it has been established. 11.3.1 AVAILABLE PINS The number of available pins is dependent on the particular device and its pin count. Pins that support the peripheral pin select feature include the designation "RPn" in their full pin designation, where "RP" designates a remappable peripheral and "n" is the remappable port number. 11.3.2 AVAILABLE PERIPHERALS The peripherals managed by the peripheral pin select are all digital-only peripherals. These include general serial communications (UART and SPI), general purpose timer clock inputs, timer-related peripherals (input capture and output compare) and interrupt-on-change inputs. When a remappable peripheral is active on a given I/O pin, it takes priority over all other digital I/O and digital communication peripherals associated with the pin. Priority is given regardless of the type of peripheral that is mapped. Remappable peripherals never take priority over any analog functions associated with the pin. 11.3.3 Peripheral pin select features are controlled through two sets of SFRs: one to map peripheral inputs, and one to map outputs. Because they are separately controlled, a particular peripheral's input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. The association of a peripheral to a peripheral-selectable pin is handled in two different ways, depending on whether an input or output is being mapped. 11.3.4 INPUT MAPPING The inputs of the peripheral pin select options are mapped on the basis of the peripheral. That is, a control register associated with a peripheral dictates the pin it will be mapped to. The [pin name]R registers, where [pin name] refers to the peripheral pins listed in Table 11-1, are used to configure peripheral input mapping (see Register 11-1). Each register contains sets of 4 bit fields. Programming these bit fields with an appropriate value maps the RPn pin with the corresponding value to that peripheral. For any given device, the valid range of values for any bit field is shown in Table 11-1. For example, Figure 11-2 illustrates the remappable pin selection for the U1RX input. FIGURE 11-2: REMAPPABLE INPUT EXAMPLE FOR U1RX U1RXR<3:0> 0 RPA2 1 In comparison, some digital-only peripheral modules are never included in the peripheral pin select feature. This is because the peripheral's function requires special I/O circuitry on a specific port and cannot be easily connected to multiple pins. These modules include I2C among others. A similar requirement excludes all modules with analog inputs, such as the Analog-to-Digital Converter (ADC). RPB6 A key difference between remappable and non-remappable peripherals is that remappable peripherals are not associated with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be used. In contrast, non-remappable peripherals are always available on a default pin, assuming that the peripheral is active and not conflicting with another peripheral. RPn 2014-2017 Microchip Technology Inc. CONTROLLING PERIPHERAL PIN SELECT 2 RPA4 U1RX input to peripheral n Note: For input only, peripheral pin select functionality does not have priority over TRISx settings. Therefore, when configuring RPn pin for input, the corresponding bit in the TRISx register must also be configured for input (set to `1'). DS60001290E-page 131 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 11-1: INPUT PIN SELECTION [pin name]R Value to RPn Pin Selection Peripheral Pin [pin name]R SFR [pin name]R bits INT3 INT3R INT3R<3:0> T2CK T2CKR T2CKR<3:0> IC3 IC3R IC3R<3:0> U1RX U1RXR U1RXR<3:0> U2RX U2RXR U2RXR<3:0> U5CTS(3) U5CTSR U5CTSR<3:0> SDI3 SDI3R SDI3R<3:0> SDI4(3) SDI4R SDI4R<3:0> REFCLKI REFCLKIR REFCLKIR<3:0> INT4 INT4R INT4R<3:0> T5CK T5CKR T5CKR<3:0> IC4 IC4R IC4R<3:0> U3RX U3RXR U3RXR<3:0> U4CTS U4CTSR U4CTSR<3:0> SDI1 SDI1R SDI1R<3:0> SDI2 SDI2R SDI2R<3:0> C1RX(5) C1RXR(5) C1RXR<3:0>(5) INT2 INT2R INT2R<3:0> T4CK T4CKR T4CKR<3:0> IC2 IC2R IC2R<3:0> IC5 IC5R IC5R<3:0> U1CTS U1CTSR U1CTSR<3:0> U2CTS U2CTSR U2CTSR<3:0> SS1 SS1R SS1R<3:0> SS3 SS3R SS1R<3:0> SS4(3) SS3R SS3R<3:0> Note 1: 2: 3: 4: 5: 6: 7: 0000 = RPD2 0001 = RPG8 0010 = RPF4 0011 = RPD10 0100 = RPF1 0101 = RPB9 0110 = RPB10 0111 = RPC14 1000 = RPB5(7) 1001 = Reserved 1010 = RPC1(3) 1011 = RPD14(3) 1100 = RPG1(3) 1101 = RPA14(3) 1110 = Reserved 1111 = RPF2(1) 0000 = RPD3 0001 = RPG7 0010 = RPF5 0011 = RPD11 0100 = RPF0 0101 = RPB1 0110 = RPE5 0111 = RPC13 1000 = RPB3 1001 = RPF12(3) 1010 = RPC4(3) 1011 = RPD15(3) 1100 = RPG0(3) 1101 = RPA15(3) 1110 = RPF2(1) 1111 = RPF7(2) 0000 = RPD9 0001 = RPG6 0010 = RPB8 0011 = RPB15 0100 = RPD4 0101 = RPB0 0110 = RPE3 0111 = RPB7 1000 = Reserved 1001 = RPF12(3) 1010 = RPD12(3) 1011 = RPF8(3) 1100 = RPC3(3) 1101 = RPE9(3) 1110 = RPD14(3) 1111 = RPB2 This selection is not available on 64-pin USB devices. This selection is only available on 100-pin General Purpose devices. This selection is not available on 64-pin devices. This selection is not available when USBID functionality is used on USB devices. This selection is not available on devices without a CAN module. This selection is not available on USB devices. This selection is not available when VBUSON functionality is used on USB devices. DS60001290E-page 132 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 11-1: INPUT PIN SELECTION (CONTINUED) Peripheral Pin [pin name]R SFR [pin name]R bits INT1 INT1R INT1R<3:0> T3CK T3CKR T3CKR<3:0> IC1 IC1R IC1R<3:0> U3CTS U3CTSR U3CTSR<3:0> U4RX U4RXR U4RXR<3:0> U5RX U5RXR U5RXR<3:0> SS2 SS2R SS2R<3:0> OCFA OCFAR OCFAR<3:0> Note 1: 2: 3: 4: 5: 6: 7: [pin name]R Value to RPn Pin Selection 0000 = RPD1 0001 = RPG9 0010 = RPB14 0011 = RPD0 0100 = RPD8 0101 = RPB6 0110 = RPD5 0111 = RPB2 1000 = RPF3(4) 1001 = RPF13(3) 1010 = Reserved 1011 = RPF2(1) 1100 = RPC2(3) 1101 = RPE8(3) 1110 = Reserved 1111 = Reserved This selection is not available on 64-pin USB devices. This selection is only available on 100-pin General Purpose devices. This selection is not available on 64-pin devices. This selection is not available when USBID functionality is used on USB devices. This selection is not available on devices without a CAN module. This selection is not available on USB devices. This selection is not available when VBUSON functionality is used on USB devices. 2014-2017 Microchip Technology Inc. DS60001290E-page 133 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 11.3.5 OUTPUT MAPPING 11.3.6.1 In contrast to inputs, the outputs of the peripheral pin select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPnR registers (Register 11-2) are used to control output mapping. Like the [pin name]R registers, each register contains sets of 4 bit fields. The value of the bit field corresponds to one of the peripherals, and that peripheral's output is mapped to the pin (see Table 11-2 and Figure 11-3). A null output is associated with the output register reset value of `0'. This is done to ensure that remappable outputs remain disconnected from all output pins by default. FIGURE 11-3: EXAMPLE OF MULTIPLEXING OF REMAPPABLE OUTPUT FOR RPA0 RPA0R<3:0> Default U1TX Output U1RTS Output 0 1 2 RPA0 Control Register Lock Under normal operation, writes to the RPnR and [pin name]R registers are not allowed. Attempted writes appear to execute normally, but the contents of the registers remain unchanged. To change these registers, they must be unlocked in hardware. The register lock is controlled by the IOLOCK Configuration bit (CFGCON<13>). Setting IOLOCK prevents writes to the control registers; clearing IOLOCK allows writes. To set or clear the IOLOCK bit, an unlock sequence must be executed. Refer to Section 6. "Oscillator" (DS60001112) in the "PIC32 Family Reference Manual" for details. 11.3.6.2 Configuration Bit Select Lock As an additional level of safety, the device can be configured to prevent more than one write session to the RPnR and [pin name]R registers. The IOL1WAY Configuration bit (DEVCFG3<29>) blocks the IOLOCK bit from being cleared after it has been set once. If IOLOCK remains set, the register unlock procedure does not execute, and the peripheral pin select control registers cannot be written to. The only way to clear the bit and re-enable peripheral remapping is to perform a device Reset. In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. Output Data 14 15 11.3.6 CONTROLLING CONFIGURATION CHANGES Because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. PIC32 devices include two features to prevent alterations to the peripheral map: * Control register lock sequence * Configuration bit select lock DS60001290E-page 134 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 11-2: OUTPUT PIN SELECTION RPn Port Pin RPnR SFR RPnR bits RPD2 RPD2R RPD2R<3:0> RPG8 RPG8R RPG8R<3:0> RPF4 RPF4R RPF4R<3:0> RPD10 RPD10R RPD10R<3:0> RPF1 RPF1R RPF1R<3:0> RPB9 RPB9R RPB9R<3:0> RPB10 RPB10R RPB10R<3:0> RPC14 RPC14R RPC14R<3:0> RPB5(7) RPB5R RPB5R<3:0> RPC1(3) RPC1R RPC1R<3:0> RPD14(3) RPD14R RPD14R<3:0> RPG1(3) RPG1R RPG1R<3:0> RPA14(3) RPA14R RPA14R<3:0> RPD3 RPD3R RPD3R<3:0> RPG7 RPG7R RPG7R<3:0> RPF5 RPF5R RPF5R<3:0> RPD11 RPD11R RPD11R<3:0> RPF0 RPF0R RPF0R<3:0> RPB1 RPB1R RPB1R<3:0> RPE5 RPE5R RPE5R<3:0> RPC13 RPC13R RPC13R<3:0> RPB3 RPB3R RPB3R<3:0> RPF3(4) RPF3R RPF3R<3:0> RPC4(3) RPC4R RPC4R<3:0> RPD15(3) RPD15R RPD15R<3:0> RPG0(3) RPG0R RPG0R<3:0> (3) RPA15R RPA15R<3:0> RPA15 Note 1: 2: 3: 4: 5: 6: 7: RPnR Value to Peripheral Selection 0000 = No Connect 0001 = U3TX 0010 = U4RTS 0011 = Reserved 0100 = Reserved 0101 = Reserved 0110 = SDO2 0111 = Reserved 1000 = Reserved 1001 = Reserved 1010 = Reserved 1011 = OC3 1100 = C1TX(5) 1101 = C2OUT 1110 = SDO3 1111 = SDO4(3) 0000 = No Connect 0001 = U2TX 0010 = Reserved 0011 = U1TX 0100 = U5RTS(3) 0101 = Reserved 0110 = SDO2 0111 = Reserved 1000 = SDO1 1001 = Reserved 1010 = Reserved 1011 = OC4 1100 = Reserved 1101 = C3OUT 1110 = SDO3 1111 = SDO4(3) This selection is not available on 64-pin USB devices. This selection is only available on 100-pin General Purpose devices. This selection is not available on 64-pin devices. This selection is not available when USBID functionality is used on USB devices. This selection is not available on devices without a CAN module. This selection is not available on USB devices. This selection is not available when VBUSON functionality is used on USB devices. 2014-2017 Microchip Technology Inc. DS60001290E-page 135 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 11-2: OUTPUT PIN SELECTION (CONTINUED) RPn Port Pin RPnR SFR RPnR bits RPD9 RPD9R RPD9R<3:0> RPG6 RPG6R RPG6R<3:0> RPB8 RPB8R RPB8R<3:0> RPB15 RPB15R RPB15R<3:0> RPD4 RPD4R RPD4R<3:0> RPB0 RPB0R RPB0R<3:0> RPE3 RPE3R RPE3R<3:0> RPB7 RPB7R RPB7R<3:0> RPB2 RPB2R RPB2R<3:0> RPF12(3) RPF12R RPF12R<3:0> RPD12(3) RPD12R RPD12R<3:0> RPF8(3) RPF8R RPF8R<3:0> RPC3(3) RPC3R RPC3R<3:0> RPE9(3) RPE9R RPE9R<3:0> RPD1 RPD1R RPD1R<3:0> RPG9 RPG9R RPG9R<3:0> RPB14 RPB14R RPB14R<3:0> RPD0 RPD0R RPD0R<3:0> RPD8 RPD8R RPD8R<3:0> RPB6 RPB6R RPB6R<3:0> RPD5 RPD5R RPD5R<3:0> RPF3(1) RPF3R RPF3R<3:0> RPF6(2) RPF6R RPF6R<3:0> RPF13(3) RPF13R RPF13R<3:0> RPC2(3) RPC2R RPC2R<3:0> (3) RPE8R RPE8R<3:0> RPF2(1) RPF2R RPF2R<3:0> RPE8 Note 1: 2: 3: 4: 5: 6: 7: RPnR Value to Peripheral Selection 0000 = No Connect 0001 = U3RTS 0010 = U4TX 0011 = REFCLKO 0100 = U5TX(3) 0101 = Reserved 0110 = Reserved 0111 = SS1 1000 = SDO1 1001 = Reserved 1010 = Reserved 1011 = OC5 1100 = Reserved 1101 = C1OUT 1110 = SS3 1111 = SS4(3) 0000 = No Connect 0001 = U2RTS 0010 = Reserved 0011 = U1RTS 0100 = U5TX(3) 0101 = Reserved 0110 = SS2 0111 = Reserved 1000 = SDO1 1001 = Reserved 1010 = Reserved 1011 = OC2 1100 = OC1 1101 = Reserved 1110 = Reserved 1111 = Reserved This selection is not available on 64-pin USB devices. This selection is only available on 100-pin General Purpose devices. This selection is not available on 64-pin devices. This selection is not available when USBID functionality is used on USB devices. This selection is not available on devices without a CAN module. This selection is not available on USB devices. This selection is not available when VBUSON functionality is used on USB devices. DS60001290E-page 136 2014-2017 Microchip Technology Inc. Control Registers ANSELA 6010 6020 6030 6040 TRISA PORTA LATA ODCA 6050 CNPUA 6060 CNPDA 6070 CNCONA 6080 CNENA Legend: Note 1: 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- 0060 -- -- -- -- -- -- -- -- -- -- 0000 TRISA10 TRISA9 -- TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 C6FF 31/15 30/14 29/13 28/12 27/11 31:16 -- -- -- -- -- 15:0 -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- 15:0 TRISA15 TRISA14 ANSELA10 ANSELA9 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 RA15 RA14 -- -- -- RA10 RA9 -- RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 LATA15 LATA14 -- -- -- LATA10 LATA9 -- LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- ODCA10 ODCA9 -- ODCA7 ODCA6 ODCA5 ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 CNPUA15 CNPUA14 -- -- -- 31:16 -- -- -- -- -- -- 15:0 31:16 ODCA15 ODCA14 -- -- -- -- 15:0 CNPDA15 CNPDA14 CNPUA10 CNPUA9 -- -- CNPDA10 CNPDA9 -- -- -- CNPUA7 CNPUA6 CNPUA5 CNPUA4 CNPUA3 CNPUA2 CNPUA1 CNPUA0 0000 -- -- -- -- -- -- -- -- 0000 CNPDA7 CNPDA6 CNPDA5 CNPDA4 CNPDA3 CNPDA2 CNPDA1 CNPDA0 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ON -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- CNIEA10 CNIEA9 -- CNIEA7 CNIEA6 CNIEA5 CNIEA4 CNIEA3 CNIEA2 CNIEA1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- CN STATA10 CN STATA9 -- CN STATA7 CN STATA6 CN STATA5 CN STATA4 CN STATA3 CN STATA2 CN STATA1 CN STATA0 0000 15:0 31:16 6090 CNSTATA Bits All Resets Register Name(1) 6000 PORTA REGISTER MAP 100-PIN DEVICES ONLY Bit Range Virtual Address (BF88_#) TABLE 11-3: 15:0 CNIEA15 CNIEA14 -- -- CN CN STATA15 STATA14 -- -- CNIEA0 0000 x = Unknown value on Reset; -- = Unimplemented, read as `0'; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. DS60001290E-page 137 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 2014-2017 Microchip Technology Inc. 11.4 Virtual Address (BF88_#) 6110 TRISB 6120 PORTB 6130 LATB 6140 ODCB 6150 CNPUB 6160 CNPDB 6170 CNCONB CNENB 6190 CNSTATB Legend: Note 1: 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Register Name(1) Bits 6100 ANSELB 6180 PORTB REGISTER MAP -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ANSELB15 ANSELB14 ANSELB13 ANSELB12 ANSELB11 ANSELB10 ANSELB9 ANSELB8 ANSELB7 ANSELB6 ANSELB5 ANSELB4 ANSELB3 ANSELB2 ANSELB1 ANSELB0 FFFF 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 TRISB15 31:16 -- TRISB14 -- TRISB13 -- TRISB12 -- TRISB11 -- TRISB10 -- TRISB9 -- TRISB8 -- TRISB7 -- TRISB6 -- TRISB5 -- TRISB4 -- TRISB3 -- TRISB2 -- TRISB1 -- TRISB0 -- FFFF 0000 15:0 31:16 RB15 -- RB14 -- RB13 -- RB12 -- RB11 -- RB10 -- RB9 -- RB8 -- RB7 -- RB6 -- RB5 -- RB4 -- RB3 -- RB2 -- RB1 -- RB0 -- xxxx 0000 15:0 31:16 LATB15 -- LATB14 -- LATB13 -- LATB12 -- LATB11 -- LATB10 -- LATB9 -- LATB8 -- LATB7 -- LATB6 -- LATB5 -- LATB4 -- LATB3 -- LATB2 -- LATB1 -- LATB0 -- xxxx 0000 15:0 ODCB15 31:16 -- ODCB14 -- ODCB13 -- ODCB12 -- ODCB11 -- ODCB10 -- ODCB9 -- ODCB8 -- ODCB7 -- ODCB6 -- ODCB5 -- ODCB4 -- ODCB3 -- ODCB2 -- ODCB1 -- ODCB0 -- 0000 0000 15:0 CNPUB15 CNPUB14 CNPUB13 CNPUB12 CNPUB11 CNPUB10 CNPUB9 CNPUB8 CNPUB7 CNPUB6 CNPUB5 31:16 -- -- -- -- -- -- -- -- -- -- -- CNPUB4 -- CNPUB3 CNPUB2 CNPUB1 CNPUB0 0000 -- -- -- -- 0000 15:0 CNPDB15 CNPDB14 CNPDB13 CNPDB12 CNPDB11 CNPDB10 CNPDB9 CNPDB8 CNPDB7 CNPDB6 CNPDB5 31:16 -- -- -- -- -- -- -- -- -- -- -- CNPDB4 -- CNPDB3 CNPDB2 CNPDB1 CNPDB0 0000 -- -- -- -- 0000 15:0 31:16 ON -- 15:0 CNIEB15 31:16 -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CNIEB14 -- CNIEB13 -- CNIEB12 -- CNIEB11 -- CNIEB10 -- CNIEB9 -- CNIEB8 -- CNIEB7 -- CNIEB6 -- CNIEB5 -- CNIEB4 -- CNIEB3 -- CNIEB2 -- CNIEB1 -- -- -- 0000 0000 CNIEB0 0000 -- 0000 CN CN CN CN CN CN CN CN CN CN CN CN CN CN CN CN 0000 STATB15 STATB14 STATB13 STATB12 STATB11 STATB10 STATB9 STATB8 STATB7 STATB6 STATB5 STATB4 STATB3 STATB2 STATB1 STATB0 x = Unknown value on Reset; -- = Unimplemented, read as `0'; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. 15:0 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 138 TABLE 11-4: Virtual Address (BF88_#) Register Name(1) Bit Range PORTC REGISTER MAP FOR 100-PIN DEVICES ONLY 6200 ANSELC 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ANSELC3 -- ANSELC2 -- ANSELC1 -- -- 0000 000E 6210 TRISC 31:16 15:0 -- TRISC15 -- TRISC14 -- TRISC13 -- TRISC12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRISC4 -- TRISC3 -- TRISC2 -- TRISC1 -- -- 0000 FFFF 6220 PORTC 31:16 15:0 -- RC15 -- RC14 -- RC13 -- RC12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RC4 -- RC3 -- RC2 -- RC1 -- -- 0000 xxxx 6230 LATC 31:16 15:0 -- LATC15 -- LATC14 -- LATC13 -- LATC12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- LATC4 -- LATC3 -- LATC2 -- LATC1 -- -- 0000 xxxx 6240 ODCC 31:16 15:0 -- ODCC15 -- ODCC14 -- ODCC13 -- ODCC12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ODCC4 -- ODCC3 -- ODCC2 -- ODCC1 -- -- 0000 0000 6250 CNPUC 31:16 15:0 -- CNPUC15 -- CNPUC14 -- CNPUC13 -- CNPUC12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CNPUC4 -- CNPUC3 -- CNPUC2 -- CNPUC1 -- -- 0000 0000 6260 CNPDC 31:16 15:0 -- CNPDC15 -- CNPDC14 -- CNPDC13 -- CNPDC12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CNPDC4 -- CNPDC3 -- CNPDC2 -- CNPDC1 -- -- 0000 0000 6270 CNCONC 31:16 15:0 -- ON -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 6280 31:16 15:0 -- CNIEC15 -- CNIEC14 CNIEC13 -- CNIEC12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CNIEC4 -- CNIEC3 -- CNIEC2 -- CNIEC1 -- -- 0000 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 CNENC 6290 CNSTATC Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bits 31:16 -- -- -- -- 15:0 CNSTATC15 CNSTATC14 CNSTATC13 CNSTATC12 -- -- -- -- CNSTATC4 CNSTATC3 CNSTATC2 CNSTATC1 x = Unknown value on Reset; -- = Unimplemented, read as `0'; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. DS60001290E-page 139 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 2014-2017 Microchip Technology Inc. TABLE 11-5: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 -- -- 0000 000E 6200 ANSELC 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 6210 TRISC 31:16 15:0 -- TRISC15 -- TRISC14 -- TRISC13 -- TRISC12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 F000 6220 PORTC 31:16 15:0 -- RC15 -- RC14 -- RC13 -- RC12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 xxxx 6230 LATC 31:16 15:0 -- LATC15 -- LATC14 -- LATC13 -- LATC12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 xxxx 6240 ODCC 31:16 15:0 -- ODCC15 -- ODCC14 -- ODCC13 -- ODCC12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 6250 CNPUC 31:16 15:0 -- CNPUC15 -- CNPUC14 -- CNPUC13 -- CNPUC12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 6260 CNPDC 31:16 15:0 -- CNPDC15 -- CNPDC14 -- CNPDC13 -- CNPDC12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 6270 CNCONC 31:16 15:0 -- ON -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 6280 31:16 15:0 -- CNIEC15 -- CNIEC14 CNIEC13 -- CNIEC12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 CNENC 6290 CNSTATC Legend: Note 1: 31:16 -- -- -- -- 15:0 CNSTATC15 CNSTATC14 CNSTATC13 CNSTATC12 -- -- -- ANSELC3 ANSELC2 ANSELC1 16/0 All Resets Bit Range Bits Register Name(1) Virtual Address (BF88_#) PORTC REGISTER MAP FOR 64-PIN DEVICES ONLY x = Unknown value on Reset; -- = Unimplemented, read as `0'; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 140 TABLE 11-6: Virtual Address (BF88_#) Register Name(1) PORTD REGISTER MAP FOR 100-PIN DEVICES ONLY 6300 ANSELD 6310 TRISD 31:16 -- 15:0 TRISD15 5320 PORTD 31:16 15:0 6330 LATD 31:16 15:0 6340 31/15 30/14 29/13 28/12 31:16 -- -- -- -- 15:0 ANSELD15 ANSELD14 ANSELD13 ANSELD12 27/11 26/10 25/9 24/8 -- -- -- -- -- -- -- -- 23/7 22/6 -- -- ANSELD7 ANSELD6 21/5 20/4 -- -- -- -- 19/3 18/2 17/1 -- -- -- ANSELD3 ANSELD2 ANSELD1 16/0 All Resets Bit Range Bits -- -- 0000 F0CE -- TRISD14 -- TRISD13 -- TRISD12 -- TRISD11 -- TRISD10 -- TRISD9 -- TRISD8 -- TRISD7 -- TRISD6 -- TRISD5 -- TRISD4 -- TRISD3 -- TRISD2 -- TRISD1 -- RD15 -- RD14 -- RD13 -- RD12 -- RD11 -- RD10 -- RD9 -- RD8 -- RD7 -- RD6 -- RD5 -- RD4 -- RD3 -- RD2 -- RD1 -- RD0 0000 xxxx -- LATD15 -- LATD14 -- LATD13 -- LATD12 -- LATD11 -- LATD10 -- LATD9 -- LATD8 -- LATD7 -- LATD6 -- LATD5 -- LATD4 -- LATD3 -- LATD2 -- LATD1 -- LATD0 0000 xxxx ODCD 31:16 -- 15:0 ODCD15 -- ODCD14 -- ODCD13 -- ODCD12 -- ODCD11 -- ODCD10 -- ODCD9 -- ODCD8 -- ODCD7 -- ODCD6 -- ODCD5 -- ODCD4 -- ODCD3 -- ODCD2 -- ODCD1 -- ODCD0 0000 0000 6350 CNPUD 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 CNPUD15 CNPUD14 CNPUD13 CNPUD12 CNPUD11 CNPUD10 CNPUD9 CNPUD8 CNPUD7 CNPUD6 CNPUD5 CNPUD4 CNPUD3 CNPUD2 CNPUD1 CNPUD0 0000 6360 CNPDD 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 CNPDD15 CNPDD14 CNPDD13 CNPDD12 CNPDD11 CNPDD10 CNPDD9 CNPDD8 CNPDD7 CNPDD6 CNPDD5 CNPDD4 CNPDD3 CNPDD2 CNPDD1 CNPDD0 0000 6370 CNCOND 31:16 15:0 6380 31:16 -- 15:0 CNIED15 CNEND 31:16 -- -- -- SIDL -- -- -- -- -- CNIED14 -- CNIED13 -- CNIED12 -- CNIED11 -- -- -- -- -- -- -- -- -- CNIED10 CNIED9 CNIED8 -- -- -- CNIED7 -- -- -- -- -- -- -- -- -- CNIED6 CNIED5 CNIED4 -- -- -- -- -- -- -- CNIED3 -- CNIED2 -- CNIED1 -- -- 0000 0000 -- 0000 CNIED0 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 CNS CN CN CN CN CN CN CN CN CN CN CN CN CN CN CN 0000 TATD15 STATD14 STATD13 STATD12 STATD11 STATD10 STATD9 STATD8 STATD7 STATD6 STATD5 STATD4 STATD3 STATD2 STATD1 STATD0 x = Unknown value on Reset; -- = Unimplemented, read as `0'; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. 6390 CNSTATD Legend: Note 1: -- ON -- 0000 TRISD0 FFFF 15:0 DS60001290E-page 141 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 2014-2017 Microchip Technology Inc. TABLE 11-7: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 -- -- 0000 000E 6300 ANSELD 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 6310 TRISD 31:16 15:0 -- -- -- -- -- -- -- -- -- TRISD11 -- TRISD10 -- TRISD9 -- TRISD8 -- TRISD7 -- TRISD6 -- TRISD5 -- TRISD4 -- TRISD3 -- TRISD2 -- TRISD1 -- TRISD0 0000 0FFF 5320 PORTD 31:16 15:0 -- -- -- -- -- -- -- -- -- RD11 -- RD10 -- RD9 -- RD8 -- RD7 -- RD6 -- RD5 -- RD4 -- RD3 -- RD2 -- RD1 -- RD0 0000 xxxx 6330 LATD 31:16 15:0 -- -- -- -- -- -- -- -- -- LATD11 -- LATD10 -- LATD9 -- LATD8 -- LATD7 -- LATD6 -- LATD5 -- LATD4 -- LATD3 -- LATD2 -- LATD1 -- LATD0 0000 xxxx 6340 ODCD 31:16 15:0 -- -- -- -- -- -- -- -- -- ODCD11 -- ODCD10 -- ODCD9 -- ODCD8 -- ODCD7 -- ODCD6 -- ODCD5 -- ODCD4 -- ODCD3 -- ODCD2 -- ODCD1 -- ODCD0 0000 0000 6350 CNPUD 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 CNPUD11 CNPUD10 CNPUD9 CNPUD8 CNPUD7 CNPUD6 CNPUD5 CNPUD4 CNPUD3 CNPUD2 CNPUD1 CNPUD0 0000 6360 CNPDD 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 CNPDD11 CNPDD10 CNPDD9 CNPDD8 CNPDD7 CNPDD6 CNPDD5 CNPDD4 CNPDD3 CNPDD2 CNPDD1 CNPDD0 0000 6370 CNCOND 31:16 15:0 -- ON -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 6380 31:16 15:0 -- -- -- -- -- -- -- -- -- CNIED11 -- CNIED10 -- CNIED9 -- CNIED8 -- CNIED7 -- CNIED6 -- CNIED5 -- CNIED4 -- CNIED3 -- CNIED2 -- CNIED1 -- CNIED0 0000 0000 31:16 -- -- -- -- CNEND -- -- -- -- -- -- -- -- -- -- -- -- 0000 CN CN CN CN CN CN CN CN CN CN CN CN 15:0 -- -- -- -- 0000 STATD11 STATD10 STATD9 STATD8 STATD7 STATD6 STATD5 STATD4 STATD3 STATD2 STATD1 STATD0 x = Unknown value on Reset; -- = Unimplemented, read as `0'; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. 6390 CNSTATD Legend: Note 1: -- -- -- ANSELD3 ANSELD2 ANSELD1 16/0 All Resets Bit Range Bits Register Name(1) Virtual Address (BF88_#) PORTD REGISTER MAP FOR 64-PIN DEVICES ONLY 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 142 TABLE 11-8: Virtual Address (BF88_#) Register Name(1) Bit Range PORTE REGISTER MAP FOR 100-PIN DEVICES ONLY 6400 ANSELE 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 6410 TRISE 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- TRISE9 -- TRISE8 -- TRISE7 -- TRISE6 -- TRISE5 -- TRISE4 -- TRISE3 -- TRISE2 -- TRISE1 -- TRISE0 0000 03FF 6420 PORTE 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- RE9 -- RE8 -- RE7 -- RE6 -- RE5 -- RE4 -- RE3 -- RE2 -- RE1 -- RE0 0000 xxxx 6440 LATE 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- LATE9 -- LATE8 -- LATE7 -- LATE6 -- LATE5 -- LATE4 -- LATE3 -- LATE2 -- LATE1 -- LATE0 0000 xxxx 6440 ODCE 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- ODCE9 -- ODCE8 -- ODCE7 -- ODCE6 -- ODCE5 -- ODCE4 -- ODCE3 -- ODCE2 -- ODCE1 -- ODCE0 0000 0000 6450 CNPUE 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CNPUE9 CNPUE8 CNPUE7 -- CNPUE6 -- CNPUE5 -- -- -- -- -- 0000 CNPUE4 CNPDE3 CNPUE2 CNPUE1 CNPUE0 0000 6460 CNPDE 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CNPDE9 CNPDE8 CNPDE7 -- CNPDE6 -- CNPDE5 -- -- -- -- -- 0000 CNPDE4 CNPDE3 CNPDE2 CNPDE1 CNPDE0 0000 6470 CNCONE 31:16 15:0 -- ON -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 6480 CNENE 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- CNIEE9 -- CNIEE8 -- CNIEE7 -- CNIEE6 -- CNIEE5 -- CNIEE4 -- CNIEE3 -- CNIEE2 -- CNIEE1 31:16 -- -- -- -- -- -- 15:0 -- -- -- -- -- -- 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 -- -- -- -- -- -- ANSELE9 ANSELE8 ANSELE7 ANSELE6 ANSELE5 ANSELE4 19/3 -- -- 18/2 17/1 16/0 -- -- -- 0000 ANSELE2 ANSELE1 ANSELE0 03F7 -- -- 0000 0000 -- 0000 CNIEE0 0000 -- -- -- -- -- -- -- -- -- -- 0000 CN CN CN CN CN CN CN CN CN CN 0000 STATE9 STATE8 STATE7 STATE6 STATE5 STATE4 STATE3 STATE2 STATE1 STATE0 x = Unknown value on Reset; -- = Unimplemented, read as `0'; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. 6490 CNSTATE Legend: Note 1: 31/15 All Resets Bits DS60001290E-page 143 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 2014-2017 Microchip Technology Inc. TABLE 11-9: Virtual Address (BF88_#) Register Name(1) Bit Range 6400 ANSELE 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 6410 TRISE 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRISE7 -- TRISE6 -- TRISE5 -- TRISE4 -- TRISE3 -- TRISE2 -- TRISE1 -- TRISE0 0000 00FF 6420 PORTE 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RE7 -- RE6 -- RE5 -- RE4 -- RE3 -- RE2 -- RE1 -- RE0 0000 xxxx 6440 LATE 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- LATE7 -- LATE6 -- LATE5 -- LATE4 -- LATE3 -- LATE2 -- LATE1 -- LATE0 0000 xxxx 6440 ODCE 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ODCE7 -- ODCE6 -- ODCE5 -- ODCE4 -- ODCE3 -- ODCE2 -- ODCE1 -- ODCE0 0000 0000 6450 CNPUE 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CNPUE7 -- CNPUE6 -- CNPUE5 -- -- -- -- -- 0000 CNPUE4 CNPDE3 CNPUE2 CNPUE1 CNPUE0 0000 6460 CNPDE 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CNPDE7 -- CNPDE6 -- CNPDE5 -- -- -- -- -- 0000 CNPDE4 CNPDE3 CNPDE2 CNPDE1 CNPDE0 0000 6470 CNCONE 31:16 15:0 -- ON -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 6480 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CNIEE7 -- CNIEE6 -- CNIEE5 -- CNIEE4 -- CNIEE3 -- CNIEE2 -- CNIEE1 31:16 -- -- -- -- -- -- -- -- CNENE 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 -- -- -- -- ANSELE7 ANSELE6 ANSELE5 ANSELE4 19/3 18/2 17/1 16/0 -- -- -- ANSELE2 -- -- -- -- 0000 03F4 -- -- 0000 0000 -- 0000 CNIEE0 0000 -- -- -- -- -- -- -- -- 0000 CN CN CN CN CN CN CN CN 15:0 -- -- -- -- -- -- -- -- 0000 STATE7 STATE6 STATE5 STATE4 STATE3 STATE2 STATE1 STATE0 x = Unknown value on Reset; -- = Unimplemented, read as `0'; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. 6490 CNSTATE Legend: Note 1: 31/15 All Resets Bits 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 144 TABLE 11-10: PORTE REGISTER MAP FOR 64-PIN DEVICES ONLY 31/15 30/14 29/13 28/12 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 -- -- -- -- -- -- -- ANSELE8 -- -- -- -- -- -- -- -- -- -- 18/2 17/1 16/0 6500 ANSELF 31:16 15:0 -- -- -- -- 6510 TRISF 31:16 15:0 -- -- -- -- -- TRISF13 -- TRISF12 -- -- -- -- -- -- -- TRISF8 -- TRISF7 -- TRISF6 -- TRISF5 -- TRISF4 -- TRISF3 -- TRISF2 -- TRISF1 -- TRISF0 0000 31FF 6520 PORTF 31:16 15:0 -- -- -- -- -- RF13 -- RF12 -- -- -- -- -- -- -- RF8 -- RF7 -- RF6 -- RF5 -- RF4 -- RF3 -- RF2 -- RF1 -- RF0 0000 xxxx 6530 LATF 31:16 15:0 -- -- -- -- -- LATF13 -- LATF12 -- -- -- -- -- -- -- LATF8 -- LATF7 -- LATF6 -- LATF5 -- LATF4 -- LATF3 -- LATF2 -- LATF1 -- LATF0 0000 xxxx 6540 ODCF 31:16 15:0 -- -- -- -- -- ODCF13 -- ODCF12 -- -- -- -- -- -- -- ODCF8 -- ODCF7 -- ODCF6 -- ODCF5 -- ODCF4 -- ODCF3 -- ODCF2 -- ODCF1 -- ODCF0 0000 0000 6550 CNPUF 31:16 15:0 -- -- -- -- -- -- CNPUF13 CNPUF12 -- -- -- -- -- -- -- CNPUF8 -- CNPUF7 -- CNPUF6 -- CNPUF5 -- CNPUF4 -- -- -- -- 0000 CNPDF3 CNPUF2 CNPUF1 CNPUF0 0000 6560 CNPDF 31:16 15:0 -- -- -- -- -- -- CNPDF13 CNPDF12 -- -- -- -- -- -- -- CNPDF8 -- CNPDF7 -- CNPDF6 -- CNPDF5 -- CNPDF4 -- -- -- -- 0000 CNPDF3 CNPDF2 CNPDF1 CNPDF0 0000 6570 CNCONF 31:16 15:0 -- ON -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 6580 31:16 15:0 -- -- -- -- -- CNIEF13 -- CNIEF12 -- -- -- -- -- -- -- CNIEF8 -- CNIEF7 -- CNIEF6 -- CNIEF5 -- CNIEF4 -- CNIEF3 -- CNIEF2 -- CNIEF1 31:16 -- -- 15:0 -- -- CNENF -- -- -- 0000 ANSELE2 ANSELE1 ANSELE0 3107 -- -- 0000 0000 -- 0000 CNIEF0 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 CN CN CN CN CN CN CN CN CN CN CN -- -- -- 0000 STATF13 STATF12 STATF8 STATF7 STATF6 STATF5 STATF4 STATF3 STATF2 STATF1 STATF0 x = Unknown value on Reset; -- = Unimplemented, read as `0'; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. 6590 CNSTATF Legend: Note 1: -- -- ANSELE13 ANSELE12 27/11 All Resets Bit Range Register Name(1) Virtual Address (BF88_#) Bits DS60001290E-page 145 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 2014-2017 Microchip Technology Inc. TABLE 11-11: PORTF REGISTER MAP FOR PIC32MX130F128L, PIC32MX150F256L, AND PIC32MX170F512L DEVICES ONLY 31/15 30/14 29/13 28/12 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 -- -- -- -- -- -- -- ANSELE8 -- -- -- -- -- -- -- -- -- -- 18/2 17/1 16/0 6500 ANSELF 31:16 15:0 -- -- -- -- 6510 TRISF 31:16 15:0 -- -- -- -- -- TRISF13 -- TRISF12 -- -- -- -- -- -- -- TRISF8 -- -- -- -- -- TRISF5 -- TRISF4 -- TRISF3 -- TRISF2 -- TRISF1 -- TRISF0 0000 313F 6520 PORTF 31:16 15:0 -- -- -- -- -- RF13 -- RF12 -- -- -- -- -- -- -- RF8 -- -- -- -- -- RF5 -- RF4 -- RF3 -- RF2 -- RF1 -- RF0 0000 xxxx 6530 LATF 31:16 15:0 -- -- -- -- -- LATF13 -- LATF12 -- -- -- -- -- -- -- LATF8 -- -- -- -- -- LATF5 -- LATF4 -- LATF3 -- LATF2 -- LATF1 -- LATF0 0000 xxxx 6540 ODCF 31:16 15:0 -- -- -- -- -- ODCF13 -- ODCF12 -- -- -- -- -- -- -- ODCF8 -- -- -- -- -- ODCF5 -- ODCF4 -- ODCF3 -- ODCF2 -- ODCF1 -- ODCF0 0000 0000 6550 CNPUF 31:16 15:0 -- -- -- -- -- -- CNPUF13 CNPUF12 -- -- -- -- -- -- -- CNPUF8 -- -- -- -- -- CNPUF5 -- CNPUF4 -- -- -- -- 0000 CNPDF3 CNPUF2 CNPUF1 CNPUF0 0000 6560 CNPDF 31:16 15:0 -- -- -- -- -- -- CNPDF13 CNPDF12 -- -- -- -- -- -- -- CNPDF8 -- -- -- -- -- CNPDF5 -- CNPFF4 -- -- -- -- 0000 CNPDF3 CNPDF2 CNPDF1 CNPDF0 0000 6570 CNCONF 31:16 15:0 -- ON -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 6580 31:16 15:0 -- -- -- -- -- CNIEF13 -- CNIEF12 -- -- -- -- -- -- -- CNIEF8 -- -- -- -- -- CNIEF5 -- CNIEF4 -- CNIEF3 -- CNIEF2 -- CNIEF1 31:16 -- -- CNENF -- -- -- 0000 ANSELE2 ANSELE1 ANSELE0 3107 -- -- 0000 0000 -- 0000 CNIEF0 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 CN CN CN CN CN CN CN CN CN 15:0 -- -- -- -- -- -- -- 0000 STATF13 STATF12 STATF8 STATF5 STATF4 STATF3 STATF2 STATF1 STATF0 x = Unknown value on Reset; -- = Unimplemented, read as `0'; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. 6590 CNSTATF Legend: Note 1: -- -- ANSELE13 ANSELE12 27/11 All Resets Bit Range Register Name(1) Virtual Address (BF88_#) Bits 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 146 TABLE 11-12: PORTF REGISTER MAP FOR PIC32MX230F128L, PIC32MX530F128L, PIC32MX250F256L, PIC32MX550F256L, PIC32MX270F512L, AND PIC32MX570F512L DEVICES ONLY Virtual Address (BF88_#) Register Name(1) Bit Range 6510 TRISF 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRISF6 -- TRISF5 -- TRISF4 -- TRISF3 -- TRISF2 -- TRISF1 -- TRISF0 0000 007F 6520 PORTF 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RF6 -- RF5 -- RF4 -- RF3 -- RF2 -- RF1 -- RF0 0000 xxxx 6530 LATF 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- LATF6 -- LATF5 -- LATF4 -- LATF3 -- LATF2 -- LATF1 -- LATF0 0000 xxxx 6540 ODCF 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ODCF6 -- ODCF5 -- ODCF4 -- ODCF3 -- ODCF2 -- ODCF1 -- ODCF0 0000 0000 6550 CNPUF 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CNPUF6 -- CNPUF5 -- CNPUF4 -- CNPUF3 -- CNPUF2 -- CNPUF1 -- 0000 CNPUF0 0000 6560 CNPDF 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CNPDF6 -- CNPDF5 -- CNPDF4 -- CNPDF3 -- CNPDF2 -- CNPDF1 -- 0000 CNPDF0 0000 6570 CNCONF 31:16 15:0 -- ON -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 6580 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CNIEF6 -- CNIEF5 -- CNIEF4 -- CNIEF3 -- CNIEF2 -- CNIEF1 -- CNIEF0 0000 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CN STATF5 -- CN STATF4 -- CN STATF3 -- CN STATF2 -- CN STATF1 -- CN STATF0 0000 15:0 -- CN STATF6 CNENF 6590 CNSTATF Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bits 0000 x = Unknown value on Reset; -- = Unimplemented, read as `0'; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. DS60001290E-page 147 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 2014-2017 Microchip Technology Inc. TABLE 11-13: PORTF REGISTER MAP FOR PIC32MX120F064H, PIC32MX130F128H, PIC32MX150F256H, AND PIC32MX170F512H DEVICES ONLY Virtual Address (BF88_#) Register Name(1) Bit Range 6510 TRISF 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRISF5 -- TRISF4 -- TRISF3 -- -- -- TRISF1 -- TRISF0 0000 003B 6520 PORTF 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RF5 -- RF4 -- RF3 -- -- -- RF1 -- RF0 0000 xxxx 6530 LATF 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- LATF5 -- LATF4 -- LATF3 -- -- -- LATF1 -- LATF0 0000 xxxx 6540 ODCF 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ODCF5 -- ODCF4 -- ODCF3 -- -- -- ODCF1 -- ODCF0 0000 0000 6550 CNPUF 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CNPUF5 -- CNPUF4 -- CNPUF3 -- -- -- CNPUF1 -- 0000 CNPUF0 0000 6560 CNPDF 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CNPDF5 -- CNPDF4 -- CNPDF3 -- -- -- CNPDF1 -- 0000 CNPDF0 0000 6570 CNCONF 31:16 15:0 -- ON -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 6580 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CNIEF5 -- CNIEF4 -- CNIEF3 -- -- -- CNIEF1 -- CNIEF0 0000 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CN STATF4 -- CN STATF3 -- CN STATF1 -- CN STATF0 0000 -- -- CN STATF5 -- 15:0 CNENF 6590 CNSTATF Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bits -- 0000 x = Unknown value on Reset; -- = Unimplemented, read as `0'; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 148 TABLE 11-14: PORTF REGISTER MAP FOR PIC32MX230F128H, PIC32MX530F128H, PIC32MX250F256H, PIC32MX550F256H, PIC32MX270F512H, AND PIC32MX570F512H DEVICES ONLY 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRISG9 -- TRISG8 -- TRISG7 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Register Name(1) Virtual Address (BF88_#) Bits -- -- -- -- -- -- -- -- -- -- -- -- 0000 83C0 -- TRISG6 -- -- -- -- -- TRISG3 -- TRISG2 -- TRISG1 -- TRISG0 0000 F3CF 22/6 6600 ANSELG 31:16 -- 15:0 ANSELG15 6610 TRISG 31:16 -- 15:0 TRISG15 6620 PORTG 31:16 15:0 -- RG15 -- RG14 -- RG13 -- RG12 -- -- -- -- -- RG9 -- RG8 -- RG7 -- RG6 -- -- -- -- -- RG3(2) -- RG2(2) -- RG1 -- RG0 0000 xxxx 6630 LATG 31:16 15:0 -- LATG15 -- LATG14 -- LATG13 -- LATG12 -- -- -- -- -- LATG9 -- LATG8 -- LATG7 -- LATG6 -- -- -- -- -- LATG3 -- LATG2 -- LATG1 -- LATG0 0000 xxxx 6640 ODCG 31:16 15:0 -- ODCG15 -- ODCG14 -- ODCG13 -- ODCG12 -- -- -- -- -- ODCG9 -- ODCG8 -- ODCG7 -- ODCG6 -- -- -- -- -- ODCG3 -- ODCG2 -- ODCG1 -- ODCG0 0000 0000 6650 CNPUG 31:16 -- -- -- -- 15:0 CNPUG15 CNPUG14 CNPUG13 CNPUG12 -- -- -- -- -- CNPUG9 -- CNPUG8 -- CNPUG7 -- CNPUG6 -- -- -- -- -- -- -- -- 0000 CNPUG3 CNPUG2 CNPUG1 CNPUG0 0000 6660 CNPDG 31:16 -- -- -- -- 15:0 CNPDG15 CNPDG14 CNPDG13 CNPDG12 -- -- -- -- -- CNPDG9 -- CNPDG8 -- CNPDG7 -- CNPDG6 -- -- -- -- -- -- -- -- 0000 CNPDG3 CNPDG2 CNPDG1 CNPDG0 0000 6670 CNCONG 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 6680 31:16 -- 15:0 CNIEG15 -- -- -- -- -- CNIEG9 -- CNIEG8 -- CNIEG7 -- CNIEG6 -- -- -- -- -- CNIEG3 -- CNIEG2 -- CNIEG1 CNENG 31:16 2: -- -- -- SIDL -- -- -- -- -- CNIEG14 CNIEG13 CNIEG12 -- -- 0000 0000 -- 0000 CNIEG0 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 CN CN CN CN CN CN CN CN CN CN CN CN -- -- -- -- 0000 STATG15 STATG14 STATG13 STATG12 STATG9 STATG8 STATG7 STATG6 STATG3 STATG2 STATG1 STATG0 x = Unknown value on Reset; -- = Unimplemented, read as `0'; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. This bit is only available on devices without a USB module. 6690 CNSTATG Legend: Note 1: -- ON -- -- -- TRISG14 TRISG13 TRISG12 -- -- -- -- ANSELG9 ANSELG8 ANSELG7 ANSELG6 15:0 DS60001290E-page 149 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 2014-2017 Microchip Technology Inc. TABLE 11-15: PORTG REGISTER MAP FOR 100-PIN DEVICES ONLY 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- -- -- -- -- -- -- -- 0000 03C0 6600 ANSELG 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 6610 TRISG 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- TRISG9 -- TRISG8 -- TRISG7 -- TRISG6 -- -- -- -- -- TRISG3 -- TRISG2 -- -- -- -- 0000 03CC 6620 PORTG 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- RG9 -- RG8 -- RG7 -- RG6 -- -- -- -- -- RG3(2) -- RG2(2) -- -- -- -- 0000 xxxx 6630 LATG 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- LATG9 -- LATG8 -- LATG7 -- LATG6 -- -- -- -- -- LATG3 -- LATG2 -- -- -- -- 0000 xxxx 6640 ODCG 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- ODCG9 -- ODCG8 -- ODCG7 -- ODCG6 -- -- -- -- -- ODCG3 -- ODCG2 -- -- -- -- 0000 0000 6650 CNPUG 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- CNPUG9 -- CNPUG8 -- CNPUG7 -- CNPUG6 -- -- -- -- -- -- CNPUG3 CNPUG2 -- -- -- -- 0000 0000 6660 CNPDG 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- CNPDG9 -- CNPDG8 -- CNPDG7 -- CNPDG6 -- -- -- -- -- -- CNPDG3 CNPDG2 -- -- -- -- 0000 0000 6670 CNCONG 31:16 15:0 -- ON -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 6680 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- CNIEG9 -- CNIEG8 -- CNIEG7 -- CNIEG6 -- -- -- -- -- CNIEG3 -- CNIEG2 -- -- -- -- 0000 0000 31:16 -- -- -- -- -- -- CNENG -- -- -- -- -- -- -- -- -- -- 0000 CN CN CN CN CN CN 15:0 -- -- -- -- -- -- -- -- -- -- 0000 STATG9 STATG8 STATG7 STATG6 STATG3 STATG2 x = Unknown value on Reset; -- = Unimplemented, read as `0'; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. This bit is only available on devices without a USB module. 6690 CNSTATG Legend: Note 1: 2: -- -- -- -- ANSELG9 ANSELG8 ANSELG7 ANSELG6 21/5 All Resets Bit Range Register Name(1) Virtual Address (BF88_#) Bits 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 150 TABLE 11-16: PORTG REGISTER MAP FOR 64-PIN DEVICES ONLY INT1R FA08 INT2R FA0C INT3R FA10 INT4R FA18 T2CKR FA1C T3CKR FA20 T4CKR FA24 T5CKR FA28 IC1R FA2C IC2R FA30 IC3R FA34 IC4R FA38 IC5R FA48 OCFAR FA50 U1RXR FA54 U1CTSR FA58 U2RXR Legend: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. INT1R<3:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- U2RXR<3:0> 0000 0000 -- U1CTSR<3:0> -- 0000 0000 U1RXR<3:0> -- 0000 0000 OCFAR<3:0> -- 0000 0000 IC5R<3:0> -- 0000 0000 IC4R<3:0> -- 0000 0000 IC3R<3:0> -- 0000 0000 IC2R<3:0> -- 0000 0000 IC1R<3:0> -- 0000 0000 T5CKR<3:0> -- 0000 0000 T4CKR<3:0> -- 0000 0000 T3CKR<3:0> -- 0000 0000 T2CKR<3:0> -- 0000 0000 INT4R<3:0> -- 0000 0000 INT3R<3:0> -- 0000 0000 INT2R<3:0> -- All Resets FA04 Bit Range Register Name DS60001290E-page 151 Virtual Address (BF80_#) Bits 0000 0000 -- 0000 0000 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 2014-2017 Microchip Technology Inc. TABLE 11-17: PERIPHERAL PIN SELECT INPUT REGISTER MAP U2CTSR FA60 U3RXR FA64 U3CTSR FA68 U4RXR FA6C U4CTSR FA70 U5RXR FA74 U5CTSR FA84 SDI1R FA88 SS1R FA90 SDI2R FA94 SS2R FA9C SDI3R FAA0 SS3R FAA8 SDI4R FAAC SS4R FAC8 C1RXR FAD0 REFCLKIR Legend: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. 18/2 17/1 16/0 -- -- -- U2CTSR<3:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- REFCLKIR<3:0> 0000 0000 -- C1RXR<3:0> -- 0000 0000 SS4R<3:0> -- 0000 0000 SDI4R<3:0> -- 0000 0000 SS3R<3:0> -- 0000 0000 SDI3R<3:0> -- 0000 0000 SS2R<3:0> -- 0000 0000 SDI2R<3:0> -- 0000 0000 SS1R<3:0> -- 0000 0000 SDI1R<3:0> -- 0000 0000 U5CTSR<3:0> -- 0000 0000 U5RXR<3:0> -- 0000 0000 U4CTSR<3:0> -- 0000 0000 U4RXR<3:0> -- 0000 0000 U3CTSR<3:0> -- 0000 0000 U3RXR<3:0> -- All Resets FA5C Bit Range Register Name 2014-2017 Microchip Technology Inc. Virtual Address (BF80_#) Bits 0000 0000 -- 0000 0000 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 152 TABLE 11-17: PERIPHERAL PIN SELECT INPUT REGISTER MAP (CONTINUED) DS60001290E-page 153 FB38 RPA14R FB3C RPA15R FB40 RPB0R FB44 RPB1R FB48 RPB2R FB4C RPB3R FB54 RPB5R FB58 RPB6R FB5C RPB7R FB60 RPB8R FB64 RPB9R FB68 RPB10R FB78 RPB14R FB7C RPB15R FB84 RPC1R Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- RPA14<3:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register is not available if the associated RPx function is not present on the device. Refer to the pin table for the specific device to determine availability. -- -- RPC1<3:0> 0000 0000 -- RPB15<3:0> -- 0000 0000 RPB14<3:0> -- 0000 0000 RPB10<3:0> -- 0000 0000 RPB9<3:0> -- 0000 0000 RPB8<3:0> -- 0000 0000 RPB7<3:0> -- 0000 0000 RPB6<3:0> -- 0000 0000 RPB5<3:0> -- 0000 0000 RPB3<3:0> -- 0000 0000 RPB2<3:0> -- 0000 0000 RPB1<3:0> -- 0000 0000 RPB0<3:0> -- 0000 0000 RPA15<3:0> -- All Resets Bit Range Register Name Virtual Address (BF80_#) Bits 0000 0000 -- 0000 0000 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 2014-2017 Microchip Technology Inc. TABLE 11-18: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FB88 RPC2R FB8C RPC3R FB90 RPC4R FBB4 RPC13R FBB8 RPC14R FBC0 RPD0R FBC4 RPD1R FBC8 RPD2R FBCC RPD3R 2014-2017 Microchip Technology Inc. FBD0 RPD4R FBD4 RPD5R FBE0 RPD8R FBE4 RPD9R FBE8 RPD10R FBEC RPD11R FBF0 RPD12R FBF8 RPD14R Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- RPC2<3:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register is not available if the associated RPx function is not present on the device. Refer to the pin table for the specific device to determine availability. -- -- RPD14<3:0> 0000 0000 -- RPD12<3:0> -- 0000 0000 RPD11<3:0> -- 0000 0000 RPD10<3:0> -- 0000 0000 RPD9<3:0> -- 0000 0000 RPD8<3:0> -- 0000 0000 RPD5<3:0> -- 0000 0000 RPD4<3:0> -- 0000 0000 RPD3<3:0> -- 0000 0000 RPD2<3:0> -- 0000 0000 RPD1<3:0> -- 0000 0000 RPD0<3:0> -- 0000 0000 RPC14<3:0> -- 0000 0000 RPC13<3:0> -- 0000 0000 RPC4<3:0> -- 0000 0000 RPC3<3:0> -- All Resets Bit Range Register Name Virtual Address (BF80_#) Bits 0000 0000 -- 0000 0000 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 154 TABLE 11-18: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED) DS60001290E-page 155 FBFC RPD15R FC0C RPE3R FC14 RPE5R FC20 RPE8R FC24 RPE9R FC40 RPF0R FC44 RPF1R FC48 RPF2R FC4C RPF3R FC50 RPF4R FC54 RPF5R FC58 RPF6R FC5C RPF7R FC60 RPF8R FC70 RPF12R FC74 RPF13R FC80 RPG0R Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- RPD15<3:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register is not available if the associated RPx function is not present on the device. Refer to the pin table for the specific device to determine availability. -- -- RPG0<3:0> 0000 0000 -- RPF13<3:0> -- 0000 0000 RPF12<3:0> -- 0000 0000 RPF7<3:0> -- 0000 0000 RPF6<3:0> -- 0000 0000 RPF6<3:0> -- 0000 0000 RPF5<3:0> -- 0000 0000 RPF4<3:0> -- 0000 0000 RPF3<3:0> -- 0000 0000 RPF2<3:0> -- 0000 0000 RPF1<3:0> -- 0000 0000 RPF0<3:0> -- 0000 0000 RPE9<3:0> -- 0000 0000 RPE8<3:0> -- 0000 0000 RPE5<3:0> -- 0000 0000 RPE3<3:0> -- All Resets Bit Range Register Name Virtual Address (BF80_#) Bits 0000 0000 -- 0000 0000 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 2014-2017 Microchip Technology Inc. TABLE 11-18: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED) FC84 RPG1R FC98 RPG6R FC9C RPG7R FCA0 RPG8R FCA4 RPG9R Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- RPG1<3:0> -- -- -- -- -- -- -- -- -- x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register is not available if the associated RPx function is not present on the device. Refer to the pin table for the specific device to determine availability. -- -- RPG9<3:0> 0000 0000 -- RPG8<3:0> -- 0000 0000 RPG7<3:0> -- 0000 0000 RPG6<3:0> -- All Resets Bit Range Register Name Virtual Address (BF80_#) Bits 0000 0000 -- 0000 0000 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 156 TABLE 11-18: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED) PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 11-1: Bit Range 31:24 23:16 15:8 7:0 [pin name]R: PERIPHERAL PIN SELECT INPUT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- -- [pin name]R<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-4 Unimplemented: Read as `0' bit 3-0 [pin name]R<3:0>: Peripheral Pin Select Input bits Where [pin name] refers to the pins that are used to configure peripheral input mapping. See Table 11-1 for input pin selection values. Note: Register values can only be changed if the IOLOCK Configuration bit (CFGCON<13>) = 0. REGISTER 11-2: Bit Range 31:24 23:16 15:8 7:0 RPnR: PERIPHERAL PIN SELECT OUTPUT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- -- RPnR<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-4 Unimplemented: Read as `0' bit 3-0 RPnR<3:0>: Peripheral Pin Select Output bits See Table 11-2 for output pin selection values. Note: x = Bit is unknown Register values can only be changed if the IOLOCK Configuration bit (CFGCON<13>) = 0. 2014-2017 Microchip Technology Inc. DS60001290E-page 157 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 11-3: Bit Range 31:24 23:16 15:8 7:0 CNCONx: CHANGE NOTICE CONTROL FOR PORTx REGISTER (x = A - G) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 ON -- SIDL -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: Change Notice (CN) Control ON bit 1 = CN is enabled 0 = CN is disabled bit 14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Control bit 1 = CPU Idle Mode halts CN operation 0 = CPU Idle does not affect CN operation bit 12-0 Unimplemented: Read as `0' DS60001290E-page 158 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 12.0 This family of PIC32 devices features one synchronous/ asynchronous 16-bit timer that can operate as a freerunning interval timer for various timing applications and counting external events. This timer can also be used with the Low-Power Secondary Oscillator (SOSC) for Real-Time Clock (RTC) applications. The following modes are supported: TIMER1 Note: This data sheet summarizes the features of the PIC32MX1XX/2XX/5XX 64/100-pin family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14. "Timers" (DS60001105) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). * * * * Synchronous Internal Timer Synchronous Internal Gated Timer Synchronous External Timer Asynchronous External Timer 12.1 Additional Supported Features * Selectable clock prescaler * Timer operation during CPU Idle and Sleep mode * Fast bit manipulation using CLR, SET and INV registers * Asynchronous mode can be used with the SOSC to function as a Real-Time Clock (RTC) FIGURE 12-1: TIMER1 BLOCK DIAGRAM Data Bus<31:0> TSYNC <15:0> 1 Reset Sync TMR1 0 Equal 16-bit Comparator PR1 T1IF Event Flag 0 Q 1 TGATE D Q TGATE TCS ON SOSCO/T1CK x1 SOSCEN SOSCI Gate Sync PBCLK 10 00 Prescaler 1, 8, 64, 256 2 TCKPS<1:0> Note: The default state of the SOSCEN (OSCCON<1>) bit during a device Reset is controlled by the FSOSCEN bit in Configuration Word, DEVCFG1. 2014-2017 Microchip Technology Inc. DS60001290E-page 159 Control Registers Virtual Address (BF80_#) TABLE 12-1: TMR1 0620 Legend: Note 1: PR1 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 -- -- -- 15:0 31:16 ON -- -- -- SIDL -- 15:0 31:16 -- -- -- -- 23/7 22/6 21/5 20/4 19/3 -- -- -- -- TWDIS -- TWIP -- -- -- -- -- -- -- -- TMR1<15:0> -- -- -- -- -- -- -- -- -- -- TGATE -- -- -- TCKPS<1:0> -- -- -- -- -- -- -- -- 15:0 PR1<15:0> x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. -- 18/2 All Resets Bit Range Register Name(1) Bits 0600 T1CON 0610 TIMER1 REGISTER MAP 17/1 16/0 -- -- -- 0000 TSYNC -- TCS -- -- -- 0000 0000 -- -- 0000 0000 FFFF All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 160 12.2 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 12-1: Bit Range 31:24 23:16 15:8 7:0 T1CON: TYPE A TIMER CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 (1) U-0 R/W-0 R/W-0 R-0 U-0 U-0 U-0 ON -- SIDL TWDIS TWIP -- -- -- R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 TGATE -- -- TSYNC TCS -- TCKPS<1:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: Timer On bit(1) 1 = Timer is enabled 0 = Timer is disabled bit 14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue operation when device enters Idle mode 0 = Continue operation even in Idle mode bit 12 TWDIS: Asynchronous Timer Write Disable bit 1 = Writes to TMR1 are ignored until pending write operation completes 0 = Back-to-back writes are enabled (Legacy Asynchronous Timer functionality) bit 11 TWIP: Asynchronous Timer Write in Progress bit In Asynchronous Timer mode: 1 = Asynchronous write to TMR1 register in progress 0 = Asynchronous write to TMR1 register complete In Synchronous Timer mode: This bit is read as `0'. bit 10-8 Unimplemented: Read as `0' bit 7 TGATE: Timer Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 6 Unimplemented: Read as `0' bit 5-4 TCKPS<1:0>: Timer Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 3 Unimplemented: Read as `0' Note 1: When using 1:1 PBCLK divisor, the user's software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. 2014-2017 Microchip Technology Inc. DS60001290E-page 161 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 12-1: T1CON: TYPE A TIMER CONTROL REGISTER (CONTINUED) bit 2 TSYNC: Timer External Clock Input Synchronization Selection bit When TCS = 1: 1 = External clock input is synchronized 0 = External clock input is not synchronized When TCS = 0: This bit is ignored. bit 1 TCS: Timer Clock Source Select bit 1 = External clock from TxCKI pin 0 = Internal peripheral clock bit 0 Unimplemented: Read as `0' Note 1: When using 1:1 PBCLK divisor, the user's software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. DS60001290E-page 162 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 13.0 Note: Two 32-bit synchronous timers are available by combining Timer2 with Timer3 and Timer4 with Timer5. The 32-bit timers can operate in three modes: TIMER2/3, TIMER4/5 This data sheet summarizes the features of the PIC32MX1XX/2XX/5XX 64/100-pin family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14. "Timers" (DS60001105) of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). * Synchronous internal 32-bit timer * Synchronous internal 32-bit gated timer * Synchronous external 32-bit timer Note: This family of PIC32 devices features four synchronous 16-bit timers (default) that can operate as a freerunning interval timer for various timing applications and counting external events. The following modes are supported: 13.1 Additional Supported Features * Selectable clock prescaler * Timers operational during CPU idle * Time base for Input Capture and Output Compare modules (Timer2 and Timer3 only) * ADC event trigger (Timer3 in 16-bit mode, Timer2/ 3 in 32-bit mode) * Fast bit manipulation using CLR, SET and INV registers * Synchronous internal 16-bit timer * Synchronous internal 16-bit gated timer * Synchronous external 16-bit timer FIGURE 13-1: In this chapter, references to registers, TxCON, TMRx and PRx, use `x' to represent Timer2 through 5 in 16-bit modes. In 32-bit modes, `x' represents Timer2 or 4; `y' represents Timer3 or 5. TIMER2, 3, 4, 5 BLOCK DIAGRAM (16-BIT) Data Bus<31:0> <15:0> Reset Sync TMRx ADC Event Trigger(1) Equal Comparator x 16 PRx TxIF Event Flag 0 1 TGATE Q TGATE D Q TCS ON TxCK x1 Gate Sync PBCLK Note 1: ADC event trigger is available on Timer3 only. 2014-2017 Microchip Technology Inc. 10 00 Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS DS60001290E-page 163 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT)(1) FIGURE 13-2: Data Bus<31:0> <31:0> Reset TMRy(1) MS Half Word ADC Event Trigger(2) Equal Sync LS Half Word 32-bit Comparator PRy TyIF Event Flag TMRx(1) PRx 0 1 TGATE Q D TGATE Q TCS ON TxCK x1 Gate Sync PBCLK 10 00 Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS Note 1: 2: In this diagram, the use of `x' in registers, TxCON, TMRx, PRx and TxCK, refers to either Timer2 or Timer4; the use of `y' in registers, TyCON, TMRy, PRy, TyIF, refers to either Timer3 or Timer5. ADC event trigger is available only on the Timer2/3 pair. DS60001290E-page 164 2014-2017 Microchip Technology Inc. Control Registers Virtual Address (BF80_#) TABLE 13-1: TMR2 0820 PR2 0A00 T3CON 0A10 TMR3 0A20 PR3 0C00 T4CON 0C10 TMR4 0C20 PR4 0E00 T5CON 0E10 TMR5 0E20 Legend: Note 1: PR5 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 -- 15:0 31:16 ON -- 15:0 31:16 23/7 22/6 21/5 20/4 19/3 18/2 -- -- -- -- -- -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- TGATE -- -- -- -- TCKPS<2:0> -- -- -- -- T32 -- -- -- -- -- -- -- -- TMR2<15:0> -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- PR2<15:0> -- -- -- -- 15:0 31:16 ON -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- TMR3<15:0> -- -- 15:0 31:16 -- -- -- -- -- -- -- 15:0 31:16 ON -- -- -- SIDL -- -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- 15:0 31:16 -- -- -- -- 15:0 31:16 ON -- -- -- SIDL -- 15:0 31:16 -- -- -- All Resets Bit Range Register Name(1) Bits 0800 T2CON 0810 TIMER2 THROUGH TIMER5 REGISTER MAP 17/1 16/0 -- -- -- 0000 -- -- TCS -- -- -- 0000 0000 -- -- -- -- 0000 0000 -- -- -- -- -- FFFF 0000 TCKPS<2:0> -- -- -- -- -- -- TCS -- -- -- 0000 0000 -- -- -- -- -- -- -- 0000 0000 PR3<15:0> -- -- -- -- -- -- -- -- -- FFFF 0000 -- -- -- -- -- TCKPS<2:0> -- -- T32 -- -- -- TCS -- -- -- 0000 0000 -- -- TMR4<15:0> -- -- -- -- -- -- -- -- -- 0000 0000 -- -- -- PR4<15:0> -- -- -- -- -- -- -- -- -- FFFF 0000 -- -- -- -- -- -- -- -- -- -- -- TCKPS<2:0> -- -- -- -- -- -- TCS -- -- -- 0000 0000 -- -- -- -- TMR5<15:0> -- -- -- -- -- -- -- -- -- 0000 0000 TGATE -- TGATE -- TGATE -- 15:0 PR5<15:0> x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. FFFF All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. DS60001290E-page 165 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 2014-2017 Microchip Technology Inc. 13.2 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 13-1: Bit Range 31:24 23:16 15:8 7:0 TxCON: TYPE B TIMER `x' CONTROL REGISTER (`x' = 2 THROUGH 5) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 ON(1,3) -- SIDL(4) -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 T32(2) -- TCS(3) -- TGATE(3) TCKPS<2:0>(3) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: Timer On bit(1,3) 1 = Module is enabled 0 = Module is disabled bit 14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Mode bit(4) 1 = Discontinue operation when device enters Idle mode 0 = Continue operation even in Idle mode bit 12-8 Unimplemented: Read as `0' bit 7 TGATE: Timer Gated Time Accumulation Enable bit(3) When TCS = 1: This bit is ignored and is read as `0'. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 6-4 TCKPS<2:0>: Timer Input Clock Prescale Select bits(3) 111 = 1:256 prescale value 110 = 1:64 prescale value 101 = 1:32 prescale value 100 = 1:16 prescale value 011 = 1:8 prescale value 010 = 1:4 prescale value 001 = 1:2 prescale value 000 = 1:1 prescale value Note 1: When using 1:1 PBCLK divisor, the user's software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. This bit is available only on even numbered timers (Timer2 and Timer4). While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer3 and Timer5). All timer functions are set through the even numbered timers. While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer in Idle mode. 2: 3: 4: DS60001290E-page 166 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 13-1: TxCON: TYPE B TIMER `x' CONTROL REGISTER (CONTINUED)(`x' = 2 bit 3 T32: 32-Bit Timer Mode Select bit(2) 1 = Odd numbered and even numbered timers form a 32-bit timer 0 = Odd numbered and even numbered timers form a separate 16-bit timer bit 2 Unimplemented: Read as `0' bit 1 TCS: Timer Clock Source Select bit(3) 1 = External clock from TxCK pin 0 = Internal peripheral clock bit 0 Unimplemented: Read as `0' Note 1: When using 1:1 PBCLK divisor, the user's software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. This bit is available only on even numbered timers (Timer2 and Timer4). While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer3 and Timer5). All timer functions are set through the even numbered timers. While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer in Idle mode. 2: 3: 4: 2014-2017 Microchip Technology Inc. DS60001290E-page 167 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY NOTES: DS60001290E-page 168 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 14.0 WATCHDOG TIMER (WDT) Note: This data sheet summarizes the features of the PIC32MX1XX/2XX/5XX 64/100-pin Family family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 9. "Watchdog, Deadman, and Power-up Timers" (DS60001114) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). FIGURE 14-1: The Watchdog Timer (WDT), when enabled, operates from the internal Low-Power Oscillator (LPRC) clock source and can be used to detect system software malfunctions by resetting the device if the WDT is not cleared periodically in software. Various WDT time-out periods can be selected using the WDT postscaler. The WDT can also be used to wake the device from Sleep or Idle mode. The following are some of the key features of the WDT module: * Configuration or software controlled * User-configurable time-out period * Can wake the device from Sleep or Idle WATCHDOG AND POWER-UP TIMER BLOCK DIAGRAM PWRT Enable WDT Enable LPRC Control PWRT Enable 1:64 Output LPRC Oscillator PWRT 1 Clock 25-bit Counter WDTCLR = 1 WDT Enable Wake WDT Enable Reset Event 25 WDT Counter Reset 0 Device Reset 1 NMI (Wake-up) Power Save Decoder FWDTPS<4:0> (DEVCFG1<20:16>) 2014-2017 Microchip Technology Inc. DS60001290E-page 169 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 -- -- -- -- -- -- -- -- -- -- -- 15:0 ON -- -- -- -- -- -- -- -- x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. 20/4 19/3 18/2 -- -- -- SWDTPS<4:0> 17/1 16/0 -- -- WDTWINEN WDTCLR All Resets Bit Range Register Name(1) Virtual Address (BF80_#) Bits 0000 WDTCON Legend: WATCHDOG TIMER REGISTER MAP 0000 0000 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 170 TABLE 14-1: PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 14-1: Bit Range 31:24 23:16 15:8 7:0 WDTCON: WATCHDOG TIMER CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- R/W-0 (1,2) -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- U-0 R-y R-y R-y R-y R-y R/W-0 R/W-0 ON -- SWDTPS<4:0> WDTWINEN WDTCLR Legend: y = Values set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: Watchdog Timer Enable bit(1,2) 1 = Enables the WDT if it is not enabled by the device configuration 0 = Disable the WDT if it was enabled in software bit 14-7 Unimplemented: Read as `0' bit 6-2 SWDTPS<4:0>: Shadow Copy of Watchdog Timer Postscaler Value from Device Configuration bits On reset, these bits are set to the values of the WDTPS <4:0> of Configuration bits. bit 1 WDTWINEN: Watchdog Timer Window Enable bit 1 = Enable windowed Watchdog Timer 0 = Disable windowed Watchdog Timer bit 0 WDTCLR: Watchdog Timer Reset bit 1 = Writing a `1' will clear the WDT 0 = Software cannot force this bit to a `0' Note 1: 2: A read of this bit results in a `1' if the Watchdog Timer is enabled by the device configuration or software. When using the 1:1 PBCLK divisor, the user software should not read or write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. 2014-2017 Microchip Technology Inc. DS60001290E-page 171 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY NOTES: DS60001290E-page 172 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 15.0 Note: * Prescaler capture event modes: - Capture timer value on every 4th rising edge of input at ICx pin - Capture timer value on every 16th rising edge of input at ICx pin INPUT CAPTURE This data sheet summarizes the features of the PIC32MX1XX/2XX/5XX 64/100-pin family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 15. "Input Capture" (DS60001122) of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). Each input capture channel can select between one of two 16-bit timers (Timer2 or Timer3) for the time base, or two 16-bit timers (Timer2 and Timer3) together to form a 32-bit timer. The selected timer can use either an internal or external clock. The other operational features include: * Device wake-up from capture pin during CPU Sleep and Idle modes * Interrupt on input capture event * 4-word FIFO buffer for capture values Interrupt optionally generated after 1, 2, 3, or 4 buffer locations are filled * Input capture can also be used to provide additional sources of external interrupts The Input Capture module is useful in applications requiring frequency (period) and pulse measurement. The Input Capture module captures the 16-bit or 32-bit value of the selected Time Base registers when an event occurs at the ICx pin. The following events cause capture events: * Simple capture event modes: - Capture timer value on every falling edge of input at ICx pin - Capture timer value on every rising edge of input at ICx pin - Capture timer value on every edge (rising and falling) - Capture timer value on every edge (rising and falling), specified edge first. FIGURE 15-1: INPUT CAPTURE BLOCK DIAGRAM FEDGE Specified/Every Edge Mode ICM<2:0> 110 Prescaler Mode (16th Rising Edge) 101 Prescaler Mode (4th Rising Edge) 100 TMR2 TMR3 C32 | ICTMR CaptureEvent ICx pin Rising Edge Mode 011 Falling Edge Mode 010 To CPU FIFO CONTROL ICxBUF FIFO ICI<1:0> Edge Detection Mode 001 ICM<2:0> Set Flag ICxIF (In IFSx Register) /N Sleep/Idle Wake-up Mode 001 111 Note: An `x' in a signal, register or bit name denotes the number of the capture channel. 2014-2017 Microchip Technology Inc. DS60001290E-page 173 Control Registers Virtual Address (BF80_#) TABLE 15-1: IC1BUF 31/15 30/14 31:16 -- 15:0 ON 31:16 15:0 2210 31:16 15:0 2400 IC3CON(1) 31:16 15:0 2410 31:16 15:0 IC3BUF 2600 IC4CON(1) 31:16 15:0 2610 31:16 15:0 IC4BUF 2800 IC5CON(1) 31:16 15:0 2810 31:16 15:0 IC5BUF Legend: Note 1: 28/12 27/11 26/10 25/9 -- -- -- -- -- -- -- SIDL -- -- -- FEDGE 31:16 15:0 2200 IC2CON(1) IC2BUF 29/13 24/8 23/7 22/6 21/5 -- -- -- -- C32 ICTMR ICI<1:0> 20/4 19/3 18/2 -- -- -- ICOV ICBNE 17/1 16/0 -- -- ICM<2:0> -- -- -- SIDL -- -- -- -- -- -- -- FEDGE -- C32 -- ICTMR xxxx xxxx -- -- ICI<1:0> -- ICOV -- ICBNE -- -- ICM<2:0> -- -- -- -- SIDL -- -- -- -- -- -- -- FEDGE -- C32 -- ICTMR -- -- ICI<1:0> -- ICOV -- ICBNE -- -- ICM<2:0> -- -- -- -- SIDL -- -- -- -- -- -- -- FEDGE -- C32 -- ICTMR -- -- ICI<1:0> -- ICOV -- ICBNE -- -- ICM<2:0> -- -- -- -- SIDL -- -- -- -- -- -- -- FEDGE -- C32 -- ICTMR 0000 0000 xxxx xxxx IC4BUF<31:0> -- ON 0000 0000 xxxx xxxx IC3BUF<31:0> -- ON 0000 0000 xxxx xxxx IC2BUF<31:0> -- ON 0000 0000 IC1BUF<31:0> -- ON All Resets Bit Range Register Name Bits 2000 IC1CON(1) 2010 INPUT CAPTURE 1 THROUGH INPUT CAPTURE 5 REGISTER MAP -- -- ICI<1:0> -- ICOV -- ICBNE -- -- ICM<2:0> -- IC5BUF<31:0> 2014-2017 Microchip Technology Inc. x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. 0000 0000 xxxx xxxx PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 174 15.1 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 15-1: Bit Range Bit 31/23/15/7 Bit 30/22/14/6 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- R/W-0 (1) U-0 R/W-0 -- SIDL R/W-0 R/W-0 31:24 23:16 15:8 7:0 ICXCON: INPUT CAPTURE `X' CONTROL REGISTER (`x' = 1 THROUGH 5) ON ICTMR Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 R/W-0 R/W-0 -- -- -- FEDGE C32 R-0 R-0 R/W-0 R/W-0 R/W-0 ICOV ICBNE R/W-0 ICI<1:0> ICM<2:0> Legend: R = Readable bit W = Writable bit -n = Bit Value at POR: (`0', `1', x = unknown) U = Unimplemented bit P = Programmable bit r = Reserved bit bit 31-16 Unimplemented: Read as `0' bit 15 ON: Input Capture Module Enable bit(1) 1 = Module enabled 0 = Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications bit 14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Control bit 1 = Halt in CPU Idle mode 0 = Continue to operate in CPU Idle mode bit 12-10 Unimplemented: Read as `0' bit 9 FEDGE: First Capture Edge Select bit (only used in mode 6, ICM<2:0> = 110) 1 = Capture rising edge first 0 = Capture falling edge first bit 8 C32: 32-bit Capture Select bit 1 = 32-bit timer resource capture 0 = 16-bit timer resource capture bit 7 ICTMR: Timer Select bit (Does not affect timer selection when C32 (ICxCON<8>) is `1') 0 = Timer3 is the counter source for capture 1 = Timer2 is the counter source for capture bit 6-5 ICI<1:0>: Interrupt Control bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event bit 4 ICOV: Input Capture Overflow Status Flag bit (read-only) 1 = Input capture overflow occurred 0 = No input capture overflow occurred bit 3 ICBNE: Input Capture Buffer Not Empty Status bit (read-only) 1 = Input capture buffer is not empty; at least one more capture value can be read 0 = Input capture buffer is empty Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. 2014-2017 Microchip Technology Inc. DS60001290E-page 175 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 15-1: bit 2-0 Note 1: ICXCON: INPUT CAPTURE `X' CONTROL REGISTER (CONTINUED)(`x' = 1 ICM<2:0>: Input Capture Mode Select bits 111 = Interrupt-Only mode (only supported while in Sleep mode or Idle mode) 110 = Simple Capture Event mode - every edge, specified edge first and every edge thereafter 101 = Prescaled Capture Event mode - every sixteenth rising edge 100 = Prescaled Capture Event mode - every fourth rising edge 011 = Simple Capture Event mode - every rising edge 010 = Simple Capture Event mode - every falling edge 001 = Edge Detect mode - every edge (rising and falling) 000 = Input Capture module is disabled When using 1:1 PBCLK divisor, the user software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. DS60001290E-page 176 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 16.0 Note: The Output Compare module is used to generate a single pulse or a train of pulses in response to selected time base events. For all modes of operation, the Output Compare module compares the values stored in the OCxR and/or the OCxRS registers to the value in the selected timer. When a match occurs, the Output Compare module generates an event based on the selected mode of operation. OUTPUT COMPARE This data sheet summarizes the features of the PIC32MX1XX/2XX/5XX 64/100-pin family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 16. "Output Compare" (DS60001111) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). FIGURE 16-1: The following are the key features of this module: * Multiple Output Compare modules in a device * Programmable interrupt generation on compare event * Single and Dual Compare modes * Single and continuous output pulse generation * Pulse-Width Modulation (PWM) mode * Hardware-based PWM Fault detection and automatic output disable * Can operate from either of two available 16-bit time bases or a single 32-bit time base OUTPUT COMPARE MODULE BLOCK DIAGRAM Set Flag bit OCxIF(1) OCxRS(1) Output Logic OCxR(1) 3 OCM<2:0> Mode Select Comparator 0 16 Timer2 OCTSEL 1 0 S R Output Enable Q OCx(1) Output Enable Logic OCFA or OCFB(2) 1 16 Timer3 Timer2 Rollover Timer3 Rollover Note 1:Where `x' is shown, reference is made to the registers associated with the respective output compare channels, 1 through 5. 2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel. 2014-2017 Microchip Technology Inc. DS60001290E-page 177 Control Registers Virtual Address (BF80_#) TABLE 16-1: 3010 OC1R 3020 OC1RS 3200 OC2CON 3210 OC2R 3220 OC2RS 3400 OC3CON 3410 OC3R 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 31:16 -- 15:0 31:16 ON -- -- -- -- -- -- -- -- -- -- -- SIDL -- -- -- -- -- -- -- OC32 15:0 31:16 15:0 31:16 3610 OC4R 2014-2017 Microchip Technology Inc. 3810 OC5R 3820 OC5RS Legend: Note 1: 18/2 -- -- -- OCFLT OCTSEL -- -- -- -- -- -- -- -- -- -- -- -- ON -- SIDL -- -- -- -- -- -- -- OC32 OCFLT OCTSEL 16/0 -- -- OCM<2:0> -- -- -- OCM<2:0> xxxx xxxx -- -- -- -- -- -- -- -- -- -- -- -- -- ON -- SIDL -- -- -- -- -- -- -- OC32 OCFLT OCTSEL -- -- -- OCM<2:0> xxxx xxxx OC3RS<31:0> 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 31:16 ON -- SIDL -- -- -- -- -- -- -- OC32 OCFLT OCTSEL -- -- -- OCM<2:0> xxxx 0000 0000 xxxx OC4R<31:0> xxxx xxxx OC4RS<31:0> 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 31:16 ON -- SIDL -- -- -- -- -- -- -- OC32 OCFLT OCTSEL OC5RS<31:0> 15:0 x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. xxxx 0000 0000 xxxx OC3R<31:0> OC5R<31:0> xxxx 0000 0000 xxxx OC2RS<31:0> 15:0 0000 0000 xxxx OC2R<31:0> 15:0 15:0 31:16 17/1 xxxx xxxx -- 31:16 OC4RS 15:0 3800 OC5CON 19/3 OC1RS<31:0> 15:0 31:16 15:0 31:16 20/4 OC1R<31:0> 15:0 31:16 15:0 31:16 21/5 All Resets 31/15 31:16 OC3RS 15:0 3600 OC4CON 3620 Bit Range Register Name(1) Bits 3000 OC1CON 3420 OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 5 REGISTER MAP -- -- OCM<2:0> -- xxxx 0000 0000 xxxx xxxx xxxx xxxx All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 178 16.1 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 16-1: Bit Range 31:24 23:16 15:8 7:0 OCxCON: OUTPUT COMPARE `x' CONTROL REGISTER (`x' = 1 THROUGH 5) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 (1) U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 -- SIDL -- -- -- -- -- U-0 U-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- OC32 OCFLT(2) OCTSEL ON OCM<2:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: Output Compare Peripheral On bit(1) 1 = Output Compare peripheral is enabled 0 = Output Compare peripheral is disabled bit 14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue operation when CPU enters Idle mode 0 = Continue operation in Idle mode bit 12-6 Unimplemented: Read as `0' bit 5 OC32: 32-bit Compare Mode bit 1 = OCxR<31:0> and/or OCxRS<31:0> are used for comparisons to the 32-bit timer source 0 = OCxR<15:0> and OCxRS<15:0> are used for comparisons to the 16-bit timer source bit 4 OCFLT: PWM Fault Condition Status bit(2) 1 = PWM Fault condition has occurred (cleared in HW only) 0 = No PWM Fault condition has occurred bit 3 OCTSEL: Output Compare Timer Select bit 1 = Timer3 is the clock source for this Output Compare module 0 = Timer2 is the clock source for this Output Compare module bit 2-0 OCM<2:0>: Output Compare Mode Select bits 111 = PWM mode on OCx; Fault pin enabled 110 = PWM mode on OCx; Fault pin disabled 101 = Initialize OCx pin low; generate continuous output pulses on OCx pin 100 = Initialize OCx pin low; generate single output pulse on OCx pin 011 = Compare event toggles OCx pin 010 = Initialize OCx pin high; compare event forces OCx pin low 001 = Initialize OCx pin low; compare event forces OCx pin high 000 = Output compare peripheral is disabled but continues to draw current Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. This bit is only used when OCM<2:0> = `111'. It is read as `0' in all other modes. 2: 2014-2017 Microchip Technology Inc. DS60001290E-page 179 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY NOTES: DS60001290E-page 180 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 17.0 Note: The SPI module is a synchronous serial interface that is useful for communicating with external peripherals and other microcontroller devices. These peripheral devices may be Serial EEPROMs, Shift registers, display drivers, Analog-to-Digital Converters (ADC), etc. The PIC32 SPI module is compatible with Motorola(R) SPI and SIOP interfaces. SERIAL PERIPHERAL INTERFACE (SPI) This data sheet summarizes the features of the PIC32MX1XX/2XX/5XX 64/100-pin family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 23. "Serial Peripheral Interface (SPI)" (DS60001106) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). FIGURE 17-1: Some of the key features of the SPI module are: * * * * * Master and Slave modes support Four different clock formats Enhanced Framed SPI protocol support User-configurable 8-bit, 16-bit and 32-bit data width Separate SPI FIFO buffers for receive and transmit - FIFO buffers act as 4/8/16-level deep FIFOs based on 32/16/8-bit data width * Programmable interrupt event on every 8-bit, 16-bit and 32-bit data transfer * Operation during CPU Sleep and Idle mode * Audio Codec Support: - I2S protocol - Left-justified - Right-justified - PCM SPI MODULE BLOCK DIAGRAM Internal Data Bus SPIxBUF Read Write SPIxRXB FIFO FIFOs Share Address SPIxBUF SPIxTXB FIFO Transmit Receive SPIxSR SDIx bit 0 SDOx SSx/FSYNC Slave Select and Frame Sync Control Shift Control Clock Control MCLKSEL Edge Select SCKx Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register. 2014-2017 Microchip Technology Inc. 1 REFCLK 0 PBCLK Baud Rate Generator MSTEN DS60001290E-page 181 Control Registers Virtual Address (BF80_#) Register Name(1) TABLE 17-1: 5800 SPI1CON SPI1STAT 5820 SPI1BUF SPI1BRG 5840 SPI1CON2 5A00 SPI2CON 5A10 SPI2STAT 5A20 SPI2BUF 5A30 SPI2BRG 5A40 SPI2CON2 2014-2017 Microchip Technology Inc. 5C00 SPI3CON 5C10 SPI3STAT 5C20 SPI3BUF 5C30 SPI3BRG 31/15 30/14 29/13 28/12 27/11 31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW 15:0 ON -- SIDL DISSDO MODE32 31:16 -- -- -- 15:0 -- -- -- 26/10 25/9 24/8 FRMCNT<2:0> MODE16 SMP CKE RXBUFELM<4:0> FRMERR SPIBUSY -- -- SPITUR 31:16 23/7 22/6 21/5 20/4 MCLKSEL -- -- -- SSEN CKP MSTEN DISSDI -- -- -- SRMT SPIROV SPIRBE 19/3 18/2 17/1 -- -- SPIFE STXISEL<1:0> 16/0 ENHBUF 0000 SRXISEL<1:0> TXBUFELM<4:0> -- SPITBE -- 31:16 -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- FRM ERREN SPI ROVEN SPI TUREN 31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW 15:0 ON -- SIDL DISSDO MODE32 31:16 -- -- -- 15:0 -- -- -- SPI 15:0 SGNEXT -- IGNROV -- SPIRBF 19EB 0000 -- IGNTUR SMP CKE RXBUFELM<4:0> FRMERR SPIBUSY -- -- 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- AUD MONO -- -- -- BRG<8:0> FRMCNT<2:0> MODE16 -- SPITUR 31:16 -- AUDEN -- -- -- -- MCLKSEL -- -- -- SSEN CKP MSTEN DISSDI -- -- -- SRMT SPIROV SPIRBE AUDMOD<1:0> SPIFE STXISEL<1:0> SPITBE -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- 15:0 SPI SGNEXT -- -- FRM ERREN SPI ROVEN SPI TUREN IGNROV IGNTUR AUDEN -- -- 31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW 15:0 ON -- SIDL DISSDO MODE32 31:16 -- -- -- 15:0 -- -- -- SMP 0000 SPITBF SPIRBF 19EB RXBUFELM<4:0> FRMERR SPIBUSY -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- AUD MONO -- -- -- BRG<8:0> CKE SPITUR MCLKSEL -- -- -- SSEN CKP MSTEN DISSDI -- -- -- SRMT SPIROV SPIRBE AUDMOD<1:0> SPIFE STXISEL<1:0> SPITBE -- 31:16 -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- 0000 0000 ENHBUF 0000 SRXISEL<1:0> TXBUFELM<4:0> -- 0000 0000 0000 0000 SPITBF SPIRBF 19EB 0000 DATA<31:0> 15:0 0000 0000 -- FRMCNT<2:0> 0000 0000 31:16 MODE16 -- 0000 ENHBUF 0000 SRXISEL<1:0> TXBUFELM<4:0> -- 0000 0000 DATA<31:0> 15:0 0000 0000 SPITBF DATA<31:0> 15:0 All Resets Bit Range Bits 5810 5830 SPI1 THROUGH SPI4 REGISTER MAP 0000 -- -- -- BRG<8:0> -- -- -- -- 0000 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. This register is only available on 100-pin devices. 2: PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 182 17.1 Virtual Address (BF80_#) 5E00 SPI4CON(2) (2) 5E10 SPI4STAT (2) 5E20 SPI4BUF SPI4BRG(2) (2) 5E40 SPI4CON2 31/15 30/14 29/13 28/12 27/11 26/10 25/9 31:16 -- -- -- -- -- -- -- 15:0 SPI SGNEXT -- -- FRM ERREN SPI ROVEN SPI TUREN IGNROV 31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW 15:0 ON -- SIDL DISSDO MODE32 31:16 -- -- -- 15:0 -- -- -- 24/8 23/7 22/6 21/5 20/4 -- -- -- -- IGNTUR AUDEN -- -- FRMCNT<2:0> MODE16 SMP CKE RXBUFELM<4:0> FRMERR SPIBUSY -- -- 31:16 SPITUR 19/3 18/2 -- -- -- -- AUD MONO -- -- -- MCLKSEL -- -- -- SSEN CKP MSTEN DISSDI -- -- -- SRMT SPIROV SPIRBE 17/1 16/0 -- -- AUDMOD<1:0> SPIFE STXISEL<1:0> SPITBE -- 31:16 -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- FRM ERREN SPI ROVEN SPI TUREN SPI 15:0 SGNEXT -- IGNROV -- -- IGNTUR -- AUDEN 0000 SPIRBF 19EB 0000 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- AUD MONO -- BRG<8:0> -- 0000 0000 SPITBF DATA<31:0> 15:0 0000 ENHBUF 0000 SRXISEL<1:0> TXBUFELM<4:0> -- All Resets Register Name(1) Bit Range Bits 5C40 SPI3CON2 5E30 SPI1 THROUGH SPI4 REGISTER MAP (CONTINUED) -- -- -- -- 0000 0000 AUDMOD<1:0> 0000 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. This register is only available on 100-pin devices. 2: DS60001290E-page 183 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 2014-2017 Microchip Technology Inc. TABLE 17-1: PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 17-1: Bit Range 31:24 23:16 15:8 7:0 SPIxCON: SPI CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 FRMCNT<2:0> R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 MCLKSEL(2) -- -- -- -- -- SPIFE ENHBUF(2) R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ON(1) -- SIDL DISSDO MODE32 MODE16 SMP CKE(3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSEN CKP(4) MSTEN DISSDI Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set STXISEL<1:0> SRXISEL<1:0> U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31 FRMEN: Framed SPI Support bit 1 = Framed SPI support is enabled (SSx pin used as FSYNC input/output) 0 = Framed SPI support is disabled bit 30 FRMSYNC: Frame Sync Pulse Direction Control on SSx pin bit (Framed SPI mode only) 1 = Frame sync pulse input (Slave mode) 0 = Frame sync pulse output (Master mode) bit 29 FRMPOL: Frame Sync Polarity bit (Framed SPI mode only) 1 = Frame pulse is active-high 0 = Frame pulse is active-low bit 28 MSSEN: Master Mode Slave Select Enable bit 1 = Slave select SPI support enabled. The SS pin is automatically driven during transmission in Master mode. Polarity is determined by the FRMPOL bit. 0 = Slave select SPI support is disabled. bit 27 FRMSYPW: Frame Sync Pulse Width bit 1 = Frame sync pulse is one character wide 0 = Frame sync pulse is one clock wide bit 26-24 FRMCNT<2:0>: Frame Sync Pulse Counter bits. Controls the number of data characters transmitted per pulse. This bit is only valid in FRAMED_SYNC mode. 111 = Reserved; do not use 110 = Reserved; do not use 101 = Generate a frame sync pulse on every 32 data characters 100 = Generate a frame sync pulse on every 16 data characters 011 = Generate a frame sync pulse on every 8 data characters 010 = Generate a frame sync pulse on every 4 data characters 001 = Generate a frame sync pulse on every 2 data characters 000 = Generate a frame sync pulse on every data character bit 23 MCLKSEL: Master Clock Enable bit(2) 1 = REFCLK is used by the Baud Rate Generator 0 = PBCLK is used by the Baud Rate Generator bit 22-18 Unimplemented: Read as `0' Note 1: When using the 1:1 PBCLK divisor, the user software should not read or write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. 2: This bit can only be written when the ON bit = 0. 3: This bit is not used in the Framed SPI mode. The user should program this bit to `0' for the Framed SPI mode (FRMEN = 1). 4: When AUDEN = 1, the SPI module functions as if the CKP bit is equal to `1', regardless of the actual value of CKP. DS60001290E-page 184 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 17-1: SPIxCON: SPI CONTROL REGISTER (CONTINUED) bit 17 SPIFE: Frame Sync Pulse Edge Select bit (Framed SPI mode only) 1 = Frame synchronization pulse coincides with the first bit clock 0 = Frame synchronization pulse precedes the first bit clock bit 16 ENHBUF: Enhanced Buffer Enable bit(2) 1 = Enhanced Buffer mode is enabled 0 = Enhanced Buffer mode is disabled bit 15 ON: SPI Peripheral On bit(1) 1 = SPI Peripheral is enabled 0 = SPI Peripheral is disabled bit 14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue operation when CPU enters in Idle mode 0 = Continue operation in Idle mode bit 12 DISSDO: Disable SDOx pin bit 1 = SDOx pin is not used by the module. Pin is controlled by associated PORT register 0 = SDOx pin is controlled by the module bit 11-10 MODE<32,16>: 32/16-Bit Communication Select bits When AUDEN = 1: MODE32 MODE16 Communication 11 24-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame 10 32-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame 01 16-bit Data, 16-bit FIFO, 32-bit Channel/64-bit Frame 00 16-bit Data, 16-bit FIFO, 16-bit Channel/32-bit Frame When AUDEN = 0: MODE32 MODE16 Communication 1x 32-bit 01 16-bit 00 8-bit SMP: SPI Data Input Sample Phase bit Master mode (MSTEN = 1): 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time Slave mode (MSTEN = 0): SMP value is ignored when SPI is used in Slave mode. The module always uses SMP = 0. CKE: SPI Clock Edge Select bit(3) 1 = Serial output data changes on transition from active clock state to Idle clock state (see CKP bit) 0 = Serial output data changes on transition from Idle clock state to active clock state (see CKP bit) SSEN: Slave Select Enable (Slave mode) bit 1 = SSx pin used for Slave mode 0 = SSx pin not used for Slave mode, pin controlled by port function. CKP: Clock Polarity Select bit(4) 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level bit 9 bit 8 bit 7 bit 6 bit 5 Note 1: 2: 3: 4: MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode When using the 1:1 PBCLK divisor, the user software should not read or write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. This bit can only be written when the ON bit = 0. This bit is not used in the Framed SPI mode. The user should program this bit to `0' for the Framed SPI mode (FRMEN = 1). When AUDEN = 1, the SPI module functions as if the CKP bit is equal to `1', regardless of the actual value of CKP. 2014-2017 Microchip Technology Inc. DS60001290E-page 185 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 17-1: bit 4 SPIxCON: SPI CONTROL REGISTER (CONTINUED) DISSDI: Disable SDI bit 1 = SDI pin is not used by the SPI module (pin is controlled by PORT function) 0 = SDI pin is controlled by the SPI module STXISEL<1:0>: SPI Transmit Buffer Empty Interrupt Mode bits 11 = Interrupt is generated when the buffer is not full (has one or more empty elements) 10 = Interrupt is generated when the buffer is empty by one-half or more 01 = Interrupt is generated when the buffer is completely empty 00 = Interrupt is generated when the last transfer is shifted out of SPISR and transmit operations are complete SRXISEL<1:0>: SPI Receive Buffer Full Interrupt Mode bits 11 = Interrupt is generated when the buffer is full 10 = Interrupt is generated when the buffer is full by one-half or more 01 = Interrupt is generated when the buffer is not empty 00 = Interrupt is generated when the last word in the receive buffer is read (i.e., buffer is empty) bit 3-2 bit 1-0 Note 1: 2: 3: 4: When using the 1:1 PBCLK divisor, the user software should not read or write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. This bit can only be written when the ON bit = 0. This bit is not used in the Framed SPI mode. The user should program this bit to `0' for the Framed SPI mode (FRMEN = 1). When AUDEN = 1, the SPI module functions as if the CKP bit is equal to `1', regardless of the actual value of CKP. DS60001290E-page 186 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 17-2: Bit Range 31:24 23:16 15:8 7:0 SPIxCON2: SPI CONTROL REGISTER 2 Bit 31/23/15/7 Bit Bit 30/22/14/6 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit Bit Bit 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- U-0 -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPISGNEXT -- -- FRMERREN SPIROVEN R/W-0 U-0 U-0 U-0 R/W-0 U-0 AUDEN(1) -- -- -- AUDMONO(1,2) -- Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set SPITUREN IGNROV R/W-0 IGNTUR R/W-0 AUDMOD<1:0>(1,2) U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 SPISGNEXT: Sign Extend Read Data from the RX FIFO bit 1 = Data from RX FIFO is sign extended 0 = Data from RX FIFO is not sign extened bit 14-13 Unimplemented: Read as `0' bit 12 FRMERREN: Enable Interrupt Events via FRMERR bit 1 = Frame Error overflow generates error events 0 = Frame Error does not generate error events bit 11 SPIROVEN: Enable Interrupt Events via SPIROV bit 1 = Receive overflow generates error events 0 = Receive overflow does not generate error events bit 10 SPITUREN: Enable Interrupt Events via SPITUR bit 1 = Transmit Underrun Generates Error Events 0 = Transmit Underrun Does Not Generates Error Events bit 9 IGNROV: Ignore Receive Overflow bit (for Audio Data Transmissions) 1 = A ROV is not a critical error; during ROV data in the fifo is not overwritten by receive data 0 = A ROV is a critical error which stop SPI operation bit 8 IGNTUR: Ignore Transmit Underrun bit (for Audio Data Transmissions) 1 = A TUR is not a critical error and zeros are transmitted until the SPIxTXB is not empty 0 = A TUR is a critical error which stop SPI operation bit 7 AUDEN: Enable Audio CODEC Support bit(1) 1 = Audio protocol enabled 0 = Audio protocol disabled bit 6-5 Unimplemented: Read as `0' bit 3 AUDMONO: Transmit Audio Data Format bit(1,2) 1 = Audio data is mono (Each data word is transmitted on both left and right channels) 0 = Audio data is stereo bit 2 Unimplemented: Read as `0' bit 1-0 AUDMOD<1:0>: Audio Protocol Mode bit(1,2) 11 = PCM/DSP mode 10 = Right Justified mode 01 = Left Justified mode 00 = I2S mode Note 1: 2: This bit can only be written when the ON bit = 0. This bit is only valid for AUDEN = 1. 2014-2017 Microchip Technology Inc. DS60001290E-page 187 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 17-3: Bit Range 31:24 23:16 15:8 7:0 SPIxSTAT: SPI STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 U-0 R-0 SPITUR -- -- -- U-0 U-0 U-0 RXBUFELM<4:0> -- -- -- U-0 U-0 U-0 R/C-0, HS R-0 R-0 TXBUFELM<4:0> U-0 -- -- -- FRMERR SPIBUSY -- -- R-0 R/W-0 R-0 U-0 R-1 U-0 R-0 R-0 SRMT SPIROV SPIRBE -- SPITBE -- SPITBF SPIRBF Legend: C = Clearable bit HS = Set in hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-29 Unimplemented: Read as `0' bit 28-24 RXBUFELM<4:0>: Receive Buffer Element Count bits (valid only when ENHBUF = 1) bit 23-21 Unimplemented: Read as `0' bit 20-16 TXBUFELM<4:0>: Transmit Buffer Element Count bits (valid only when ENHBUF = 1) bit 15-13 Unimplemented: Read as `0' bit 12 FRMERR: SPI Frame Error status bit 1 = Frame error detected 0 = No Frame error detected This bit is only valid when FRMEN = 1. bit 11 SPIBUSY: SPI Activity Status bit 1 = SPI peripheral is currently busy with some transactions 0 = SPI peripheral is currently idle bit 10-9 Unimplemented: Read as `0' bit 8 SPITUR: Transmit Under Run bit 1 = Transmit buffer has encountered an underrun condition 0 = Transmit buffer has no underrun condition This bit is only valid in Framed Sync mode; the underrun condition must be cleared by disabling (ON bit = 0) and re-enabling (ON bit = 1) the module, or writing a `0' to SPITUR. bit 7 SRMT: Shift Register Empty bit (valid only when ENHBUF = 1) 1 = When SPI module shift register is empty 0 = When SPI module shift register is not empty bit 6 SPIROV: Receive Overflow Flag bit 1 = A new data is completely received and discarded. The user software has not read the previous data in the SPIxBUF register. 0 = No overflow has occurred This bit is set in hardware; can bit only be cleared by disabling (ON bit = 0) and re-enabling (ON bit = 1) the module, or by writing a `0' to SPIROV. bit 5 SPIRBE: RX FIFO Empty bit (valid only when ENHBUF = 1) 1 = RX FIFO is empty (CRPTR = SWPTR) 0 = RX FIFO is not empty (CRPTR SWPTR) bit 4 Unimplemented: Read as `0' DS60001290E-page 188 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 17-3: SPIxSTAT: SPI STATUS REGISTER (CONTINUED) bit 3 SPITBE: SPI Transmit Buffer Empty Status bit 1 = Transmit buffer, SPIxTXB is empty 0 = Transmit buffer, SPIxTXB is not empty Automatically set in hardware when SPI transfers data from SPIxTXB to SPIxSR. Automatically cleared in hardware when SPIxBUF is written to, loading SPIxTXB. bit 2 Unimplemented: Read as `0' bit 1 SPITBF: SPI Transmit Buffer Full Status bit 1 = Transmit not yet started, SPITXB is full 0 = Transmit buffer is not full Standard Buffer Mode: Automatically set in hardware when the core writes to the SPIBUF location, loading SPITXB. Automatically cleared in hardware when the SPI module transfers data from SPITXB to SPISR. Enhanced Buffer Mode: Set when CWPTR + 1 = SRPTR; cleared otherwise bit 0 SPIRBF: SPI Receive Buffer Full Status bit 1 = Receive buffer, SPIxRXB is full 0 = Receive buffer, SPIxRXB is not full Standard Buffer Mode: Automatically set in hardware when the SPI module transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when SPIxBUF is read from, reading SPIxRXB. Enhanced Buffer Mode: Set when SWPTR + 1 = CRPTR; cleared otherwise 2014-2017 Microchip Technology Inc. DS60001290E-page 189 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY NOTES: DS60001290E-page 190 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 18.0 Note: INTER-INTEGRATED CIRCUIT (I2C) This data sheet summarizes the features of the PIC32MX1XX/2XX/5XX 64/100-pin family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 24. "InterIntegrated Circuit (I2C)" (DS60001116) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2014-2017 Microchip Technology Inc. The I2C module provides complete hardware support for both Slave and Multi-Master modes of the I2C serial communication standard. Figure 18-1 illustrates the I2C module block diagram. Each I2C module has a 2-pin interface: the SCLx pin is clock and the SDAx pin is data. Each I2C module offers the following key features: * I2C interface supporting both master and slave operation * I2C Slave mode supports 7-bit and 10-bit addressing * I2C Master mode supports 7-bit and 10-bit addressing * I2C port allows bidirectional transfers between master and slaves * Serial clock synchronization for the I2C port can be used as a handshake mechanism to suspend and resume serial transfer (SCLREL control) * I2C supports multi-master operation; detects bus collision and arbitrates accordingly * Provides support for address bit masking DS60001290E-page 191 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY FIGURE 18-1: I2C BLOCK DIAGRAM Internal Data Bus I2CxRCV Read SCLx Shift Clock I2CxRSR LSB SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSB Read Shift Clock Reload Control BRG Down Counter Write I2CxBRG Read PBCLK DS60001290E-page 192 2014-2017 Microchip Technology Inc. Control Registers Virtual Address (BF80_#) TABLE 18-1: 5010 I2C1STAT 5020 I2C1ADD 5030 I2C1MSK 5040 I2C1BRG I2C1TRN 5060 I2C1RCV 5100 I2C2CON 5110 I2C2STAT 5120 I2C2ADD 5130 I2C2MSK 5140 I2C2BRG 5150 I2C2TRN 5160 I2C2RCV DS60001290E-page 193 Legend: Note 1: 29/13 28/12 27/11 26/10 25/9 24/8 31/15 30/14 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 31:16 ON -- -- -- SIDL -- SCLREL -- STRICT -- A10M -- DISSLW -- SMEN -- GCEN -- STREN -- ACKDT -- ACKEN -- RCEN -- PEN -- RSEN -- SEN -- BFFF 0000 15:0 ACKSTAT TRSTAT 31:16 -- -- -- -- -- -- -- -- BCL -- GCSTAT -- ADD10 -- IWCOL -- I2COV -- D_A -- P -- S -- R_W -- RBF -- TBF -- 0000 0000 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Address Register -- -- -- -- -- -- 0000 0000 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Address Mask Register -- -- -- -- -- -- 0000 0000 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Transmit Register -- -- -- -- -- 0000 0000 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Receive Register -- -- -- -- -- 0000 0000 15:0 31:16 ON -- -- -- SIDL -- SCLREL -- STRICT -- A10M -- DISSLW -- SMEN -- GCEN -- STREN -- ACKDT -- ACKEN -- RCEN -- PEN -- RSEN -- SEN -- BFFF 0000 15:0 ACKSTAT TRSTAT 31:16 -- -- -- -- -- -- -- -- BCL -- GCSTAT -- ADD10 -- IWCOL -- I2COV -- D_A -- P -- S -- R_W -- RBF -- TBF -- 0000 0000 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Address Register -- -- -- -- -- -- 0000 0000 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Address Mask Register -- -- -- -- -- -- 0000 0000 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 15:0 -- -- -- -- -- -- -- -- x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. 23/7 22/6 21/5 20/4 Baud Rate Generator Register -- -- -- Baud Rate Generator Register -- -- -- -- -- 19/3 Transmit Register -- -- Receive Register 18/2 17/1 16/0 All Resets Bit Range Register Name(1) Bits 5000 I2C1CON 5050 I2C1 AND I2C2 REGISTER MAP 0000 All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 2014-2017 Microchip Technology Inc. 18.1 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 18-1: Bit Range 31:24 23:16 15:8 7:0 I2CXCON: I2C `x' CONTROL REGISTER (`x' = 1 AND 2) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 (1) U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0 -- SIDL SCLREL STRICT A10M DISSLW SMEN R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN ON Legend: HC = Cleared in Hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: I2C Enable bit(1) 1 = Enables the I2C module and configures the SDA and SCL pins as serial port pins 0 = Disables the I2C module; all I2C pins are controlled by PORT functions bit 14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12 SCLREL: SCLx Release Control bit (when operating as I2C slave) 1 = Release SCLx clock 0 = Hold SCLx clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software can write `0' to initiate stretch and write `1' to release clock). Hardware clear at beginning of slave transmission. Hardware clear at end of slave reception. If STREN = 0: Bit is R/S (i.e., software can only write `1' to release clock). Hardware clear at beginning of slave transmission. bit 11 STRICT: Strict I2C Reserved Address Rule Enable bit 1 = Strict reserved addressing is enforced. Device does not respond to reserved address space or generate addresses in reserved address space. 0 = Strict I2C Reserved Address Rule not enabled bit 10 A10M: 10-bit Slave Address bit 1 = I2CxADD is a 10-bit slave address 0 = I2CxADD is a 7-bit slave address bit 9 DISSLW: Disable Slew Rate Control bit 1 = Slew rate control disabled 0 = Slew rate control enabled bit 8 SMEN: SMBus Input Levels bit 1 = Enable I/O pin thresholds compliant with SMBus specification 0 = Disable SMBus input thresholds Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. DS60001290E-page 194 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 18-1: I2CXCON: I2C `x' CONTROL REGISTER (CONTINUED)(`x' = 1 AND 2) bit 7 GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enable interrupt when a general call address is received in the I2CxRSR (module is enabled for reception) 0 = General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with SCLREL bit. 1 = Enable software or receive clock stretching 0 = Disable software or receive clock stretching bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive) Value that is transmitted when the software initiates an Acknowledge sequence. 1 = Send NACK during Acknowledge 0 = Send ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master, applicable during master receive) 1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. Hardware clear at end of master Acknowledge sequence. 0 = Acknowledge sequence not in progress bit 3 RCEN: Receive Enable bit (when operating as I2C master) 1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte. 0 = Receive sequence not in progress bit 2 PEN: Stop Condition Enable bit (when operating as I2C master) 1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence. 0 = Stop condition not in progress bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I2C master) 1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master Repeated Start sequence. 0 = Repeated Start condition not in progress bit 0 SEN: Start Condition Enable bit (when operating as I2C master) 1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence. 0 = Start condition not in progress Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. 2014-2017 Microchip Technology Inc. DS60001290E-page 195 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 18-2: Bit Range 31:24 23:16 15:8 7:0 I2CXSTAT: I2C STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC ACKSTAT TRSTAT -- -- -- BCL GCSTAT ADD10 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC IWCOL I2COV D_A P S R_W RBF TBF Legend: HS = Set in hardware HSC = Hardware set/cleared R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared C = Clearable bit bit 31-16 Unimplemented: Read as `0' bit 15 ACKSTAT: Acknowledge Status bit (when operating as I2C master, applicable to master transmit operation) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave Hardware set or clear at end of slave Acknowledge. bit 14 TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge. bit 13-11 Unimplemented: Read as `0' bit 10 BCL: Master Bus Collision Detect bit 1 = A bus collision has been detected during a master operation 0 = No collision Hardware set at detection of bus collision. This condition can only be cleared by disabling (ON bit = 0) and re-enabling (ON bit = 1) the module. bit 9 GCSTAT: General Call Status bit 1 = General call address was received 0 = General call address was not received Hardware set when address matches general call address. Hardware clear at Stop detection. bit 8 ADD10: 10-bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection. bit 7 IWCOL: Write Collision Detect bit 1 = An attempt to write the I2CxTRN register failed because the I2C module is busy 0 = No collision Hardware set at occurrence of write to I2CxTRN while busy (cleared by software). bit 6 I2COV: Receive Overflow Flag bit 1 = A byte was received while the I2CxRCV register is still holding the previous byte 0 = No overflow Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software). bit 5 D_A: Data/Address bit (when operating as I2C slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was device address Hardware clear at device address match. Hardware set by reception of slave byte. DS60001290E-page 196 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 18-2: I2CXSTAT: I2C STATUS REGISTER (CONTINUED) bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 2 R_W: Read/Write Information bit (when operating as I2C slave) 1 = Read - indicates data transfer is output from slave 0 = Write - indicates data transfer is input to slave Hardware set or clear after reception of I 2C device address byte. bit 1 RBF: Receive Buffer Full Status bit 1 = Receive complete, I2CxRCV is full 0 = Receive not complete, I2CxRCV is empty Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. 2014-2017 Microchip Technology Inc. DS60001290E-page 197 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY NOTES: DS60001290E-page 198 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 19.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) Note: This data sheet summarizes the features of the PIC32MX1XX/2XX/5XX 64/100-pin family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 21. "Universal Asynchronous Receiver Transmitter (UART)" (DS60001107) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). The UART module is one of the serial I/O modules available in PIC32MX1XX/2XX/5XX 64/100-pin family devices. The UART is a full-duplex, asynchronous communication channel that communicates with peripheral devices and personal computers through protocols, such as RS-232, RS-485, LIN and IrDA(R). The module also supports the hardware flow control option, with UxCTS and UxRTS pins, and also includes an IrDA encoder and decoder. FIGURE 19-1: The primary features of the UART module are: * * * * * * * * * * * * * Full-duplex, 8-bit or 9-bit data transmission Even, odd or no parity options (for 8-bit data) One or two Stop bits Hardware auto-baud feature Hardware flow control option Fully integrated Baud Rate Generator (BRG) with 16-bit prescaler Baud rates ranging from 38 bps to 12.5 Mbps at 50 MHz 8-level deep First-In-First-Out (FIFO) transmit data buffer 8-level deep FIFO receive data buffer Parity, framing and buffer overrun error detection Support for interrupt-only on address detect (9th bit = 1) Separate transmit and receive interrupts Loopback mode for diagnostic support * LIN Protocol support * IrDA encoder and decoder with 16x baud clock output for external IrDA encoder/decoder support Figure 19-1 illustrates a simplified block diagram of the UART. UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA(R) Hardware Flow Control Note: UxRTS/BCLKx UxCTS UARTx Receiver UxRX UARTx Transmitter UxTX Not all pins are available for all UART modules. Refer to the device-specific pin diagram for more information. 2014-2017 Microchip Technology Inc. DS60001290E-page 199 Control Registers Register Name 6000 U1MODE(1) U1STA(1) 6030 U1TXREG U1RXREG U1BRG(1) 6040 6200 U2MODE(1) U2STA(1) 6210 6220 6230 U2TXREG U2RXREG U2BRG(1) 6240 2014-2017 Microchip Technology Inc. 6400 U3MODE(1) U3STA(1) 6410 6420 6430 U3TXREG U3RXREG Bit Range Bits 6010 6020 UART1 THROUGH UART5 REGISTER MAP 31/15 30/14 31:16 -- -- -- 15:0 ON -- SIDL 31:16 -- -- -- 15:0 UTXISEL<1:0> 29/13 28/12 27/11 26/10 25/9 24/8 -- -- -- -- -- IREN RTSMD -- -- -- -- -- ADM_EN UTXINV URXEN UTXBRK UTXEN UTXBF TRMT UEN<1:0> 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- TX8 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- RX8 31:16 -- -- -- -- -- -- -- -- 15:0 31:16 15:0 -- -- -- -- -- ON -- SIDL IREN RTSMD -- 31:16 -- -- -- -- -- -- -- ADM_EN UTXINV URXEN UTXBRK UTXEN UTXBF TRMT UTXISEL<1:0> -- -- UEN<1:0> 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- TX8 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- RX8 31:16 -- -- -- -- -- -- -- -- 15:0 21/5 20/4 19/3 18/2 17/1 -- -- -- -- -- -- -- WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> 16/0 -- 0000 STSEL 0000 ADDR<7:0> URXISEL<1:0> 0000 ADDEN RIDLE PERR FERR OERR URXDA FFFF -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- Transmit Register -- -- 0000 Receive Register -- -- 0000 -- -- -- -- -- -- -- -- 0000 STSEL 0000 -- -- -- -- WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> ADDR<7:0> 0000 ADDEN RIDLE PERR FERR OERR URXDA FFFF -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- Transmit Register -- -- 0000 Receive Register -- -- 31:16 15:0 -- -- -- -- -- ON -- SIDL IREN RTSMD -- 31:16 -- -- -- -- -- -- -- ADM_EN UTXINV URXEN UTXBRK UTXEN UTXBF TRMT UTXISEL<1:0> -- -- UEN<1:0> 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- TX8 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- RX8 0000 -- -- -- -- -- -- -- -- 0000 STSEL 0000 -- -- -- WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> ADDR<7:0> 0000 ADDEN RIDLE PERR FERR OERR URXDA FFFF -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- Transmit Register -- -- 0000 Receive Register x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. This register is only available on 100-pin devices. 2: 0000 0000 -- Legend: 1: 0000 -- -- URXISEL<1:0> 0000 0000 -- URXISEL<1:0> 0000 -- Baud Rate Generator Prescaler -- 15:0 22/6 Baud Rate Generator Prescaler -- 15:0 23/7 All Resets Virtual Address (BF80_#) TABLE 19-1: 0000 0000 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 200 19.1 Register Name U3BRG(1) 6600 U4MODE 6610 6620 U4STA Bit Range Bits (1) (1) U4TXREG 6630 U4RXREG 6640 U4BRG(1) 6800 U5MODE(1,2) 6810 U5STA(1,2) 6820 U5TXREG(1,2) 6830 U5RXREG(1,2) 6840 U5BRG(1,2) 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 STSEL 0000 15:0 Baud Rate Generator Prescaler 31:16 15:0 -- -- -- -- -- -- ON -- SIDL IREN RTSMD -- 31:16 -- -- -- -- -- -- -- ADM_EN UTXINV URXEN UTXBRK UTXEN UTXBF TRMT 15:0 UTXISEL<1:0> -- -- UEN<1:0> 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- TX8 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- RX8 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- ON -- SIDL IREN RTSMD -- 31:16 -- -- -- -- -- -- -- ADM_EN UTXINV URXEN UTXBRK UTXEN UTXBF TRMT UTXISEL<1:0> -- -- UEN<1:0> 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- TX8 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- RX8 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> ADDR<7:0> URXISEL<1:0> 0000 ADDEN RIDLE PERR FERR OERR URXDA FFFF -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- Transmit Register -- -- 0000 Receive Register -- -- 0000 -- -- -- -- -- -- -- -- 0000 STSEL 0000 -- -- -- WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> ADDR<7:0> 0000 ADDEN RIDLE PERR FERR OERR URXDA FFFF -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- -- -- -- Transmit Register -- -- 0000 Receive Register -- -- -- -- Baud Rate Generator Prescaler x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. This register is only available on 100-pin devices. 2: 0000 0000 Legend: 1: 0000 0000 -- -- 0000 -- -- URXISEL<1:0> 0000 0000 -- Baud Rate Generator Prescaler 31:16 15:0 15:0 All Resets Virtual Address (BF80_#) 6440 UART1 THROUGH UART5 REGISTER MAP (CONTINUED) 0000 0000 DS60001290E-page 201 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 2014-2017 Microchip Technology Inc. TABLE 19-1: PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 19-1: Bit Range 31:24 23:16 15:8 7:0 UxMODE: UARTx MODE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 (1) U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 -- SIDL IREN RTSMD -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD RXINV BRGH ON UEN<1:0> R/W-0 PDSEL<1:0> R/W-0 STSEL Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: UARTx Enable bit(1) 1 = UARTx is enabled. UARTx pins are controlled by UARTx as defined by UEN<1:0> and UTXEN control bits 0 = UARTx is disabled. All UARTx pins are controlled by corresponding bits in the PORTx, TRISx and LATx registers; UARTx power consumption is minimal bit 14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue operation when device enters Idle mode 0 = Continue operation in Idle mode bit 12 IREN: IrDA Encoder and Decoder Enable bit 1 = IrDA is enabled 0 = IrDA is disabled bit 11 RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin is in Simplex mode 0 = UxRTS pin is in Flow Control mode bit 10 Unimplemented: Read as `0' bit 9-8 UEN<1:0>: UARTx Enable bits 11 = UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by corresponding bits in the PORTx register 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits in the PORTx register 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by corresponding bits in the PORTx register bit 7 WAKE: Enable Wake-up on Start bit Detect During Sleep Mode bit 1 = Wake-up enabled 0 = Wake-up disabled bit 6 LPBACK: UARTx Loopback Mode Select bit 1 = Loopback mode is enabled 0 = Loopback mode is disabled Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. DS60001290E-page 202 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 19-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 5 ABAUD: Auto-Baud Enable bit 1 = Enable baud rate measurement on the next character - requires reception of Sync character (0x55); cleared by hardware upon completion 0 = Baud rate measurement disabled or completed bit 4 RXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is `0' 0 = UxRX Idle state is `1' bit 3 BRGH: High Baud Rate Enable bit 1 = High-Speed mode - 4x baud clock enabled 0 = Standard Speed mode - 16x baud clock enabled bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Selection bit 1 = 2 Stop bits 0 = 1 Stop bit Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. 2014-2017 Microchip Technology Inc. DS60001290E-page 203 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 19-2: Bit Range 31:24 23:16 15:8 7:0 UxSTA: UARTx STATUS AND CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 -- -- -- -- -- -- -- ADM_EN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR<7:0> R/W-0 R/W-0 UTXISEL<1:0> R/W-0 R/W-0 URXISEL<1:0> R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-1 UTXINV URXEN UTXBRK UTXEN UTXBF TRMT R/W-0 R-1 R-0 R-0 R/W-0 R-0 ADDEN RIDLE PERR FERR OERR URXDA Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-25 Unimplemented: Read as `0' bit 24 ADM_EN: Automatic Address Detect Mode Enable bit 1 = Automatic Address Detect mode is enabled 0 = Automatic Address Detect mode is disabled bit 23-16 ADDR<7:0>: Automatic Address Mask bits When the ADM_EN bit is `1', this value defines the address character to use for automatic address detection. bit 15-14 UTXISEL<1:0>: TX Interrupt Mode Selection bits 11 = Reserved, do not use 10 = Interrupt is generated and asserted while the transmit buffer is empty 01 = Interrupt is generated and asserted when all characters have been transmitted 00 =Interrupt is generated and asserted while the transmit buffer contains at least one empty space bit 13 UTXINV: Transmit Polarity Inversion bit If IrDA mode is disabled (i.e., IREN (UxMODE<12>) is `0'): 1 = UxTX Idle state is `0' 0 = UxTX Idle state is `1' If IrDA mode is enabled (i.e., IREN (UxMODE<12>) is `1'): 1 = IrDA encoded UxTX Idle state is `1' 0 = IrDA encoded UxTX Idle state is `0' bit 12 URXEN: Receiver Enable bit 1 = UARTx receiver is enabled. UxRX pin is controlled by UARTx (if ON = 1) 0 = UARTx receiver is disabled. UxRX pin is ignored by the UARTx module. UxRX pin is controlled by the port. bit 11 UTXBRK: Transmit Break bit 1 = Send Break on next transmission. Start bit followed by twelve `0' bits, followed by Stop bit; cleared by hardware upon completion 0 = Break transmission is disabled or completed bit 10 UTXEN: Transmit Enable bit 1 = UARTx transmitter is enabled. UxTX pin is controlled by UARTx (if ON = 1) 0 = UARTx transmitter is disabled. Any pending transmission is aborted and buffer is reset. UxTX pin is controlled by the port. bit 9 UTXBF: Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written DS60001290E-page 204 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 19-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 8 TRMT: Transmit Shift Register is Empty bit (read-only) 1 = Transmit shift register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bit 11 = Reserved; do not use 10 = Interrupt flag bit is asserted while receive buffer is 3/4 or more full (i.e., has 6 or more data characters) 01 = Interrupt flag bit is asserted while receive buffer is 1/2 or more full (i.e., has 4 or more data characters) 00 =Interrupt flag bit is asserted while receive buffer is not empty (i.e., has at least 1 data character) bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode is enabled. If 9-bit mode is not selected, this control bit has no effect 0 = Address Detect mode is disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Data is being received bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character 0 = Parity error has not been detected bit 2 FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character 0 = Framing error has not been detected bit 1 OERR: Receive Buffer Overrun Error Status bit. This bit is set in hardware and can only be cleared (= 0) in software. Clearing a previously set OERR bit resets the receiver buffer and RSR to empty state. 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed bit 0 URXDA: Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty 2014-2017 Microchip Technology Inc. DS60001290E-page 205 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 19.2 Timing Diagrams Figure 19-2 and Figure 19-3 illustrate typical receive and transmit timing for the UART module. FIGURE 19-2: UART RECEPTION Char 1 Char 2-4 Char 5-10 Char 11-13 Read to UxRXREG Start 1 Stop Start 2 Stop 4 Start 5 Stop 10 Start 11 Stop 13 UxRX RIDLE Cleared by Software OERR Cleared by Software UxRXIF URXISEL = 00 Cleared by Software UxRXIF URXISEL = 01 UxRXIF URXISEL = 10 FIGURE 19-3: TRANSMISSION (8-BIT OR 9-BIT DATA) 8 into TxBUF Write to UxTXREG TSR Pull from Buffer BCLK/16 (Shift Clock) UxTX Start Bit 0 Bit 1 Stop Start Bit 1 UxTXIF UTXISEL = 00 UxTXIF UTXISEL = 01 UxTXIF UTXISEL = 10 DS60001290E-page 206 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 20.0 PARALLEL MASTER PORT (PMP) Note: This data sheet summarizes the features of the PIC32MX1XX/2XX/5XX 64/100-pin family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 13. "Parallel Master Port (PMP)" (DS60001128) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). The PMP is a parallel 8-bit or 16-bit input/output module specifically designed to communicate with a wide variety of parallel devices, such as communications peripherals, LCDs, external memory devices and microcontrollers. Because the interface to parallel peripherals varies significantly, the PMP module is highly configurable. The following are the key features of the PMP module: * * * * * * * * * * * * * 8-bit,16-bit interface Up to 16 programmable address lines Up to two Chip Select lines Programmable strobe options: - Individual read and write strobes, or - Read/write strobe with enable strobe - Selectable polarity Address auto-increment/auto-decrement Programmable address/data multiplexing Programmable polarity on control signals Parallel Slave Port support: - Legacy addressable - Address support Read and Write 4-byte deep auto-incrementing buffer Programmable Wait states Operate during CPU Sleep and Idle modes Fast bit manipulation using CLR, SET and INV registers Freeze option for in-circuit debugging Note: FIGURE 20-1: On 64-pin devices, data pins PMD<15:8> are not available in 16-bit Master modes. PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES Address Bus Data Bus Parallel Master Port Control Lines PMA<0> PMALL PMA<1> PMALH Flash EEPROM SRAM Up to 16-bit Address PMA<13:2> PMA<14> PMCS1 PMA<15> PMCS2 PMRD PMRD/PMWR PMWR PMENB PMD<7:0> PMD<15:8>(1) Note: Microcontroller LCD FIFO Buffer 8-bit/16-bit Data (with or without multiplexed addressing) On 64-pin devices, data pins PMD<15:8> are not available in 16-bit Master modes. 2014-2017 Microchip Technology Inc. DS60001290E-page 207 Control Registers Virtual Address (BF80_#) Register Name(1) TABLE 20-1: 7000 PMCON 7020 PMADDR 7030 PMDOUT 7040 PMDIN 7050 PMAEN PMSTAT 7070 PMWADDR 31/15 30/14 31:16 -- -- -- 15:0 31:16 ON -- -- -- SIDL -- 15:0 31:16 BUSY -- 15:0 CS2 ADDR15 CS1 ADDR14 31:16 -- -- 2014-2017 Microchip Technology Inc. 7090 PMRDIN Legend: Note 1: IRQM<1:0> -- -- 28/12 27/11 -- -- ADRMUX<1:0> -- -- INCM<1:0> -- -- 26/10 25/9 24/8 23/7 22/6 -- -- -- RDSTART -- 31:16 -- -- 18/2 17/1 16/0 -- -- -- -- DUALBUF -- 0000 CS2P -- CS1P -- -- -- WRSP -- RDSP -- 0000 0000 MODE16 -- WAITB<1:0> -- -- -- MODE<1:0> -- -- WAITM<3:0> -- -- -- WAITE<1:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- DATAOUT<15:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PTEN<15:0> -- -- -- -- -- -- -- -- -- 0000 OBE -- OBUF -- -- -- -- -- OB3E -- OB2E -- OB1E -- OB0E -- BFBF 0000 -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- 0000 -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- -- -- 15:0 31:16 IBF -- IBOV -- -- -- -- -- IB3F -- IB2F -- IB1F -- IB0F -- WCS2 WCS1 -- -- -- -- -- -- WADDR15 WADDR14 -- -- -- -- -- -- -- -- RCS2 RCS1 -- -- -- -- -- -- RADDR15 RADDR14 15:0 15:0 -- -- -- -- -- 0000 -- -- 31:16 0000 -- -- 31:16 0000 0000 DATAIN<15:0> -- 0000 0000 0000 0000 ADDR<13:0> 31:16 15:0 19/3 ALP -- 15:0 15:0 20/4 CSF<1:0> -- -- 15:0 31:16 21/5 PMPTTL PTWREN PTRDEN -- -- -- 15:0 31:16 7080 PMRADDR 29/13 All Resets Bit Range Bits 7010 PMMODE 7060 PARALLEL MASTER PORT REGISTER MAP -- -- 0000 0000 WADDR<13:0> -- -- -- -- RADDR<13:0> -- -- RDATAIN<15:0> 0000 0000 0000 0000 x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 208 20.1 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 20-1: Bit Range 31:24 23:16 15:8 7:0 PMCON: PARALLEL PORT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0, HC U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 RDSTART -- -- -- -- -- DUALBUF -- R/W-0 (1) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- SIDL PMPTTL PTWREN PTRDEN R/W-0 R/W-0 (2) R/W-0 (2) U-0 R/W-0 R/W-0 -- WRSP RDSP ON CSF<1:0> Legend: R = Readable bit -n = Value at POR ALP ADRMUX<1:0> R/W-0 (2) CS2P HC = Hardware cleared W = Writable bit `1' = Bit is set R/W-0 (2) CS1P U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as `0' bit 23 RDSTART: Start a Read on the PMP Bus bit(3) 1 = Start a read cycle on the PMP bus 0 = No effect This bit is cleared by hardware at the end of the read cycle when the BUSY bit (PMMODE<15>) = 0. bit 22-18 Unimplemented: Read as `0' bit 17 DUALBUF: Parallel Master Port Dual Read/Write Buffer Enable bit This bit is only valid in Master mode. 1 = PMP uses separate registers for reads and writes Reads: PMRADDR and PMRDIN Writes: PMRWADDR and PMDOUT 0 = PMP uses legacy registers for reads and writes Reads/Writes: PMADDR and PMRDIN bit 16 Unimplemented: Read as `0' bit 15 ON: Parallel Master Port Enable bit(1) 1 = PMP enabled 0 = PMP disabled, no off-chip access performed bit 14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits 11 = Lower 8 bits of address are multiplexed on PMD<15:0> pins 10 = All 16 bits of address are multiplexed on PMD<7:0> pins 01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper bits are on PMA<15:8> 00 = Address and data appear on separate pins bit 10 PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt Trigger input buffer bit 9 PTWREN: Write Enable Strobe Port Enable bit 1 = PMWR/PMENB port enabled 0 = PMWR/PMENB port disabled Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON control bit. 2: These bits have no effect when their corresponding pins are used as address lines. 2014-2017 Microchip Technology Inc. DS60001290E-page 209 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 20-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED) bit 8 PTRDEN: Read/Write Strobe Port Enable bit 1 = PMRD/PMWR port enabled 0 = PMRD/PMWR port disabled bit 7-6 CSF<1:0>: Chip Select Function bits(2) 11 = Reserved 10 = PMCS1 and PMCS2 function as Chip Select 01 = PMCS1 functions as address bit 14; PMCS2 functions as Chip Select 00 = PMCS1 and PMCS2 function as address bits 14 and 15, respectively ALP: Address Latch Polarity bit(2) 1 = Active-high (PMALL and PMALH) 0 = Active-low (PMALL and PMALH) CS2P: Chip Select 0 Polarity bit(2) 1 = Active-high (PMCS2) 0 = Active-low (PMCS2) CS1P: Chip Select 0 Polarity bit(2) 1 = Active-high (PMCS1) 0 = Active-low (PMCS1) Unimplemented: Read as `0' WRSP: Write Strobe Polarity bit For Slave Modes and Master mode 2 (MODE<1:0> = 00,01,10): 1 = Write strobe active-high (PMWR) 0 = Write strobe active-low (PMWR) bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 For Master mode 1 (MODE<1:0> = 11): 1 = Enable strobe active-high (PMENB) 0 = Enable strobe active-low (PMENB) RDSP: Read Strobe Polarity bit For Slave modes and Master mode 2 (MODE<1:0> = 00,01,10): 1 = Read Strobe active-high (PMRD) 0 = Read Strobe active-low (PMRD) For Master mode 1 (MODE<1:0> = 11): 1 = Read/write strobe active-high (PMRD/PMWR) 0 = Read/write strobe active-low (PMRD/PMWR) Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON control bit. 2: These bits have no effect when their corresponding pins are used as address lines. DS60001290E-page 210 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 20-2: Bit Range 31:24 23:16 15:8 PMMODE: PARALLEL PORT MODE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUSY R/W-0 7:0 IRQM<1:0> R/W-0 R/W-0 WAITB<1:0>(1) INCM<1:0> R/W-0 MODE16 R/W-0 MODE<1:0> R/W-0 R/W-0 WAITM<3:0>(1) R/W-0 WAITE<1:0>(1) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 BUSY: Busy bit (Master mode only) 1 = Port is busy 0 = Port is not busy bit 14-13 IRQM<1:0>: Interrupt Request Mode bits 11 = Reserved, do not use 10 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode) or on a read or write operation when PMA<1:0> =11 (Addressable Slave mode only) 01 = Interrupt generated at the end of the read/write cycle 00 = No Interrupt generated bit 12-11 INCM<1:0>: Increment Mode bits 11 = Slave mode read and write buffers auto-increment (MODE<1:0> = 00 only) 10 = Decrement ADDR<15:0> by 1 every read/write cycle(2) 01 = Increment ADDR<15:0> by 1 every read/write cycle(2) 00 = No increment or decrement of address bit 10 MODE16: 8/16-bit Mode bit 1 = 16-bit mode: a read or write to the data register invokes a single 16-bit transfer 0 = 8-bit mode: a read or write to the data register invokes a single 8-bit transfer bit 9-8 MODE<1:0>: Parallel Port Mode Select bits 11 = Master mode 1 (PMCSx, PMRD/PMWR, PMENB, PMA<x:0>, PMD<7:0> and PMD<8:15>(3)) 10 = Master mode 2 (PMCSx, PMRD, PMWR, PMA<x:0>, PMD<7:0> and PMD<8:15>(3)) 01 = Enhanced Slave mode, control signals (PMRD, PMWR, PMCS, PMD<7:0> and PMA<1:0>) 00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS and PMD<7:0>) bit 7-6 WAITB<1:0>: Data Setup to Read/Write Strobe Wait States bits(1) 11 = Data wait of 4 TPB; multiplexed address phase of 4 TPB 10 = Data wait of 3 TPB; multiplexed address phase of 3 TPB 01 = Data wait of 2 TPB; multiplexed address phase of 2 TPB 00 = Data wait of 1 TPB; multiplexed address phase of 1 TPB (default) Note 1: Whenever WAITM<3:0> = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for a write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation. 2: Address bits, A15 and A14, are not subject to automatic increment/decrement if configured as Chip Select CS2 and CS1. 3: These pins are active when MODE16 = 1 (16-bit mode). 2014-2017 Microchip Technology Inc. DS60001290E-page 211 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 20-2: PMMODE: PARALLEL PORT MODE REGISTER (CONTINUED) bit 5-2 WAITM<3:0>: Data Read/Write Strobe Wait States bits(1) 1111 = Wait of 16 TPB * * * 0001 = Wait of 2 TPB 0000 = Wait of 1 TPB (default) bit 1-0 WAITE<1:0>: Data Hold After Read/Write Strobe Wait States bits(1) 11 = Wait of 4 TPB 10 = Wait of 3 TPB 01 = Wait of 2 TPB 00 = Wait of 1 TPB (default) For Read operations: 11 = Wait of 3 TPB 10 = Wait of 2 TPB 01 = Wait of 1 TPB 00 = Wait of 0 TPB (default) Note 1: Whenever WAITM<3:0> = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for a write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation. 2: Address bits, A15 and A14, are not subject to automatic increment/decrement if configured as Chip Select CS2 and CS1. 3: These pins are active when MODE16 = 1 (16-bit mode). DS60001290E-page 212 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 20-3: Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 (1) R/W-0 (3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CS2 ADDR15 7:0 PMADDR: PARALLEL PORT ADDRESS REGISTER R/W-0 CS1 (2) ADDR<13:8> ADDR14(4) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 CS2: Chip Select 2 bit(1) 1 = Chip Select 2 is active 0 = Chip Select 2 is inactive bit 15 ADDR<15>: Target Address bit 15(2) bit 14 CS1: Chip Select 1 bit(3) 1 = Chip Select 1 is active 0 = Chip Select 1 is inactive bit 14 ADDR<14>: Target Address bit 14(4) bit 13-0 ADDR<13:0>: Address bits Note 1: 2: 3: 4: When the CSF<1:0> bits (PMCON<7:6>) = 10 or 01. When the CSF<1:0> bits (PMCON<7:6>) = 00. When the CSF<1:0> bits (PMCON<7:6>) = 10. When the CSF<1:0> bits (PMCON<7:6>) = 00 or 01. Note: If the DUALBUF bit (PMCON<17>) = 0, the bits in this register control both read and write target addressing. If the DUALBUF bit = 1, the bits in this register are not used. In this instance, use the PMRADDR register for Read operations and the PMWADDR register for Write operations. 2014-2017 Microchip Technology Inc. DS60001290E-page 213 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 20-4: Bit Range 31:24 23:16 15:8 7:0 PMDOUT: PARALLEL PORT OUTPUT DATA REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DATAOUT<15:8> R/W-0 R/W-0 DATAOUT<7:0> Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 DATAOUT<15:0>: Port Data Output bits This register is used for Read operations in the Enhanced Parallel Slave mode and Write operations for Dual Buffer Master mode. In Dual Buffer Master mode, the DUALBUF bit (PMPCON<17>) = 1, a write to the MSB triggers the transaction on the PMP port. When MODE16 = 1, MSB = DATAOUT<15:8>. When MODE16 = 0, MSB = DATAOUT<7:0>. Note: In Master mode, a read will return the last value written to the register. In Slave mode, a read will return indeterminate results. REGISTER 20-5: Bit Range 31:24 23:16 15:8 7:0 PMDIN: PARALLEL PORT INPUT DATA REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DATAIN<15:8> R/W-0 R/W-0 DATAIN<7:0> Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 DATAIN<15:0>: Port Data Input bits This register is used for both Parallel Master Port mode and Enhanced Parallel Slave mode. In Parallel Master mode, a write to the MSB triggers the write transaction on the PMP port. Similarly, a read to the MSB triggers the read transaction on the PMP port. When MODE16 = 1, MSB = DATAIN<15:8>. When MODE16 = 0, MSB = DATAIN<7:0>. Note: This register is not used in Dual Buffer Master mode (i.e., DUALBUF bit (PMPCON<17>) = 1). DS60001290E-page 214 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 20-6: Bit Range 31:24 23:16 15:8 7:0 PMAEN: PARALLEL PORT PIN ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN<15:14>(1) R/W-0 R/W-0 PTEN<13:8> R/W-0 PTEN<1:0>(2) PTEN<7:2> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Write `0'; ignore read bit 15-14 PTEN<15:14>: PMCSx Address Port Enable bits 1 = PMA15 and PMA14 function as either PMA<15:14> or PMCS2 and PMCS1(1) 0 = PMA15 and PMA14 function as port I/O bit 13-2 PTEN<13:2>: PMP Address Port Enable bits 1 = PMA<13:2> function as PMP address lines 0 = PMA<13:2> function as port I/O bit 1-0 PTEN<1:0>: PMALH/PMALL Address Port Enable bits 1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL(2) 0 = PMA1 and PMA0 pads function as port I/O Note 1: 2: The use of these pins as PMA15/PMA14 or CS2/CS1 is selected by the CSF<1:0> bits (PMCON<7:6>). The use of these pins as PMA1/PMA0 or PMALH/PMALL depends on the Address/Data Multiplex mode selected by the ADRMUX<1:0> bits in the PMCON register. 2014-2017 Microchip Technology Inc. DS60001290E-page 215 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 20-7: Bit Range 31:24 23:16 15:8 7:0 PMSTAT: PARALLEL PORT STATUS REGISTER (SLAVE MODES ONLY) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-0 R/W-0, HSC U-0 U-0 R-0 R-0 R-0 R-0 IB0F IBF IBOV -- -- IB3F IB2F IB1F R-1 R/W-0, HSC U-0 U-0 R-1 R-1 R-1 R-1 OBE OBUF -- -- OB3E OB2E OB1E OB0E Legend: HSC = Set by Hardware; Cleared by Software R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 IBF: Input Buffer Full Status bit 1 = All writable input buffer registers are full 0 = Some or all of the writable input buffer registers are empty bit 14 IBOV: Input Buffer Overflow Status bit 1 = A write attempt to a full input byte buffer occurred (must be cleared in software) 0 = No overflow occurred bit 13-12 Unimplemented: Read as `0' bit 11-8 IBxF: Input Buffer `x' Status Full bits 1 = Input Buffer contains data that has not been read (reading buffer will clear this bit) 0 = Input Buffer does not contain any unread data bit 7 OBE: Output Buffer Empty Status bit 1 = All readable output buffer registers are empty 0 = Some or all of the readable output buffer registers are full bit 6 OBUF: Output Buffer Underflow Status bit 1 = A read occurred from an empty output byte buffer (must be cleared in software) 0 = No underflow occurred bit 5-4 Unimplemented: Read as `0' bit 3-0 OBxE: Output Buffer `x' Status Empty bits 1 = Output buffer is empty (writing data to the buffer will clear this bit) 0 = Output buffer contains data that has not been transmitted DS60001290E-page 216 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 20-8: Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 (1) R/W-0 (3) WCS2 WADDR15 7:0 PMWADDR: PARALLEL PORT WRITE ADDRESS REGISTER R/W-0 WCS1 (2) WADDR<13:8> WADDR14(4) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WADDR<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 WCS2: Chip Select 2 bit(1) 1 = Chip Select 2 is active 0 = Chip Select 2 is inactive bit 15 WADDR<15>: Target Address bit 15(2) bit 14 WCS1: Chip Select 1 bit(3) 1 = Chip Select 1 is active 0 = Chip Select 1 is inactive bit 14 WADDR<14>: Target Address bit 14(4) bit 13-0 WADDR<13:0>: Address bits Note 1: 2: 3: 4: When the CSF<1:0> bits (PMCON<7:6>) = 10 or 01. When the CSF<1:0> bits (PMCON<7:6>) = 00. When the CSF<1:0> bits (PMCON<7:6>) = 10. When the CSF<1:0> bits (PMCON<7:6>) = 00 or 01. Note: This register is only used when the DUALBUF bit (PMCON<17>) is set to `1'. 2014-2017 Microchip Technology Inc. DS60001290E-page 217 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 20-9: Bit Range 31:24 23:16 15:8 7:0 PMRADDR: PARALLEL PORT READ ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- R/W-0 (1) RCS2 -- R/W-0 (3) -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RCS1 RADDR15(2) RADDR14(4) R/W-0 R/W-0 RADDR<13:8> R/W-0 R/W-0 R/W-0 R/W-0 RADDR<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 RCS2: Chip Select 2 bit(1) 1 = Chip Select 2 is active 0 = Chip Select 2 is inactive (RADDR15 function is selected) bit 15 RADDR<15>: Target Address bit 15(2) bit 14 RCS1: Chip Select 1 bit(3) 1 = Chip Select 1 is active 0 = Chip Select 1 is inactive (RADDR14 function is selected) bit 14 RADDR<14>: Target Address bit 14(4) bit 13-0 RADDR<13:0>: Address bits Note 1: 2: 3: 4: When the CSF<1:0> bits (PMCON<7:6>) = 10 or 01. When the CSF<1:0> bits (PMCON<7:6>) = 00. When the CSF<1:0> bits (PMCON<7:6>) = 10. When the CSF<1:0> bits (PMCON<7:6>) = 00 or 01. Note: This register is only used when the DUALBUF bit (PMCON<17>) is set to `1'. DS60001290E-page 218 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 20-10: PMRDIN: PARALLEL PORT READ INPUT DATA REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RDATAIN<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RDATAIN<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 Note: RDATAIN<15:0>: Port Read Input Data bits This register is only used when the DUALBUF bit (PMCON<17>) is set to `1' and exclusively for reads. If the DUALBUF bit is `0', the PMDIN register (Register 20-5) is used for reads instead of PMRDIN. 2014-2017 Microchip Technology Inc. DS60001290E-page 219 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY NOTES: DS60001290E-page 220 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 21.0 Note: REAL-TIME CLOCK AND CALENDAR (RTCC) This data sheet summarizes the features of the PIC32MX1XX/2XX/5XX 64/100-pin family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 29. "Real-Time Clock and Calendar (RTCC)" (DS60001125) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). The PIC32 RTCC module is intended for applications in which accurate time must be maintained for extended periods of time with minimal or no CPU intervention. Low-power optimization provides extended battery lifetime while keeping track of time. The following are the key features of this module: * * * * * * * * * * * * * * * * * FIGURE 21-1: Time: hours, minutes and seconds 24-hour format (military time) Visibility of one-half second period Provides calendar: Weekday, date, month and year Alarm intervals are configurable for half of a second, one second, 10 seconds, one minute, 10 minutes, one hour, one day, one week, one month and one year Alarm repeat with decrementing counter Alarm with indefinite repeat: Chime Year range: 2000 to 2099 Leap year correction BCD format for smaller firmware overhead Optimized for long-term battery operation Fractional second synchronization User calibration of the clock crystal frequency with auto-adjust Calibration range: 0.66 seconds error per month Calibrates up to 260 ppm of crystal error Requirements: External 32.768 kHz clock crystal Alarm pulse or seconds clock output on RTCC pin RTCC BLOCK DIAGRAM CAL<9:0> 32.768 kHz Input from Secondary Oscillator (SOSC) RTCC Prescalers RTCTIME 0.5s HR, MIN, SEC RTCC Timer Alarm Event RTCVAL RTCDATE YEAR, MONTH, DAY, WDAY Comparator ALRMTIME Compare Registers with Masks HR, MIN, SEC ALRMVAL ALRMDATE MONTH, DAY, WDAY Repeat Counter Set RTCC Flag RTCC Interrupt Logic Alarm Pulse Seconds Pulse 0 1 RTCC RTSECSEL RTCOE 2014-2017 Microchip Technology Inc. DS60001290E-page 221 Control Registers Virtual Address (BF80_#) Register Name(1) TABLE 21-1: 0200 RTCCON RTCC REGISTER MAP 0210 RTCALRM 0220 RTCTIME 0230 RTCDATE 0240 ALRMTIME 0250 ALRMDATE Legend: Note 1: 31/15 30/14 31:16 -- 15:0 31:16 ON -- 15:0 ALRMEN 31:16 29/13 28/12 27/11 26/10 -- -- -- -- -- -- -- SIDL -- -- -- -- -- -- -- CHIME PIV HR10<3:0> ALRMSYNC 25/9 24/8 -- -- -- -- 23/7 22/6 21/5 20/4 AMASK<3:0> HR01<3:0> -- -- -- -- -- -- MONTH10<3:0> -- 15:0 31:16 DAY10<3:0> HR10<3:0> DAY01<3:0> HR01<3:0> -- -- -- MIN10<3:0> -- -- -- -- MONTH10<3:0> -- -- SEC01<3:0> -- -- 0000 -- -- -- -- MONTH01<3:0> -- WDAY01<3:0> MIN01<3:0> -- -- -- MONTH01<3:0> 0000 0000 0000 xxxx MIN01<3:0> -- -- 16/0 ARPT<7:0> SEC01<3:0> YEAR01<3:0> SEC10<3:0> -- -- 17/1 RTCWREN RTCSYNC HALFSEC RTCOE -- -- -- -- MIN10<3:0> SEC10<3:0> YEAR10<3:0> -- 18/2 CAL<9:0> RTSECSEL RTCCLKON -- -- 15:0 31:16 15:0 31:16 19/3 All Resets Bit Range Bits xx00 xxxx xx00 xxxx -- xx00 00xx 15:0 DAY10<3:0> DAY01<3:0> -- -- -- -- WDAY01<3:0> xx0x x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 222 21.1 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 21-1: Bit Range 31:24 23:16 Bit 30/22/14/6 Bit Bit 29/21/13/5 28/20/12/4 U-0 U-0 U-0 -- -- -- R/W-0 R/W-0 R/W-0 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 R/W-0 R/W-0 -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 CAL<9:8> CAL<7:0> 15:8 7:0 RTCCON: RTC CONTROL REGISTER Bit 31/23/15/7 R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 ON(1,2) -- SIDL -- -- -- -- -- R/W-0 R-0 U-0 U-0 R/W-0 R-0 R-0 R/W-0 -- -- RTSECSEL(3) RTCCLKON Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set RTCWREN(4) RTCSYNC HALFSEC(5) RTCOE U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-26 Unimplemented: Read as `0' bit 25-16 CAL<9:0>: RTC Drift Calibration bits, which contain a signed 10-bit integer value 0111111111 = Maximum positive adjustment, adds 511 RTC clock pulses every one minute * * * 0000000001 = Minimum positive adjustment, adds 1 RTC clock pulse every one minute 0000000000 = No adjustment 1111111111 = Minimum negative adjustment, subtracts 1 RTC clock pulse every one minute * * * bit 15 bit 14 bit 13 bit 12-8 bit 7 bit 6 bit 5-4 Note 1: 2: 3: 4: 5: Note: 1000000000 = Maximum negative adjustment, subtracts 512 clock pulses every one minute ON: RTCC On bit(1,2) 1 = RTCC module is enabled 0 = RTCC module is disabled Unimplemented: Read as `0' SIDL: Stop in Idle Mode bit 1 = Disables the PBCLK to the RTCC when CPU enters in Idle mode 0 = Continue normal operation in Idle mode Unimplemented: Read as `0' RTSECSEL: RTCC Seconds Clock Output Select bit(3) 1 = RTCC Seconds Clock is selected for the RTCC pin 0 = RTCC Alarm Pulse is selected for the RTCC pin RTCCLKON: RTCC Clock Enable Status bit 1 = RTCC Clock is actively running 0 = RTCC Clock is not running Unimplemented: Read as `0' The ON bit is only writable when RTCWREN = 1. When using the 1:1 PBCLK divisor, the user software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. Requires RTCOE = 1 (RTCCON<0>) for the output to be active. The RTCWREN bit can be set only when the write sequence is enabled. This bit is read-only. It is cleared to `0' on a write to the seconds bit fields (RTCTIME<14:8>). This register is reset only on a Power-on Reset (POR). 2014-2017 Microchip Technology Inc. DS60001290E-page 223 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 21-1: RTCCON: RTC CONTROL REGISTER (CONTINUED) RTCWREN: RTC Value Registers Write Enable bit(4) 1 = RTC Value registers can be written to by the user 0 = RTC Value registers are locked out from being written to by the user RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTC Value registers can change while reading, due to a rollover ripple that results in an invalid data read If the register is read twice and results in the same data, the data can be assumed to be valid 0 = RTC Value registers can be read without concern about a rollover ripple HALFSEC: Half-Second Status bit(5) 1 = Second half period of a second 0 = First half period of a second RTCOE: RTCC Output Enable bit 1 = RTCC clock output enabled - clock presented onto an I/O 0 = RTCC clock output disabled bit 3 bit 2 bit 1 bit 0 Note 1: 2: 3: 4: 5: Note: The ON bit is only writable when RTCWREN = 1. When using the 1:1 PBCLK divisor, the user software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. Requires RTCOE = 1 (RTCCON<0>) for the output to be active. The RTCWREN bit can be set only when the write sequence is enabled. This bit is read-only. It is cleared to `0' on a write to the seconds bit fields (RTCTIME<14:8>). This register is reset only on a Power-on Reset (POR). DS60001290E-page 224 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 21-2: Bit Range 31:24 23:16 15:8 7:0 RTCALRM: RTC ALARM CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit Bit 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 -- -- -- U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R-0 R/W-0 R/W-0 CHIME(2) R/W-0 (3) R/W-0 ALRMEN(1,2) R/W-0 (2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PIV ALRMSYNC(3) R/W-0 AMASK<3:0> R/W-0 ARPT<7:0>(3) Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ALRMEN: Alarm Enable bit(1,2) 1 = Alarm is enabled 0 = Alarm is disabled bit 14 CHIME: Chime Enable bit(2) 1 = Chime is enabled - ARPT<7:0> is allowed to rollover from 0x00 to 0xFF 0 = Chime is disabled - ARPT<7:0> stops once it reaches 0x00 bit 13 PIV: Alarm Pulse Initial Value bit(2) When ALRMEN = 0, PIV is writable and determines the initial value of the Alarm Pulse. When ALRMEN = 1, PIV is read-only and returns the state of the Alarm Pulse. bit 12 ALRMSYNC: Alarm Sync bit(3) 1 = ARPT<7:0> and ALRMEN may change as a result of a half second rollover during a read. The ARPT must be read repeatedly until the same value is read twice. This must be done since multiple bits may be changing, which are then synchronized to the PB clock domain 0 = ARPT<7:0> and ALRMEN can be read without concerns of rollover because the prescaler is > 32 RTC clocks away from a half-second rollover bit 11-8 AMASK<3:0>: Alarm Mask Configuration bits(3) 0000 = Every half-second 0001 = Every second 0010 = Every 10 seconds 0011 = Every minute 0100 = Every 10 minutes 0101 = Every hour 0110 = Once a day 0111 = Once a week 1000 = Once a month 1001 = Once a year (except when configured for February 29, once every four years) 1010 = Reserved; do not use 1011 = Reserved; do not use 11xx = Reserved; do not use Note 1: 2: 3: Note: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and CHIME = 0. This field should not be written when the RTCC ON bit = `1' (RTCCON<15>) and ALRMSYNC = 1. This assumes a CPU read will execute in less than 32 PBCLKs. This register is reset only on a Power-on Reset (POR). 2014-2017 Microchip Technology Inc. DS60001290E-page 225 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 21-2: RTCALRM: RTC ALARM CONTROL REGISTER (CONTINUED) ARPT<7:0>: Alarm Repeat Counter Value bits(3) 11111111 =Alarm will trigger 256 times bit 7-0 * * * 00000000 =Alarm will trigger one time The counter decrements on any alarm event. The counter only rolls over from 0x00 to 0xFF if CHIME = 1. Note 1: 2: 3: Note: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and CHIME = 0. This field should not be written when the RTCC ON bit = `1' (RTCCON<15>) and ALRMSYNC = 1. This assumes a CPU read will execute in less than 32 PBCLKs. This register is reset only on a Power-on Reset (POR). DS60001290E-page 226 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 21-3: Bit Range 31:24 23:16 15:8 7:0 RTCTIME: RTC TIME VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x HR10<3:0> R/W-x R/W-x HR01<3:0> R/W-x R/W-x R/W-x R/W-x MIN10<3:0> R/W-x R/W-x R/W-x R/W-x R/W-x MIN01<3:0> R/W-x R/W-x R/W-x SEC10<3:0> R/W-x R/W-x SEC01<3:0> U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-28 HR10<3:0>: Binary-Coded Decimal Value of Hours bits, 10s place digits; contains a value from 0 to 2 bit 27-24 HR01<3:0>: Binary-Coded Decimal Value of Hours bits, 1s place digit; contains a value from 0 to 9 bit 23-20 MIN10<3:0>: Binary-Coded Decimal Value of Minutes bits, 10s place digits; contains a value from 0 to 5 bit 19-16 MIN01<3:0>: Binary-Coded Decimal Value of Minutes bits, 1s place digit; contains a value from 0 to 9 bit 15-12 SEC10<3:0>: Binary-Coded Decimal Value of Seconds bits, 10s place digits; contains a value from 0 to 5 bit 11-8 SEC01<3:0>: Binary-Coded Decimal Value of Seconds bits, 1s place digit; contains a value from 0 to 9 bit 7-0 Unimplemented: Read as `0' Note: This register is only writable when RTCWREN = 1 (RTCCON<3>). 2014-2017 Microchip Technology Inc. DS60001290E-page 227 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 21-4: Bit Range 31:24 23:16 15:8 7:0 RTCDATE: RTC DATE VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x YEAR10<3:0> R/W-x YEAR01<3:0> MONTH10<3:0> R/W-x R/W-x U-0 U-0 -- -- R/W-x R/W-x R/W-x MONTH01<3:0> R/W-x R/W-x R/W-x U-0 U-0 R/W-x R/W-x -- -- DAY10<3:0> R/W-x R/W-x DAY01<3:0> R/W-x R/W-x WDAY01<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-28 YEAR10<3:0>: Binary-Coded Decimal Value of Years bits, 10s place digits bit 27-24 YEAR01<3:0>: Binary-Coded Decimal Value of Years bits, 1s place digit bit 23-20 MONTH10<3:0>: Binary-Coded Decimal Value of Months bits, 10s place digits; contains a value of 0 or 1 bit 19-16 MONTH01<3:0>: Binary-Coded Decimal Value of Months bits, 1s place digit; contains a value from 0 to 9 bit 15-12 DAY10<3:0>: Binary-Coded Decimal Value of Days bits, 10s place digits; contains a value from 0 to 3 bit 11-8 DAY01<3:0>: Binary-Coded Decimal Value of Days bits, 1s place digit; contains a value from 0 to 9 bit 7-4 Unimplemented: Read as `0' bit 3-0 WDAY01<3:0>: Binary-Coded Decimal Value of Weekdays bits,1s place digit; contains a value from 0 to 6 Note: This register is only writable when RTCWREN = 1 (RTCCON<3>). DS60001290E-page 228 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 21-5: Bit Range 31:24 23:16 15:8 7:0 ALRMTIME: ALARM TIME VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x HR10<3:0> R/W-x R/W-x HR01<3:0> R/W-x R/W-x R/W-x R/W-x MIN10<3:0> R/W-x R/W-x R/W-x R/W-x R/W-x MIN01<3:0> R/W-x R/W-x R/W-x SEC10<3:0> R/W-x R/W-x SEC01<3:0> U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-28 HR10<3:0>: Binary Coded Decimal value of hours bits, 10s place digits; contains a value from 0 to 2 bit 27-24 HR01<3:0>: Binary Coded Decimal value of hours bits, 1s place digit; contains a value from 0 to 9 bit 23-20 MIN10<3:0>: Binary Coded Decimal value of minutes bits, 10s place digits; contains a value from 0 to 5 bit 19-16 MIN01<3:0>: Binary Coded Decimal value of minutes bits, 1s place digit; contains a value from 0 to 9 bit 15-12 SEC10<3:0>: Binary Coded Decimal value of seconds bits, 10s place digits; contains a value from 0 to 5 bit 11-8 SEC01<3:0>: Binary Coded Decimal value of seconds bits, 1s place digit; contains a value from 0 to 9 bit 7-0 Unimplemented: Read as `0' 2014-2017 Microchip Technology Inc. DS60001290E-page 229 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 21-6: Bit Range 31:24 23:16 15:8 7:0 ALRMDATE: ALARM DATE VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 U-0 U-0 U-0 U-0 Bit Bit 27/19/11/3 26/18/10/2 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x U-0 U-0 U-0 U-0 R/W-x R/W-x -- -- -- -- MONTH10<3:0> R/W-x MONTH01<3:0> DAY10<1:0> R/W-x R/W-x DAY01<3:0> R/W-x R/W-x WDAY01<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as `0' bit 23-20 MONTH10<3:0>: Binary Coded Decimal value of months bits, 10s place digits; contains a value of 0 or 1 bit 19-16 MONTH01<3:0>: Binary Coded Decimal value of months bits, 1s place digit; contains a value from 0 to 9 bit 15-12 DAY10<3:0>: Binary Coded Decimal value of days bits, 10s place digits; contains a value from 0 to 3 bit 11-8 DAY01<3:0>: Binary Coded Decimal value of days bits, 1s place digit; contains a value from 0 to 9 bit 7-4 Unimplemented: Read as `0' bit 3-0 WDAY01<3:0>: Binary Coded Decimal value of weekdays bits, 1s place digit; contains a value from 0 to 6 DS60001290E-page 230 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 22.0 Note: The 10-bit Analog-to-Digital Converter (ADC) includes the following features: * Successive Approximation Register (SAR) conversion * Up to 1 Msps conversion speed * Up to 48 analog input pins * External voltage reference input pins * One unipolar, differential Sample and Hold Amplifier (SHA) * Automatic Channel Scan mode * Selectable conversion trigger source * 16-word conversion result buffer * Selectable buffer fill modes * Eight conversion result format options * Operation during CPU Sleep and Idle modes 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) This data sheet summarizes the features of the PIC32MX1XX/2XX/5XX 64/100-pin family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 17. "10-bit Analog-to-Digital Converter (ADC)" (DS60001104) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). A block diagram of the 10-bit ADC is illustrated in Figure 22-1. The 10-bit ADC has up to 28 analog input pins, designated AN0-AN27. In addition, there are two analog input pins for external voltage reference connections. These voltage reference inputs may be shared with other analog input pins and may be common to other analog module references. FIGURE 22-1: ADC1 MODULE BLOCK DIAGRAM CTMUI(3) VREF+(1) AVDD VREF-(1) AVSS AN0 AN47 VCFG<2:0> IVREF(3) ADC1BUF0 CTMUT(2) ADC1BUF1 Open(4) S&H Channel Scan VREFH VREFL ADC1BUF2 + CH0SB<5:0> CH0SA<5:0> - SAR ADC CSCNA AN1 ADC1BUFE VREFL ADC1BUFF CH0NA CH0NB Alternate Input Selection ALTS (AD1CON2<0>) Note 1: VREF+ and VREF- inputs can be multiplexed with other analog inputs. 2: Connected to the CTMU temperature reference diode. See Section 26.0 "Charge Time Measurement Unit (CTMU)" for more information. 3: Internal precision 1.2V reference. See Section 24.0 "Comparator" for more information. 4: This selection is only used with CTMU capacitive and time measurement. 2014-2017 Microchip Technology Inc. DS60001290E-page 231 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY FIGURE 22-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADRC FRC(1) Div 2 1 TAD ADCS<7:0> 0 8 ADC Conversion Clock Multiplier TPB(2) 2, 4,..., 512 Note 1: 2: See Section 31.0 "40 MHz Electrical Characteristics" for the exact FRC clock value. Refer to Figure 8-1 in Section 8.0 "Oscillator Configuration" for more information. DS60001290E-page 232 2014-2017 Microchip Technology Inc. Control Registers Virtual Address (BF80_#) TABLE 22-1: Register Name (1) 9010 AD1CON2 (1) 9050 AD1CSSL(1,3) 9060 AD1CSSL2 30/14 31:16 -- 15:0 ON 31:16 -- 15:0 9020 AD1CON3(1) AD1CHS 31/15 (1) 9070 ADC1BUF0 9080 ADC1BUF1 9090 ADC1BUF2 90A0 ADC1BUF3 90B0 ADC1BUF4 2014-2017 Microchip Technology Inc. 90C0 ADC1BUF5 90D0 ADC1BUF6 90E0 ADC1BUF7 90F0 ADC1BUF8 29/13 28/12 27/11 26/10 -- -- -- -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- OFFCAL -- CSCNA -- -- BUFS -- -- -- -- -- -- -- -- VCFG<2:0> 25/9 24/8 23/7 -- -- -- FORM<2:0> 31:16 -- -- -- 15:0 ADRC -- -- 31:16 CH0NB -- 15:0 -- -- -- -- -- -- -- 31:16 CSSL31 CSSL30 CSSL29 CSSL28 CSSL27 CSSL26 22/6 21/5 -- -- SSRC<2:0> -- 20/4 19/3 18/2 SAMC<4:0> 16/0 -- -- -- -- -- 0000 CLRASAM -- ASAM SAMP DONE 0000 -- -- -- -- -- 0000 BUFM ALTS 0000 -- -- 0000 SMPI<3:0> -- 17/1 -- -- -- ADCS<7:0> CH0SB<5:0>(2) All Resets Bit Range Bits 9000 AD1CON1(1) 9040 ADC REGISTER MAP 0000 CH0SA<5:0>(2) CH0NA -- -- -- -- -- -- -- -- -- CSSL25 CSSL24 CSSL23 CSSL22 CSSL21 CSSL20 CSSL19 CSSL18 CSSL17 0000 -- 0000 CSSL16 0000 15:0 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- CSSL50 CSSL49 CSSL48 0000 15:0 CSSL47 CSSL46 CSSL45 CSSL44 CSSL43 CSSL42 CSSL41 CSSL40 CSSL39 CSSL38 CSSL37 CSSL36 CSSL35 CSSL34 CSSL33 CSSL32 0000 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 ADC Result Word 0 (ADC1BUF0<31:0>) ADC Result Word 1 (ADC1BUF1<31:0>) ADC Result Word 2 (ADC1BUF2<31:0>) ADC Result Word 3 (ADC1BUF3<31:0>) ADC Result Word 4 (ADC1BUF4<31:0>) ADC Result Word 5 (ADC1BUF5<31:0>) ADC Result Word 6 (ADC1BUF6<31:0>) ADC Result Word 7 (ADC1BUF7<31:0>) ADC Result Word 8 (ADC1BUF8<31:0>) Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: 2: 3: This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for details. For 64-pin devices, the MSB of these bits is not available. For 64-pin devices, only the CSSL30:CSSL0 bits are available. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 233 22.1 Register Name 9100 ADC1BUF9 9110 ADC1BUFA 9120 ADC1BUFB 9130 ADC1BUFC 9140 ADC1BUFD 9150 ADC1BUFE 9160 ADC1BUFF 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 ADC Result Word 9 (ADC1BUF9<31:0>) ADC Result Word A (ADC1BUFA<31:0>) ADC Result Word B (ADC1BUFB<31:0>) ADC Result Word C (ADC1BUFC<31:0>) ADC Result Word D (ADC1BUFD<31:0>) ADC Result Word E (ADC1BUFE<31:0>) ADC Result Word F (ADC1BUFF<31:0>) Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: 2: 3: This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for details. For 64-pin devices, the MSB of these bits is not available. For 64-pin devices, only the CSSL30:CSSL0 bits are available. All Resets Bits Bit Range Virtual Address (BF80_#) ADC REGISTER MAP (CONTINUED) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 234 TABLE 22-1: PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 22-1: Bit Range 31:24 23:16 15:8 7:0 AD1CON1: ADC CONTROL REGISTER 1 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 (1) U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 -- SIDL -- -- R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 CLRASAM -- ASAM ON SSRC<2:0> Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set FORM<2:0> R/W-0, HSC (2) SAMP R/C-0, HSC (3) DONE U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: ADC Operating Mode bit(1) 1 = ADC module is operating 0 = ADC module is not operating bit 14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-11 Unimplemented: Read as `0' bit 10-8 FORM<2:0>: Data Output Format bits 011 = Signed Fractional 16-bit (DOUT = 0000 0000 0000 0000 sddd dddd dd00 0000) 010 = Fractional 16-bit (DOUT = 0000 0000 0000 0000 dddd dddd dd00 0000) 001 = Signed Integer 16-bit (DOUT = 0000 0000 0000 0000 ssss sssd dddd dddd) 000 = Integer 16-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd) 111 = Signed Fractional 32-bit (DOUT = sddd dddd dd00 0000 0000 0000 0000) 110 = Fractional 32-bit (DOUT = dddd dddd dd00 0000 0000 0000 0000 0000) 101 = Signed Integer 32-bit (DOUT = ssss ssss ssss ssss ssss sssd dddd dddd) 100 = Integer 32-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd) bit 7-5 SSRC<2:0>: Conversion Trigger Source Select bits 111 = Internal counter ends sampling and starts conversion (auto convert) 110 = Reserved 101 = Reserved 100 = Reserved 011 = CTMU ends sampling and starts conversion 010 = Timer 3 period match ends sampling and starts conversion 001 = Active transition on INT0 pin ends sampling and starts conversion 000 = Clearing SAMP bit ends sampling and starts conversion Note 1: 2: 3: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. If ASAM = 0, software can write a `1' to start sampling. This bit is automatically set by hardware if ASAM = 1. If SSRC = 0, software can write a `0' to end sampling and start conversion. If SSRC 0, this bit is automatically cleared by hardware to end sampling and start conversion. This bit is automatically set by hardware when analog-to-digital conversion is complete. Software can write a `0' to clear this bit (a write of `1' is not allowed). Clearing this bit does not affect any operation already in progress. This bit is automatically cleared by hardware at the start of a new conversion. 2014-2017 Microchip Technology Inc. DS60001290E-page 235 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 22-1: bit 4 AD1CON1: ADC CONTROL REGISTER 1 (CONTINUED) CLRASAM: Stop Conversion Sequence bit (when the first ADC interrupt is generated) 1 = Stop conversions when the first ADC interrupt is generated. Hardware clears the ASAM bit when the ADC interrupt is generated. 0 = Normal operation, buffer contents will be overwritten by the next conversion sequence Unimplemented: Read as `0' ASAM: ADC Sample Auto-Start bit 1 = Sampling begins immediately after last conversion completes; SAMP bit is automatically set. 0 = Sampling begins when SAMP bit is set SAMP: ADC Sample Enable bit(2) 1 = The ADC sample and hold amplifier is sampling 0 = The ADC sample/hold amplifier is holding When ASAM = 0, writing `1' to this bit starts sampling. When SSRC = 000, writing `0' to this bit will end sampling and start conversion. DONE: Analog-to-Digital Conversion Status bit(3) 1 = Analog-to-digital conversion is done 0 = Analog-to-digital conversion is not done or has not started Clearing this bit will not affect any operation in progress. bit 3 bit 2 bit 1 bit 0 Note 1: 2: 3: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. If ASAM = 0, software can write a `1' to start sampling. This bit is automatically set by hardware if ASAM = 1. If SSRC = 0, software can write a `0' to end sampling and start conversion. If SSRC 0, this bit is automatically cleared by hardware to end sampling and start conversion. This bit is automatically set by hardware when analog-to-digital conversion is complete. Software can write a `0' to clear this bit (a write of `1' is not allowed). Clearing this bit does not affect any operation already in progress. This bit is automatically cleared by hardware at the start of a new conversion. DS60001290E-page 236 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 22-2: Bit Range 31:24 23:16 15:8 AD1CON2: ADC CONTROL REGISTER 2 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 OFFCAL -- CSCNA -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFM ALTS VCFG<2:0> 7:0 Bit Bit 28/20/12/4 27/19/11/3 R-0 U-0 BUFS -- R/W-0 SMPI<3:0> Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-13 VCFG<2:0>: Voltage Reference Configuration bits 000 001 010 011 1xx bit 12 bit 11 bit 10 bit 9-8 bit 7 bit 6 bit 5-2 VREFH VREFL AVDD External VREF+ pin AVDD External VREF+ pin AVDD AVss AVSS External VREF- pin External VREF- pin AVSS OFFCAL: Input Offset Calibration Mode Select bit 1 = Enable Offset Calibration mode Positive and negative inputs of the sample and hold amplifier are connected to VREFL 0 = Disable Offset Calibration mode The inputs to the sample and hold amplifier are controlled by AD1CHS or AD1CSSL Unimplemented: Read as `0' CSCNA: Input Scan Select bit 1 = Scan inputs 0 = Do not scan inputs Unimplemented: Read as `0' BUFS: Buffer Fill Status bit Only valid when BUFM = 1. 1 = ADC is currently filling buffer 0x8-0xF, user should access data in 0x0-0x7 0 = ADC is currently filling buffer 0x0-0x7, user should access data in 0x8-0xF Unimplemented: Read as `0' SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits 1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence 1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence * * * bit 1 bit 0 0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence 0000 = Interrupts at the completion of conversion for each sample/convert sequence BUFM: ADC Result Buffer Mode Select bit 1 = Buffer configured as two 8-word buffers, ADC1BUF7-ADC1BUF0, ADC1BUFF-ADCBUF8 0 = Buffer configured as one 16-word buffer ADC1BUFF-ADC1BUF0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses Sample A input multiplexer settings for first sample, then alternates between Sample B and Sample A input multiplexer settings for all subsequent samples 0 = Always use Sample A input multiplexer settings 2014-2017 Microchip Technology Inc. DS60001290E-page 237 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 22-3: Bit Range 31:24 23:16 15:8 7:0 AD1CON3: ADC CONTROL REGISTER 3 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC -- -- R/W-0 R/W-0 R/W-0 R/W R/W-0 SAMC<4:0>(1) R/W-0 R/W-0 R/W-0 ADCS<7:0>(2) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ADRC: ADC Conversion Clock Source bit 1 = Clock derived from FRC 0 = Clock derived from Peripheral Bus Clock (PBCLK) bit 14-13 Unimplemented: Read as `0' bit 12-8 SAMC<4:0>: Auto-Sample Time bits(1) 11111 = 31 TAD * * * 00001 = 1 TAD 00000 = 0 TAD (Not allowed) bit 7-0 ADCS<7:0>: ADC Conversion Clock Select bits(2) 11111111 =TPB * 2 * (ADCS<7:0> + 1) = 512 * TPB = TAD * * * 00000001 =TPB * 2 * (ADCS<7:0> + 1) = 4 * TPB = TAD 00000000 =TPB * 2 * (ADCS<7:0> + 1) = 2 * TPB = TAD Note 1: 2: This bit is only used if the SSRC<2:0> bits (AD1CON1<7:5>) = 111. This bit is not used if the ADRC bit (AD1CON3<15>) = 1. DS60001290E-page 238 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 22-4: Bit Range 31:24 23:16 15:8 7:0 AD1CHS: ADC INPUT SELECT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 U-0 CH0NB -- Bit Bit 28/20/12/4 27/19/11/3 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0SB<5:0> R/W-0 U-0 CH0NA -- R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- CH0SA<5:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31 CH0NB: Negative Input Select bit for Sample B 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VREFL bit 30 Unimplemented: Read as `0' bit 29-24 CH0SB<5:0>: Positive Input Select bits for Sample B For 64-pin devices: 011110 = Channel 0 positive input is Open(1) 011101 = Channel 0 positive input is CTMU temperature sensor (CTMUT)(2) 011100 = Channel 0 positive input is IVREF(3) 011011 = Channel 0 positive input is AN27 x = Bit is unknown * * * 000001 = Channel 0 positive input is AN1 000000 = Channel 0 positive input is AN0 For 100-pin devices: 110010 = Channel 0 positive input is Open(1) 110001 = Channel 0 positive input is CTMU temperature sensor (CTMUT)(2) 110000 = Channel 0 positive input is IVREF(3) 101111 = Channel 0 positive input is AN47 * * * 0000001 = Channel 0 positive input is AN1 0000000 = Channel 0 positive input is AN0 bit 23 CH0NA: Negative Input Select bit for Sample A Multiplexer Setting(3) 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VREFL bit 22 Unimplemented: Read as `0' Note 1: 2: 3: This selection is only used with CTMU capacitive and time measurement. See Section 26.0 "Charge Time Measurement Unit (CTMU)" for more information. Internal precision 1.2V reference. See Section 24.0 "Comparator" for more information. 2014-2017 Microchip Technology Inc. DS60001290E-page 239 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 22-4: bit 21-16 AD1CHS: ADC INPUT SELECT REGISTER (CONTINUED) CH0SA<5:0>: Positive Input Select bits for Sample A Multiplexer Setting For 64-pin devices: 011110 = Channel 0 positive input is Open(1) 011101 = Channel 0 positive input is CTMU temperature sensor (CTMUT)(2) 011100 = Channel 0 positive input is IVREF(3) 011011 = Channel 0 positive input is AN27 * * * 000001 = Channel 0 positive input is AN1 000000 = Channel 0 positive input is AN0 For 100-pin devices: 110010 = Channel 0 positive input is Open(1) 110001 = Channel 0 positive input is CTMU temperature sensor (CTMUT)(2) 110000 = Channel 0 positive input is IVREF(3) 101111 = Channel 0 positive input is AN47 * * * 0000001 = Channel 0 positive input is AN1 0000000 = Channel 0 positive input is AN0 bit 15-0 Unimplemented: Read as `0' Note 1: 2: 3: This selection is only used with CTMU capacitive and time measurement. See Section 26.0 "Charge Time Measurement Unit (CTMU)" for more information. Internal precision 1.2V reference. See Section 24.0 "Comparator" for more information. DS60001290E-page 240 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 22-5: Bit Range 31:24 23:16 15:8 7:0 AD1CSSL: ADC INPUT SCAN SELECT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL31(2) CSSL30(1) CSSL29(1) CSSL28(1) CSSL27 CSSL26 CSSL25 CSSL24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL23 CSSL21 CSSL21 CSSL20 CSSL19 CSSL18 CSSL17 CSSL16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-0 CSSL<31:0>: ADC Input Pin Scan Selection bits 1 = Select ANx for input scan; CSSLx = ANx, where `x' = 0-31 0 = Skip ANx for input scan; CSSLx = ANx, where `x' = 0-31 Note 1: For devices with 64 pins, CSSL28 selects IVREF (Band Gap) for scan; CSSL29 selects CTMU temperature diode for scan; and CSSL30 selects CTMU input for scan On devices with less than 32 analog inputs, all CSSLx bits can be selected; however, inputs selected for scan without a corresponding input on the device will convert to VREFL. 2: REGISTER 22-6: Bit Range 31:24 23:16 15:8 7:0 AD1CSSL2: ADC INPUT SCAN SELECT REGISTER 2 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 -- -- -- -- -- CSSL50(1) CSSL49(1) CSSL48(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL47 CSSL46 CSSL45 CSSL44 CSSL43 CSSL42 CSSL41 CSSL40 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL39 CSSL38 CSSL37 CSSL36 CSSL35 CSSL34 CSSL33 CSSL32 Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-19 Unimplemented: Read as `0' bit 18-0 CSSL<50:32>: ADC Input Pin Scan Selection bits 1 = Select ANx for input scan; CSSLx = ANx, where `x' = 32-50 0 = Skip ANx for input scan; CSSLx = ANx, where `x' = 32-50 Note 1: Note: For devices with 100 or more pins, CSSL48 selects IVREF (Band Gap) for scan; CSSL49 selects CTMU temperature diode for scan; and CSSL50 selects CTMU input for scan The ANx inputs in this register only support devices with 100 or more pins. 2014-2017 Microchip Technology Inc. DS60001290E-page 241 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY NOTES: DS60001290E-page 242 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 23.0 Note: CONTROLLER AREA NETWORK (CAN) This data sheet summarizes the features of the PIC32MX1XX/2XX/5XX 64/100-pin family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 34. "Controller Area Network (CAN)" (DS60001154) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). The Controller Area Network (CAN) module supports the following key features: * Standards Compliance: - Full CAN 2.0B compliance - Programmable bit rate up to 1 Mbps * Message Reception and Transmission: - 16 message FIFOs - Each FIFO can have up to 16 messages for a total of 256 messages FIGURE 23-1: - FIFO can be a transmit message FIFO or a receive message FIFO - User-defined priority levels for message FIFOs used for transmission - 16 acceptance filters for message filtering - Four acceptance filter mask registers for message filtering - Automatic response to remote transmit request - DeviceNetTM addressing support * Additional Features: - Loopback, Listen All Messages, and Listen Only modes for self-test, system diagnostics and bus monitoring - Low-power operating modes - CAN module is a bus master on the PIC32 system bus - Use of DMA is not required - Dedicated time-stamp timer - Dedicated DMA channels - Data-only Message Reception mode Figure 23-1 illustrates the general structure of the CAN module. PIC32 CAN MODULE BLOCK DIAGRAM CxTX 16 Filters 4 Masks CPU CxRX CAN Module Up to 16 Message Buffers System Bus Message Buffer Size 2 or 4 Words System RAM Message Buffer 15 Message Buffer 15 Message Buffer 15 Message Buffer 1 Message Buffer 0 Message Buffer 1 Message Buffer 0 Message Buffer 1 Message Buffer 0 FIFO1 FIFO15 FIFO0 CAN Message FIFO (up to 16 FIFOs) 2014-2017 Microchip Technology Inc. DS60001290E-page 243 Control Registers Virtual Address (BF88_#) Register Name(1) TABLE 23-1: B000 C1CON C1CFG B020 C1INT B030 C1VEC C1TREC B050 C1FSTAT B060 C1RXOVF B070 C1TMR B080 C1RXM0 B090 C1RXM1 B0A0 C1RXM2 B0B0 C1RXM3 2014-2017 Microchip Technology Inc. B0C0 C1FLTCON0 B0D0 C1FLTCON1 B0E0 C1FLTCON2 B0F0 C1FLTCON3 B140 C1RXFn (n = 0-15) Legend: Note 1: 31/15 30/14 31:16 -- 15:0 ON 31:16 -- 15:0 SEG2PHTS 29/13 28/12 -- -- -- ABAT -- SIDLE -- CANBUSY -- -- -- -- -- -- SAM 27/11 26/10 25/9 24/8 23/7 -- -- -- -- -- -- -- -- WAKFIL -- REQOP<2:0> SEG1PH<2:0> 22/6 21/5 OPMOD<2:0> PRSEG<2:0> 20/4 19/3 CANCAP -- 18/2 17/1 16/0 -- -- -- DNCNT<4:0> -- SJW<1:0> -- All Resets Bit Range Bits B010 B040 CAN1 REGISTER SUMMARY 0480 0000 SEG2PH<2:0> 0000 BRP<5:0> 0000 31:16 IVRIE WAKIE CERRIE SERRIE RBOVIE -- -- -- -- -- -- -- MODIE CTMRIE RBIE TBIE 0000 15:0 IVRIF WAKIF CERRIF SERRIF RBOVIF -- -- -- -- -- -- -- MODIF CTMRIF RBIF TBIF 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- 31:16 -- -- -- TXWARN RXWARN 31:16 -- -- -- 15:0 FIFOIP15 FIFOIP14 31:16 -- -- 15:0 FILHIT<4:0> -- -- -- ICODE<6:0> -- -- -- -- TXBO -- -- -- -- -- -- -- -- -- -- FIFOIP10 FIFOIP9 FIFOIP8 FIFOIP7 FIFOIP6 FIFOIP5 FIFOIP4 FIFOIP3 FIFOIP2 FIFOIP1 TERRCNT<7:0> -- -- FIFOIP13 FIFOIP12 FIFOIP11 -- -- -- TXBP RXBP 0040 -- EWARN 0000 RERRCNT<7:0> -- 15:0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 31:16 0000 -- -- -- -- -- -- -- -- -- RXOVF9 RXOVF8 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 -- -- 0000 CANTSPRE<15:0> 31:16 0000 SID<10:0> 15:0 --- MIDE -- EID<17:16> xxxx xxxx --- MIDE -- EID<17:16> xxxx xxxx --- MIDE -- EID<17:16> xxxx --- MIDE -- EID<17:16> EID<15:0> 31:16 SID<10:0> 15:0 EID<15:0> 31:16 SID<10:0> 15:0 EID<15:0> 31:16 xxxx SID<10:0> 15:0 0000 RXOVF0 0000 CANTS<15:0> 15:0 0000 FIFOIP0 0000 EID<15:0> xxxx xxxx 31:16 FLTEN3 MSEL3<1:0> FSEL3<4:0> FLTEN2 MSEL2<1:0> FSEL2<4:0> 0000 15:0 FLTEN1 MSEL1<1:0> FSEL1<4:0> FLTEN0 MSEL0<1:0> FSEL0<4:0> 0000 31:16 FLTEN7 MSEL7<1:0> FSEL7<4:0> FLTEN6 MSEL6<1:0> FSEL6<4:0> 0000 15:0 FLTEN5 MSEL5<1:0> FSEL5<4:0> FLTEN4 MSEL4<1:0> FSEL4<4:0> 0000 31:16 FLTEN11 MSEL11<1:0> FSEL11<4:0> FLTEN10 MSEL10<1:0> FSEL10<4:0> 0000 15:0 FLTEN9 MSEL9<1:0> FSEL9<4:0> FLTEN8 MSEL8<1:0> FSEL8<4:0> 0000 31:16 FLTEN15 MSEL15<1:0> FSEL15<4:0> FLTEN14 MSEL14<1:0> FSEL14<4:0> 0000 15:0 MSEL13<1:0> FSEL13<4:0> FLTEN12 MSEL12<1:0> FSEL12<4:0> 31:16 15:0 FLTEN13 SID<10:0> --- EXID -- 0000 EID<17:16> EID<15:0> x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. xxxx xxxx PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 244 23.1 Virtual Address (BF88_#) Register Name(1) B340 C1FIFOBA B350 B360 CAN1 REGISTER SUMMARY (CONTINUED) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 31:16 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0000 C1FIFOBA<31:0> 15:0 All Resets Bit Range Bits 0000 C1FIFOCONn 31:16 (n = 0-15) 15:0 -- -- -- -- -- -- -- -- -- -- -- -- FRESET UINC DONLY -- -- -- -- TXEN TXABAT TXLARB TXERR 31:16 -- -- -- -- -- TXNFULLIE TXHALFIE TXEMPTYIE -- -- -- -- RXOVFLIE RXFULLIE RXHALFIE RXN 0000 EMPTYIE 15:0 -- -- -- -- -- TXNFULLIF TXHALFIF TXEMPTYIF -- -- -- -- RXOVFLIF RXFULLIF RXHALFIF RXN 0000 EMPTYIF C1FIFOINTn (n = 0-15) B370 C1FIFOUAn 31:16 (n = 0-15) 15:0 B380 C1FIFOCIn 31:16 (n = 0-15) 15:0 Legend: Note 1: FSIZE<4:0> TXREQ RTREN 0000 TXPRI<1:0> 0000 0000 C1FIFOUA<31:0> 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- C1FIFOCIn<4:0> x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. 0000 0000 DS60001290E-page 245 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 2014-2017 Microchip Technology Inc. TABLE 23-1: PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 23-1: Bit Range 31:24 23:16 15:8 7:0 C1CON: CAN MODULE CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 U-0 U-0 U-0 U-0 S/HC-0 R/W-1 -- -- -- -- ABAT R-0 R-0 R-1 OPMOD<2:0> R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 REQOP<2:0> R/W-0 U-0 U-0 U-0 CANCAP -- -- -- U-0 -- U-0 R-0 U-0 U-0 U-0 U-0 R/W-0 ON(1) -- SIDLE -- CANBUSY -- -- -- U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- DNCNT<4:0> Legend: HC = Hardware Clear S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-28 Unimplemented: Read as `0' bit 27 ABAT: Abort All Pending Transmissions bit 1 = Signal all transmit buffers to abort transmission 0 = Module will clear this bit when all transmissions aborted bit 26-24 REQOP<2:0>: Request Operation Mode bits 111 = Set Listen All Messages mode 110 = Reserved 101 = Reserved 100 = Set Configuration mode 011 = Set Listen Only mode 010 = Set Loopback mode 001 = Set Disable mode 000 = Set Normal Operation mode bit 23-21 OPMOD<2:0>: Operation Mode Status bits 111 = Module is in Listen All Messages mode 110 = Reserved 101 = Reserved 100 = Module is in Configuration mode 011 = Module is in Listen Only mode 010 = Module is in Loopback mode 001 = Module is in Disable mode 000 = Module is in Normal Operation mode bit 20 CANCAP: CAN Message Receive Time Stamp Timer Capture Enable bit 1 = CANTMR value is stored on valid message reception and is stored with the message 0 = Disable CAN message receive time stamp timer capture and stop CANTMR to conserve power bit 19-16 Unimplemented: Read as `0' bit 15 ON: CAN On bit(1) 1 = CAN module is enabled 0 = CAN module is disabled bit 14 Unimplemented: Read as `0' Note 1: If the user application clears this bit, it may take a number of cycles before the CAN module completes the current transaction and responds to this request. The user application should poll the CANBUSY bit to verify that the request has been honored. DS60001290E-page 246 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 23-1: C1CON: CAN MODULE CONTROL REGISTER (CONTINUED) bit 13 SIDLE: CAN Stop in Idle bit 1 = CAN Stops operation when system enters Idle mode 0 = CAN continues operation when system enters Idle mode bit 12 Unimplemented: Read as `0' bit 11 CANBUSY: CAN Module is Busy bit 1 = The CAN module is active 0 = The CAN module is completely disabled bit 10-5 Unimplemented: Read as `0' bit 4-0 DNCNT<4:0>: Device Net Filter Bit Number bits 10011-11111 = Invalid Selection (compare up to 18-bits of data with EID) 10010 = Compare up to data byte 2 bit 6 with EID17 (C1RXFn<17>) * * * 00001 = Compare up to data byte 0 bit 7 with EID0 (C1RXFn<0>) 00000 = Do not compare data bytes Note 1: If the user application clears this bit, it may take a number of cycles before the CAN module completes the current transaction and responds to this request. The user application should poll the CANBUSY bit to verify that the request has been honored. 2014-2017 Microchip Technology Inc. DS60001290E-page 247 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 23-2: Bit Range 31:24 23:16 15:8 7:0 C1CFG: CAN BAUD RATE CONFIGURATION REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 -- WAKFIL -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEG2PHTS (1) (2) SAM R/W-0 R/W-0 SEG2PH<2:0>(1,4) SEG1PH<2:0> R/W-0 R/W-0 (3) SJW<1:0> R/W-0 R/W-0 PRSEG<2:0> R/W-0 R/W-0 BRP<5:0> Legend: HC = Hardware Clear S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-23 Unimplemented: Read as `0' bit 22 WAKFIL: CAN Bus Line Filter Enable bit 1 = Use CAN bus line filter for wake-up 0 = CAN bus line filter is not used for wake-up bit 21-19 Unimplemented: Read as `0' bit 18-16 SEG2PH<2:0>: Phase Buffer Segment 2 bits(1,4) 111 = Length is 8 x TQ * * * 000 = Length is 1 x TQ bit 15 SEG2PHTS: Phase Segment 2 Time Select bit(1) 1 = Freely programmable 0 = Maximum of SEG1PH or Information Processing Time, whichever is greater bit 14 SAM: Sample of the CAN Bus Line bit(2) 1 = Bus line is sampled three times at the sample point 0 = Bus line is sampled once at the sample point bit 13-11 SEG1PH<2:0>: Phase Buffer Segment 1 bits(4) 111 = Length is 8 x TQ * * * 000 = Length is 1 x TQ Note 1: 2: 3: 4: Note: SEG2PH SEG1PH. If SEG2PHTS is clear, SEG2PH will be set automatically. 3 Time bit sampling is not allowed for BRP < 2. SJW SEG2PH. The Time Quanta per bit must be greater than 7 (that is, TQBIT > 7). This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> (C1CON<23:21>) = 100). DS60001290E-page 248 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 23-2: C1CFG: CAN BAUD RATE CONFIGURATION REGISTER (CONTINUED) bit 10-8 PRSEG<2:0>: Propagation Time Segment bits(4) 111 = Length is 8 x TQ * * * 000 = Length is 1 x TQ bit 7-6 SJW<1:0>: Synchronization Jump Width bits(3) 11 = Length is 4 x TQ 10 = Length is 3 x TQ 01 = Length is 2 x TQ 00 = Length is 1 x TQ bit 5-0 BRP<5:0>: Baud Rate Prescaler bits 111111 = TQ = (2 x 64)/SYSCLK 111110 = TQ = (2 x 63)/SYSCLK * * * 000001 = TQ = (2 x 2)/SYSCLK 000000 = TQ = (2 x 1)/SYSCLK Note 1: 2: 3: 4: SEG2PH SEG1PH. If SEG2PHTS is clear, SEG2PH will be set automatically. 3 Time bit sampling is not allowed for BRP < 2. SJW SEG2PH. The Time Quanta per bit must be greater than 7 (that is, TQBIT > 7). Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> (C1CON<23:21>) = 100). 2014-2017 Microchip Technology Inc. DS60001290E-page 249 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 23-3: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 C1INT: CAN INTERRUPT REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 IVRIE WAKIE CERRIE SERRIE RBOVIE -- -- -- U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- -- MODIE CTMRIE RBIE TBIE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 (1) IVRIF WAKIF CERRIF RBOVIF -- -- -- U-0 U-0 U-0 SERRIF U-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- -- MODIF CTMRIF RBIF TBIF Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31 IVRIE: Invalid Message Received Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 30 WAKIE: CAN Bus Activity Wake-up Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 29 CERRIE: CAN Bus Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 28 SERRIE: System Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 27 RBOVIE: Receive Buffer Overflow Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled x = Bit is unknown bit 26-20 Unimplemented: Read as `0' bit 19 MODIE: Mode Change Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 18 CTMRIE: CAN Timestamp Timer Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 17 RBIE: Receive Buffer Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 16 TBIE: Transmit Buffer Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 15 IVRIF: Invalid Message Received Interrupt Flag bit 1 = An invalid messages interrupt has occurred 0 = An invalid message interrupt has not occurred Note 1: This bit can only be cleared by turning the CAN module Off and On by clearing or setting the ON bit (C1CON<15>). DS60001290E-page 250 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 23-3: C1INT: CAN INTERRUPT REGISTER (CONTINUED) bit 14 WAKIF: CAN Bus Activity Wake-up Interrupt Flag bit 1 = A bus wake-up activity interrupt has occurred 0 = A bus wake-up activity interrupt has not occurred bit 13 CERRIF: CAN Bus Error Interrupt Flag bit 1 = A CAN bus error has occurred 0 = A CAN bus error has not occurred bit 12 SERRIF: System Error Interrupt Flag bit(1) 1 = A system error occurred (typically an illegal address was presented to the system bus) 0 = A system error has not occurred bit 11 RBOVIF: Receive Buffer Overflow Interrupt Flag bit 1 = A receive buffer overflow has occurred 0 = A receive buffer overflow has not occurred bit 10-4 Unimplemented: Read as `0' bit 3 MODIF: CAN Mode Change Interrupt Flag bit 1 = A CAN module mode change has occurred (OPMOD<2:0> has changed to reflect REQOP) 0 = A CAN module mode change has not occurred bit 2 CTMRIF: CAN Timer Overflow Interrupt Flag bit 1 = A CAN timer (CANTMR) overflow has occurred 0 = A CAN timer (CANTMR) overflow has not occurred bit 1 RBIF: Receive Buffer Interrupt Flag bit 1 = A receive buffer interrupt is pending 0 = A receive buffer interrupt is not pending bit 0 TBIF: Transmit Buffer Interrupt Flag bit 1 = A transmit buffer interrupt is pending 0 = A transmit buffer interrupt is not pending Note 1: This bit can only be cleared by turning the CAN module Off and On by clearing or setting the ON bit (C1CON<15>). 2014-2017 Microchip Technology Inc. DS60001290E-page 251 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 23-4: Bit Range 31:24 23:16 15:8 7:0 C1VEC: CAN INTERRUPT CODE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 -- -- -- U-0 R-1 R-0 FILHIT<4:0> Legend: R = Readable bit -n = Value at POR R-0 ICODE<6:0>(1) -- W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-13 Unimplemented: Read as `0' bit 12-8 FILHIT<4:0>: Filter Hit Number bit 11111 = Reserved * * * 10000 = Reserved 01111 = Filter 15 * * * bit 7 bit 6-0 00000 = Filter 0 Unimplemented: Read as `0' ICODE<6:0>: Interrupt Flag Code bits(1) 1111111 = Reserved * * * 1001001 = Reserved 1001000 = Invalid message received (IVRIF) 1000111 = CAN module mode change (MODIF) 1000110 = CAN timestamp timer (CTMRIF) 1000101 = Bus bandwidth error (SERRIF) 1000100 = Address error interrupt (SERRIF) 1000011 = Receive FIFO overflow interrupt (RBOVIF) 1000010 = Wake-up interrupt (WAKIF) 1000001 = Error Interrupt (CERRIF) 1000000 = No interrupt 0111111 = Reserved * * * 0010000 = Reserved 0001111 = FIFO15 Interrupt (C1FSTAT<15> set) * * * 0000000 = FIFO0 Interrupt (C1FSTAT<0> set) Note 1: These bits are only updated for enabled interrupts. DS60001290E-page 252 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 23-5: Bit Range 31:24 23:16 15:8 7:0 C1TREC: CAN TRANSMIT/RECEIVE ERROR COUNT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 -- -- TXBO TXBP RXBP TXWARN RXWARN EWARN R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 TERRCNT<7:0> R-0 RERRCNT<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-22 Unimplemented: Read as `0' bit 21 TXBO: Transmitter in Error State Bus OFF (TERRCNT 256) bit 20 TXBP: Transmitter in Error State Bus Passive (TERRCNT 128) bit 19 RXBP: Receiver in Error State Bus Passive (RERRCNT 128) bit 18 TXWARN: Transmitter in Error State Warning (128 > TERRCNT 96) bit 17 RXWARN: Receiver in Error State Warning (128 > RERRCNT 96) bit 16 EWARN: Transmitter or Receiver is in Error State Warning bit 15-8 TERRCNT<7:0>: Transmit Error Counter bit 7-0 RERRCNT<7:0>: Receive Error Counter REGISTER 23-6: Bit Range 31:24 23:16 15:8 7:0 C1FSTAT: CAN FIFO STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 FIFOIP15 FIFOIP14 FIFOIP13 FIFOIP12 FIFOIP11 FIFOIP10 FIFOIP9 FIFOIP8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 FIFOIP7 FIFOIP6 FIFOIP5 FIFOIP4 FIFOIP3 FIFOIP2 FIFOIP1 FIFOIP0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 FIFOIP<15:0>: FIFOx Interrupt Pending bits 1 = One or more enabled FIFO interrupts are pending 0 = No FIFO interrupts are pending 2014-2017 Microchip Technology Inc. DS60001290E-page 253 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 23-7: Bit Range 31:24 23:16 15:8 7:0 C1RXOVF: CAN RECEIVE FIFO OVERFLOW STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-16 Unimplemented: Read as `0' bit 15-0 RXOVF<15:0>: FIFOx Receive Overflow Interrupt Pending bit 1 = FIFO has overflowed 0 = FIFO has not overflowed REGISTER 23-8: Bit Range 31:24 x = Bit is unknown C1TMR: CAN TIMER REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CANTS<15:8> 23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CANTS<7:0> 15:8 R/W-0 CANTSPRE<15:8> 7:0 R/W-0 R/W-0 CANTSPRE<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 CANTS<15:0>: CAN Time Stamp Timer bits This is a free-running timer that increments every CANTSPRE system clocks when the CANCAP bit (C1CON<20>) is set. bit 15-0 CANTSPRE<15:0>: CAN Time Stamp Timer Prescaler bits 1111 1111 1111 1111 = CAN time stamp timer (CANTS) increments every 65,535 system clocks * * * 0000 0000 0000 0000 = CAN time stamp timer (CANTS) increments every system clock Note 1: 2: C1TMR will be paused when CANCAP = 0. The C1TMR prescaler count will be reset on any write to C1TMR (CANTSPRE will be unaffected). DS60001290E-page 254 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 23-9: Bit Range 31:24 23:16 15:8 7:0 C1RXMn: CAN ACCEPTANCE FILTER MASK `n' REGISTER (n = 0, 1, 2 OR 3) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SID<10:3> R/W-0 R/W-0 R/W-0 SID<2:0> U-0 R/W-0 U-0 -- MIDE -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EID<17:16> EID<15:8> R/W-0 EID<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-21 SID<10:0>: Standard Identifier bits 1 = Include the SIDx bit in filter comparison 0 = The SIDx bit is a `don't care' in filter operation bit 20 Unimplemented: Read as `0' bit 19 MIDE: Identifier Receive Mode bit 1 = Match only message types (standard/extended address) that correspond to the EXID bit in filter 0 = Match either standard or extended address message if filters match (that is, if (Filter SID) = (Message SID) or if (FILTER SID/EID) = (Message SID/EID)) bit 18 Unimplemented: Read as `0' bit 17-0 EID<17:0>: Extended Identifier bits 1 = Include the EIDx bit in filter comparison 0 = The EIDx bit is a `don't care' in filter operation Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> (C1CON<23:21>) = 100). 2014-2017 Microchip Technology Inc. DS60001290E-page 255 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 23-10: C1FLTCON0: CAN FILTER CONTROL REGISTER 0 Bit Range 31:24 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN3 R/W-0 23:16 FLTEN2 R/W-0 15:8 FLTEN1 R/W-0 7:0 FLTEN0 MSEL3<1:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL2<4:0> R/W-0 R/W-0 R/W-0 R/W-0 MSEL1<1:0> R/W-0 Bit 25/17/9/1 FSEL3<4:0> MSEL2<1:0> R/W-0 Bit 26/18/10/2 R/W-0 FSEL1<4:0> MSEL0<1:0> R/W-0 FSEL0<4:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31 FLTEN3: Filter 3 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 30-29 MSEL3<1:0>: Filter 3 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 28-24 FSEL3<4:0>: FIFO Selection bits 11111 = Reserved x = Bit is unknown * * * 10000 = Reserved 01111 = Message matching filter is stored in FIFO buffer 15 * * * 00000 = Message matching filter is stored in FIFO buffer 0 bit 23 FLTEN2: Filter 2 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 22-21 MSEL2<1:0>: Filter 2 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is `0'. DS60001290E-page 256 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 23-10: C1FLTCON0: CAN FILTER CONTROL REGISTER 0 (CONTINUED) bit 20-16 FSEL2<4:0>: FIFO Selection bits 11111 = Reserved * * * 10000 = Reserved 01111 = Message matching filter is stored in FIFO buffer 15 * * * 00000 = Message matching filter is stored in FIFO buffer 0 bit 15 FLTEN1: Filter 1 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL1<1:0>: Filter 1 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL1<4:0>: FIFO Selection bits 11111 = Reserved * * * 10000 = Reserved 01111 = Message matching filter is stored in FIFO buffer 15 * * * 00000 = Message matching filter is stored in FIFO buffer 0 bit 7 FLTEN0: Filter 0 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 6-5 MSEL0<1:0>: Filter 0 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 4-0 FSEL0<4:0>: FIFO Selection bits 11111 = Reserved * * * 10000 = Reserved 01111 = Message matching filter is stored in FIFO buffer 15 * * * 00000 = Message matching filter is stored in FIFO buffer 0 Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is `0'. 2014-2017 Microchip Technology Inc. DS60001290E-page 257 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 23-11: C1FLTCON1: CAN FILTER CONTROL REGISTER 1 Bit Range 31:24 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN7 R/W-0 23:16 FLTEN6 R/W-0 15:8 FLTEN5 R/W-0 7:0 FLTEN4 MSEL7<1:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL6<4:0> R/W-0 R/W-0 R/W-0 R/W-0 MSEL5<1:0> R/W-0 Bit 25/17/9/1 FSEL7<4:0> MSEL6<1:0> R/W-0 Bit 26/18/10/2 R/W-0 FSEL5<4:0> MSEL4<1:0> R/W-0 FSEL4<4:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31 x = Bit is unknown FLTEN7: Filter 7 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 30-29 MSEL7<1:0>: Filter 7 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 28-24 FSEL7<4:0>: FIFO Selection bits 11111 = Reserved * * * 10000 = Reserved 01111 = Message matching filter is stored in FIFO buffer 15 * * * 00000 = Message matching filter is stored in FIFO buffer 0 bit 23 FLTEN6: Filter 6 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 22-21 MSEL6<1:0>: Filter 6 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is `0'. DS60001290E-page 258 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 23-11: C1FLTCON1: CAN FILTER CONTROL REGISTER 1 (CONTINUED) bit 20-16 FSEL6<4:0>: FIFO Selection bits 11111 = Reserved * * * 10000 = Reserved 01111 = Message matching filter is stored in FIFO buffer 15 * * * 00000 = Message matching filter is stored in FIFO buffer 0 bit 15 FLTEN5: Filter 17 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL5<1:0>: Filter 5 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL5<4:0>: FIFO Selection bits 11111 = Reserved * * * 10000 = Reserved 01111 = Message matching filter is stored in FIFO buffer 15 * * * 00000 = Message matching filter is stored in FIFO buffer 0 bit 7 FLTEN4: Filter 4 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 6-5 MSEL4<1:0>: Filter 4 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 4-0 FSEL4<4:0>: FIFO Selection bits 11111 = Reserved * * * 10000 = Reserved 01111 = Message matching filter is stored in FIFO buffer 15 * * * 00000 = Message matching filter is stored in FIFO buffer 0 Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is `0'. 2014-2017 Microchip Technology Inc. DS60001290E-page 259 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 23-12: C1FLTCON2: CAN FILTER CONTROL REGISTER 2 Bit Range 31:24 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN11 R/W-0 23:16 FLTEN10 R/W-0 15:8 FLTEN9 R/W-0 7:0 FLTEN8 MSEL11<1:0> R/W-0 FSEL11<4:0> R/W-0 R/W-0 R/W-0 MSEL10<1:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MSEL9<1:0> R/W-0 R/W-0 FSEL10<4:0> R/W-0 FSEL9<4:0> R/W-0 MSEL8<1:0> R/W-0 FSEL8<4:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31 FLTEN11: Filter 11 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 30-29 MSEL11<1:0>: Filter 11 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 28-24 FSEL11<4:0>: FIFO Selection bits 11111 = Reserved x = Bit is unknown * * * 10000 = Reserved 01111 = Message matching filter is stored in FIFO buffer 15 * * * 00000 = Message matching filter is stored in FIFO buffer 0 bit 23 FLTEN10: Filter 10 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 22-21 MSEL10<1:0>: Filter 10 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is `0'. DS60001290E-page 260 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 23-12: C1FLTCON2: CAN FILTER CONTROL REGISTER 2 (CONTINUED) bit 20-16 FSEL10<4:0>: FIFO Selection bits 11111 = Reserved * * * 10000 = Reserved 01111 = Message matching filter is stored in FIFO buffer 15 * * * 00000 = Message matching filter is stored in FIFO buffer 0 bit 15 FLTEN9: Filter 9 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL9<1:0>: Filter 9 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL9<4:0>: FIFO Selection bits 11111 = Reserved * * * 10000 = Reserved 01111 = Message matching filter is stored in FIFO buffer 15 * * * 00000 = Message matching filter is stored in FIFO buffer 0 bit 7 FLTEN8: Filter 8 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 6-5 MSEL8<1:0>: Filter 8 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 4-0 FSEL8<4:0>: FIFO Selection bits 11111 = Reserved * * * 10000 = Reserved 01111 = Message matching filter is stored in FIFO buffer 15 * * * 00000 = Message matching filter is stored in FIFO buffer 0 Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is `0'. 2014-2017 Microchip Technology Inc. DS60001290E-page 261 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 23-13: C1FLTCON3: CAN FILTER CONTROL REGISTER 3 Bit Range 31:24 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN15 R/W-0 23:16 FLTEN14 R/W-0 15:8 FLTEN13 R/W-0 7:0 FLTEN12 MSEL15<1:0> R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL14<4:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MSEL13<1:0> R/W-0 Bit 25/17/9/1 FSEL15<4:0> MSEL14<1:0> R/W-0 Bit 26/18/10/2 R/W-0 FSEL13<4:0> R/W-0 MSEL12<1:0> R/W-0 FSEL12<4:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31 FLTEN15: Filter 15 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 30-29 MSEL15<1:0>: Filter 15 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 28-24 FSEL15<4:0>: FIFO Selection bits 11111 = Reserved x = Bit is unknown * * * 10000 = Reserved 01111 = Message matching filter is stored in FIFO buffer 15 * * * 00000 = Message matching filter is stored in FIFO buffer 0 bit 23 FLTEN14: Filter 14 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 22-21 MSEL14<1:0>: Filter 14 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is `0'. DS60001290E-page 262 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 23-13: C1FLTCON3: CAN FILTER CONTROL REGISTER 3 (CONTINUED) bit 20-16 FSEL14<4:0>: FIFO Selection bits 11111 = Reserved * * * 10000 = Reserved 01111 = Message matching filter is stored in FIFO buffer 15 * * * 00000 = Message matching filter is stored in FIFO buffer 0 bit 15 FLTEN13: Filter 13 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL13<1:0>: Filter 13 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL13<4:0>: FIFO Selection bits 11111 = Reserved * * * 10000 = Reserved 01111 = Message matching filter is stored in FIFO buffer 15 * * * 00000 = Message matching filter is stored in FIFO buffer 0 bit 7 FLTEN12: Filter 12 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 6-5 MSEL12<1:0>: Filter 12 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 4-0 FSEL12<4:0>: FIFO Selection bits 11111 = Reserved * * * 10000 = Reserved 01111 = Message matching filter is stored in FIFO buffer 15 * * * 00000 = Message matching filter is stored in FIFO buffer 0 Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is `0'. 2014-2017 Microchip Technology Inc. DS60001290E-page 263 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 23-14: C1RXFn: CAN ACCEPTANCE FILTER `n' REGISTER (`n' = 0 THROUGH 15) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID<10:3> R/W-x R/W-x R/W-x SID<2:0> U-0 R/W-0 U-0 -- EXID -- R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID<17:16> EID<15:8> R/W-x EID<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-21 SID<10:0>: Standard Identifier bits 1 = Message address bit SIDx must be `1' to match filter 0 = Message address bit SIDx must be `0' to match filter bit 20 Unimplemented: Read as `0' bit 19 EXID: Extended Identifier Enable bits 1 = Match only messages with extended identifier addresses 0 = Match only messages with standard identifier addresses bit 18 Unimplemented: Read as `0' bit 17-0 EID<17:0>: Extended Identifier bits 1 = Message address bit EIDx must be `1' to match filter 0 = Message address bit EIDx must be `0' to match filter Note: This register can only be modified when the filter is disabled (FLTENn = 0). DS60001290E-page 264 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 23-15: C1FIFOBA: CAN MESSAGE BUFFER BASE ADDRESS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0(1) R-0(1) C1FIFOBA<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C1FIFOBA<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C1FIFOBA<15:8> R/W-0 C1FIFOBA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 C1FIFOBA<31:0>: CAN FIFO Base Address bits These bits define the base address of all message buffers. Individual message buffers are located based on the size of the previous message buffers. This address is a physical address. Bits <1:0> are read-only and read as `0', forcing the messages to be 32-bit word-aligned in device RAM. Note 1: This bit is unimplemented and will always read `0', which forces word-alignment of messages. Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> (C1CON<23:21>) = 100). 2014-2017 Microchip Technology Inc. DS60001290E-page 265 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 23-16: C1FIFOCONn: CAN FIFO CONTROL REGISTER `n' (`n' = 0 THROUGH 15) Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- U-0 S/HC-0 S/HC-0 U-0 U-0 31:24 23:16 15:8 7:0 FSIZE<4:0>(1) R/W-0 DONLY U-0 (1) U-0 -- FRESET UINC -- -- -- -- R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 TXEN TXABAT(2) TXLARB(3) TXERR(3) TXREQ RTREN TXPR<1:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-21 Unimplemented: Read as `0' bit 20-16 FSIZE<4:0>: FIFO Size bits(1) 11111 = Reserved * * * 10000 = Reserved 01111 = FIFO is 16 messages deep * * * 00000 = FIFO is 1 message deep bit 15 Unimplemented: Read as `0' bit 14 FRESET: FIFO Reset bits 1 = FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user should poll whether this bit is clear before taking any action. 0 = No effect bit 13 UINC: Increment Head/Tail bit TXEN = 1: (FIFO configured as a Transmit FIFO) When this bit is set the FIFO head will increment by a single message TXEN = 0: (FIFO configured as a Receive FIFO) When this bit is set the FIFO tail will increment by a single message bit 12 DONLY: Store Message Data Only bit(1) TXEN = 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect. TXEN = 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO 0 = Full message is stored, including identifier bit 11-8 Unimplemented: Read as `0' Note 1: These bits can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> bits (C1CON<23:21>) = 100). This bit is updated when a message completes (or aborts) or when the FIFO is reset. This bit is reset on any read of this register or when the FIFO is reset. 2: 3: DS60001290E-page 266 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 23-16: C1FIFOCONn: CAN FIFO CONTROL REGISTER `n' (`n' = 0 THROUGH 15) bit 7 TXEN: TX/RX Buffer Selection bit 1 = FIFO is a Transmit FIFO 0 = FIFO is a Receive FIFO bit 6 TXABAT: Message Aborted bit(2) 1 = Message was aborted 0 = Message completed successfully bit 5 TXLARB: Message Lost Arbitration bit(3) 1 = Message lost arbitration while being sent 0 = Message did not lose arbitration while being sent bit 4 TXERR: Error Detected During Transmission bit(3) 1 = A bus error occured while the message was being sent 0 = A bus error did not occur while the message was being sent bit 3 TXREQ: Message Send Request TXEN = 1: (FIFO configured as a Transmit FIFO) Setting this bit to `1' requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to `0' while set (`1') will request a message abort. TXEN = 0: (FIFO configured as a receive FIFO) This bit has no effect. bit 2 RTREN: Auto RTR Enable bit 1 = When a remote transmit is received, TXREQ will be set 0 = When a remote transmit is received, TXREQ will be unaffected bit 1-0 TXPR<1:0>: Message Transmit Priority bits 11 = Highest message priority 10 = High intermediate message priority 01 = Low intermediate message priority 00 = Lowest message priority Note 1: These bits can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> bits (C1CON<23:21>) = 100). This bit is updated when a message completes (or aborts) or when the FIFO is reset. This bit is reset on any read of this register or when the FIFO is reset. 2: 3: 2014-2017 Microchip Technology Inc. DS60001290E-page 267 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 23-17: C1FIFOINTn: CAN FIFO INTERRUPT REGISTER `n' (`n' = 0 THROUGH 15) Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 31:24 23:16 15:8 7:0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 -- -- -- -- -- TXNFULLIE TXHALFIE TXEMPTYIE U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- -- RXOVFLIE RXFULLIE RXHALFIE RXNEMPTYIE U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 -- -- -- -- -- TXNFULLIF(1) TXHALFIF TXEMPTYIF(1) U-0 U-0 U-0 U-0 R/W-0 R-0 R-0 R-0 -- -- -- -- (1) RXOVFLIF RXFULLIF (1) RXHALFIF RXNEMPTYIF(1) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-27 Unimplemented: Read as `0' bit 26 TXNFULLIE: Transmit FIFO Not Full Interrupt Enable bit 1 = Interrupt enabled for FIFO not full 0 = Interrupt disabled for FIFO not full bit 25 TXHALFIE: Transmit FIFO Half Full Interrupt Enable bit 1 = Interrupt enabled for FIFO half full 0 = Interrupt disabled for FIFO half full bit 24 TXEMPTYIE: Transmit FIFO Empty Interrupt Enable bit 1 = Interrupt enabled for FIFO empty 0 = Interrupt disabled for FIFO empty bit 23-20 Unimplemented: Read as `0' bit 19 RXOVFLIE: Overflow Interrupt Enable bit 1 = Interrupt enabled for overflow event 0 = Interrupt disabled for overflow event bit 18 RXFULLIE: Full Interrupt Enable bit 1 = Interrupt enabled for FIFO full 0 = Interrupt disabled for FIFO full bit 17 RXHALFIE: FIFO Half Full Interrupt Enable bit 1 = Interrupt enabled for FIFO half full 0 = Interrupt disabled for FIFO half full bit 16 RXNEMPTYIE: Empty Interrupt Enable bit 1 = Interrupt enabled for FIFO not empty 0 = Interrupt disabled for FIFO not empty bit 15-11 Unimplemented: Read as `0' bit 10 TXNFULLIF: Transmit FIFO Not Full Interrupt Flag bit(1) TXEN = 1: (FIFO configured as a transmit buffer) 1 = FIFO is not full 0 = FIFO is full TXEN = 0: (FIFO configured as a receive buffer) Unused, reads `0' Note 1: This bit is read-only and reflects the status of the FIFO. DS60001290E-page 268 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 23-17: C1FIFOINTn: CAN FIFO INTERRUPT REGISTER `n' (`n' = 0 THROUGH 15) bit 9 TXHALFIF: FIFO Transmit FIFO Half Empty Interrupt Flag bit(1) TXEN = 1: (FIFO configured as a transmit buffer) 1 = FIFO is half full 0 = FIFO is > half full TXEN = 0: (FIFO configured as a receive buffer) Unused, reads `0' bit 8 TXEMPTYIF: Transmit FIFO Empty Interrupt Flag bit(1) TXEN = 1: (FIFO configured as a transmit buffer) 1 = FIFO is empty 0 = FIFO is not empty, at least 1 message queued to be transmitted TXEN = 0: (FIFO configured as a receive buffer) Unused, reads `0' bit 7-4 Unimplemented: Read as `0' bit 3 RXOVFLIF: Receive FIFO Overflow Interrupt Flag bit TXEN = 1: (FIFO configured as a transmit buffer) Unused, reads `0' TXEN = 0: (FIFO configured as a receive buffer) 1 = Overflow event has occurred 0 = No overflow event occured bit 2 RXFULLIF: Receive FIFO Full Interrupt Flag bit(1) TXEN = 1: (FIFO configured as a transmit buffer) Unused, reads `0' TXEN = 0: (FIFO configured as a receive buffer) 1 = FIFO is full 0 = FIFO is not full bit 1 RXHALFIF: Receive FIFO Half Full Interrupt Flag bit(1) TXEN = 1: (FIFO configured as a transmit buffer) Unused, reads `0' TXEN = 0: (FIFO configured as a receive buffer) 1 = FIFO is half full 0 = FIFO is < half full bit 0 RXNEMPTYIF: Receive Buffer Not Empty Interrupt Flag bit(1) TXEN = 1: (FIFO configured as a transmit buffer) Unused, reads `0' TXEN = 0: (FIFO configured as a receive buffer) 1 = FIFO is not empty, has at least 1 message 0 = FIFO is empty Note 1: This bit is read-only and reflects the status of the FIFO. 2014-2017 Microchip Technology Inc. DS60001290E-page 269 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 23-18: C1FIFOUAn: CAN FIFO USER ADDRESS REGISTER `n' (`n' = 0 THROUGH 15) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-0(1) R-0(1) C1FIFOUAn<31:24> R-x R-x R-x R-x R-x R-x C1FIFOUAn<15:8> R-x R-x R-x R-x R-x C1FIFOUAn<7:0> Legend: R = Readable bit -n = Value at POR bit 31-0 R-x C1FIFOUAn<23:16> W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown C1FIFOUAn<31:0>: CAN FIFO User Address bits TXEN = 1: (FIFO configured as a transmit buffer) A read of this register will return the address where the next message is to be written (FIFO head). TXEN = 0: (FIFO configured as a receive buffer) A read of this register will return the address where the next message is to be read (FIFO tail). Note 1: Note: This bit will always read `0', which forces byte-alignment of messages. This register is not guaranteed to read correctly in Configuration mode, and should only be accessed when the module is not in Configuration mode. REGISTER 23-19: C1FIFOCIn: CAN MODULE MESSAGE INDEX REGISTER `n' (`n' = 0 THROUGH 15) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 -- -- -- Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set C1FIFOCIn<4:0> U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-5 Unimplemented: Read as `0' bit 4-0 C1FIFOCIn<4:0>: CAN Side FIFO Message Index bits TXEN = 1: (FIFO configured as a transmit buffer) A read of this register will return an index to the message that the FIFO will next attempt to transmit. TXEN = 0: (FIFO configured as a receive buffer) A read of this register will return an index to the message that the FIFO will use to save the next message. DS60001290E-page 270 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 24.0 The Analog Comparator module contains three comparators that can be configured in a variety of ways. COMPARATOR Note: This data sheet summarizes the features of the PIC32MX1XX/2XX/5XX 64/100-pin family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 19. "Comparator" (DS60001110) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). The following are the key features of this module: * Selectable inputs available include: - Analog inputs multiplexed with I/O pins - On-chip internal absolute voltage reference (IVREF) - Comparator voltage reference (CVREF) * Outputs can be inverted * Selectable interrupt generation A block diagram of the comparator module is provided in Figure 24-1. FIGURE 24-1: COMPARATOR BLOCK DIAGRAM CCH<1:0> C1INB C1INC COE C1IND CMP1 C1OUT CREF CMSTAT<C1OUT> CM1CON<COUT> CPOL C1INA CCH<1:0> C2INB To CTMU module (Pulse Generator) C2INC COE C2IND CMP2 C2OUT CREF CMSTAT<C2OUT> CM2CON<COUT> CPOL C2INA CCH<1:0> C3INB C3INC COE C3IND CMP3 C3OUT CREF CPOL C3INA CMSTAT<C3OUT> CM3CON<COUT> CVREF(1) IVREF (1.2V) Note 1: To ADC (Internal AN28 on 64-pin devices; Internal AN48 on 100-pin devices) Internally connected. See Section 25.0 "Comparator Voltage Reference (CVREF)" for more information. 2014-2017 Microchip Technology Inc. DS60001290E-page 271 Control Registers A000 CM1CON A010 CM2CON A020 CM3CON A060 CMSTAT Legend: Note 1: COMPARATOR REGISTER MAP 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 -- 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Bits Register Name(1) Virtual Address (BF80_#) TABLE 24-1: 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 31:16 ON -- COE -- CPOL -- -- -- -- -- -- -- -- -- COUT -- EVPOL<1:0> -- -- -- -- CREF -- -- -- -- -- CCH<1:0> -- -- E1C3 0000 15:0 31:16 ON -- COE -- CPOL -- -- -- -- -- -- -- -- -- COUT -- EVPOL<1:0> -- -- -- -- CREF -- -- -- -- -- CCH<1:0> -- -- E1C3 0000 15:0 31:16 ON -- COE -- CPOL -- -- -- -- -- -- -- -- -- COUT -- EVPOL<1:0> -- -- -- -- CREF -- -- -- -- -- CCH<1:0> -- -- E1C3 0000 -- -- -- -- C3OUT 15:0 -- -- SIDL -- -- -- -- -- x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. -- C2OUT C1OUT 0000 All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 272 24.1 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 24-1: Bit Range 31:24 23:16 15:8 7:0 CMxCON: COMPARATOR CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- R/W-0 (1) R/W-0 ON COE R/W-1 R/W-1 EVPOL<1:0> Legend: R = Readable bit -n = Value at POR Bit Bit 28/20/12/4 27/19/11/3 -- R/W-0 (2) CPOL Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- -- U-0 U-0 U-0 U-0 R-0 COUT -- -- -- -- U-0 R/W-0 U-0 U-0 R/W-1 -- CREF -- -- W = Writable bit `1' = Bit is set R/W-1 CCH<1:0> U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: Comparator ON bit(1) 1 = Module is enabled. Setting this bit does not affect the other bits in this register 0 = Module is disabled and does not consume current. Clearing this bit does not affect the other bits in this register bit 14 COE: Comparator Output Enable bit 1 = Comparator output is driven on the output CxOUT pin 0 = Comparator output is not driven on the output CxOUT pin bit 13 CPOL: Comparator Output Inversion bit(2) 1 = Output is inverted 0 = Output is not inverted bit 12-9 Unimplemented: Read as `0' bit 8 COUT: Comparator Output bit 1 = Output of the Comparator is a `1' 0 = Output of the Comparator is a `0' bit 7-6 EVPOL<1:0>: Interrupt Event Polarity Select bits 11 = Comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output 10 = Comparator interrupt is generated on a high-to-low transition of the comparator output 01 = Comparator interrupt is generated on a low-to-high transition of the comparator output 00 = Comparator interrupt generation is disabled bit 5 Unimplemented: Read as `0' bit 4 CREF: Comparator Positive Input Configure bit 1 = Comparator non-inverting input is connected to the internal CVREF 0 = Comparator non-inverting input is connected to the CXINA pin bit 3-2 Unimplemented: Read as `0' bit 1-0 CCH<1:0>: Comparator Negative Input Select bits for Comparator 11 = Comparator inverting input is connected to the IVREF 10 = Comparator inverting input is connected to the CxIND pin 01 = Comparator inverting input is connected to the CxINC pin 00 = Comparator inverting input is connected to the CxINB pin Note 1: 2: When using the 1:1 PBCLK divisor, the user's software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. Setting this bit will invert the signal to the comparator interrupt generator as well. This will result in an interrupt being generated on the opposite edge from the one selected by EVPOL<1:0>. 2014-2017 Microchip Technology Inc. DS60001290E-page 273 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 24-2: Bit Range 31:24 23:16 15:8 7:0 CMSTAT: COMPARATOR STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 -- -- -- U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- U-0 U-0 -- -- R/W-0 U-0 U-0 U-0 U-0 U-0 SIDL -- -- -- -- -- U-0 U-0 -- -- U-0 U-0 U-0 R-0 R-0 R-0 -- -- -- C3OUT C2OUT C1OUT Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-14 Unimplemented: Read as `0' bit 13 SIDL: Stop in IDLE Control bit 1 = All Comparator modules are disabled in IDLE mode 0 = All Comparator modules continue to operate in the IDLE mode bit 12-3 Unimplemented: Read as `0' bit 2 C3OUT: Comparator Output bit 1 = Output of Comparator 3 is a `1' 0 = Output of Comparator 3 is a `0' bit 1 C2OUT: Comparator Output bit 1 = Output of Comparator 2 is a `1' 0 = Output of Comparator 2 is a `0' bit 0 C1OUT: Comparator Output bit 1 = Output of Comparator 1 is a `1' 0 = Output of Comparator 1 is a `0' DS60001290E-page 274 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 25.0 Note: A block diagram of the module is illustrated in Figure 25-1. The resistor ladder is segmented to provide two ranges of voltage reference values and has a power-down function to conserve power when the reference is not being used. The module's supply reference can be provided from either device VDD/VSS or an external voltage reference. The CVREF output is available for the comparators and typically available for pin output. COMPARATOR VOLTAGE REFERENCE (CVREF) This data sheet summarizes the features of the PIC32MX1XX/2XX/5XX 64/100-pin family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 20. "Comparator Voltage Reference (CVREF)" (DS60001109) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). The CVREF module has the following features: * High and low range selection * Sixteen output levels available for each range * Internally connected to comparators to conserve device pins * Output can be connected to a pin The CVREF module is a 16-tap, resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it also may be used independently of them. FIGURE 25-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ AVDD CVRSS = 1 CVRSRC (DACREFH) 8R CVRSS = 0 CVR<3:0> CVREF R CVREN R R 16-to-1 MUX R 16 Steps R CVREFOUT CVRCON<CVROE> R R CVRR VREFAVSS 2014-2017 Microchip Technology Inc. 8R CVRSS = 1 CVRSS = 0 DS60001290E-page 275 Control Registers Virtual Address (BF80_#) TABLE 25-1: Legend: 1: 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 -- -- -- -- -- -- -- -- -- -- -- CVROE 15:0 ON -- -- -- -- -- -- -- x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. 22/6 21/5 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- -- CVRR CVRSS CVR<3:0> All Resets Register Name(1) Bit Range Bits 9800 CVRCON Note COMPARATOR VOLTAGE REFERENCE REGISTER MAP 0000 0000 The register in this table has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 276 25.1 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 25-1: Bit Range 31:24 23:16 15:8 7:0 CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 (1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 ON U-0 R/W-0 R/W-0 R/W-0 -- CVROE CVRR CVRSS CVR<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: Comparator Voltage Reference On bit(1) 1 = Module is enabled Setting this bit does not affect other bits in the register. 0 = Module is disabled and does not consume current Clearing this bit does not affect the other bits in the register. bit 14-7 Unimplemented: Read as `0' bit 6 CVROE: CVREFOUT Enable bit 1 = Voltage level is output on CVREFOUT pin 0 = Voltage level is disconnected from CVREFOUT pin bit 5 CVRR: CVREF Range Selection bit 1 = 0 to 0.625 CVRSRC, with CVRSRC/24 step size 0 = 0.25 CVRSRC to 0.719 CVRSRC, with CVRSRC/32 step size bit 4 CVRSS: CVREF Source Selection bit 1 = Comparator voltage reference source, CVRSRC = (VREF+) - (VREF-) 0 = Comparator voltage reference source, CVRSRC = AVDD - AVSS bit 3-0 CVR<3:0>: CVREF Value Selection 0 CVR<3:0> 15 bits When CVRR = 1: CVREF = (CVR<3:0>/24) (CVRSRC) When CVRR = 0: CVREF = 1/4 (CVRSRC) + (CVR<3:0>/32) (CVRSRC) Note 1: When using 1:1 PBCLK divisor, the user's software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. 2014-2017 Microchip Technology Inc. DS60001290E-page 277 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY NOTES: DS60001290E-page 278 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 26.0 The CTMU module includes the following key features: CHARGE TIME MEASUREMENT UNIT (CTMU) * Up to 13 channels available for capacitive or time measurement input * On-chip precision current source * 16-edge input trigger sources * Selection of edge or level-sensitive inputs * Polarity control for each edge source * Control of edge sequence * Control of response to edges * High precision time measurement * Time delay of external or internal signal asynchronous to system clock * Integrated temperature sensing diode * Control of current source during auto-sampling * Four current source ranges * Time measurement resolution of one nanosecond This data sheet summarizes the features of the PIC32MX1XX/2XX/5XX 64/100-pin family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 37. "Charge Time Measurement Unit (CTMU)" (DS60001167) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com). Note: The Charge Time Measurement Unit (CTMU) is a flexible analog module that has a configurable current source with a digital configuration circuit built around it. The CTMU can be used for differential time measurement between pulse sources and can be used for generating an asynchronous pulse. By working with other on-chip analog modules, the CTMU can be used for high resolution time measurement, measure capacitance, measure relative changes in capacitance or generate output pulses with a specific time delay. The CTMU is ideal for interfacing with capacitive-based sensors. FIGURE 26-1: A block diagram of the CTMU is shown in Figure 26-1. CTMU BLOCK DIAGRAM CTMUCON1 or CTMUCON2 CTMUICON ITRIM<5:0> IRNG<1:0> Current Source CTED1 * * * Edge Control Logic CTED13 Timer1 OC1 IC1-IC3 CMP1-CMP2 PBCLK EDG1STAT EDG2STAT TGEN Current Control CTMUP CTMUT (To ADC) Temperature Sensor CTMU Control Logic ADC Trigger Pulse Generator CTPLS CTMUI (To ADC S&H capacitor) C2INB CDelay Comparator 2 External capacitor for pulse generation Current Control Selection TGEN EDG1STAT, EDG2STAT CTMUT 0 EDG1STAT = EDG2STAT CTMUI 0 EDG1STAT EDG2STAT CTMUP 1 EDG1STAT EDG2STAT No Connect 1 EDG1STAT = EDG2STAT 2014-2017 Microchip Technology Inc. DS60001290E-page 279 Control Registers A200 CTMUCON Legend: Note 1: CTMU REGISTER MAP 31/15 30/14 29/13 31:16 EDG1MOD EDG1POL 15:0 ON -- CTMUSIDL 28/12 27/11 26/10 25/9 24/8 23/7 22/6 EDG2STAT EDG1STAT EDG2MOD EDG2POL EDG1SEL<3:0> TGEN EDGEN EDGSEQEN IDISSEN CTTRIG 21/5 20/4 19/3 EDG2SEL<3:0> ITRIM<5:0> 18/2 17/1 16/0 -- -- IRNG<1:0> All Resets Bit Range Bits Register Name(1) Virtual Address (BF80_#) TABLE 26-1: 0000 0000 x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 "CLR, SET, and INV Registers" for more information. 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 280 26.1 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 26-1: Bit Range 31:24 23:16 15:8 7:0 CTMUCON: CTMU CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 EDG1MOD EDG1POL R/W-0 R/W-0 R/W-0 Bit 26/18/10/2 R/W-0 EDG1SEL<3:0> R/W-0 R/W-0 EDG2MOD EDG2POL R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 EDG2STAT EDG1STAT R/W-0 EDG2SEL<3:0> U-0 U-0 -- -- R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ON -- CTMUSIDL TGEN(1) EDGEN EDGSEQEN IDISSEN(2) CTTRIG R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITRIM<5:0> Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set IRNG<1:0> U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31 EDG1MOD: Edge 1 Edge Sampling Select bit 1 = Input is edge-sensitive 0 = Input is level-sensitive bit 30 EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 programmed for a positive edge response 0 = Edge 1 programmed for a negative edge response bit 29-26 EDG1SEL<3:0>: Edge 1 Source Select bits 1111 = IC4 Capture Event is selected 1110 = C2OUT pin is selected 1101 = C1OUT pin is selected 1100 = IC3 Capture Event is selected 1011 = IC2 Capture Event is selected 1010 = IC1 Capture Event is selected 1001 = CTED8 pin is selected 1000 = CTED7 pin is selected 0111 = CTED6 pin is selected 0110 = CTED5 pin is selected 0101 = CTED4 pin is selected 0100 = CTED3 pin is selected 0011 = CTED1 pin is selected 0010 = CTED2 pin is selected 0001 = OC1 Compare Event is selected 0000 = Timer1 Event is selected bit 25 EDG2STAT: Edge 2 Status bit Indicates the status of Edge 2 and can be written to control edge source 1 = Edge 2 has occurred 0 = Edge 2 has not occurred Note 1: 2: 3: 4: When this bit is set for Pulse Delay Generation, the EDG2SEL<3:0> bits must be set to `1110' to select C2OUT. The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor before conducting the measurement. The IDISSEN bit, when set to `1', performs this function. The ADC module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor array. Refer to the CTMU Current Source Specifications (Table 31-41) in Section 31.0 "40 MHz Electrical Characteristics" for current values. This bit setting is not available for the CTMU temperature diode. 2014-2017 Microchip Technology Inc. DS60001290E-page 281 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 26-1: CTMUCON: CTMU CONTROL REGISTER (CONTINUED) bit 24 EDG1STAT: Edge 1 Status bit Indicates the status of Edge 1 and can be written to control edge source 1 = Edge 1 has occurred 0 = Edge 1 has not occurred bit 23 EDG2MOD: Edge 2 Edge Sampling Select bit 1 = Input is edge-sensitive 0 = Input is level-sensitive bit 22 EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 programmed for a positive edge response 0 = Edge 2 programmed for a negative edge response bit 21-18 EDG2SEL<3:0>: Edge 2 Source Select bits 1111 = IC4 Capture Event is selected 1110 = C2OUT pin is selected 1101 = C1OUT pin is selected 1100 = PBCLK clock is selected 1011 = IC3 Capture Event is selected 1010 = IC2 Capture Event is selected 1001 = IC1 Capture Event is selected 1000 = CTED13 pin is selected 0111 = CTED12 pin is selected 0110 = CTED11 pin is selected 0101 = CTED10 pin is selected 0100 = CTED9 pin is selected 0011 = CTED1 pin is selected 0010 = CTED2 pin is selected 0001 = OC1 Compare Event is selected 0000 = Timer1 Event is selected bit 17-16 Unimplemented: Read as `0' bit 15 ON: ON Enable bit 1 = Module is enabled 0 = Module is disabled bit 14 Unimplemented: Read as `0' bit 13 CTMUSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12 TGEN: Time Generation Enable bit(1) 1 = Enables edge delay generation 0 = Disables edge delay generation bit 11 EDGEN: Edge Enable bit 1 = Edges are not blocked 0 = Edges are blocked Note 1: 2: 3: 4: When this bit is set for Pulse Delay Generation, the EDG2SEL<3:0> bits must be set to `1110' to select C2OUT. The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor before conducting the measurement. The IDISSEN bit, when set to `1', performs this function. The ADC module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor array. Refer to the CTMU Current Source Specifications (Table 31-41) in Section 31.0 "40 MHz Electrical Characteristics" for current values. This bit setting is not available for the CTMU temperature diode. DS60001290E-page 282 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 26-1: bit 10 CTMUCON: CTMU CONTROL REGISTER (CONTINUED) EDGSEQEN: Edge Sequence Enable bit 1 = Edge 1 must occur before Edge 2 can occur 0 = No edge sequence is needed IDISSEN: Analog Current Source Control bit(2) 1 = Analog current source output is grounded 0 = Analog current source output is not grounded CTTRIG: Trigger Control bit 1 = Trigger output is enabled 0 = Trigger output is disabled ITRIM<5:0>: Current Source Trim bits 011111 = Maximum positive change from nominal current 011110 bit 9 bit 8 bit 7-2 * * * 000001 = Minimum positive change from nominal current 000000 = Nominal current output specified by IRNG<1:0> 111111 = Minimum negative change from nominal current * * * 100010 100001 = Maximum negative change from nominal current IRNG<1:0>: Current Range Select bits(3) 11 = 100 times base current 10 = 10 times base current 01 = Base current level 00 = 1000 times base current(4) bit 1-0 Note 1: 2: 3: 4: When this bit is set for Pulse Delay Generation, the EDG2SEL<3:0> bits must be set to `1110' to select C2OUT. The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor before conducting the measurement. The IDISSEN bit, when set to `1', performs this function. The ADC module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor array. Refer to the CTMU Current Source Specifications (Table 31-41) in Section 31.0 "40 MHz Electrical Characteristics" for current values. This bit setting is not available for the CTMU temperature diode. 2014-2017 Microchip Technology Inc. DS60001290E-page 283 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY NOTES: DS60001290E-page 284 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 27.0 Note: POWER-SAVING FEATURES This data sheet summarizes the features of the PIC32MX1XX/2XX/5XX 64/100-pin family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 10. "PowerSaving Features" (DS60001130) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). This section describes power-saving features for the PIC32MX1XX/2XX/5XX 64/100-pin family of devices. These PIC32 devices offer a total of nine methods and modes, organized into two categories, that allow the user to balance power consumption with device performance. In all of the methods and modes described in this section, power-saving is controlled by software. 27.1 Power Saving with CPU Running When the CPU is running, power consumption can be controlled by reducing the CPU clock frequency, lowering the PBCLK and by individually disabling modules. These methods are grouped into the following categories: * FRC Run mode: the CPU is clocked from the FRC clock source with or without postscalers. * LPRC Run mode: the CPU is clocked from the LPRC clock source. * SOSC Run mode: the CPU is clocked from the SOSC clock source. In addition, the Peripheral Bus Scaling mode is available where peripherals are clocked at the programmable fraction of the CPU clock (SYSCLK). 27.2 CPU Halted Methods The device supports two power-saving modes, Sleep and Idle, both of which Halt the clock to the CPU. These modes operate with all clock sources, as listed below: * POSC Idle mode: the system clock is derived from the POSC. The system clock source continues to operate. Peripherals continue to operate, but can optionally be individually disabled. * FRC Idle mode: the system clock is derived from the FRC with or without postscalers. Peripherals continue to operate, but can optionally be individually disabled. * SOSC Idle mode: the system clock is derived from the SOSC. Peripherals continue to operate, but can optionally be individually disabled. 2014-2017 Microchip Technology Inc. * LPRC Idle mode: the system clock is derived from the LPRC. Peripherals continue to operate, but can optionally be individually disabled. This is the lowest power mode for the device with a clock running. * Sleep mode: the CPU, the system clock source and any peripherals that operate from the system clock source are Halted. Some peripherals can operate in Sleep using specific clock sources. This is the lowest power mode for the device. 27.3 Power-Saving Operation Peripherals and the CPU can be Halted or disabled to further reduce power consumption. 27.3.1 SLEEP MODE Sleep mode has the lowest power consumption of the device power-saving operating modes. The CPU and most peripherals are Halted. Select peripherals can continue to operate in Sleep mode and can be used to wake the device from Sleep. See the individual peripheral module sections for descriptions of behavior in Sleep. Sleep mode includes the following characteristics: * The CPU is Halted. * The system clock source is typically shutdown. See Section 27.3.3 "Peripheral Bus Scaling Method" for specific information. * There can be a wake-up delay based on the oscillator selection. * The Fail-Safe Clock Monitor (FSCM) does not operate during Sleep mode. * The BOR circuit remains operative during Sleep mode. * The WDT, if enabled, is not automatically cleared prior to entering Sleep mode. * Some peripherals can continue to operate at limited functionality in Sleep mode. These peripherals include I/O pins that detect a change in the input signal, WDT, ADC, UART and peripherals that use an external clock input or the internal LPRC oscillator (e.g., RTCC, Timer1 and Input Capture). * I/O pins continue to sink or source current in the same manner as they do when the device is not in Sleep. * The USB module can override the disabling of the Posc or FRC. Refer to the USB section for specific details. * Modules can be individually disabled by software prior to entering Sleep in order to further reduce consumption. DS60001290E-page 285 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY The processor will exit, or `wake-up', from Sleep on one of the following events: * On any interrupt from an enabled source that is operating in Sleep. The interrupt priority must be greater than the current CPU priority. * On any form of device Reset * On a WDT time-out If the interrupt priority is lower than or equal to the current priority, the CPU will remain Halted, but the PBCLK will start running and the device will enter into Idle mode. 27.3.2 IDLE MODE In Idle mode, the CPU is Halted but the System Clock (SYSCLK) source is still enabled. This allows peripherals to continue operation when the CPU is Halted. Peripherals can be individually configured to Halt when entering Idle by setting their respective SIDL bit. Latency, when exiting Idle mode, is very low due to the CPU oscillator source remaining active. Note 1: Changing the PBCLK divider ratio requires recalculation of peripheral timing. For example, assume the UART is configured for 9600 baud with a PB clock ratio of 1:1 and a POSC of 8 MHz. When the PB clock divisor of 1:2 is used, the input frequency to the baud clock is cut in half; therefore, the baud rate is reduced to 1/2 its former value. Due to numeric truncation in calculations (such as the baud rate divisor), the actual baud rate may be a tiny percentage different than expected. For this reason, any timing calculation required for a peripheral should be performed with the new PB clock frequency instead of scaling the previous value based on a change in the PB divisor ratio. 2: Oscillator start-up and PLL lock delays are applied when switching to a clock source that was disabled and that uses a crystal and/or the PLL. For example, assume the clock source is switched from POSC to LPRC just prior to entering Sleep in order to save power. No oscillator startup delay would be applied when exiting Idle. However, when switching back to POSC, the appropriate PLL and/or oscillator start-up/lock delays would be applied. DS60001290E-page 286 The device enters Idle mode when the SLPEN bit (OSCCON<4>) is clear and a WAIT instruction is executed. The processor will wake or exit from Idle mode on the following events: * On any interrupt event for which the interrupt source is enabled. The priority of the interrupt event must be greater than the current priority of the CPU. If the priority of the interrupt event is lower than or equal to current priority of the CPU, the CPU will remain Halted and the device will remain in Idle mode. * On any form of device Reset * On a WDT time-out interrupt 27.3.3 PERIPHERAL BUS SCALING METHOD Most of the peripherals on the device are clocked using the PBCLK. The peripheral bus can be scaled relative to the SYSCLK to minimize the dynamic power consumed by the peripherals. The PBCLK divisor is controlled by PBDIV<1:0> (OSCCON<20:19>), allowing SYSCLK to PBCLK ratios of 1:1, 1:2, 1:4 and 1:8. All peripherals using PBCLK are affected when the divisor is changed. Peripherals such as the USB, Interrupt Controller, DMA, and the bus matrix are clocked directly from SYSCLK. As a result, they are not affected by PBCLK divisor changes. Changing the PBCLK divisor affects: * The CPU to peripheral access latency. The CPU has to wait for next PBCLK edge for a read to complete. In 1:8 mode, this results in a latency of one to seven SYSCLKs. * The power consumption of the peripherals. Power consumption is directly proportional to the frequency at which the peripherals are clocked. The greater the divisor, the lower the power consumed by the peripherals. To minimize dynamic power, the PB divisor should be chosen to run the peripherals at the lowest frequency that provides acceptable system performance. When selecting a PBCLK divider, peripheral clock requirements, such as baud rate accuracy, should be taken into account. For example, the UART peripheral may not be able to achieve all baud rate values at some PBCLK divider depending on the SYSCLK value. 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 27.4 Peripheral Module Disable The Peripheral Module Disable (PMD) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. When a peripheral is disabled using the appropriate PMD control bit, the peripheral is in a minimum power consumption state. The control and status registers associated with the peripheral are also disabled, so writes to those registers do not have effect and read values are invalid. TABLE 27-1: To disable a peripheral, the associated PMDx bit must be set to `1'. To enable a peripheral, the associated PMDx bit must be cleared (default). See Table 27-1 for more information. Note: Disabling a peripheral module while it's ON bit is set, may result in undefined behavior. The ON bit for the associated peripheral module must be cleared prior to disable a module via the PMDx bits. PERIPHERAL MODULE DISABLE BITS AND LOCATIONS Peripheral(1) ADC1 CTMU Comparator Voltage Reference Comparator 1 Comparator 2 Comparator 3 Input Capture 1 Input Capture 2 Input Capture 3 Input Capture 4 Input Capture 5 Output Compare 1 Output Compare 2 Output Compare 3 Output Compare 4 Output Compare 5 Timer1 Timer2 Timer3 Timer4 Timer5 UART1 UART2 UART3 UART4 UART5 SPI1 PMDx bit Name(1) Register Name and Bit Location AD1MD CTMUMD CVRMD CMP1MD CMP2MD CMP3MD IC1MD IC2MD IC3MD IC4MD IC5MD OC1MD OC2MD OC3MD OC4MD OC5MD T1MD T2MD T3MD T4MD T5MD U1MD U2MD U3MD U4MD U5MD SPI1MD PMD1<0> PMD1<8> PMD1<12> PMD2<0> PMD2<1> PMD2<2> PMD3<0> PMD3<1> PMD3<2> PMD3<3> PMD3<4> PMD3<16> PMD3<17> PMD3<18> PMD3<19> PMD3<20> PMD4<0> PMD4<1> PMD4<2> PMD4<3> PMD4<4> PMD5<0> PMD5<1> PMD5<2> PMD5<3> PMD5<4> PMD5<8> SPI2 SPI2MD PMD5<9> SPI3 SPI3MD PMD5<10> SPI4 SPI4MD PMD5<11> I2C1 I2C1MD PMD5<16> I2C2 I2C2MD PMD5<17> USB(2) USBMD PMD5<24> CAN CAN1MD PMD5<28> RTCC RTCCMD PMD6<0> Reference Clock Output REFOMD PMD6<1> PMP PMPMD PMD6<16> Note 1: Not all modules and associated PMDx bits are available on all devices. See TABLE 1: "PIC32MX1XX/2XX/5XX 64/100-pin Controller Family Features" for the list of available peripherals. 2: Module must not be busy after clearing the associated ON bit and prior to setting the USBMD bit. 2014-2017 Microchip Technology Inc. DS60001290E-page 287 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 27.4.1 CONTROLLING CONFIGURATION CHANGES Because peripherals can be disabled during run time, some restrictions on disabling peripherals are needed to prevent accidental configuration changes. PIC32 devices include two features to prevent alterations to enabled or disabled peripherals: * Control register lock sequence * Configuration bit select lock 27.4.1.1 Control Register Lock Under normal operation, writes to the PMDx registers are not allowed. Attempted writes appear to execute normally, but the contents of the registers remain unchanged. To change these registers, they must be unlocked in hardware. The register lock is controlled by the PMDLOCK Configuration bit (CFGCON<12>). Setting PMDLOCK prevents writes to the control registers; clearing PMDLOCK allows writes. To set or clear PMDLOCK, an unlock sequence must be executed. Refer to Section 6. "Oscillator" (DS60001112) in the "PIC32 Family Reference Manual" for details. 27.4.1.2 Configuration Bit Select Lock As an additional level of safety, the device can be configured to prevent more than one write session to the PMDx registers. The PMDL1WAY Configuration bit (DEVCFG3<28>) blocks the PMDLOCK bit from being cleared after it has been set once. If PMDLOCK remains set, the register unlock procedure does not execute, and the peripheral pin select control registers cannot be written to. The only way to clear the bit and re-enable PMD functionality is to perform a device Reset. DS60001290E-page 288 2014-2017 Microchip Technology Inc. Register Name PMD1 F250 PMD2 F260 PMD3 F270 PMD4 F280 PMD5 F290 PMD6 Legend: Note 1: Bit Range Bits 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 -- -- -- -- -- -- -- CVRMD -- -- -- -- -- -- -- CTMUMD -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- OC5MD IC5MD OC4MD IC4MD OC3MD IC3MD OC2MD IC2MD -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- T5MD -- T4MD -- T3MD -- T2MD -- -- -- -- -- -- CAN1MD -- -- SPI4MD -- SPI3MD -- -- -- -- -- -- -- U5MD -- U4MD -- U3MD I2C1MD U2MD -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- USBMD(1) SPI2MD SPI1MD -- -- -- -- x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This bit is only available on devices with a USB module. 16/0 All Resets(1) Virtual Address (BF80_#) F240 PERIPHERAL MODULE DISABLE REGISTER SUMMARY -- 0000 AD1MD 0000 -- -- -- 0000 CMP3MD CMP2MD CMP1MD 0000 OC1MD 0000 IC1MD 0000 -- T1MD 0000 0000 I2C1MD 0000 U1MD 0000 -- PMPMD 0000 REFOMD RTCCMD 0000 DS60001290E-page 289 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 2014-2017 Microchip Technology Inc. TABLE 27-2: PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY NOTES: DS60001290E-page 290 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 28.0 Note: SPECIAL FEATURES This data sheet summarizes the features of the PIC32MX1XX/2XX/5XX 64/100-pin family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 9. "Watchdog Timer and Power-up Timer" (DS60001114), Section 32. "Configuration" (DS60001124) and Section 33. "Programming and Diagnostics" (DS60001129) in the "PIC32 Family Reference Manual", which are available from the Microchip web site (www.microchip.com/PIC32). 28.1 Configuration Bits The Configuration bits can be programmed using the following registers to select various device configurations. * * * * * DEVCFG0: Device Configuration Word 0 DEVCFG1: Device Configuration Word 1 DEVCFG2: Device Configuration Word 2 DEVCFG3: Device Configuration Word 3 CFGCON: Configuration Control Register In addition, the DEVID register (Register 28-6) provides device and revision information. PIC32MX1XX/2XX/5XX 64/100-pin devices include several features intended to maximize application flexibility and reliability and minimize cost through elimination of external components. These are: * * * * Flexible device configuration Watchdog Timer (WDT) Joint Test Action Group (JTAG) interface In-Circuit Serial ProgrammingTM (ICSPTM) 2014-2017 Microchip Technology Inc. DS60001290E-page 291 Registers 0BF4 DEVCFG2 0BF8 DEVCFG1 0BFC DEVCFG0 Legend: Note 1: 29/13 28/12 27/11 26/10 25/9 -- -- -- 15:0 31:16 -- -- -- -- -- -- 15:0 31:16 UPLLEN(1) -- -- -- -- -- -- -- -- -- -- FPBDIV<1:0> -- CP -- -- OSCIOFNC -- 15:0 31:16 FCKSM<1:0> -- -- -- 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- -- -- -- -- USERID<15:0> -- -- -- -- -- -- FPLLODIV<2:0> xxxx xxxx -- FPLLIDIV<2:0> WDTPS<4:0> xxxx xxxx UPLLIDIV<2:0>(1) -- FPLLMUL<2:0> FWDTWINSZ<1:0> FWDTEN WINDIS -- POSCMOD<1:0> -- BWP 15:0 PWP<5:0> -- -- -- -- x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This bit is only available on devices with a USB module. IESO -- -- -- FSOSCEN -- -- -- -- -- -- -- ICESEL<1:0> FNOSC<2:0> PWP<9:6> JTAGEN DEBUG<1:0> 2014-2017 Microchip Technology Inc. (3) F230 SYSKEY Legend: Note 1: 2: xxxx DEVICE AND REVISION ID SUMMARY Bit Range Register Name DEVID xxxx xxxx xxxx Bits F200 CFGCON All Resets Bit Range 30/14 31:16 FVBUSONIO FUSBIDIO IOL1WAY PMDL1WAY TABLE 28-2: Virtual Address (BF80_#) 31/15 31/15 30/14 31:16 -- -- 15:0 -- -- 31:16 15:0 31:16 15:0 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- IOLOCK PMDLOCK VER<3:0> DEVID<27:16> DEVID<15:0> SYSKEY<31:0> x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Reset values are dependent on the device. This bit is not available on 64-pin devices. 19/3 18/2 17/1 -- -- -- JTAGEN TROEN(2) -- 16/0 -- All Resets(1) 0BF0 DEVCFG3 F220 DEVCFG: DEVICE CONFIGURATION WORD SUMMARY Bits Register Name Virtual Address (BFC0_#) TABLE 28-1: 0000 TDOEN 000B xxxx xxxx 0000 0000 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 292 28.2 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 28-1: Bit Range 31:24 23:16 15:8 7:0 DEVCFG0: DEVICE CONFIGURATION WORD 0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 r-0 r-1 r-1 R/P r-1 r-1 r-1 R/P -- -- -- CP -- -- -- BWP R/P R/P R/P R/P r-1 r-1 r-1 r-1 -- -- -- -- R/P R/P R/P R/P PWP<9:6> R/P R/P PWP<5:0> r-1 r-1 r-1 -- -- -- R/P R/P ICESEL<1:0> R/P JTAGEN(1) r-1 r-1 -- -- R/P R/P DEBUG<1:0> Legend: r = Reserved bit P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31 Bit 24/16/8/0 x = Bit is unknown Reserved: Write `0' bit 30-29 Reserved: Write `1' bit 28 CP: Code-Protect bit Prevents boot and program Flash memory from being read or modified by an external programming device. 1 = Protection is disabled 0 = Protection is enabled bit 27-25 Reserved: Write `1' bit 24 BWP: Boot Flash Write-Protect bit Prevents boot Flash memory from being modified during code execution. 1 = Boot Flash is writable 0 = Boot Flash is not writable bit 23-20 Reserved: Write `1' Note 1: This bit sets the value for the JTAGEN bit in the CFGCON register. 2014-2017 Microchip Technology Inc. DS60001290E-page 293 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 28-1: DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED) bit 19-10 PWP<9:0>: Program Flash Write-Protect bits Prevents selected program Flash memory pages from being modified during code execution. The PWP bits represent the one's compliment of the number of write protected program Flash memory pages. 1111111111 = Disabled 1111111110 = Memory below 0x0400 address is write-protected 1111111101 = Memory below 0x0800 address is write-protected 1111111100 = Memory below 0x0C00 address is write-protected 1111111011 = Memory below 0x1000 (4K) address is write-protected 1111111010 = Memory below 0x1400 address is write-protected 1111111001 = Memory below 0x1800 address is write-protected 1111111000 = Memory below 0x1C00 address is write-protected 1111110111 = Memory below 0x2000 (8K) address is write-protected 1111110110 = Memory below 0x2400 address is write-protected 1111110101 = Memory below 0x2800 address is write-protected 1111110100 = Memory below 0x2C00 address is write-protected 1111110011 = Memory below 0x3000 address is write-protected 1111110010 = Memory below 0x3400 address is write-protected 1111110001 = Memory below 0x3800 address is write-protected 1111110000 = Memory below 0x3C00 address is write-protected 1111101111 = Memory below 0x4000 (16K) address is write-protected * * * 1110111111 = Memory below 0x10000 (64K) address is write-protected * * * 1101111111 = Memory below 0x20000 (128K) address is write-protected * * * 1011111111 = Memory below 0x40000 (256K) address is write-protected * * * 0111111111 = Memory below 0x80000 (512K) address is write-protected * * * 0000000000 = All possible memory is write-protected Note: These bits are effective only if Boot Flash is also protected by clearing the BWP bit (DEVCFG0<24>). bit 9-5 Reserved: Write `1' bit 4-3 ICESEL<1:0>: In-Circuit Emulator/Debugger Communication Channel Select bits 11 = PGEC1/PGED1 pair is used 10 = PGEC2/PGED2 pair is used 01 = PGEC3/PGED3 pair is used 00 = Reserved bit 2 JTAGEN: JTAG Enable bit(1) 1 = JTAG is enabled 0 = JTAG is disabled bit 1-0 DEBUG<1:0>: Background Debugger Enable bits (forced to `11' if code-protect is enabled) 1x = Debugger is disabled 0x = Debugger is enabled Note 1: This bit sets the value for the JTAGEN bit in the CFGCON register. DS60001290E-page 294 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 28-2: Bit Range 31:24 23:16 15:8 7:0 DEVCFG1: DEVICE CONFIGURATION WORD 1 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 r-1 r-1 r-1 r-1 r-1 r-1 -- -- -- -- -- -- R/P R/P R/P R/P r-1 FWDTEN WINDIS -- R/P R/P R/P FCKSM<1:0> Bit 25/17/9/1 Bit 24/16/8/0 R/P R/P FWDTWINSZ<1:0> R/P R/P R/P R/P R/P WDTPS<4:0> R/P FPBDIV<1:0> r-1 R/P -- OSCIOFNC R/P R/P r-1 R/P r-1 r-1 IESO -- FSOSCEN -- -- POSCMOD<1:0> R/P R/P FNOSC<2:0> Legend: r = Reserved bit P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-26 Reserved: Write `1' bit 25-24 FWDTWINSZ: Watchdog Timer Window Size bits 11 = Window size is 25% 10 = Window size is 37.5% 01 = Window size is 50% 00 = Window size is 75% bit 23 FWDTEN: Watchdog Timer Enable bit 1 = Watchdog Timer is enabled and cannot be disabled by software 0 = Watchdog Timer is not enabled; it can be enabled in software bit 22 WINDIS: Watchdog Timer Window Enable bit 1 = Watchdog Timer is in non-Window mode 0 = Watchdog Timer is in Window mode bit 21 Reserved: Write `1' bit 20-16 WDTPS<4:0>: Watchdog Timer Postscale Select bits 10100 = 1:1048576 10011 = 1:524288 10010 = 1:262144 10001 = 1:131072 10000 = 1:65536 01111 = 1:32768 01110 = 1:16384 01101 = 1:8192 01100 = 1:4096 01011 = 1:2048 01010 = 1:1024 01001 = 1:512 01000 = 1:256 00111 = 1:128 00110 = 1:64 00101 = 1:32 00100 = 1:16 00011 = 1:8 00010 = 1:4 00001 = 1:2 00000 = 1:1 All other combinations not shown result in operation = 10100 Note 1: Do not disable the POSC (POSCMOD = 11) when using this oscillator source. 2014-2017 Microchip Technology Inc. DS60001290E-page 295 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 28-2: DEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED) bit 15-14 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled bit 13-12 FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits 11 = PBCLK is SYSCLK divided by 8 10 = PBCLK is SYSCLK divided by 4 01 = PBCLK is SYSCLK divided by 2 00 = PBCLK is SYSCLK divided by 1 bit 11 Reserved: Write `1' bit 10 OSCIOFNC: CLKO Enable Configuration bit 1 = CLKO output disabled 0 = CLKO output signal active on the OSCO pin; Primary Oscillator must be disabled or configured for the External Clock mode (EC) for the CLKO to be active (POSCMOD<1:0> = 11 or 00) bit 9-8 POSCMOD<1:0>: Primary Oscillator Configuration bits 11 = Primary Oscillator disabled 10 = HS Oscillator mode selected 01 = XT Oscillator mode selected 00 = External Clock mode selected bit 7 IESO: Internal External Switchover bit 1 = Internal External Switchover mode is enabled (Two-Speed Start-up is enabled) 0 = Internal External Switchover mode is disabled (Two-Speed Start-up is disabled) bit 6 Reserved: Write `1' bit 5 FSOSCEN: Secondary Oscillator Enable bit 1 = Enable Secondary Oscillator 0 = Disable Secondary Oscillator bit 4-3 Reserved: Write `1' bit 2-0 FNOSC<2:0>: Oscillator Selection bits 111 = Fast RC Oscillator with divide-by-N (FRCDIV) 110 = FRCDIV16 Fast RC Oscillator with fixed divide-by-16 postscaler 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator (POSC) with PLL module (XT+PLL, HS+PLL, EC+PLL) 010 = Primary Oscillator (XT, HS, EC)(1) 001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL) 000 = Fast RC Oscillator (FRC) Note 1: Do not disable the POSC (POSCMOD = 11) when using this oscillator source. DS60001290E-page 296 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 28-3: Bit Range 31:24 23:16 15:8 7:0 DEVCFG2: DEVICE CONFIGURATION WORD 2 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 -- -- -- -- -- -- -- -- R/P R/P R/P r-1 r-1 r-1 r-1 r-1 -- -- -- -- -- R/P r-1 r-1 r-1 r-1 UPLLEN(1) -- -- -- -- r-1 R/P-1 R/P R/P-1 -- r-1 FPLLMUL<2:0> FPLLODIV<2:0> R/P R/P R/P UPLLIDIV<2:0>(1) R/P -- R/P R/P FPLLIDIV<2:0> Legend: r = Reserved bit P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-19 Reserved: Write `1' bit 18-16 FPLLODIV<2:0>: Default PLL Output Divisor bits 111 = PLL output divided by 256 110 = PLL output divided by 64 101 = PLL output divided by 32 100 = PLL output divided by 16 011 = PLL output divided by 8 010 = PLL output divided by 4 001 = PLL output divided by 2 000 = PLL output divided by 1 bit 15 UPLLEN: USB PLL Enable bit(1) 1 = Disable and bypass USB PLL 0 = Enable USB PLL bit 14-11 Reserved: Write `1' bit 10-8 UPLLIDIV<2:0>: USB PLL Input Divider bits(1) 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider bit 7 Reserved: Write `1' bit 6-4 FPLLMUL<2:0>: PLL Multiplier bits 111 = 24x multiplier 110 = 21x multiplier 101 = 20x multiplier 100 = 19x multiplier 011 = 18x multiplier 010 = 17x multiplier 001 = 16x multiplier 000 = 15x multiplier bit 3 Reserved: Write `1' Note 1: This bit is available on PIC32MX2XX/5XX devices only. 2014-2017 Microchip Technology Inc. DS60001290E-page 297 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 28-3: DEVCFG2: DEVICE CONFIGURATION WORD 2 (CONTINUED) bit 2-0 FPLLIDIV<2:0>: PLL Input Divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider Note 1: This bit is available on PIC32MX2XX/5XX devices only. DS60001290E-page 298 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 28-4: Bit Range 31:24 23:16 15:8 7:0 DEVCFG3: DEVICE CONFIGURATION WORD 3 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit Bit 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 R/P R/P R/P R/P U-0 U-0 U-0 FVBUSONIO FUSBIDIO IOL1WAY PMDL1WAY -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/P R/P R/P R/P R/P R/P R/P R/P R/P R/P R/P R/P R/P R/P USERID<15:8> Legend: R = Readable bit -n = Value at POR R/P R/P USERID<7:0> r = Reserved bit W = Writable bit `1' = Bit is set P = Programmable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31 FVBUSONIO: USB VBUS_ON Selection bit 1 = VBUSON pin is controlled by the USB module 0 = VBUSON pin is controlled by the port function bit 30 FUSBIDIO: USB USBID Selection bit 1 = USBID pin is controlled by the USB module 0 = USBID pin is controlled by the port function bit 29 IOL1WAY: Peripheral Pin Select Configuration bit 1 = Allow only one reconfiguration 0 = Allow multiple reconfigurations bit 28 PMDL1WAY: Peripheral Module Disable Configuration bit 1 = Allow only one reconfiguration 0 = Allow multiple reconfigurations bit 27-16 Unimplemented: Read as `0' bit 15-0 USERID<15:0>: This is a 16-bit value that is user-defined and is readable via ICSPTM and JTAG 2014-2017 Microchip Technology Inc. DS60001290E-page 299 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 28-5: Bit Range 31:24 23:16 15:8 7:0 CFGCON: CONFIGURATION CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-1 -- -- -- -- JTAGEN -- -- TDOEN IOLOCK(1) PMDLOCK(1) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-14 Unimplemented: Read as `0' bit 13 IOLOCK: Peripheral Pin Select Lock bit(1) 1 = Peripheral Pin Select is locked. Writes to PPS registers is not allowed 0 = Peripheral Pin Select is not locked. Writes to PPS registers is allowed bit 12 PMDLOCK: Peripheral Module Disable bit(1) 1 = Peripheral module is locked. Writes to PMD registers is not allowed 0 = Peripheral module is not locked. Writes to PMD registers is allowed bit 11-4 Unimplemented: Read as `0' bit 3 JTAGEN: JTAG Port Enable bit 1 = Enable the JTAG port 0 = Disable the JTAG port bit 2-1 Unimplemented: Read as `0' bit 0 TDOEN: TDO Enable for 2-Wire JTAG 1 = 2-wire JTAG protocol uses TDO 0 = 2-wire JTAG protocol does not use TDO Note 1: To change this bit, the unlock sequence must be performed. Refer to Section 6. "Oscillator" (DS60001112) in the "PIC32 Family Reference Manual" for details. DS60001290E-page 300 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY REGISTER 28-6: Bit Range 31:24 23:16 15:8 7:0 DEVID: DEVICE AND REVISION ID REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R R R R R VER<3:0>(1) R R R Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R R R DEVID<27:24>(1) R R R R R R R R R R R DEVID<23:16>(1) R R R R R DEVID<15:8>(1) R R R R R DEVID<7:0>(1) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-28 VER<3:0>: Revision Identifier bits(1) bit 27-0 DEVID<27:0>: Device ID(1) Note 1: See the "PIC32 Flash Programming Specification" (DS60001145) for a list of Revision and Device ID values. 2014-2017 Microchip Technology Inc. DS60001290E-page 301 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 28.3 On-Chip Voltage Regulator All PIC32MX1XX/2XX/5XX 64/100-pin devices' core and digital logic are designed to operate at a nominal 1.8V. To simplify system designs, most devices in the PIC32MX1XX/2XX/5XX 64/100-pin family incorporate an on-chip regulator providing the required core logic voltage from VDD. A low-ESR capacitor (such as tantalum) must be connected to the VCAP pin (see Figure 28-1). This helps to maintain the stability of the regulator. The recommended value for the filter capacitor is provided in Section 31.1 "DC Characteristics". It is important that the low-ESR capacitor is placed as close as possible to the VCAP pin. Note: 28.3.1 HIGH VOLTAGE DETECT (HVD) The HVD module monitors the core voltage at the VCAP pin. If a voltage above the required level is detected on VCAP, the I/O pins are disabled and the device is held in Reset as long as the HVD condition persists. See parameter HV10 (VHVD) in Table 31-11 in Section 31.1 "DC Characteristics" for more information. 28.3.2 ON-CHIP REGULATOR AND POR It takes a fixed delay for the on-chip regulator to generate an output. During this time, designated as TPU, code execution is disabled. TPU is applied every time the device resumes operation after any power-down, including Sleep mode. 28.3.3 28.4 Programming and Diagnostics PIC32MX1XX/2XX/5XX 64/100-pin devices provide a complete range of programming and diagnostic features that can increase the flexibility of any application using them. These features allow system designers to include: * Simplified field programmability using two-wire In-Circuit Serial ProgrammingTM (ICSPTM) interfaces * Debugging using ICSP * Programming and debugging capabilities using the EJTAG extension of JTAG * JTAG boundary scan testing for device and board diagnostics PIC32 devices incorporate two programming and diagnostic modules that provide a range of functions to the application developer. FIGURE 28-2: BLOCK DIAGRAM OF PROGRAMMING, DEBUGGING AND TRACE PORTS PGEC1 PGED1 ICSPTM Controller PGEC3 PGED3 ON-CHIP REGULATOR AND BOR PIC32MX1XX/2XX/5XX 64/100-pin devices also have a simple brown-out capability. If the voltage supplied to the regulator is inadequate to maintain a regulated level, the regulator Reset circuitry will generate a Brown-out Reset. This event is captured by the BOR flag bit (RCON<1>). The brown-out voltage levels are specific in Section 31.1 "DC Characteristics". FIGURE 28-1: CONNECTIONS FOR THE ON-CHIP REGULATOR ICESEL Core TDI TDO TCK JTAG Controller TMS JTAGEN DEBUG<1:0> 3.3V(1) PIC32 VDD VCAP CEFC(2,3) (10 F typ) Note 1: 2: 3: VSS These are typical operating voltages. Refer to Section 31.1 "DC Characteristics" for the full operating ranges of VDD. It is important that the low-ESR capacitor is placed as close as possible to the VCAP pin. The typical voltage on the VCAP pin is 1.8V. DS60001290E-page 302 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 29.0 INSTRUCTION SET The PIC32MX1XX/2XX/5XX 64/100-pin family instruction set complies with the MIPS32(R) Release 2 instruction set architecture. The PIC32 device family does not support the following features: * Core extend instructions * Coprocessor 1 instructions * Coprocessor 2 instructions Note: Refer to "MIPS32(R) Architecture for Programmers Volume II: The MIPS32(R) Instruction Set" at www.imgtec.com for more information. 2014-2017 Microchip Technology Inc. DS60001290E-page 303 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY NOTES: DS60001290E-page 304 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 30.0 DEVELOPMENT SUPPORT (R) 30.1 (R) The PIC microcontrollers (MCU) and dsPIC digital signal controllers (DSC) are supported with a full range of software and hardware development tools: * Integrated Development Environment - MPLAB(R) X IDE Software * Compilers/Assemblers/Linkers - MPLAB XC Compiler - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families * Simulators - MPLAB X SIM Software Simulator * Emulators - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debuggers/Programmers - MPLAB ICD 3 - PICkitTM 3 * Device Programmers - MPLAB PM3 Device Programmer * Low-Cost Demonstration/Development Boards, Evaluation Kits and Starter Kits * Third-party development tools MPLAB X Integrated Development Environment Software The MPLAB X IDE is a single, unified graphical user interface for Microchip and third-party software, and hardware development tool that runs on Windows(R), Linux and Mac OS(R) X. Based on the NetBeans IDE, MPLAB X IDE is an entirely new IDE with a host of free software components and plug-ins for highperformance application development and debugging. Moving between tools and upgrading from software simulators to hardware debugging and programming tools is simple with the seamless user interface. With complete project management, visual call graphs, a configurable watch window and a feature-rich editor that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new users. With the ability to support multiple tools on multiple projects with simultaneous debugging, MPLAB X IDE is also suitable for the needs of experienced users. Feature-Rich Editor: * Color syntax highlighting * Smart code completion makes suggestions and provides hints as you type * Automatic code formatting based on user-defined rules * Live parsing User-Friendly, Customizable Interface: * Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. * Call graph window Project-Based Workspaces: * * * * Multiple projects Multiple tools Multiple configurations Simultaneous debugging sessions File History and Bug Tracking: * Local file history feature * Built-in support for Bugzilla issue tracker 2014-2017 Microchip Technology Inc. DS60001290E-page 305 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 30.2 MPLAB XC Compilers The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip's 8, 16, and 32-bit MCU and DSC devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use. MPLAB XC Compilers run on Windows, Linux or MAC OS X. For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE. The free MPLAB XC Compiler editions support all devices and commands, with no time or memory restrictions, and offer sufficient code optimization for most applications. MPLAB XC Compilers include an assembler, linker and utilities. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler to produce its object file. Notable features of the assembler include: * * * * * * Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility 30.3 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code, and COFF files for debugging. The MPASM Assembler features include: 30.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction 30.5 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC DSC devices. MPLAB XC Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility * Integration into MPLAB X IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multipurpose source files * Directives that allow complete control over the assembly process DS60001290E-page 306 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 30.6 MPLAB X SIM Software Simulator The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB X SIM Software Simulator fully supports symbolic debugging using the MPLAB XC Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 30.7 MPLAB REAL ICE In-Circuit Emulator System The MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs all 8, 16 and 32-bit MCU, and DSC devices with the easy-to-use, powerful graphical user interface of the MPLAB X IDE. The emulator is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB X IDE. MPLAB REAL ICE offers significant advantages over competitive emulators including full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, logic probes, a ruggedized probe interface and long (up to three meters) interconnection cables. 2014-2017 Microchip Technology Inc. 30.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost-effective, high-speed hardware debugger/programmer for Microchip Flash DSC and MCU devices. It debugs and programs PIC Flash microcontrollers and dsPIC DSCs with the powerful, yet easy-to-use graphical user interface of the MPLAB IDE. The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a highspeed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 30.9 PICkit 3 In-Circuit Debugger/ Programmer The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB IDE. The MPLAB PICkit 3 is connected to the design engineer's PC using a fullspeed USB interface and can be connected to the target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the Reset line to implement in-circuit debugging and In-Circuit Serial ProgrammingTM (ICSPTM). 30.10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various package types. The ICSP cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications. DS60001290E-page 307 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 30.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. 30.12 Third-Party Development Tools Microchip also offers a great collection of tools from third-party vendors. These tools are carefully selected to offer good value and unique functionality. * Device Programmers and Gang Programmers from companies, such as SoftLog and CCS * Software Tools from companies, such as Gimpel and Trace Systems * Protocol Analyzers from companies, such as Saleae and Total Phase * Demonstration Boards from companies, such as MikroElektronika, Digilent(R) and Olimex * Embedded Ethernet Solutions from companies, such as EZ Web Lynx, WIZnet and IPLogika(R) The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. DS60001290E-page 308 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 31.0 40 MHz ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC32MX1XX/2XX/5XX 64/100-pin Family electrical characteristics for devices that operate at 40 MHz. Refer to Section 32.0 "50 MHz Electrical Characteristics" for additional specifications for operations at higher frequency. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC32MX1XX/2XX/5XX 64/100-pin Family devices are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions, above the parameters indicated in the operation listings of this specification, is not implied. Absolute Maximum Ratings (See Note 1) Ambient temperature under bias............................................................................................................ .-40C to +105C Storage temperature .............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant, with respect to VSS (Note 3)......................................... -0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD 2.3V (Note 3)........................................ -0.3V to +5.5V Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V (Note 3)........................................ -0.3V to +3.6V Voltage on D+ or D- pin with respect to VUSB3V3 .................................................................... -0.3V to (VUSB3V3 + 0.3V) Voltage on VBUS with respect to VSS ....................................................................................................... -0.3V to +5.5V Maximum current out of VSS pin(s) .......................................................................................................................300 mA Maximum current into VDD pin(s) (Note 2)............................................................................................................300 mA Maximum output current sunk by any I/O pin..........................................................................................................15 mA Maximum output current sourced by any I/O pin ....................................................................................................15 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports (Note 2)....................................................................................................200 mA Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions, above those indicated in the operation listings of this specification, is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table 31-2). 3: See the "Device Pin Tables" section for the 5V tolerant pins. 2014-2017 Microchip Technology Inc. DS60001290E-page 309 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 31.1 DC Characteristics TABLE 31-1: OPERATING MIPS VS. VOLTAGE Max. Frequency Characteristic VDD Range (in Volts)(1) Temp. Range (in C) DC5 VBOR-3.6V -40C to +105C Note 1: PIC32MX1XX/2XX/5XX 64/100-pin Family 40 MHz Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN. Refer to parameter BO10 in Table 31-10 for BOR values. TABLE 31-2: THERMAL OPERATING CONDITIONS Rating Symbol Min. Typical Max. Unit Industrial Temperature Devices Operating Junction Temperature Range TJ -40 -- +125 C Operating Ambient Temperature Range TA -40 -- +85 C TJ -40 -- +140 C TA -40 -- +105 C V-temp Temperature Devices Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD - S IOH) I/O Pin Power Dissipation: I/O = S (({VDD - VOH} x IOH) + S (VOL x IOL)) Maximum Allowed Power Dissipation TABLE 31-3: PD PINT + PI/O W PDMAX (TJ - TA)/JA W THERMAL PACKAGING CHARACTERISTICS Characteristics Symbol Typical Max. Unit Notes Package Thermal Resistance, 64-pin QFN JA 28 -- C/W 1 Package Thermal Resistance, 64-pin TQFP, 10 mm x 10 mm JA 55 -- C/W 1 Package Thermal Resistance, 100-pin TQFP, 12 mm x 12 mm JA 52 -- C/W 1 Package Thermal Resistance, 100-pin TQFP, 14 mm x 14 mm JA 50 -- C/W 1 Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations. DS60001290E-page 310 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 31-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp DC CHARACTERISTICS Param. Symbol No. Characteristics Min. Typ. Max. Units Conditions Operating Voltage DC10 VDD Supply Voltage (Note 2) 2.3 -- 3.6 V -- DC12 VDR RAM Data Retention Voltage (Note 1) 1.75 -- -- V -- DC16 VPOR VDD Start Voltage to Ensure Internal Power-on Reset Signal 1.75 -- 2.1 V -- DC17 SVDD VDD Rise Rate to Ensure Internal Power-on Reset Signal 0.00005 -- 0.115 V/s -- Note 1: 2: This is the limit to which VDD can be lowered without losing RAM data. Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN. Refer to parameter BO10 in Table 31-10 for BOR values. 2014-2017 Microchip Technology Inc. DS60001290E-page 311 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 31-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp DC CHARACTERISTICS Parameter No. Typical(3) Max. Units Conditions Operating Current (IDD) (Notes 1, 2, 5) DC20 2 8 mA 4 MHz (Note 4) DC21 7 13 mA 10 MHz DC22 10 18 mA 20 MHz (Note 4) DC23 15 25 mA 30 MHz (Note 4) DC24 20 32 mA DC25 180 250 A Note 1: 2: 3: 4: 5: 40 MHz +25C, 3.3V LPRC (31 kHz) (Note 4) A device's IDD supply current is mainly a function of the operating voltage and frequency. Other factors, such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate, oscillator type, as well as temperature, can have an impact on the current consumption. The test conditions for IDD measurements are as follows: * Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required) * OSC2/CLKO is configured as an I/O input pin * USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8 * CPU, Program Flash, and SRAM data memory are operational, SRAM data memory Wait states = 1 * No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is cleared * WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled * All I/O pins are configured as inputs and pulled to VSS * MCLR = VDD * CPU executing while(1) statement from Flash * RTCC and JTAG are disabled Data in the "Typical" column is at 3.3V, 25C at specified operating frequency unless otherwise stated. Parameters are for design guidance only and are not tested. This parameter is characterized, but not tested in manufacturing. IPD electrical characteristics for devices with 256 KB Flash are only provided as Preliminary information. DS60001290E-page 312 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 31-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp DC CHARACTERISTICS Parameter No. Typical(2) Max. Units Conditions Idle Current (IIDLE): Core Off, Clock on Base Current (Notes 1, 4) DC30a 1.5 5 mA 4 MHz (Note 3) DC31a 3 8 mA 10 MHz DC32a 5 12 mA 20 MHz (Note 3) DC33a 6.5 15 mA 30 MHz (Note 3) DC34a 8 20 mA DC37a 75 100 A DC37b 180 250 A +25C DC37c 280 380 A +85C Note 1: 2: 3: 4: 40 MHz -40C 3.3V LPRC (31 kHz) (Note 3) The test conditions for IIDLE current measurements are as follows: * Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required) * OSC2/CLKO is configured as an I/O input pin * USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8 * CPU is in Idle mode (CPU core Halted), and SRAM data memory Wait states = 1 * No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is cleared * WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled * All I/O pins are configured as inputs and pulled to VSS * MCLR = VDD * RTCC and JTAG are disabled Data in the "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. This parameter is characterized, but not tested in manufacturing. IIDLE electrical characteristics for devices with 256 KB Flash are only provided as Preliminary information. 2014-2017 Microchip Technology Inc. DS60001290E-page 313 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 31-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) DC CHARACTERISTICS Param. Typical(2) No. Max. Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp Units Conditions Power-Down Current (IPD) (Notes 1, 5) DC40k 33 78 A -40C DC40l 49 78 A +25C DC40n 281 450 A +85C DC40m 559 895 A +105C Base Power-Down Current Module Differential Current DC41e 10 25 A 3.6V Watchdog Timer Current: IWDT (Note 3) DC42e 29 50 A 3.6V RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3) 1000 1300 A 3.6V ADC: IADC (Notes 3,4) DC43d Note 1: 2: 3: 4: 5: The test conditions for IPD current measurements are as follows: * Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required) * OSC2/CLKO is configured as an I/O input pin * USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8 * CPU is in Sleep mode, and SRAM data memory Wait states = 1 * No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is set * WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled * All I/O pins are configured as inputs and pulled to VSS * MCLR = VDD * RTCC and JTAG are disabled Data in the "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled. IPD electrical characteristics for devices with 256 KB Flash are only provided as Preliminary information. DS60001290E-page 314 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 31-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param. Symbol No. VIL DI10 Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp Min. Typical(1) Max. Units Conditions Input Low Voltage I/O Pins with PMP VSS -- 0.15 VDD V I/O Pins VSS -- 0.2 VDD V DI18 SDAx, SCLx VSS -- 0.3 VDD V SMBus disabled (Note 4) DI19 SDAx, SCLx VSS -- 0.8 V SMBus enabled (Note 4) I/O Pins not 5V-tolerant(5) 0.65 VDD -- VDD V (Note 4,6) I/O Pins 5V-tolerant with PMP(5) 0.25 VDD + 0.8V -- 5.5 V (Note 4,6) I/O Pins 5V-tolerant(5) 0.65 VDD -- 5.5 V DI28 SDAx, SCLx 0.65 VDD -- 5.5 V SMBus disabled (Note 4,6) DI29 SDAx, SCLx 2.1 -- 5.5 V SMBus enabled, 2.3V VPIN 5.5 (Note 4,6) VIH DI20 Input High Voltage DI30 ICNPU Change Notification Pull-up Current -- -200 -50 A VDD = 3.3V, VPIN = VSS (Note 3,6) DI31 ICNPD Change Notification Pull-down Current(4) 50 200 -- A VDD = 3.3V, VPIN = VDD IIL Input Leakage Current (Note 3) DI50 I/O Ports -- -- +1 A VSS VPIN VDD, Pin at high-impedance DI51 Analog Input Pins -- -- +1 A VSS VPIN VDD, Pin at high-impedance DI55 MCLR(2) -- -- +1 A VSS VPIN VDD DI56 OSC1 -- -- +1 A VSS VPIN VDD, XT and HS modes Note 1: 2: 3: 4: 5: 6: Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. This parameter is characterized, but not tested in manufacturing. See the "Device Pin Tables" section for the 5V-tolerant pins. The VIH specifications are only in relation to externally applied inputs, and not with respect to the userselectable internal pull-ups. External open drain input signals utilizing the internal pull-ups of the PIC32 device are guaranteed to be recognized only as a logic "high" internally to the PIC32 device, provided that the external load does not exceed the minimum value of ICNPU. For External "input" logic inputs that require a pull-up source, to guarantee the minimum VIH of those components, it is recommended to use an external pull-up resistor rather than the internal pull-ups of the PIC32 device. 2014-2017 Microchip Technology Inc. DS60001290E-page 315 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 31-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp DC CHARACTERISTICS Param. Symbol DO10 VOL Characteristic Output Low Voltage I/O Pins: 4x Sink Driver Pins - All I/O output pins not defined as 8x Sink Driver pins Output Low Voltage I/O Pins: 8x Sink Driver Pins - RB14, RC15, RD2, RD10, RD15, RF6, RF13, RG6 Min. Typ. Max. Units Conditions -- -- 0.4 V IOL 9 mA, VDD = 3.3V -- -- 0.4 V IOL 15 mA, VDD = 3.3V -- -- V IOH -10 mA, VDD = 3.3V -- -- V IOH -15 mA, VDD = 3.3V -- -- -- -- -- -- IOH -7 mA, VDD = 3.3V -- -- IOH -22 mA, VDD = 3.3V -- -- -- -- Output High Voltage I/O Pins: 2.4 4x Source Driver Pins - All I/O output pins not defined as 8x Source Driver pins DO20 VOH Output High Voltage I/O Pins: 8x Source Driver Pins - RB14, 2.4 RC15, RD2, RD10, RD15, RF6, RF13, RG6 Output High Voltage 1.5(1) I/O Pins: 2.0(1) 4x Source Driver Pins - All I/O output pins not defined as 8x 3.0(1) Sink Driver pins DO20A VOH1 Output High Voltage 1.5(1) I/O Pins: 2.0(1) 8x Source Driver Pins - RB14, RC15, RD2, RD10, RD15, RF6, 3.0(1) RF13, RG6 Note 1: Parameters are characterized, but not tested. DS60001290E-page 316 IOH -14 mA, VDD = 3.3V V V IOH -12 mA, VDD = 3.3V IOH -18 mA, VDD = 3.3V IOH -10 mA, VDD = 3.3V 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 31-10: ELECTRICAL CHARACTERISTICS: BOR Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp DC CHARACTERISTICS Param. Symbol No. BO10 Note 1: 2: VBOR Characteristics BOR Event on VDD transition high-to-low(2) Min.(1) Typical 2.0 -- Max. Units Conditions 2.3 V -- Parameters are for design guidance only and are not tested in manufacturing. Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN. TABLE 31-11: ELECTRICAL CHARACTERISTICS: HVD Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp DC CHARACTERISTICS Param. Symbol No.(1) HV10 Note 1: VHVD Characteristics High Voltage Detect on VCAP pin Min. Typical Max. Units Conditions -- 2.5 -- V -- Parameters are for design guidance only and are not tested in manufacturing. 2014-2017 Microchip Technology Inc. DS60001290E-page 317 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 31-12: DC CHARACTERISTICS: PROGRAM MEMORY DC CHARACTERISTICS Param. Symbol No. Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp Min. Typical(1) Max. Units Conditions Program Flash Memory(3) D130 EP Cell Endurance 20,000 -- -- E/W -- D131 VPR VDD for Read 2.3 -- 3.6 V -- D132 VPEW VDD for Erase or Write 2.3 -- 3.6 V D134 TRETD Characteristic Retention 20 -- -- Year D135 IDDP Supply Current during Programming -- 10 -- mA TWW Word Write Cycle Time -- 411 -- FRC Cycles See Note 4 D136 TRW Row Write Cycle Time -- 6675 -- FRC Cycles See Note 2,4 D137 TPE Page Erase Cycle Time -- 20011 -- FRC Cycles See Note 4 TCE Chip Erase Cycle Time -- 80180 -- FRC Cycles See Note 4 Note 1: 2: 3: 4: -- Provided no other specifications are violated -- Data in "Typical" column is at 3.3V, 25C unless otherwise stated. The minimum SYSCLK for row programming is 4 MHz. Care should be taken to minimize bus activities during row programming, such as suspending any memory-to-memory DMA operations. If heavy bus loads are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The default Arbitration mode is mode 1 (CPU has lowest priority). Refer to the "PIC32 Flash Programming Specification" (DS60001145) for operating conditions during programming and erase cycles. This parameter depends on FRC accuracy (See Table 31-19) and FRC tuning values (See Register 8-2). DS60001290E-page 318 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 31-13: COMPARATOR SPECIFICATIONS Standard Operating Conditions (see Note 4): 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp DC CHARACTERISTICS Param. Symbol No. Characteristics Min. Typ. Max. Units Comments D300 VIOFF Input Offset Voltage -- 7.5 25 mV AVDD = VDD, AVSS = VSS D301 VICM(2) Input Common Mode Voltage 0 -- VDD V AVDD = VDD, AVSS = VSS D302 CMRR(2) Common Mode Rejection Ratio 55 -- -- dB Max VICM = (VDD - 1)V D303 TRESP(1,2) Response Time -- 150 400 ns AVDD = VDD, AVSS = VSS D304 ON2OV(2) Comparator Enabled to Output Valid -- -- 10 s Comparator module is configured before setting the comparator ON bit D305 IVREF 1.14 1.2 1.26 V Note 1: 2: 3: 4: Internal Voltage Reference -- Response time measured with one comparator input at (VDD - 1.5)/2, while the other input transitions from VSS to VDD. These parameters are characterized but not tested. Settling time measured while CVRR = 1 and CVR<3:0> transitions from `0000' to `1111'. This parameter is characterized, but not tested in manufacturing. The Comparator module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless otherwise stated, module functionality is tested, but not characterized. 2014-2017 Microchip Technology Inc. DS60001290E-page 319 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 31-14: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp DC CHARACTERISTICS Param. Symbol No. Characteristics D312 TSET D313 DACREFH CVREF Input Voltage Reference Range D314 DVREF D315 DACRES D316 DACACC Note 1: 2: Min. Typ. Max. Units -- -- 10 s See Note 1 Internal 4-bit DAC Comparator Reference Settling time. Comments AVSS -- AVDD V CVRSRC with CVRSS = 0 VREF- -- VREF+ V CVRSRC with CVRSS = 1 0 -- 0.625 x DACREFH V 0 to 0.625 DACREFH with DACREFH/24 step size 0.25 x DACREFH -- 0.719 x DACREFH V 0.25 x DACREFH to 0.719 DACREFH with DACREFH/ 32 step size -- -- DACREFH/24 CVRCON<CVRR> = 1 -- -- DACREFH/32 CVRCON<CVRR> = 0 -- -- 1/4 LSB DACREFH/24, CVRCON<CVRR> = 1 -- -- 1/2 LSB DACREFH/32, CVRCON<CVRR> = 0 CVREF Programmable Output Range Resolution Absolute Accuracy(2) Settling time was measured while CVRR = 1 and CVR<3:0> transitions from `0000' to `1111'. This parameter is characterized, but is not tested in manufacturing. These parameters are characterized but not tested. TABLE 31-15: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp DC CHARACTERISTICS Param. No. D321 Symbol CEFC Characteristics Min. Typical Max. Units Comments External Filter Capacitor Value 8 10 -- F Capacitor must be low series resistance ( 3 ohm). Typical voltage on the VCAP pin is 1.8V. DS60001290E-page 320 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 31.2 AC Characteristics and Timing Parameters The information contained in this section defines PIC32MX1XX/2XX/5XX 64/100-pin AC characteristics and timing parameters. FIGURE 31-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 - for all pins except OSC2 Load Condition 2 - for OSC2 VDD/2 CL Pin RL VSS CL Pin RL = 464 CL = 50 pF for all pins 50 pF for OSC2 pin (EC mode) VSS TABLE 31-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp Param. Symbol No. Min. Typical(1) Max. Units OSC2 pin -- -- 15 pF In XT and HS modes when an external crystal is used to drive OSC1 DO50a CSOSC SOSCI/SOSCO pins -- 33 -- pF Epson P/N: MC-306 32.7680KA0:ROHS DO56 CIO All I/O pins and OSC2 -- -- 50 pF EC mode DO58 CB SCLx, SDAx -- -- 400 pF In I2C mode DO50 COSCO Note 1: Characteristics Conditions Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. FIGURE 31-2: EXTERNAL CLOCK TIMING OS20 OS30 OS31 OSC1 OS30 2014-2017 Microchip Technology Inc. OS31 DS60001290E-page 321 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 31-17: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. Symbol No. Min. Typical(1) Max. Units Conditions External CLKI Frequency (External clocks allowed only in EC and ECPLL modes) DC 4 -- -- 40 40 MHz MHz EC (Note 4) ECPLL (Note 3) Oscillator Crystal Frequency 3 -- 10 MHz XT (Note 4) OS12 4 -- 10 MHz XTPLL (Notes 3,4) OS13 10 -- 25 MHz HS (Note 5) OS14 10 -- 25 MHz HSPLL (Notes 3,4) 32 32.768 100 kHz SOSC (Note 4) -- -- -- -- See parameter OS10 for FOSC value OS10 FOSC OS11 Characteristics OS15 OS20 TOSC TOSC = 1/FOSC = TCY (Note 2) OS30 TOSL, TOSH External Clock In (OSC1) High or Low Time 0.45 x TOSC -- -- ns EC (Note 4) OS31 TOSR, TOSF External Clock In (OSC1) Rise or Fall Time -- -- 0.05 x TOSC ns EC (Note 4) OS40 TOST Oscillator Start-up Timer Period (Only applies to HS, HSPLL, XT, XTPLL and SOSC Clock Oscillator modes) -- 1024 -- OS41 TFSCM Primary Clock Fail Safe Time-out Period -- 2 -- OS42 GM External Oscillator Transconductance (Primary Oscillator only) -- 12 -- Note 1: 2: 3: 4: TOSC (Note 4) ms (Note 4) mA/V VDD = 3.3V, TA = +25C (Note 4) Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are characterized but are not tested. Instruction cycle period (TCY) equals the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKI pin. PLL input requirements: 4 MHZ FPLLIN 5 MHZ (use PLL prescaler to reduce FOSC). This parameter is characterized, but tested at 10 MHz only at manufacturing. This parameter is characterized, but not tested in manufacturing. DS60001290E-page 322 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 31-18: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typical Max. Units Conditions OS50 FPLLI PLL Voltage Controlled Oscillator (VCO) Input Frequency Range 3.92 -- 5 MHz OS51 FSYS On-Chip VCO System Frequency 60 -- 120 MHz -- OS52 TLOCK PLL Start-up Time (Lock Time) -- -- 2 ms -- -0.25 -- +0.25 % OS53 Note 1: 2: DCLK Stability(2) CLKO (Period Jitter or Cumulative) ECPLL, HSPLL, XTPLL, FRCPLL modes Measured over 100 ms period These parameters are characterized, but not tested in manufacturing. This jitter specification is based on clock-cycle by clock-cycle measurements. To get the effective jitter for individual time-bases on communication clocks, use the following formula: D CLK -------------------------------------------------------------EffectiveJitter SYSCLK ---------------------------------------------------------CommunicationClock For example, if SYSCLK = 40 MHz and SPI bit rate = 20 MHz, the effective jitter is as follows: EffectiveJitter TABLE 31-19: D CLK -------------1.41 INTERNAL FRC ACCURACY AC CHARACTERISTICS Param. No. D CLK ------------40 -----20 Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp Min. Typical Max. Units Conditions Internal FRC Accuracy @ 8.00 MHz(1) F20a FRC -0.9 -- +0.9 % -40C TA +85C F20b FRC -2 -- +2 % -40C TA +105C Note 1: Frequency calibrated at 25C and 3.3V. The TUN bits can be used to compensate for temperature drift. TABLE 31-20: INTERNAL LPRC ACCURACY AC CHARACTERISTICS Param. No. Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp Min. Typical Max. Units Conditions -15 -- +15 % -- LPRC @ 31.25 kHz(1) F21 Note 1: LPRC Change of LPRC frequency as VDD changes. 2014-2017 Microchip Technology Inc. DS60001290E-page 323 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY FIGURE 31-3: I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) Note: Refer to Figure 31-1 for load conditions. DO31 DO32 TABLE 31-21: I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. No. Characteristics(2) Symbol Min. Typical(1) Max. Units -- 5 15 ns VDD < 2.5V Conditions DO31 TIOR Port Output Rise Time -- 5 10 ns VDD > 2.5V DO32 TIOF Port Output Fall Time -- 5 15 ns VDD < 2.5V -- 5 10 ns VDD > 2.5V DI35 TINP INTx Pin High or Low Time 10 -- -- ns -- DI40 TRBP CNx High or Low Time (input) 2 -- -- TSYSCLK -- Note 1: 2: Data in "Typical" column is at 3.3V, 25C unless otherwise stated. This parameter is characterized, but not tested in manufacturing. DS60001290E-page 324 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY FIGURE 31-4: POWER-ON RESET TIMING CHARACTERISTICS Internal Voltage Regulator Enabled Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) VDD VPOR (TSYSDLY) SY02 Power-up Sequence (Note 2) CPU Starts Fetching Code SY00 (TPU) (Note 1) Internal Voltage Regulator Enabled Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) VDD VPOR (TSYSDLY) SY02 Power-up Sequence (Note 2) SY00 (TPU) (Note 1) Note 1: 2: SY10 (TOST) CPU Starts Fetching Code The power-up period will be extended if the power-up sequence completes before the device exits from BOR (VDD < VDDMIN). Includes interval voltage regulator stabilization delay. 2014-2017 Microchip Technology Inc. DS60001290E-page 325 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY FIGURE 31-5: EXTERNAL RESET TIMING CHARACTERISTICS Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) MCLR TMCLR (SY20) BOR TBOR (SY30) (TSYSDLY) SY02 Reset Sequence CPU Starts Fetching Code Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) (TSYSDLY) SY02 Reset Sequence CPU Starts Fetching Code TOST (SY10) TABLE 31-22: RESETS TIMING Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typical(2) Max. Units Conditions SY00 TPU Power-up Period Internal Voltage Regulator Enabled -- 400 600 s -- SY02 TSYSDLY System Delay Period: Time Required to Reload Device Configuration Fuses plus SYSCLK Delay before First instruction is Fetched. -- s + 8 SYSCLK cycles -- -- -- SY20 TMCLR MCLR Pulse Width (low) 2 -- -- s -- SY30 TBOR BOR Pulse Width (low) -- 1 -- s -- Note 1: 2: These parameters are characterized, but not tested in manufacturing. Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Characterized by design but not tested. DS60001290E-page 326 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY FIGURE 31-6: TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 Tx20 OS60 TMRx Note: Refer to Figure 31-1 for load conditions. TABLE 31-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS(1) Param. No. TA10 TA11 TA15 Symbol TTXH TTXL TTXP Characteristics(2) TxCK High Time TxCK Low Time Typical Max. Units Conditions Synchronous, with prescaler [(12.5 ns or 1 TPB)/N] + 25 ns -- -- ns Must also meet parameter TA15 Asynchronous, with prescaler 10 -- -- ns -- Synchronous, with prescaler [(12.5 ns or 1 TPB)/N] + 25 ns -- -- ns Must also meet parameter TA15 Asynchronous, with prescaler 10 -- -- ns -- [(Greater of 25 ns or 2 TPB)/N] + 30 ns -- -- ns VDD > 2.7V [(Greater of 25 ns or 2 TPB)/N] + 50 ns -- -- ns VDD < 2.7V 20 -- -- ns VDD > 2.7V (Note 3) 50 -- -- ns VDD < 2.7V (Note 3) 32 -- 100 kHz -- 1 TPB -- TxCK Synchronous, Input Period with prescaler Asynchronous, with prescaler OS60 FT1 TA20 TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment Note 1: 2: 3: Min. SOSC1/T1CK Oscillator Input Frequency Range (oscillator enabled by setting the TCS (T1CON<1>) bit) -- Timer1 is a Type A timer. This parameter is characterized, but not tested in manufacturing. N = Prescale Value (1, 8, 64, 256). 2014-2017 Microchip Technology Inc. DS60001290E-page 327 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 31-24: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Max. Units TB10 TTXH TxCK Synchronous, with High Time prescaler [(12.5 ns or 1 TPB)/N] + 25 ns -- ns TB11 TTXL TxCK Synchronous, with Low Time prescaler [(12.5 ns or 1 TPB)/N] + 25 ns -- ns Conditions Must also meet N = prescale parameter value TB15 (1, 2, 4, 8, Must also meet 16, 32, 64, 256) parameter TB15 TB15 TB20 TTXP TxCK Input Period Synchronous, with prescaler [(Greater of [(25 ns or 2 TPB)/N] + 30 ns -- ns VDD > 2.7V [(Greater of [(25 ns or 2 TPB)/N] + 50 ns -- ns VDD < 2.7V -- 1 TPB TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment Note 1: -- These parameters are characterized, but not tested in manufacturing. FIGURE 31-7: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICx IC10 IC11 IC15 Note: Refer to Figure 31-1 for load conditions. TABLE 31-25: INPUT CAPTURE MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param. Symbol No. Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp Characteristics(1) Min. Max. Units Conditions IC10 TCCL ICx Input Low Time [(12.5 ns or 1 TPB)/N] + 25 ns -- ns Must also meet parameter IC15. IC11 TCCH ICx Input High Time [(12.5 ns or 1 TPB)/N] + 25 ns -- ns Must also meet parameter IC15. IC15 TCCP ICx Input Period [(25 ns or 2 TPB)/N] + 50 ns -- ns Note 1: These parameters are characterized, but not tested in manufacturing. DS60001290E-page 328 N = prescale value (1, 4, 16) -- 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY FIGURE 31-8: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM mode) OC10 OC11 Note: Refer to Figure 31-1 for load conditions. TABLE 31-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typical(2) Max. Units Conditions OC10 TCCF OCx Output Fall Time -- -- -- ns See parameter DO32 OC11 TCCR OCx Output Rise Time -- -- -- ns See parameter DO31 Note 1: 2: These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. FIGURE 31-9: OCx/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA/OCFB OC15 OCx OCx is tri-stated Note: Refer to Figure 31-1 for load conditions. TABLE 31-27: SIMPLE OCx/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param No. Symbol Characteristics(1) Min Typical(2) Max Units Conditions OC15 TFD Fault Input to PWM I/O Change -- -- 50 ns -- OC20 TFLT Fault Input Pulse Width 50 -- -- ns -- Note 1: 2: These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 2014-2017 Microchip Technology Inc. DS60001290E-page 329 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY FIGURE 31-10: SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 SP31 SDIx MSb In LSb SP30 LSb In Bit 14 - - - -1 SP40 SP41 Note: Refer to Figure 31-1 for load conditions. TABLE 31-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions SP10 TSCL SCKx Output Low Time (Note 3) TSCK/2 -- -- ns -- SP11 TSCH SCKx Output High Time (Note 3) TSCK/2 -- -- ns -- SP20 TSCF SCKx Output Fall Time (Note 4) -- -- -- ns See parameter DO32 SP21 TSCR SCKx Output Rise Time (Note 4) -- -- -- ns See parameter DO31 SP30 TDOF SDOx Data Output Fall Time (Note 4) -- -- -- ns See parameter DO32 SP31 TDOR SDOx Data Output Rise Time (Note 4) -- -- -- ns See parameter DO31 SP35 TSCH2DOV, SDOx Data Output Valid after TSCL2DOV SCKx Edge -- -- 15 ns VDD > 2.7V -- -- 20 ns VDD < 2.7V SP40 TDIV2SCH, Setup Time of SDIx Data Input TDIV2SCL to SCKx Edge 10 -- -- ns -- SP41 TSCH2DIL, Hold Time of SDIx Data Input TSCL2DIL to SCKx Edge 10 -- -- ns -- Note 1: 2: 3: 4: These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 50 ns. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. DS60001290E-page 330 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY FIGURE 31-11: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS SP36 SCKX (CKP = 0) SP11 SCKX (CKP = 1) SP10 SP21 SP20 SP20 SP21 SP35 LSb Bit 14 - - - - - -1 MSb SDOX SP30,SP31 SDIX MSb In SP40 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 31-1 for load conditions. TABLE 31-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Typ.(2) Max. Units Conditions SP10 TSCL SCKx Output Low Time (Note 3) TSCK/2 -- -- ns -- SP11 TSCH SCKx Output High Time (Note 3) TSCK/2 -- -- ns -- SP20 TSCF SCKx Output Fall Time (Note 4) -- -- -- ns See parameter DO32 SP21 TSCR SCKx Output Rise Time (Note 4) -- -- -- ns See parameter DO31 SP30 TDOF SDOx Data Output Fall Time (Note 4) -- -- -- ns See parameter DO32 SP31 TDOR SDOx Data Output Rise Time (Note 4) -- -- -- ns See parameter DO31 SP35 TSCH2DOV, SDOx Data Output Valid after TSCL2DOV SCKx Edge -- -- 15 ns VDD > 2.7V -- -- 20 ns VDD < 2.7V SP36 TDOV2SC, SDOx Data Output Setup to TDOV2SCL First SCKx Edge 15 -- -- ns SP40 TDIV2SCH, Setup Time of SDIx Data Input to TDIV2SCL SCKx Edge 15 -- -- ns VDD > 2.7V 20 -- -- ns VDD < 2.7V TSCH2DIL, TSCL2DIL 15 -- -- ns VDD > 2.7V 20 -- -- ns VDD < 2.7V SP41 Note 1: 2: 3: 4: Hold Time of SDIx Data Input to SCKx Edge -- These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 50 ns. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. 2014-2017 Microchip Technology Inc. DS60001290E-page 331 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY FIGURE 31-12: SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX LSb Bit 14 - - - - - -1 SP51 SP30,SP31 SDIX MSb In SP40 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 31-1 for load conditions. TABLE 31-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Typ.(2) Max. Units Conditions SP70 SP71 SP72 SP73 SP30 SP31 SP35 TSCL TSCH TSCF TSCR TDOF TDOR TSCH2DOV, TSCL2DOV SCKx Input Low Time (Note 3) SCKx Input High Time (Note 3) SCKx Input Fall Time SCKx Input Rise Time SDOx Data Output Fall Time (Note 4) SDOx Data Output Rise Time (Note 4) SDOx Data Output Valid after SCKx Edge SP40 TDIV2SCH, TDIV2SCL TSCH2DIL, TSCL2DIL Setup Time of SDIx Data Input to SCKx Edge Hold Time of SDIx Data Input to SCKx Edge TSCK/2 TSCK/2 -- -- -- -- -- -- 10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15 20 -- ns ns ns ns ns ns ns ns ns -- -- See parameter DO32 See parameter DO31 See parameter DO32 See parameter DO31 VDD > 2.7V VDD < 2.7V -- 10 -- -- ns -- 175 -- -- ns -- 5 -- 25 ns -- SP41 SP50 TSSL2SCH, SSx to SCKx or SCKx Input TSSL2SCL SP51 TSSH2DOZ SSx to SDOx Output High-Impedance (Note 3) SP52 TSCH2SSH SSx after SCKx Edge TSCK + 20 -- -- ns -- TSCL2SSH These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 50 ns. Assumes 50 pF load on all SPIx pins. Note 1: 2: 3: 4: DS60001290E-page 332 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY FIGURE 31-13: SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDI SDIx MSb In SP40 SP51 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 31-1 for load conditions. TABLE 31-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions SP70 TSCL SCKx Input Low Time (Note 3) TSCK/2 -- -- ns -- SP71 TSCH SCKx Input High Time (Note 3) TSCK/2 -- -- ns -- SP72 TSCF SCKx Input Fall Time -- 5 10 ns -- SP73 TSCR SCKx Input Rise Time -- 5 10 ns -- SP30 TDOF SDOx Data Output Fall Time (Note 4) -- -- -- ns See parameter DO32 SP31 TDOR SDOx Data Output Rise Time (Note 4) -- -- -- ns See parameter DO31 SP35 TSCH2DOV, SDOx Data Output Valid after TSCL2DOV SCKx Edge -- -- 20 ns VDD > 2.7V -- -- 30 ns VDD < 2.7V SP40 TDIV2SCH, Setup Time of SDIx Data Input TDIV2SCL to SCKx Edge 10 -- -- ns -- SP41 TSCH2DIL, Hold Time of SDIx Data Input TSCL2DIL to SCKx Edge 10 -- -- ns -- SP50 TSSL2SCH, SSx to SCKx or SCKx Input TSSL2SCL 175 -- -- ns -- Note 1: 2: 3: 4: These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 50 ns. Assumes 50 pF load on all SPIx pins. 2014-2017 Microchip Technology Inc. DS60001290E-page 333 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 31-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions SP51 TSSH2DOZ SSx to SDOX Output High-Impedance (Note 4) 5 -- 25 ns -- SP52 TSCH2SSH SSx after SCKx Edge TSCL2SSH TSCK + 20 -- -- ns -- SP60 TSSL2DOV SDOx Data Output Valid after SSx Edge -- -- 25 ns -- Note 1: 2: 3: 4: These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 50 ns. Assumes 50 pF load on all SPIx pins. DS60001290E-page 334 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY FIGURE 31-14: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Stop Condition Start Condition Note: Refer to Figure 31-1 for load conditions. FIGURE 31-15: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCLx IM11 IM26 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure 31-1 for load conditions. 2014-2017 Microchip Technology Inc. DS60001290E-page 335 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 31-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. Symbol No. IM10 IM11 IM20 IM21 IM25 IM26 IM30 IM31 IM33 IM34 Min.(1) Max. Units Conditions TLO:SCL Clock Low Time 100 kHz mode TPB * (BRG + 2) -- s -- 400 kHz mode TPB * (BRG + 2) -- s -- 1 MHz mode (Note 2) TPB * (BRG + 2) -- s -- Clock High Time 100 kHz mode TPB * (BRG + 2) -- s -- 400 kHz mode TPB * (BRG + 2) -- s -- 1 MHz mode (Note 2) TPB * (BRG + 2) -- s -- -- 300 ns THI:SCL TF:SCL TR:SCL Characteristics SDAx and SCLx 100 kHz mode Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 1 MHz mode (Note 2) -- 100 ns SDAx and SCLx 100 kHz mode Rise Time 400 kHz mode -- 1000 ns TSU:DAT Data Input Setup Time THD:DAT Data Input Hold Time TSU:STA Start Condition Setup Time THD:STA Start Condition Hold Time TSU:STO Stop Condition Setup Time THD:STO Stop Condition Hold Time Note 1: 2: 3: 20 + 0.1 CB 300 ns 1 MHz mode (Note 2) -- 300 ns 100 kHz mode 250 -- ns 400 kHz mode 100 -- ns 1 MHz mode (Note 2) 100 -- ns 100 kHz mode 0 -- s 400 kHz mode 0 0.9 s 1 MHz mode (Note 2) 0 0.3 s 100 kHz mode TPB * (BRG + 2) -- s 400 kHz mode TPB * (BRG + 2) -- s 1 MHz mode (Note 2) TPB * (BRG + 2) -- s 100 kHz mode TPB * (BRG + 2) -- s 400 kHz mode TPB * (BRG + 2) -- s 1 MHz mode (Note 2) TPB * (BRG + 2) -- s 100 kHz mode TPB * (BRG + 2) -- s 400 kHz mode TPB * (BRG + 2) -- s 1 MHz mode (Note 2) TPB * (BRG + 2) -- s 100 kHz mode TPB * (BRG + 2) -- ns 400 kHz mode TPB * (BRG + 2) -- ns 1 MHz mode (Note 2) TPB * (BRG + 2) -- ns CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF -- -- Only relevant for Repeated Start condition After this period, the first clock pulse is generated -- -- BRG is the value of the I2C Baud Rate Generator. Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). The typical value for this parameter is 104 ns. DS60001290E-page 336 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 31-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. Symbol No. IM40 IM45 Min.(1) Max. Units Conditions 100 kHz mode -- 3500 ns -- 400 kHz mode -- 1000 ns -- 1 MHz mode (Note 2) -- 350 ns -- The amount of time the bus must be free before a new transmission can start Characteristics TAA:SCL Output Valid from Clock TBF:SDA Bus Free Time 100 kHz mode 4.7 -- s 400 kHz mode 1.3 -- s 1 MHz mode (Note 2) 0.5 -- s IM50 CB Bus Capacitive Loading -- 400 pF -- IM51 TPGD Pulse Gobbler Delay 52 312 ns See Note 3 Note 1: 2: 3: BRG is the value of the I2C Baud Rate Generator. Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). The typical value for this parameter is 104 ns. 2014-2017 Microchip Technology Inc. DS60001290E-page 337 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY FIGURE 31-16: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS34 IS31 IS30 IS33 SDAx Stop Condition Start Condition Note: Refer to Figure 31-1 for load conditions. FIGURE 31-17: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCLx IS30 IS26 IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out Note: Refer to Figure 31-1 for load conditions. DS60001290E-page 338 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 31-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. No. IS10 IS11 IS20 IS21 IS25 IS26 IS30 IS31 IS33 Note 1: Symbol TLO:SCL THI:SCL TF:SCL TR:SCL TSU:DAT THD:DAT TSU:STA THD:STA TSU:STO Characteristics Clock Low Time Clock High Time SDAx and SCLx Fall Time SDAx and SCLx Rise Time Data Input Setup Time Data Input Hold Time Start Condition Setup Time Start Condition Hold Time Stop Condition Setup Time Min. Max. Units 100 kHz mode 4.7 -- s PBCLK must operate at a minimum of 800 kHz 400 kHz mode 1.3 -- s PBCLK must operate at a minimum of 3.2 MHz 1 MHz mode (Note 1) 0.5 -- s 100 kHz mode 4.0 -- s PBCLK must operate at a minimum of 800 kHz 400 kHz mode 0.6 -- s PBCLK must operate at a minimum of 3.2 MHz 1 MHz mode (Note 1) 0.5 -- s 100 kHz mode -- 300 ns 400 kHz mode 20 + 0.1 CB 300 ns 1 MHz mode (Note 1) -- 100 ns 100 kHz mode -- 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns 1 MHz mode (Note 1) -- 300 ns 100 kHz mode 250 -- ns 400 kHz mode 100 -- ns 1 MHz mode (Note 1) 100 -- ns 100 kHz mode 0 -- ns 400 kHz mode 0 0.9 s 1 MHz mode (Note 1) 0 0.3 s 100 kHz mode 4700 -- ns 400 kHz mode 600 -- ns 1 MHz mode (Note 1) 250 -- ns 100 kHz mode 4000 -- ns 400 kHz mode 600 -- ns 1 MHz mode (Note 1) 250 -- ns 100 kHz mode 4000 -- ns 400 kHz mode 600 -- ns 1 MHz mode (Note 1) 600 -- ns Conditions -- -- CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF -- -- Only relevant for Repeated Start condition After this period, the first clock pulse is generated -- Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). 2014-2017 Microchip Technology Inc. DS60001290E-page 339 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 31-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. No. IS34 IS40 IS45 IS50 Note 1: Symbol THD:STO TAA:SCL TBF:SDA CB Characteristics Stop Condition Hold Time Min. Max. Units Conditions -- 100 kHz mode 4000 -- ns 400 kHz mode 600 -- ns 1 MHz mode (Note 1) 250 ns Output Valid from 100 kHz mode Clock 400 kHz mode 0 3500 ns 0 1000 ns 1 MHz mode (Note 1) 0 350 ns Bus Free Time 100 kHz mode 4.7 -- s 400 kHz mode 1.3 -- s 1 MHz mode (Note 1) 0.5 -- s -- 400 pF Bus Capacitive Loading -- The amount of time the bus must be free before a new transmission can start -- Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). DS60001290E-page 340 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 31-34: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param. Symbol No. Standard Operating Conditions (see Note 5): 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp Characteristics Min. Typical Max. Units Conditions -- Device Supply AD01 AVDD Module VDD Supply Greater of VDD - 0.3 or 2.5 -- Lesser of VDD + 0.3 or 3.6 V AD02 AVSS Module VSS Supply VSS -- AVDD V (Note 1) -- -- AVDD 3.6 V V (Note 1) VREFH = AVDD (Note 3) Reference Inputs AD05 VREFH AD05a Reference Voltage High AVSS + 2.0 2.5 AD06 VREFL Reference Voltage Low AVSS -- VREFH - 2.0 V (Note 1) AD07 VREF Absolute Reference Voltage (VREFH - VREFL) 2.0 -- AVDD V (Note 3) Current Drain -- -- 250 -- 400 3 A A ADC operating ADC off VREFL -- VREFH V -- AD08 IREF AD08a Analog Input AD12 VINH-VINL Full-Scale Input Span AD13 VINL Absolute VINL Input Voltage AVSS - 0.3 -- AVDD/2 V -- AD14 VIN Absolute Input Voltage AVSS - 0.3 -- AVDD + 0.3 V -- Leakage Current -- 0.001 0.610 A VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V Source Impedance = 10 k Recommended Impedance of Analog Voltage Source -- -- 5k (Note 1) AD15 AD17 -- RIN ADC Accuracy - Measurements with External VREF+/VREFAD20c Nr Resolution AD21c INL Integral Non-linearity > -1 -- <1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V AD22c DNL Differential Non-linearity > -1 -- <1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V (Note 2) AD23c GERR Gain Error > -1 -- <1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V AD24c EOFF Offset Error > -1 -- <1 Lsb VINL = AVSS = 0V, AVDD = 3.3V AD25c Monotonicity -- -- -- Note 1: 2: 3: 4: 5: -- 10 data bits bits -- -- Guaranteed These parameters are not characterized or tested in manufacturing. With no missing codes. These parameters are characterized, but not tested in manufacturing. Characterized with a 1 kHz sine wave. The ADC module is functional at VBORMIN < VDD < 2.5V, but with degraded performance. Unless otherwise stated, module functionality is tested, but not characterized. 2014-2017 Microchip Technology Inc. DS60001290E-page 341 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 31-34: ADC MODULE SPECIFICATIONS (CONTINUED) AC CHARACTERISTICS Param. Symbol No. Characteristics Standard Operating Conditions (see Note 5): 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp Min. Typical Max. Units Conditions ADC Accuracy - Measurements with Internal VREF+/VREFAD20d Nr Resolution AD21d INL Integral Non-linearity > -1 -- <1 LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Note 3) AD22d DNL Differential Non-linearity > -1 -- <1 LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Notes 2,3) AD23d GERR Gain Error > -4 -- <4 LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Note 3) AD24d EOFF Offset Error > -2 -- <2 Lsb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Note 3) AD25d Monotonicity -- -- -- -- Guaranteed -- 10 data bits bits (Note 3) Dynamic Performance AD32b SINAD Signal to Noise and Distortion 55 58.5 -- dB (Notes 3,4) AD34b ENOB Effective Number of bits 9.0 9.5 -- bits (Notes 3,4) Note 1: 2: 3: 4: 5: These parameters are not characterized or tested in manufacturing. With no missing codes. These parameters are characterized, but not tested in manufacturing. Characterized with a 1 kHz sine wave. The ADC module is functional at VBORMIN < VDD < 2.5V, but with degraded performance. Unless otherwise stated, module functionality is tested, but not characterized. DS60001290E-page 342 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 31-35: 10-BIT CONVERSION RATE PARAMETERS Standard Operating Conditions (see Note 3): 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp (2) AC CHARACTERISTICS ADC Speed TAD Min. Sampling Time Min. RS Max. VDD 1 Msps to 400 ksps(1) 65 ns 132 ns 500 3.0V to 3.6V ADC Channels Configuration VREF- VREF+ ANx Up to 400 ksps 200 ns 200 ns 5.0 k CHX SHA ADC 2.5V to 3.6V VREF- VREF+ or or AVSS AVDD ANx CHX SHA ADC ANx or VREF- Note 1: 2: 3: External VREF- and VREF+ pins must be used for correct operation. These parameters are characterized, but not tested in manufacturing. The ADC module is functional at VBORMIN < VDD < 2.5V, but with degraded performance. Unless otherwise stated, module functionality is tested, but not characterized. 2014-2017 Microchip Technology Inc. DS60001290E-page 343 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 31-36: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS Standard Operating Conditions (see Note 4): 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. Symbol No. Min. Typical(1) Max. Units ADC Clock Period(2) 65 -- -- ns Characteristics Conditions Clock Parameters AD50 TAD See Table 31-35 Conversion Rate AD55 TCONV Conversion Time -- 12 TAD -- -- AD56 FCNV Throughput Rate (Sampling Speed) -- -- 1000 ksps AVDD = 3.0V to 3.6V -- AVDD = 2.5V to 3.6V AD57 TSAMP Sample Time -- -- 400 ksps 1 TAD -- -- -- TSAMP must be 132 ns -- 1.0 TAD -- -- Auto-Convert Trigger (SSRC<2:0> = 111) not selected Timing Parameters AD60 TPCS Conversion Start from Sample Trigger(3) AD61 TPSS Sample Start from Setting Sample (SAMP) bit 0.5 TAD -- 1.5 TAD -- -- AD62 TCSS Conversion Completion to Sample Start (ASAM = 1)(3) -- 0.5 TAD -- -- -- AD63 TDPU Time to Stabilize Analog Stage from ADC Off to ADC On(3) -- -- 2 s -- Note 1: 2: 3: 4: These parameters are characterized, but not tested in manufacturing. Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. Characterized by design but not tested. The ADC module is functional at VBORMIN < VDD < 2.5V, but with degraded performance. Unless otherwise stated, module functionality is tested, but not characterized. DS60001290E-page 344 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY FIGURE 31-18: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP ch0_dischrg ch0_samp eoc AD61 AD60 AD55 TSAMP AD55 CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 8 5 6 7 8 1 - Software sets ADxCON. SAMP to start sampling. 2 - Sampling starts after discharge period. TSAMP is described in Section 17. "10-bit Analog-to-Digital Converter (ADC)" (DS60001104) in the "PIC32 Family Reference Manual". 3 - Software clears ADxCON. SAMP to start conversion. 4 - Sampling ends, conversion sequence starts. 5 - Convert bit 9. 6 - Convert bit 8. 7 - Convert bit 0. 8 - One TAD for end of conversion. 2014-2017 Microchip Technology Inc. DS60001290E-page 345 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY FIGURE 31-19: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001) AD50 ADCLK Instruction Execution Set ADON SAMP ch0_dischrg ch0_samp eoc TSAMP AD55 TSAMP AD55 TCONV CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 3 4 5 6 8 3 4 1 - Software sets ADxCON. ADON to start AD operation. 5 - Convert bit 0. 2 - Sampling starts after discharge period. TSAMP is described in Section 17. "10-bit Analog-to-Digital Converter (ADC)" (DS60001104). 6 - One TAD for end of conversion. 3 - Convert bit 9. 8 - Sample for time specified by SAMC<4:0>. 7 - Begin conversion of next channel. 4 - Convert bit 8. DS60001290E-page 346 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY FIGURE 31-20: PARALLEL SLAVE PORT TIMING CS PS5 RD PS6 WR PS4 PS7 PMD<7:0> PS3 PS1 PS2 2014-2017 Microchip Technology Inc. DS60001290E-page 347 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 31-37: PARALLEL SLAVE PORT REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Para Symbol m.No. Characteristics(1) Min. Typ. Max. Units Conditions PS1 TdtV2wr Data In Valid before WR or CS H Inactive (setup time) 20 -- -- ns -- PS2 TwrH2dt WR or CS Inactive to Data-In I Invalid (hold time) 40 -- -- ns -- PS3 TrdL2dt RD and CS Active to Data-Out V Valid -- -- 60 ns -- PS4 TrdH2dtI RD Activeor CS Inactive to Data-Out Invalid 0 -- 10 ns -- PS5 Tcs CS Active Time TPB + 40 -- -- ns -- PS6 TWR WR Active Time TPB + 25 -- -- ns -- PS7 TRD RD Active Time TPB + 25 -- -- ns -- Note 1: These parameters are characterized, but not tested in manufacturing. FIGURE 31-21: PARALLEL MASTER PORT READ TIMING DIAGRAM TPB TPB TPB TPB TPB TPB TPB TPB PB Clock PM4 Address PMA<13:18> PM6 PMD<7:0> Data Data Address<7:0> Address<7:0> PM2 PM3 PM7 PMRD PM5 PMWR PM1 PMALL/PMALH PMCS<2:1> DS60001290E-page 348 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 31-38: PARALLEL MASTER PORT READ TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typ. Max. Units Conditions PM1 TLAT PMALL/PMALH Pulse Width -- 1 TPB -- -- -- PM2 TADSU Address Out Valid to PMALL/ PMALH Invalid (address setup time) -- 2 TPB -- -- -- PM3 TADHOLD PMALL/PMALH Invalid to Address Out Invalid (address hold time) -- 1 TPB -- -- -- PM4 TAHOLD PMRD Inactive to Address Out Invalid (address hold time) 5 -- -- ns -- PM5 TRD PMRD Pulse Width -- 1 TPB -- -- -- PM6 TDSU PMRD or PMENB Active to Data In Valid (data setup time) 15 -- -- ns -- PM7 TDHOLD PMRD or PMENB Inactive to Data In Invalid (data hold time) -- 80 -- ns -- Note 1: These parameters are characterized, but not tested in manufacturing. FIGURE 31-22: PARALLEL MASTER PORT WRITE TIMING DIAGRAM TPB TPB TPB TPB TPB TPB TPB TPB PB Clock Address PMA<13:18> PM2 + PM3 PMD<7:0> Address<7:0> Data PM12 PM13 PMRD PM11 PMWR PM1 PMALL/PMALH PMCS<2:1> 2014-2017 Microchip Technology Inc. DS60001290E-page 349 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 31-39: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typ. Max. Units Conditions PM11 TWR PMWR Pulse Width -- 1 TPB -- -- -- PM12 TDVSU Data Out Valid before PMWR or PMENB goes Inactive (data setup time) -- 2 TPB -- -- -- PM13 TDVHOLD PMWR or PMEMB Invalid to Data Out Invalid (data hold time) -- 1 TPB -- -- -- Note 1: These parameters are characterized, but not tested in manufacturing. TABLE 31-40: OTG ELECTRICAL SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typ. Max. Units USB313 VUSB3V3 USB Voltage 3.0 -- 3.6 V USB315 VILUSB Input Low Voltage for USB Buffer -- -- 0.8 V USB316 VIHUSB Input High Voltage for USB Buffer 2.0 -- -- V -- USB318 VDIFS Differential Input Sensitivity -- -- 0.2 V The difference between D+ and Dmust exceed this value while VCM is met USB319 VCM Differential Common Mode Range 0.8 -- 2.5 V -- USB320 ZOUT Driver Output Impedance 28.0 -- 44.0 USB321 VOL Voltage Output Low 0.0 -- 0.3 V 1.425 k load connected to VUSB3V3 USB322 VOH Voltage Output High 2.8 -- 3.6 V 1.425 k load connected to ground Note 1: Conditions Voltage on VUSB3V3 must be in this range for proper USB operation -- -- These parameters are characterized, but not tested in manufacturing. DS60001290E-page 350 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 31-41: CTMU CURRENT SOURCE SPECIFICATIONS DC CHARACTERISTICS Param No. Symbol Characteristic Standard Operating Conditions (see Note 3):2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp Min. Typ. Max. Units Conditions CTMU CURRENT SOURCE CTMUI1 IOUT1 Base Range(1) -- 0.55 -- A CTMUCON<9:8> = 01 CTMUI2 IOUT2 10x Range(1) -- 5.5 -- A CTMUCON<9:8> = 10 CTMUI3 IOUT3 100x Range(1) -- 55 -- A CTMUCON<9:8> = 11 CTMUI4 IOUT4 1000x Range(1) -- 550 -- A CTMUCON<9:8> = 00 Temperature Diode Forward Voltage(1,2) -- 0.598 -- V TA = +25C, CTMUCON<9:8> = 01 -- 0.658 -- V TA = +25C, CTMUCON<9:8> = 10 -- 0.721 -- V TA = +25C, CTMUCON<9:8> = 11 -- -1.92 -- -- -1.74 -- mV/C CTMUCON<9:8> = 10 -- -1.56 -- mV/C CTMUCON<9:8> = 11 CTMUFV1 VF CTMUFV2 VFVR Note 1: 2: 3: Temperature Diode Rate of Change(1,2) mV/C CTMUCON<9:8> = 01 Nominal value at center point of current trim range (CTMUCON<15:10> = 000000). Parameters are characterized but not tested in manufacturing. Measurements taken with the following conditions: * VREF+ = AVDD = 3.3V * ADC module configured for conversion speed of 500 ksps * All PMD bits are cleared (PMDx = 0) * Executing a while(1) statement * Device operating from the FRC with no PLL The CTMU module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless otherwise stated, module functionality is tested, but not characterized. 2014-2017 Microchip Technology Inc. DS60001290E-page 351 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY FIGURE 31-23: EJTAG TIMING CHARACTERISTICS TTCKcyc TTCKhigh TTCKlow Trf TCK Trf TMS TDI TTsetup TThold Trf Trf TDO TTRST*low TTDOout TTDOzstate TRST* Defined Trf Undefined TABLE 31-42: EJTAG TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. No. Symbol Description(1) Min. Max. Units Conditions EJ1 TTCKCYC TCK Cycle Time 25 -- ns -- EJ2 TTCKHIGH TCK High Time 10 -- ns -- EJ3 TTCKLOW TCK Low Time 10 -- ns -- EJ4 TTSETUP TAP Signals Setup Time Before Rising TCK 5 -- ns -- EJ5 TTHOLD TAP Signals Hold Time After Rising TCK 3 -- ns -- EJ6 TTDOOUT TDO Output Delay Time from Falling TCK -- 5 ns -- EJ7 TTDOZSTATE TDO 3-State Delay Time from Falling TCK -- 5 ns -- EJ8 TTRSTLOW TRST Low Time 25 -- ns -- EJ9 TRF TAP Signals Rise/Fall Time, All Input and Output -- -- ns -- Note 1: These parameters are characterized, but not tested in manufacturing. DS60001290E-page 352 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 32.0 50 MHz ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC32MX1XX/2XX/5XX 64/100-pin Family electrical characteristics for devices operating at 50 MHz. The specifications for 50 MHz are identical to those shown in Section 31.0 "40 MHz Electrical Characteristics", with the exception of the parameters listed in this chapter. Parameters in this chapter begin with the letter "M", which denotes 50 MHz operation. For example, parameter DC29a in Section 31.0 "40 MHz Electrical Characteristics", is the up to 40 MHz operation equivalent for MDC29a. Absolute maximum ratings for the PIC32MX1XX/2XX/5XX 64/100-pin Family 50 MHz devices are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions, above the parameters indicated in the operation listings of this specification, is not implied. Absolute Maximum Ratings (See Note 1) Ambient temperature under bias.............................................................................................................. .-40C to +85C Storage temperature .............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant, with respect to VSS (Note 3)......................................... -0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD 2.3V (Note 3)........................................ -0.3V to +5.5V Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V (Note 3)........................................ -0.3V to +3.6V Voltage on D+ or D- pin with respect to VUSB3V3 .................................................................... -0.3V to (VUSB3V3 + 0.3V) Voltage on VBUS with respect to VSS ....................................................................................................... -0.3V to +5.5V Maximum current out of VSS pin(s) .......................................................................................................................300 mA Maximum current into VDD pin(s) (Note 2)............................................................................................................300 mA Maximum output current sunk by any I/O pin..........................................................................................................15 mA Maximum output current sourced by any I/O pin ....................................................................................................15 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports (Note 2)....................................................................................................200 mA Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions, above those indicated in the operation listings of this specification, is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table 32-2). 3: See the "Device Pin Tables" section for the 5V tolerant pins. 2014-2017 Microchip Technology Inc. DS60001290E-page 353 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 32.1 DC Characteristics TABLE 32-1: OPERATING MIPS VS. VOLTAGE Max. Frequency Characteristic VDD Range (in Volts)(1) Temp. Range (in C) MDC5 VBOR-3.6V -40C to +85C Note 1: PIC32MX1XX/2XX/5XX 64/100-pin Family 50 MHz Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN. Refer to parameter BO10 in Table 31-10 for BOR values. TABLE 32-2: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial DC CHARACTERISTICS Parameter No. Typical(3) Max. Units Conditions mA 50 MHz Operating Current (IDD) (Note 1, 2) MDC24 Note 1: 2: 3: 4: 25 40 A device's IDD supply current is mainly a function of the operating voltage and frequency. Other factors, such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate, oscillator type, as well as temperature, can have an impact on the current consumption. The test conditions for IDD measurements are as follows: * Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required) * OSC2/CLKO is configured as an I/O input pin * USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8 * CPU, Program Flash, and SRAM data memory are operational, SRAM data memory Wait states = 1 * No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is cleared * WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled * All I/O pins are configured as inputs and pulled to VSS * MCLR = VDD * CPU executing while(1) statement from Flash RTCC and JTAG are disabled Data in "Typical" column is at 3.3V, 25C at specified operating frequency unless otherwise stated. Parameters are for design guidance only and are not tested. DS60001290E-page 354 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 32-3: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial DC CHARACTERISTICS Parameter No. Typical(2) Max. Units Conditions Idle Current (IIDLE): Core Off, Clock on Base Current (Note 1) MDC34a Note 1: 2: 9.5 24 TABLE 32-4: 50 MHz DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial DC CHARACTERISTICS Param. No. mA The test conditions for IIDLE current measurements are as follows: * Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required) * OSC2/CLKO is configured as an I/O input pin * USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8 * CPU is in Idle mode (CPU core Halted), and SRAM data memory Wait states = 1 * No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is cleared * WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled * All I/O pins are configured as inputs and pulled to VSS * MCLR = VDD * RTCC and JTAG are disabled Data in the "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. Typical(2) Max. Units Conditions Power-Down Current (IPD) (Note 1) MDC40k 50 150 A -40C MDC40n 250 650 A +85C 55 A 3.6V Watchdog Timer Current: IWDT (Note 3) Base Power-Down Current Module Differential Current MDC41e 15 MDC42e 34 55 A 3.6V RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3) MDC43d 1100 1800 A 3.6V ADC: IADC (Notes 3,4) Note 1: 2: 3: 4: The test conditions for IPD current measurements are as follows: * Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required) * OSC2/CLKO is configured as an I/O input pin * USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8 * CPU is in Sleep mode, and SRAM data memory Wait states = 1 * No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is set * WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled * All I/O pins are configured as inputs and pulled to VSS * MCLR = VDD * RTCC and JTAG are disabled Data in the "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled. 2014-2017 Microchip Technology Inc. DS60001290E-page 355 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 32.2 AC Characteristics and Timing Parameters The information contained in this section defines PIC32MX1XX/2XX/5XX 64/100-pin AC characteristics and timing parameters. TABLE 32-5: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial AC CHARACTERISTICS Param. Symbol No. MOS10 FOSC Note 1: 2: Characteristics External CLKI Frequency (External clocks allowed only in EC and ECPLL modes) Typical Max. Units Conditions DC 4 -- -- 50 50 MHz MHz EC (Note 2) ECPLL (Note 1) PLL input requirements: 4 MHz FPLLIN 5 MHz (use PLL prescaler to reduce Fosc). This parameter is characterized, but tested at 10 MHz only at manufacturing. This parameter is characterized, but not tested in manufacturing. TABLE 32-6: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial AC CHARACTERISTICS Param. No. Min. Symbol Characteristics Min. Typical Max. Units Conditions MSP10 TSCL SCKx Output Low Time (Note 1,2) TSCK/2 -- -- ns -- MSP11 TSCH SCKx Output High Time (Note 1,2) TSCK/2 -- -- ns -- Note 1: 2: These parameters are characterized, but not tested in manufacturing. The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not violate this specification. TABLE 32-7: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Typ. Max. Units Conditions MSP10 TSCL SCKx Output Low Time (Note 1,2) TSCK/2 -- -- ns -- MSP11 TSCH SCKx Output High Time (Note 1,2) TSCK/2 -- -- ns -- Note 1: 2: These parameters are characterized, but not tested in manufacturing. The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not violate this specification. DS60001290E-page 356 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY TABLE 32-8: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. No. Symbol Min. Typ. Max. Units Conditions TSCK/2 TSCK/2 -- -- -- -- ns ns -- -- 5 -- 25 MSP51 TSSH2DOZ SSx to SDOx Output High-Impedance (Note 2) Note 1: These parameters are characterized, but not tested in manufacturing. 2: The minimum clock period for SCKx is 40 ns. ns -- MSP70 TSCL MSP71 TSCH TABLE 32-9: Characteristics SCKx Input Low Time (Note 1,2) SCKx Input High Time (Note 1,2) SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial AC CHARACTERISTICS Param. No. Symbol Characteristics Min. Typical Max. Units Conditions SP70 TSCL SCKx Input Low Time (Note 1,2) TSCK/2 -- -- ns -- SP71 TSCH SCKx Input High Time (Note 1,2) TSCK/2 -- -- ns -- Note 1: 2: These parameters are characterized, but not tested in manufacturing. The minimum clock period for SCKx is 40 ns. 2014-2017 Microchip Technology Inc. DS60001290E-page 357 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY NOTES: DS60001290E-page 358 2014-2017 Microchip Technology Inc. DC AND AC DEVICE CHARACTERISTICS GRAPHS Note: The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. FIGURE 33-1: VOH - 4x DRIVER PINS FIGURE 33-3: 40.00 45.000 3.3V 35.00 40.000 3.3V 35.000 30.00 25.00 Current(mA) Current(mA) VOL - 4x DRIVER PINS 20.00 15.00 Absolute Maximum 30.000 25.000 20.000 15.000 10.00 10.000 5.00 5.000 0.000 0.000 0.00 0.0 FIGURE 33-2: 0.5 1.0 1.5 Voltage(V) 2.0 2.5 3.0 0.500 1.000 1.500 2.000 2.500 3.000 Voltage(V) FIGURE 33-4: VOH - 8x DRIVER PINS Absolute Maximum VOL - 8x DRIVER PINS 80.000 70.00 70.000 60.00 3.3V 3.3V 60.000 Current(mA) DS60001290E-page 359 Current(mA) 50.00 40.00 30.00 Absolute Maximum 20.00 40.000 30.000 Absolute Maximum 20.000 10.000 10.00 0.00 50.000 0.0 0.5 1.0 1.5 2.0 Voltage(V) 2.5 3.0 0.000 0.000 0.500 1.000 1.500 2.000 Voltage(V) 2.500 3.000 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 2014-2017 Microchip Technology Inc. 33.0 TYPICAL CTMU TEMPERATURE DIODE FORWARD VOLTAGE 0.850 0.800 Forward Voltage (V) 0.750 0.700 VF = 0.721 0.650 VF = 0.658 0.600 55 A , VFV R = -1.5 6 mV 5.5 A, V FV VF = 0.598 R 0.55 0.550 0.500 0 500 /C = -1. 74 m V/C A, VFV R= -1.9 2 0.450 mV/ C 0.400 0.350 -40 -30 -20 -10 0 10 20 30 40 50 Temperature (Celsius) 60 70 80 90 100 110 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DS60001290E-page 360 FIGURE 33-5: PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 34.0 PACKAGING INFORMATION 34.1 Package Marking Information 64-Lead TQFP (10x10x1 mm) PIC32MX150F 256H-I/PT XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN e3 0510017 64-Lead QFN (9x9x0.9 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN e3 0510017 XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 100-Lead TQFP (12x12x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN * Note: Example PIC32MX150F 256H-I/MR 100-Lead TQFP (14x14x1 mm) Legend: XX...X Y YY WW NNN Example Example PIC32MX150F 256L-I/PF e3 0510017 Example PIC32MX150F 256L-I/PT e3 0510017 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e)3 can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2014-2017 Microchip Technology Inc. DS60001290E-page 361 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY 34.2 Package Details The following sections give the technical details of the packages. /HDG3ODVWLF7KLQ4XDG)ODWSDFN 37 [[PP%RG\PP>74)3@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D D1 E e E1 N b NOTE 1 123 NOTE 2 A c A2 A1 L L1 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI/HDGV 0,//,0(7(56 0,1 1 120 0$; /HDG3LWFK H 2YHUDOO+HLJKW $ %6& 0ROGHG3DFNDJH7KLFNQHVV $ 6WDQGRII $ )RRW/HQJWK / )RRWSULQW / 5() )RRW$QJOH 2YHUDOO:LGWK ( %6& 2YHUDOO/HQJWK ' %6& 0ROGHG3DFNDJH:LGWK ( %6& 0ROGHG3DFNDJH/HQJWK ' %6& /HDG7KLFNQHVV F /HDG:LGWK E 0ROG'UDIW$QJOH7RS 0ROG'UDIW$QJOH%RWWRP 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD &KDPIHUVDWFRUQHUVDUHRSWLRQDOVL]HPD\YDU\ 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% DS60001290E-page 362 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2014-2017 Microchip Technology Inc. DS60001290E-page 363 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY /HDG3ODVWLF7KLQ4XDG)ODWSDFN 3) [[PP%RG\PP>74)3@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D D1 e E1 E b N NOTE 1 1 23 A NOTE 2 c A2 A1 L L1 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI/HDGV 0,//,0(7(56 0,1 1 120 0$; /HDG3LWFK H 2YHUDOO+HLJKW $ %6& 0ROGHG3DFNDJH7KLFNQHVV $ 6WDQGRII $ )RRW/HQJWK / )RRWSULQW / 5() )RRW$QJOH 2YHUDOO:LGWK ( %6& 2YHUDOO/HQJWK ' %6& 0ROGHG3DFNDJH:LGWK ( %6& 0ROGHG3DFNDJH/HQJWK ' %6& /HDG7KLFNQHVV F /HDG:LGWK E 0ROG'UDIW$QJOH7RS 0ROG'UDIW$QJOH%RWWRP 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD &KDPIHUVDWFRUQHUVDUHRSWLRQDOVL]HPD\YDU\ 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% DS60001290E-page 364 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2014-2017 Microchip Technology Inc. DS60001290E-page 365 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY /HDG3ODVWLF7KLQ4XDG)ODWSDFN 37 [[PP%RG\PP>74)3@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D D1 e E E1 N b NOTE 1 1 23 NOTE 2 c A L A1 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI/HDGV A2 L1 0,//,0(7(56 0,1 1 120 0$; /HDG3LWFK H 2YHUDOO+HLJKW $ %6& 0ROGHG3DFNDJH7KLFNQHVV $ 6WDQGRII $ )RRW/HQJWK / )RRWSULQW / 5() )RRW$QJOH 2YHUDOO:LGWK ( %6& 2YHUDOO/HQJWK ' %6& 0ROGHG3DFNDJH:LGWK ( %6& 0ROGHG3DFNDJH/HQJWK ' %6& /HDG7KLFNQHVV F /HDG:LGWK E 0ROG'UDIW$QJOH7RS 0ROG'UDIW$QJOH%RWWRP 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD &KDPIHUVDWFRUQHUVDUHRSWLRQDOVL]HPD\YDU\ 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% DS60001290E-page 366 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2014-2017 Microchip Technology Inc. DS60001290E-page 367 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS60001290E-page 368 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2014-2017 Microchip Technology Inc. DS60001290E-page 369 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS60001290E-page 370 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY INDEX A AC Characteristics .................................................... 321, 356 10-Bit Conversion Rate Parameters ......................... 343 ADC Specifications ................................................... 341 Analog-to-Digital Conversion Requirements............. 344 EJTAG Timing Requirements ................................... 352 Internal FRC Accuracy.............................................. 323 Internal RC Accuracy ................................................ 323 OTG Electrical Specifications ................................... 350 Parallel Master Port Read Requirements ................. 349 Parallel Master Port Write ......................................... 350 Parallel Master Port Write Requirements.................. 350 Parallel Slave Port Requirements ............................. 348 PLL Clock Timing...................................................... 323 Analog-to-Digital Converter (ADC).................................... 231 B Block Diagrams ADC Module.............................................................. 231 Comparator I/O Operating Modes............................. 271 Comparator Voltage Reference ................................ 275 Connections for On-Chip Voltage Regulator............. 302 CPU ............................................................................ 35 CTMU Configurations Time Measurement ........................................... 279 DMA ............................................................................ 85 Input Capture ............................................................ 173 Inter-Integrated Circuit (I2C)...................................... 192 Interrupt Controller ...................................................... 53 JTAG Programming, Debugging and Trace Ports .... 302 Output Compare Module........................................... 177 PIC32 CAN Module................................................... 243 PMP Pinout and Connections to External Devices ... 207 Reset System.............................................................. 69 RTCC ........................................................................ 221 SPI Module ............................................................... 181 Timer1....................................................................... 159 Timer2/3/4/5 (16-Bit) ................................................. 163 Typical Multiplexed Port Structure ............................ 129 UART ........................................................................ 199 WDT and Power-up Timer ........................................ 169 Brown-out Reset (BOR) and On-Chip Voltage Regulator................................ 302 C C Compilers MPLAB C18 .............................................................. 306 Charge Time Measurement Unit. See CTMU. Clock Diagram .................................................................... 74 Comparator Specifications.................................................... 319, 320 Comparator Module .......................................................... 271 Comparator Voltage Reference (CVref ............................. 275 Configuration Bit ............................................................... 291 Configuring Analog Port Pins ............................................ 130 Controller Area Network (CAN)......................................... 243 CPU Architecture Overview................................................. 36 Coprocessor 0 Registers ............................................ 37 Core Exception Types................................................. 38 EJTAG Debug Support ............................................... 38 Power Management .................................................... 38 CPU Module.................................................................. 25, 35 2014-2017 Microchip Technology Inc. CTMU Registers .................................................................. 281 Customer Change Notification Service............................. 379 Customer Notification Service .......................................... 379 Customer Support............................................................. 379 D DC and AC Characteristics Graphs and Tables ................................................... 359 DC Characteristics............................................................ 310 I/O Pin Input Specifications ...................................... 315 I/O Pin Output Specifications.................................... 316 Idle Current (IIDLE) .................................................... 313 Power-Down Current (IPD)........................................ 314 Program Memory...................................................... 318 Temperature and Voltage Specifications.................. 311 DC Characteristics (50 MHz) ............................................ 354 Idle Current (IIDLE) .................................................... 355 Power-Down Current (IPD)........................................ 355 Development Support ....................................................... 305 Direct Memory Access (DMA) Controller............................ 85 E Electrical Characteristics .................................................. 309 50 MHz ..................................................................... 353 Errata .................................................................................. 10 External Clock Timer1 Timing Requirements ................................... 327 Timer2, 3, 4, 5 Timing Requirements ....................... 328 Timing Requirements ............................................... 322 External Clock (50 MHz) Timing Requirements ............................................... 356 F Flash Program Memory ...................................................... 63 RTSP Operation ......................................................... 63 H High Voltage Detect (HVD)......................................... 71, 302 I I/O Ports ........................................................................... 129 Parallel I/O (PIO) ...................................................... 130 Write/Read Timing.................................................... 130 Input Change Notification ................................................. 130 Instruction Set................................................................... 303 Inter-Integrated Circuit (I2C) ............................................. 191 Internal Voltage Reference Specifications........................ 320 Internet Address ............................................................... 379 Interrupt Controller.............................................................. 53 IRG, Vector and Bit Location ...................................... 54 M Memory Maps Devices with 128 KB of Program Memory.................. 41 Devices with 256 KB of Program Memory.................. 42 Devices with 512 KB of Program Memory.................. 43 Devices with 64 KB of Program Memory.................... 40 Memory Organization ......................................................... 39 Layout......................................................................... 39 Microchip Internet Web Site.............................................. 379 MPASM Assembler........................................................... 306 MPLAB ASM30 Assembler, Linker, Librarian ................... 306 MPLAB Integrated Development Environment Software.. 305 DS60001290E-page 371 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY MPLAB PM3 Device Programmer..................................... 307 MPLAB REAL ICE In-Circuit Emulator System ................. 307 MPLINK Object Linker/MPLIB Object Librarian ................ 306 O Oscillator Configuration....................................................... 73 Output Compare................................................................ 177 P Packaging ......................................................................... 361 Details ....................................................................... 362 Marking ..................................................................... 361 Parallel Master Port (PMP) ............................................... 207 PIC32 Family USB Interface Diagram............................... 106 Pinout I/O Descriptions (table) ............................................ 14 Power-on Reset (POR) and On-Chip Voltage Regulator ................................ 302 Power-Saving Features..................................................... 285 CPU Halted Methods ................................................ 285 Operation .................................................................. 285 with CPU Running..................................................... 285 R Real-Time Clock and Calendar (RTCC)............................ 221 Register Map ADC .......................................................................... 233 Bus Matrix ................................................................... 45 Comparator ............................................................... 272 Comparator Voltage Reference ................................ 276 CTMU........................................................................ 280 Device and Revision ID Summary ............................ 292 Device Configuration Word Summary....................... 292 DMA Channel 0-3 ....................................................... 87 DMA CRC ................................................................... 86 DMA Global................................................................. 86 Flash Controller........................................................... 64 I2C1 and I2C2 ........................................................... 193 Input Capture 1-5 ...................................................... 174 Interrupt....................................................................... 56 Oscillator Configuration....................................... 76, 170 Output Compare1-5 .................................................. 178 Parallel Master Port .................................................. 208 Peripheral Pin Select Input ....................................... 151 Peripheral Pin Select Output..................................... 153 PORTA (100-pin Devices Only) ................................ 137 PORTB...................................................................... 138 PORTB (100-pin Devices Only) ................................ 139 PORTC (64-pin Devices Only) .................................. 140 PORTD (100-pin Devices Only) ................................ 141 PORTD (64-pin Devices Only) .................................. 142 PORTE (100-pin Devices Only) ................................ 143 PORTE (64-pin Devices Only) .................................. 144 PORTF (100-pin General Purpose Devices Only) .... 145 PORTF (100-pin USB Devices Only) ........................ 146 PORTF (64-pin General Purpose Devices Only) ...... 147 PORTF (64-pin USB Devices Only) .......................... 148 PORTG (100-pin Devices Only)................................ 149 PORTG (64-pin Devices Only).................................. 150 RTCC ........................................................................ 222 SPI1 through SPI4 .................................................... 182 Timer1 ....................................................................... 160 Timer2-5.................................................................... 165 UART1-5 ................................................................... 200 USB........................................................................... 107 Registers [pin name]R (Peripheral Pin Select Input)................. 157 DS60001290E-page 372 AD1CHS (ADC Input Select) .................................... 239 AD1CON1 (A/D Control 1)........................................ 230 AD1CON1 (ADC Control 1) .............................. 230, 235 AD1CON2 (ADC Control 2) ...................................... 237 AD1CON3 (ADC Control 3) ...................................... 238 AD1CSSL (ADC Input Scan Select) ......................... 241 AD1CSSL2 (ADC Input Scan Select 2) .................... 241 ALRMDATE (Alarm Date Value)............................... 230 ALRMDATECLR (ALRMDATE Clear) ...................... 230 ALRMTIME (Alarm Time Value) ............................... 229 ALRMTIMECLR (ALRMTIME Clear) ........................ 230 ALRMTIMEINV (ALRMTIME Invert) ......................... 230 ALRMTIMESET (ALRMTIME Set)............................ 230 BMXBOOTSZ (Boot Flash (IFM) Size ........................ 51 BMXCON (Bus Matrix Configuration) ......................... 46 BMXDKPBA (Data RAM Kernel Program Base Address) .................................................... 47 BMXDRMSZ (Data RAM Size Register)..................... 50 BMXDUDBA (Data RAM User Data Base Address)... 48 BMXDUPBA (Data RAM User Program Base Address) .................................................... 49 BMXPFMSZ (Program Flash (PFM) Size).................. 51 BMXPUPBA (Program Flash (PFM) User Program Base Address) .................................................... 50 CiCFG (CAN Baud Rate Configuration) ................... 248 CiCON (CAN Module Control) .................................. 246 CiFIFOBA (CAN Message Buffer Base Address)..... 265 CiFIFOCINn (CAN Module Message Index Register `n') 270 CiFIFOCONn (CAN FIFO Control Register `n') ........ 266 CiFIFOINTn (CAN FIFO Interrupt Register `n')......... 268 CiFIFOUAn (CAN FIFO User Address Register `n') . 270 CiFLTCON0 (CAN Filter Control 0) .......................... 256 CiFLTCON1 (CAN Filter Control 1) .......................... 258 CiFLTCON2 (CAN Filter Control 2) .......................... 260 CiFLTCON3 (CAN Filter Control 3) .......................... 262 CiFSTAT (CAN FIFO Status).................................... 253 CiINT (CAN Interrupt) ............................................... 250 CiRXFn (CAN Acceptance Filter `n')......................... 264 CiRXMn (CAN Acceptance Filter Mask `n') .............. 255 CiRXOVF (CAN Receive FIFO Overflow Status) ..... 254 CiTMR (CAN Timer) ................................................. 254 CiTREC (CAN Transmit/Receive Error Count) ......... 253 CiVEC (CAN Interrupt Code) .................................... 252 CM1CON (Comparator 1 Control) ............................ 273 CMSTAT (Comparator Control Register).................. 274 CNCONx (Change Notice Control for PORTx) ......... 158 CTMUCON (CTMU Control) ..................................... 281 CVRCON (Comparator Voltage Reference Control) 277 DCHxCON (DMA Channel x Control) ......................... 95 DCHxCPTR (DMA Channel x Cell Pointer) .............. 102 DCHxCSIZ (DMA Channel x Cell-Size) .................... 102 DCHxDAT (DMA Channel x Pattern Data) ............... 103 DCHxDPTR (Channel x Destination Pointer) ........... 101 DCHxDSA (DMA Channel x Destination Start Address)..................................................... 99 DCHxDSIZ (DMA Channel x Destination Size) ........ 100 DCHxECON (DMA Channel x Event Control) ............ 96 DCHxINT (DMA Channel x Interrupt Control)............. 97 DCHxSPTR (DMA Channel x Source Pointer) ......... 101 DCHxSSA (DMA Channel x Source Start Address) ... 99 DCHxSSIZ (DMA Channel x Source Size) ............... 100 DCRCCON (DMA CRC Control)................................. 92 DCRCDATA (DMA CRC Data) ................................... 94 DCRCXOR (DMA CRCXOR Enable) ......................... 94 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY DEVCFG0 (Device Configuration Word 0................. 293 DEVCFG1 (Device Configuration Word 1................. 295 DEVCFG2 (Device Configuration Word 2................. 297 DEVCFG3 (Device Configuration Word 3................. 299 DEVID (Device and Revision ID) .............................. 301 DMAADDR (DMA Address) ........................................ 91 DMAADDR (DMR Address) ........................................ 91 DMACON (DMA Controller Control) ........................... 90 DMASTAT (DMA Status) ............................................ 91 I2CxCON (I2C `x' Control Register (`x' = 1 and 2)) ... 194 I2CxSTAT (I2C Status Register)............................... 196 ICxCON (Input Capture x Control) ............................ 175 IFSx (Interrupt Flag Status)......................................... 60 INTCON (Interrupt Control)......................................... 58 INTSTAT (Interrupt Status) ......................................... 59 IPCx (Interrupt Priority Control)................................... 61 IPTMR Interrupt Proximity Timer) ............................... 59 NVMADDR (Flash Address) ....................................... 66 NVMCON (Programming Control) .............................. 65 NVMDATA (Flash Program Data) ............................... 67 NVMKEY (Programming Unlock)................................ 66 NVMSRCADDR (Source Data Address)..................... 67 OCxCON (Output Compare x Control) ..................... 179 OSCCON (Oscillator Control) ..................................... 77 PMADDR (Parallel Port Address) ............................. 213 PMAEN (Parallel Port Pin Enable)............................ 215 PMCON (Parallel Port Control) ................................. 209 PMDIN (Parallel Port Input Data)...................... 214, 219 PMDOUT (Parallel Port Output Data) ....................... 214 PMMODE (Parallel Port Mode) ................................. 211 PMRADDR (Parallel Port Read Address) ................. 218 PMSTAT (Parallel Port Status (Slave Modes Only) .. 216 PMWADDR (Parallel Port Write Address) ................ 217 REFOCON (Reference Oscillator Control) ................. 81 REFOTRIM (Reference Oscillator Trim) ..................... 83 RPnR (Peripheral Pin Select Output)........................ 157 RSWRST (Software Reset) ........................................ 72 RTCCON (RTC Control) ........................................... 223 RTCDATE (RTC Date Value) ................................... 228 RTCTIME (RTC Time Value) .................................... 227 SPIxCON (SPI Control)............................................. 184 SPIxCON2 (SPI Control 2)........................................ 187 SPIxSTAT (SPI Status)............................................. 188 T1CON (Type A Timer Control) ................................ 161 TxCON (Type B Timer Control) ................................ 166 U1ADDR (USB Address) .......................................... 123 U1BDTP1 (USB BDT Page 1) .................................. 125 U1BDTP2 (USB BDT Page 2) .................................. 126 U1BDTP3 (USB BDT Page 3) .................................. 126 U1CNFG1 (USB Configuration 1) ............................. 127 U1CON (USB Control) .............................................. 121 U1EIE (USB Error Interrupt Enable) ......................... 119 U1EIR (USB Error Interrupt Status) .......................... 117 U1EP0-U1EP15 (USB Endpoint Control) ................. 128 U1FRMH (USB Frame Number High)....................... 124 U1FRML (USB Frame Number Low) ........................ 123 U1IE (USB Interrupt Enable)..................................... 116 U1IR (USB Interrupt)................................................. 115 U1OTGCON (USB OTG Control) ............................. 113 U1OTGIE (USB OTG Interrupt Enable) .................... 111 U1OTGIR (USB OTG Interrupt Status)..................... 110 U1OTGSTAT (USB OTG Status).............................. 112 U1PWRC (USB Power Control)................................ 114 U1SOF (USB SOF Threshold).................................. 125 U1STAT (USB Status) .............................................. 120 2014-2017 Microchip Technology Inc. U1TOK (USB Token)................................................ 124 WDTCON (Watchdog Timer Control) ....................... 171 Reset SFR Summary.......................................................... 70 Resets ................................................................................ 69 Revision History................................................................ 375 RTCALRM (RTC ALARM Control).................................... 225 S Serial Peripheral Interface (SPI) ....................................... 181 Software Simulator (MPLAB SIM) .................................... 307 Special Features............................................................... 291 T Timer1 Module.................................................................. 159 Timer2/3, Timer4/5 Modules............................................. 163 Timing Diagrams 10-Bit Analog-to-Digital Conversion (ASAM = 0, SSRC<2:0> = 000)........................ 345 10-Bit Analog-to-Digital Conversion (ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001) ....... 346 EJTAG ...................................................................... 352 External Clock .......................................................... 321 I/O Characteristics .................................................... 324 I2Cx Bus Data (Master Mode) .................................. 335 I2Cx Bus Data (Slave Mode) .................................... 338 I2Cx Bus Start/Stop Bits (Master Mode)................... 335 I2Cx Bus Start/Stop Bits (Slave Mode)..................... 338 Input Capture (CAPx) ............................................... 328 OCx/PWM................................................................. 329 Output Compare (OCx) ............................................ 329 Parallel Master Port Read ........................................ 348 Parallel Master Port Write......................................... 349 Parallel Slave Port .................................................... 347 SPIx Master Mode (CKE = 0) ................................... 330 SPIx Master Mode (CKE = 1) ................................... 331 SPIx Slave Mode (CKE = 0) ..................................... 332 SPIx Slave Mode (CKE = 1) ..................................... 333 Timer1, 2, 3, 4, 5 External Clock .............................. 327 UART Reception....................................................... 206 UART Transmission (8-bit or 9-bit Data) .................. 206 Timing Requirements CLKO and I/O ........................................................... 324 Timing Specifications I2Cx Bus Data Requirements (Master Mode)........... 336 I2Cx Bus Data Requirements (Slave Mode)............. 339 Input Capture Requirements .................................... 328 Output Compare Requirements................................ 329 Simple OCx/PWM Mode Requirements ................... 329 SPIx Master Mode (CKE = 0) Requirements............ 330 SPIx Master Mode (CKE = 1) Requirements............ 331 SPIx Slave Mode (CKE = 1) Requirements.............. 333 SPIx Slave Mode Requirements (CKE = 0).............. 332 Timing Specifications (50 MHz) SPIx Master Mode (CKE = 0) Requirements............ 356 SPIx Master Mode (CKE = 1) Requirements............ 356 SPIx Slave Mode (CKE = 1) Requirements.............. 357 SPIx Slave Mode Requirements (CKE = 0).............. 357 U UART ................................................................................ 199 USB On-The-Go (OTG) .................................................... 105 V VCAP pin............................................................................ 302 Voltage Regulator (On-Chip) ............................................ 302 DS60001290E-page 373 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY W WWW Address.................................................................. 379 WWW, On-Line Support...................................................... 10 DS60001290E-page 374 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY APPENDIX A: REVISION HISTORY Revision A (July 2014) This is the initial released version of the document. Revision B (September 2014) This revision includes the following major changes, which are referenced by their respective chapter in Table A-1. In addition, minor updates to text and formatting were incorporated throughout the document. TABLE A-1: MAJOR SECTION UPDATES Section Name Update Description 1.0 "Device Overview" Added the USBOEN pin to the Pinout I/O Descriptions (see Table 1-1). 2.0 "Guidelines for Getting Started with 32-bit MCUs" Updated the Primary Oscillator loading capacitor calculations (see 2.8.1 "Crystal Oscillator Design Consideration"). Added 2.11 "Considerations When Interfacing to Remotely Powered Circuits" 10.0 "USB On-The-Go (OTG)" Updated the UOEMON bit definitions (see Register 10-20). 31.0 "40 MHz Electrical Characteristics" Updated DC Characteristics I/O Pin Input Specification parameters DI30 and DI31 (see Table 31-8). Revision C (November 2014) This revision includes the following major changes, which are referenced by their respective chapter in Table A-2. In addition, minor updates to text and formatting were incorporated throughout the document. TABLE A-2: MAJOR SECTION UPDATES Section Name Update Description 20.0 "Parallel Master Port (PMP)" Added the RDSTART bit to the Parallel Port Control Register (see Table 20-1 and Register 20-1). 31.0 "40 MHz Electrical Characteristics" Updated the IDD Operating Current DC Characteristics (see Table 31-5). Updated the IIDLE Idle Current DC Characteristics (see Table 31-6). Updated the IPD Power Down Current DC Characteristics (see Table 31-7). Updated the Internal FRC Accuracy (see Table 31-19). 32.0 "50 MHz Electrical Characteristics" Updated the IDD Operating Current DC Characteristics (see Table 32-2). Updated the IIDLE Idle Current DC Characteristics (see Table 32-3). Updated the IPD Power Down Current DC Characteristics (see Table 32-4). 2014-2017 Microchip Technology Inc. DS60001290E-page 375 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY Revision D (April 2016) This revision includes the following major changes, which are referenced by their respective chapter in Table A-2. TABLE A-3: MAJOR SECTION UPDATES Section Name 1.0 "Device Overview" Update Description Removed the USBOEN pin and all trace-related pins from the Pinout I/O Descriptions (see Table 1-1). 2.0 "Guidelines for Getting Started Section 2.7 "Trace" was removed. with 32-bit MCUs" Section 2.10 "Sosc Design Recommendation" was removed. 3.0 "CPU" References to the Shadow Register Set (SRS), which is not supported by PIC32MX1XX/2XX/5XX 64/100-pin Family devices, were removed from 3.1 "Features", 3.2.1 "Execution Unit", and Coprocessor 0 Registers (Table 3-2). 4.0 "Memory Organization" The SFR Memory Map was added (see Table 4-1). 5.0 "Interrupt Controller" The Single Vector Shadow Register Set (SSO) bit (INTCON<16>) was removed (see Register 5-1). 10.0 "USB On-The-Go (OTG)" The UOEMON bit (U1CNFG1<6>) was removed (see Register 10-20). 23.0 "Controller Area Network (CAN)" The CAN features (number of messages and FIFOs) were updated. The PIC32 CAN Block Diagram was updated (see Figure 23-1). The following registers were updated: * * * * * * * C1FSTAT (see Register 23-6) C1RXOVF (see Register 23-7) C1RXFn (see Register 23-14) C1FIFOCONn (see Register 23-16) C1FIFOINTn (see Register 23-17) C1FIFOUAn (see Register 23-18) C1FIFOCIn (see Register 23-19) The C1FLTCON4 through C1FLTCON7 registers were removed. 28.0 "Special Features" The virtual addresses for the Device Configuration Word registers were updated (see Table 28-1). 31.0 "40 MHz Electrical Characteristics" The EJTAG Timing Characteristics diagram was updated (see Figure 31-23). DS60001290E-page 376 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY Revision E (October 2017) In this revision, the Preliminary status was removed. 2014-2017 Microchip Technology Inc. DS60001290E-page 377 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY NOTES: DS60001290E-page 378 2014-2017 Microchip Technology Inc. PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under "Support", click on "Customer Change Notification" and follow the registration instructions. 2014-2017 Microchip Technology Inc. DS60001290E-page 379 PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC32 MX 1XX F 064 H T - 50 I / PT - XXX Example: PIC32MX170F512H-50I/PT: General Purpose PIC32, 32-bit RISC MCU, 512 KB program memory, 64-pin, Industrial temperature, TQFP package. Microchip Brand Architecture Product Groups Flash Memory Family Program Memory Size (KB) Pin Count Tape and Reel Flag (if applicable) Speed Temperature Range Package Pattern Flash Memory Family Architecture MX = 32-bit RISC MCU core Product Groups 1XX = General Purpose microcontroller family 2XX = USB microcontroller family 5XX = USB and CAN microcontroller family Flash Memory Family F = Flash program memory Program Memory Size 064 128 256 512 = 64 KB = 128 KB = 256 KB = 512 KB Pin Count H L = 64-pin = 100-pin 50 = 40 MHz (blank, no marking on package) = 50 MHz Temperature Range I V = -40C to +85C (Industrial) = -40C to +105C (V-Temp) Package PT PT PF MR = = = = Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample Speed 64-Lead (10x10x1 mm) TQFP (Thin Quad Flatpack) 100-Lead (12x12x1 mm) TQFP (Thin Quad Flatpack) 100-Lead (14x14x1 mm) TQFP (Thin Quad Flatpack) 64-Lead (9x9x0.9 mm) QFN (Plastic Quad Flat) 2014-2017 Microchip Technology Inc. DS60001290E-page 380 Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2014-2017 Microchip Technology Inc. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2014-2017, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. 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