1/20April 2004
■COMPLETE INTERFACE BETWEEN LNB
AND I2CTM BUS
■BUILT-IN DC/DC CONTROLLER FOR
SINGLE 12V SUPPLY OPERATION AND
HIGH EFFICIENCY (Typ. 94% @ 750mA)
■TWO SELECTABLE OUTPUT CURRENT
LIMIT (450mA / 750mA)
■BOTH COMPLIANT WITH EUTELSAT AND
DIRECT OUTPUT VOLTAGE
SPECIFICATION
■ACCURATE BUILT-IN 22KHz TONE
OSCILLATOR SUITS WIDELY ACCEPTED
STANDARDS
■FAST OSCILLATOR START-UP FACILITATES
DiSEqCTM ENCODING
■BUILT-IN 22KHz TONE DETECTOR
SUPPORTS BI-DIRECTIONAL DiSEqCTM2.0
■SEMI-LOWDROP POST REGULATOR AND
HIGH EFFICIENCY STEP-UP PWM FOR
LOW POWER LOSS: Typ. 0.56W @ 125mA
■TWO OUTPUT PINS SUITABLE TO BYPASS
THE OUTPUT R-L FILTER AND AVOID ANY
TONE DISTORSION (R-L FILTER AS PER
DiSEqC 2.0 SPECs, see application circuit on
pag. 5)
■CABLE LENGTH DIGITAL COMPENSATION
■OVERLOAD AND OVER-TEMPERATURE
INTERNAL PROTECTIONS
■OVERLOADANDOVER-TEMPERATUREI2C
DIAGNOSTIC BITs
■LNB SHORT CIRCUIT SOA PROTECTION
WITH I2C DIAGNOSTIC BIT
■+/- 4KV ESD TOLERANT ON INPUT/
OUTPUT POWER PINS
DESCRIPTION
Intended for analog and digital satellite STB
receivers/SatTV, sets/PC cards, the LNBH21 is a
monolithic voltage regulator and interface IC,
assembled in POWER SO-20, specifically
designed to provide the 13/18V power supply and
the 22KHz tone signalling to the LNB
downconverter in the antenna or to the multiswitch
box. In this application field, it offers a complete
solution with extremely low component count, low
power dissipation together with simple design and
I2CTM standard interfacing.
LNBH21
LNB SUPPLY AND CONTROL IC WITH
STEP-UP CONVERTER AND I2C INTERFACE
DSQIN
Enable
Preregul.+
U.V.lockout
+P.ON res.
V Select
Linear Post-reg
+Modulator
+Protections
Vup VoRX
SDA
SCL
Vcc
Diagnostics
I²C interf.
Tone
Detector
DSQOUT
VoTX
DETIN
LNBH21
Byp
Gate
Sense
EXTM
ADDR
22KHz
Oscill.
TEN
Vup-Feedback
Step-up PWM
Controller
ISEL
BLOCK DIAGRAM
PowerSO-20
LNBH21
2/20
ORDERING CODES
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not implied.
THERMAL DATA
PIN CONFIGUARATION (top view)
TYPE PowerSO-20
(Tube) PowerSO-20
(Tape & Reel)
LNBH21 LNBH21PD LNBH21PD-TR
Symbol Parameter Value Unit
VCC DC Input Voltage -0.3 to 16 V
VUP DC Input Voltage -0.3 to 25 V
IOOutput Current Internally Limited mA
VOTX/RX DC Output Pins Voltage -0.3 to 25 V
VILogic Input Voltage (SDA, SCL, DSQIN, ISEL) -0.3 to 7 V
VDETIN Detector Input Signal Amplitude -0.3 to 2 VPP
VOH Logic High Output Voltage (DSQOUT) -0.3 to 7 V
IGATE Gate Current ±400 mA
VSENSE Current Sense Voltage -0.3 to 1 V
VADDRESS Address Pin Voltage -0.3 to 7 V
Tstg Storage Temperature Range -40 to +150 °C
Top Operating Junction Temperature Range -40 to +125 °C
Symbol Parameter Value Unit
Rthj-case Thermal Resistance Junction-case 2°C/W
LNBH21
3/20
TABLE A: PIN CONFIGURATIONS
PIN N° SYMBOL NAME FUNCTION
18 VCC Supply Input 8V to 15V IC supply. A 220µF bypass capacitor to GND with a 470nF
(ceramic) in parallel is recommended
17 GATE External Switch Gate External MOS switch Gate connection of the step-up converter
16 SENSE Current Sense Input DC/DC Current Sense comparator input. Connected to current
sensing resistor
19 VUP Step-up Voltage Input of the linear post-regulator. The voltage on this pin is monitored
by internal step-ut controller to keep a minimum dropout across the
linear pass transistor
2V
ORX Output Port during
22KHz Tone RX RX Output to the LNB in DiSEqC 2.0 application. See truth tables for
voltage selections on page 8 and description on page 5.
12 SDA Serial Data Bidirectional data from/to I2C bus.
13 SCL Serial Clock Clock from I2C bus.
14 DSQIN DiSEqC Input When the TEN bit of the System Register is LOW, this pin will accept
the DiSEqC code from the main µcontroller. The LNBH21 will use this
code to modulate the internally generated 22kHz carrier. Set to GND
this pin if not used.
9 DETIN Tone Detector Input 22kHz Tone Detector Input. Must be AC coupled to the DiSEcQ 2.0
bus.
15 DSQOUT DiSEqC Output Open drain output of the tone Detector to the main µcontroller for
DiSEcQ 2.0 data decoding. It is LOW when tone is detected.
5 EXTM External Modulator External Modulation Input acts on VOTX. Needs DC decoupling to the
AC source. If not used, can be left open.
1, 6, 10,
11, 20 GND Ground Pins Connected to Ground.
8 BYP Bypass Capacitor Needed for internal preregulator filtering
3 ISEL Current Limit Select Set high or floating for Iout<=750mA, connect to ground for
IOUT ≤ 450mA.
4V
OTX Output Port during
22KHz Tone TX Output of the linear post-regulator/modulator to the LNB. See truth
tables for voltage selections.
7 ADDR Address Setting Four I2C bus addresses available by setting the Address Pin level
voltage. See address pin characteristics table.
LNBH21
4/20
TYPICAL APPLICATION CIRCUITS
Application Circuit for DiSEqC 1.x and Output Current < 450 mA
Full Application Circuit for Bi-directional DiSEqC 2.0 and Output Current up to 750mA
(*) Filter to be used according to EUTELSAT recommendation to implement the DiSEqCTM 2.0, (see DiSEqCTM implementation on page 8).
If bidirectional DiSEqCTM 2.0 is not implemented it can be removed both with C8 and D4.
(**) Do not leave these pins floating if not used.
(***) To be soldered as close as possible to relative pins.
-C8 and D3,4 are needed only to protect the output pins from any negative voltage spikes during high speed voltage transitions.
LNBH21
19
17
Vin
12V
L1=22µH 16
18
4
2
9
C8(***)
10nF
VoTX
SDA
SCL
15
DSQIN(**)
7
8
C5
470nF
GND
0<VADDR<VBYP
5
Rsc
0.1 Ω
ΩΩ
Ω
C3(***)
470nF
Ceramic
D1 1N4001
C1
220µF
C4(***)
470nF
Ceramic
D2(***)
BAT43
IC1
STS4DNFS30L
3
12
13
14
IC2
C2
220µF C9
100µF
Ferrite Bead Filter
F1
F1 suggested part number:
MURATA BL01RN1-A62
Panasonic EXCELS A35
EXTM
DSQOUT
(**) DETIN
VoRX
to LNB
ISEL
Byp
Tone Enable
Set TTX=1
SENSE
GATE
Vup
Address
LNBH21
19
17
Vin
12V
L1=22µH 16
18
4
2
9
C8(***)
10nF
VoTX
SDA
SCL
15
DSQIN(**)
7
8
C5
470nF
GND
0<VADDR<VBYP
5
Rsc
0.1 Ω
ΩΩ
Ω
C3(***)
470nF
Ceramic
D1 1N4001
C1
220µF
C4(***)
470nF
Ceramic
D2(***)
BAT43
IC1
STS4DNFS30L
3
12
13
14
IC2
C2
220µF
C2
220µF C9
100µF
Ferrite Bead Filter
F1
F1 suggested part number:
MURATA BL01RN1-A62
Panasonic EXCELS A35
EXTM
DSQOUT
(**) DETIN
VoRX
to LNB
ISEL
Byp
Tone Enable
Set TTX=1
SENSE
GATE
Vup
Address
22KHz Tone Enable
270µH
15 ohm
(*) see note
LNBH21
Vup
Gate
Vin
12V
L1=22µH Sense
Vcc
VoRX
VoTX
(**) DETIN
C7(***)
100nF
to LNB
SDA
SCL
DSQOUT
DSQIN (**)
ADDRESS
Byp
C5
470nF
GND
0<VADDR<VBYP
EXTM
C6
10nF
Rsc
0.05Ω
ΩΩ
Ω
C3(***)
470nF
Ceramic
D2 1N4001
C1
220µF C4(***)
470nF
Ceramic
D3(***)
BAT43
D1
1N5821 or
STPS3L40A
IC1
MOS
STN4NF03L
D4(***)
BAT43
C8(***)
100nF
ISEL
C2
220µF C9
100µF
F1
Axial Ferrite Bead Filter
F1 suggested part number:
MURATA BL01RN1-A62
Panasonic EXCELS A35
Higher current limit
Lower current limit
Floating or V>3.3V
GND
22KHz Tone Enable
270µH
15 ohm
(*) see note
LNBH21
Vup
Gate
Vin
12V
L1=22µH Sense
Vcc
VoRX
VoTX
(**) DETIN
C7(***)
100nF
to LNB
SDA
SCL
DSQOUT
DSQIN (**)
ADDRESS
Byp
C5
470nF
GND
0<VADDR<VBYP
EXTM
C6
10nF
Rsc
0.05Ω
ΩΩ
Ω
C3(***)
470nF
Ceramic
D2 1N4001
C1
220µF C4(***)
470nF
Ceramic
D3(***)
BAT43
D1
1N5821 or
STPS3L40A
IC1
MOS
STN4NF03L
D4(***)
BAT43
C8(***)
100nF
ISEL
C2
220µF C9
100µF
F1
Axial Ferrite Bead Filter
F1 suggested part number:
MURATA BL01RN1-A62
Panasonic EXCELS A35
Higher current limit
Lower current limit
Floating or V>3.3V
GND
270µH
15 ohm
(*) see note
LNBH21
Vup
Gate
Vin
12V
L1=22µH Sense
Vcc
VoRX
VoTX
(**) DETIN
C7(***)
100nF
to LNB
SDA
SCL
DSQOUT
DSQIN (**)
ADDRESS
Byp
C5
470nF
GND
0<VADDR<VBYP
0<VADDR<VBYP
EXTM
C6
10nF
Rsc
0.05Ω
ΩΩ
Ω
C3(***)
470nF
Ceramic
D2 1N4001
C1
220µF C4(***)
470nF
Ceramic
D3(***)
BAT43
D1
1N5821 or
STPS3L40A
IC1
MOS
STN4NF03L
D4(***)
BAT43
C8(***)
100nF
ISEL
C2
220µF
C2
220µF C9
100µF
F1
Axial Ferrite Bead Filter
F1 suggested part number:
MURATA BL01RN1-A62
Panasonic EXCELS A35
Axial Ferrite Bead Filter
F1 suggested part number:
MURATA BL01RN1-A62
Panasonic EXCELS A35
Higher current limit
Lower current limit
Floating or V>3.3V
GND
LNBH21
5/20
APPLICATION INFORMATION
This IC has a built in DC/DC step-up controller that, from a single supply source ranging from 8 to 15V,
generates the voltages (VUP) that let the linear post-regulator to work at a minimum dissipated power of
1.65W typ. @ 750mA load (the linear regulator drop voltage is internally kept at: VUP-VO=2.2V typ.). An
UnderVoltage Lockout circuit will disable the whole circuit when the supplied VCC drops below a fixed
threshold (6.7V typically). The internal 22KHz tone generator is factory trimmed in accordance to the
standards, and can be controlled either by the I2CTM interface or by a dedicated pin (DSQIN) that allows
immediate DiSEqCTM data encoding (*). When the TEN (Tone ENable) I2C bit it is set to HIGH, a
continuous 22KHz tone is generated on the output regardless of the DSQIN pin logic status.
The TEN bit must be set LOW when the DSQIN pin is used for DiSEqCTM encoding. The fully
bi-directional DiSEqCTM 2.0 interfacing is completed by the built-in 22KHz tone detector. Its input pin
(DETIN) must be AC coupled to the DiSEqCTM bus, and the extracted PWK data are available on the
DSQOUT pin (*).
To comply to the bi-directional DiSEqCTM 2.0 bus hardware requirements an output R-L filter is needed.
The LNBH21 is provided with two output pins: the VOTX to be used during the tone transmission and the
VORX to be used when the tone is received. This allows the 22KHz Tone to pass without any losses due
to the R-L filter impedance (see DiSeqC 2.0 application circuit on page 5). In DiSeqC 2.0 applications
during the 22KHz transmission activated by DSQIN pin (or TEN I2Cbit),theV
OTX pin must be
preventively set ON by the TTX I2C bit and, both the 13/18V power supply and the 22KHz tone, are
provided by mean of VOTX output. As soon as the tone transmission is expired, the VOTX must be set to
OFF by setting the TTX I2C bit to zero and the 13/18V power supply is provided to the LNB by the VORX
pin through the R-L filter. When the LNBH21 is used in DiSeqC 1.x applications the R-L filter is not
required (see DiSeqC 1.x application circuit on pag.5), the TTX I2C bit must be kept always to HIGH so
that, the VOTX output pin can provide both the 13/18V power supply and the 22KHz tone, enabled by
DSQIN pin or by TEN I2Cbit.
All the functions of this IC are controlled via I2C TM bus by writing 6 bits on the System Register (SR, 8
bits). The same register can be read back, and two bits will report the diagnostic status. When the IC is put
in Stand-by (EN bit LOW), the power blocks are disabled. When the regulator blocks are active (EN bit
HIGH), the output can be logic controlled to be 13 or 18 V by mean of the VSEL bit (Voltage SELect) for
remote controlling of non-DiSEqC LNBs.
Additionally, the LNBH21 is provided with the LLC I2C bit that increase the selected voltage value (+1V
when VSEL=0 and +1.5V when VSEL=1) to compensate for the excess voltage drop along the coaxial
cable (LLC bit HIGH).
By mean of the LLC bit, the LNBH21 is also compliant to the American LNB power supply standards that
require the higher output voltage level to 19.5V (typ.) (instead of 18V), by simply setting the LLC=1 when
VSEL=1.
In order to improve design flexibility and to allow implementation of newcoming LNB remote control
standards, an analogic modulation input pin is available (EXTM). An appropriate DC blocking capacitor
must be used to couple the modulating signal source to the EXTM pin. Also in this case, the VOTX output
must be set ON during the tone transmission by setting the TTX bit high. When external modulation is not
used, the relevant pin can be left open.
The current limitation block is SOA type and it is possible to select two current limit thresholds, by the
dedicated ISEL pin. The higher threshold is in the range of 750mA to 1A if the ISEL is left floating or
connected a voltage > 3.3V. The lower threshold is in the range of 450mA to 700mA when the ISEL pin is
connected to ground. When the output port is shorted to ground, the SOA current limitation block limits the
short circuit current (ISC) at typically 400mA or 200mA respectively for VO13V or 18V, to reduce the power
dissipation. Moreover, it is possible to set the Short Circuit Current protection either statically (simple
current clamp) or dynamically by the PCL bit of the I2C SR; when the PCL (Pulsed Current Limiting) bit is
set to LOW, the overcurrent protection circuit works dynamically, as soon as an overload is detected, the
output is shut-down for a time TOFF, typically 900ms. Simultaneously the OLF bit of the System Register
is set to HIGH. After this time has elapsed, the output is resumed for a time TON=1/10TOFF (typ.).Atthe
end of TON, if the overload is still detected, the protection circuit will cycle again through TOFF and TON.At
the end of a full TON in which no overload is detected, normal operation is resumed and the OLF bit is
resettoLOW.TypicalT
ON+TOFF time is 990ms and it is determined by an internal timer. This dynamic
operation can greatly reduce the power dissipation in short circuit condition, still ensuring excellent
power-on start up in most conditions.
LNBH21
6/20
However,there could be some cases in which an highly capacitive load on theoutputmay cause a difficult
start-up when the dynamic protection is chosen. This can be solved by initiating any power start-up in
static mode (PCL=HIGH) and then switching to the dynamic mode (PCL=LOW) after a chosen amount of
time. When in static mode, the OLF bit goes HIGH when the current clamp limit is reached and returns
LOW when the overload condition is cleared.
This IC is also protected against overheating: when the junction temperature exceeds 150°C (typ.), the
step-up converter and the linear regulator are shut off, and the OTF SR bit is set to HIGH. Normal
operation is resumed and the OTF bit is reset to LOW when the junction is cooled down to 140°C (typ.).
(*): External components are needed to comply to bi-directional DiSEqCTMbus hardware requirements. Full compliance of the whole appli-
cation with DiSEqCTM specifications is not implied by the use of this IC
I2C BUS INTERFACE
Data transmission from main µP to the LNBH21 and viceversa takes place through the 2 wires I2C bus
interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be
externally connected).
DATA VALIDITY
As shown in fig. 1, the data on the SDA line must be stable during the high period of the clock. The HIGH
and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
START AND STOP CONDITIONS
As shown in fig.2 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The
stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP conditions must
be sent before each START condition.
BYTE FORMAT
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge
bit. The MSB is transferred first.
ACKNOWLEDGE
The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig.
3). The peripheral (LNBH21) that acknowledges has to pull-down (LOW) the SDA line during the
acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The peripheral which
has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA
line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can
generate the STOP information in order to abort the transfer. The LNBH21 won't generate the
acknowledge if the VCC supply is below the Undervoltage Lockout threshold (6.7V typ.).
TRANSMISSION WITHOUT ACKNOWLEDGE
Avoiding to detect the acknowledge of the LNBH21, the µP can use a simpler transmission: simply it waits
one clock without checking the slave acknowledging, and sends the new data.
This approach of course is less protected from misworking and decreases the noise immunity.
Figure 1 : DATA VALIDITY ON THE I2CBUS
LNBH21
7/20
Figure 2 : TIMING DIAGRAM ON I2CBUS
Figure 3 : ACKNOWLEDGE ON I2CBUS
LNBH21 SOFTWARE DESCRIPTION
INTERFACE PROTOCOL
The interface protocol comprises:
- A start condition (S)
- A chip address byte = hex 10 / 11 (the LSB bit determines read(=1)/write(=0) transmission)
- A sequence of data (1 byte + acknowledge)
- A stop condition (P)
ACK= Acknowledge; S = Start ; P = Stop; R/W = Read/Write
SYSTEM REGISTER (SR, 1 BYTE)
R,W = read and write bit; R = Read-only bit
All bits reset to 0 at Power-On
CHIP ADDRESS DATA
MSB LSB MSB LSB
S0001000R/WACK ACKP
MSB LSB
R, W R, W R, W R, W R, W R, W R R
PCL TTX TEN LLC VSEL EN OTF OLF
LNBH21
8/20
TRANSMITTED DATA (I2C BUS WRITE MODE)
When the R/W bit in the chip address is setto 0, the main µP can write on the System Register (SR) of the
LNBH21 via I2C bus. Only 6 bits out of the 8 available can be written by the µP, since the remaining 2 are
left to the diagnostic flags, and are read-only.
X= don't care.
Values are typical unless otherwise specified
RECEIVED DATA (I2C bus READ MODE)
The LNBH21 canprovide to the Master a copy ofthe SYSTEM REGISTER information via I2C bus in read
mode. The read mode is Master activated by sending the chip address with R/W bit set to 1. At the
following master generated clocks bits, the LNBH21 issues a byte on the SDA data bus line (MSB
transmitted first).
At the ninth clock bit the MCU master can:
- acknowledge the reception, starting in this way the transmission of another byte from the LNBH21;
- no acknowledge, stopping the read mode communication.
While the whole register is read back by the µP, only the two read-only bits OLF and OTF convey
diagnostic informations about the LNBH21.
Values are typical unless otherwise specified.
Values are typical unless otherwise specified
POWER-ON I2C INTERFACE RESET
The I2C interface built in the LNBH21 is automatically reset at power-on. As long as the VCC stays below
the UnderVoltage Lockout threshold (6.7V typ.), the interface will not respond to any I2C command and
the System Register (SR) is initialized to all zeroes, thus keeping the power blocks disabled. Once the
VCC rises above 7.3V typ, the I2C interface becomes operative and the SR can be configured by the main
µP. This is due to 500mV of hysteresis provided in the UVL threshold to avoid false retriggering of the
Power-On reset circuit.
ADDRESS PIN
Connecting this pin to GND the Chip I2C interface address is 0001000, but, it is possible to choice among
4 different addresses simply setting this pin at 4 fixed voltage levels (see table on page 10).
PCL TTX TEN LLC VSEL EN OTF OLF Function
001XX
VO=13.25V,V
UP = 15.25 V
011XX
VO=18V,V
UP=20 V
101XX
VO=14.25V,V
UP = 16.25 V
111XX
VO=19.5V,V
UP =21.5V
0 1 X X 22KHz is controlled by DSQIN pin
1 1 X X 22KHz tone is ON, DSQIN pin disabled
01XX
VORX output is ON, output voltage controlled by VSEL and
LLC
1X 1XX
VOTX output is ON, 22KHz controlled by DSQIN or TEN,
output voltage level controlled by VSEL and LLC
0 1 X X Pulsed (dynamic) current limiting is selected
1 1 X X Static current limiting is selected
XXXXX0XXPowerblocksdisabled
PCL TTX TEN LLC VSEL EN OTF OLF Function
These bits are read exactly the same as
they were left after last write operation
0TJ<140°C, normal operation
1TJ>150°C, power block disabled
0IOUT<IOMAX, normal operation
1IOUT>IOMAX, overload protection triggered
LNBH21
9/20
DiSEqCTM IMPLEMENTATION
The LNBH21 helps the system designer to implement the bi-directional (2.0) DiSEqC protocol by allowing
an easy PWK modulation/demodulation of the 22KHz carrier. The PWK data are exchanged between the
LNBH21 and the main µP using logic levels that are compatible with both 3.3 and 5V microcontrollers.
This data exchange is made through two dedicated pins, DSQIN and DSQOUT, in order to maintain the
timing relationships between the PWK data and the PWK modulation as accurate as possible. These two
pins should be directly connected to two I/O pins of the µP, thus leaving to the resident firmware the task
of encoding and decoding the PWK data in accordance to the DiSEqC protocol. Full compliance of the
system to the specificationis thus not implied by thebare useofthe LNBH21. The system designer should
also take in consideration the bus hardware requirements; that can be simply accomplished by the R-L
termination connected on the VOpins of the LNBH21, as shown in the Typical Application Circuit on page
4. To avoid any losses due to the R-L impedance during the tone transmission, the LNBH21 has
dedicated output (VOTX) that, in a DiSEqC 2.0 application, is connected after the filter and must be
enabled by setting the TTX SR bit HIGH only during the tone transmission (see DiSEqC 2.O operation
description on page 2).
Unidirectional (1.x) DiSEqC andnon-DiSEqC systems normally don't need this termination, and the VOTX
pin can be directly connected to the LNB supply port of the Tuner (see DiSeqC 1.x application circuit on
pag.4). There is also no need of Tone Decoding, thus DETIN and DSQOUT pins can be left unconnected
and the Tone is provided by the VOTX.
LNBH21
10/20
ELECTRICAL CHARACTERISTICS FOR LNBP SERIES (TJ= 0 to 85°C, EN=1, TTX=0/1,DSQIN=LOW,
LLC=TEN=PCL=VSEL=0, VIN=12V, IO=50mA, unless otherwise specified. See software description
section for I2C access to the system register).
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VIN Supply Voltage IO= 750 mA TEN=VSEL=LLC=1 8 15 V
IISupply Current EN=TEN=VSEL=LLC=1, NO LOAD 20 40 mA
EN=0 3.5 7
VOOutput Voltage IO= 750 mA VSEL=1 LLC=0 17.3 18 18.7 V
LLC=1 18.7 19.5 20.3
VOOutput Voltage IO= 750 mA VSEL=0 LLC=0 12.75 13.25 13.75 V
LLC=1 13.75 14.25 14.75
∆VOLine Regulation VIN1= 8 to 15V VSEL=0 5 40 mV
VSEL=1 5 60
∆VOLoad Regulation VSEL=0 or 1, IO= 50 to 750mA 200 mV
IMAX Output Current Limiting ISEL = Floating or V > 3.3V 750 1000 mA
ISEL = GND 450 700
ISC Output Short Circuit Current VSEL=0 300 mA
VSEL=1 200
tOFF Dynamic Overload
protection OFF Time PCL=0 Output Shorted 900 ms
tON Dynamic Overload
protection ON Time PCL=0 Output Shorted tOFF/10 ms
fTONE Tone Frequency TEN=1 20 22 24 KHz
ATONE Tone Amplitude TEN=1 0.55 0.72 0.9 VPP
DTONE Tone Duty Cycle TEN=1 40 50 60 %
tr,t
fTone Rise and Fall Time TEN=1 5 8 15 µs
GEXTM External Modulation Gain ∆VOUT/∆VEXTM, f = 10Hz to 50KHz 6
VEXTM External Input Voltage AC Coupling 400 mVPP
ZEXTM External Modulation
Impedance f = 10Hz to 50KHz 260 Ω
fSW DC/DC ConverterSwitching
Frequency 220 kHz
fDETIN Tone Detector Frequency
Capture Range 0.4Vpp sinewave 18 24 kHz
VDETIN Tone Detector Input
Amplitude fIN=22kHz sinewave 0.2 1.5 VPP
ZDETIN Tone Detector Input
Impedance 150 kΩ
VOL DSQOUT Pin Logic LOW Tone present IOL=2mA 0.3 0.5 V
IOZ DSQOUT Pin Leakage
Current Tone absent VOH =6V 10 µA
VIL DSQIN Input Pin Logic
LOW 0.8 V
VIH DSQIN Input Pin Logic
HIGH 2V
IIH DSQIN Pins Input Current VIH =5V 15 µA
IOBK Output Backward Current EN=0, VOBK = 18V -6 -15 mA
TSHDN Temperature Shutdown
Threshold 150 °C
∆TSHDN Temperature Shutdown
Hysteresis 15 °C
LNBH21
11/20
GATE AND SENSE ELECTRICAL CHARACTERISTICS (TJ= 0 to 85°C, VIN = 12V)
I2C ELECTRICAL CHARACTERISTICS (TJ=0to85°C,V
I= 12V)
ADDRESS PIN CHARACTERISTICS (TJ= 0 to 85°C, VIN=12V)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
RDSON-L Gate LOW RDSON IGATE= -100mA 4.5 Ω
RDSON-H Gate HIGH RDSON IGATE= 100mA 4.5 Ω
VSENSE Current Limit Sense Voltage 200 mV
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VIL LOW Level Input Voltage SDA, SCL 0.8 V
VIH HIGH Level Input Voltage SDA, SCL 2 V
IIInput Current SDA, SCL, VI= 0.4 to 4.5V -10 10 µA
VOL Low Level Output Voltage SDA (open drain), IOL =6mA 0.6 V
fMAX Maximum Clock Frequency SCL 500 KHz
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VADDR-1 "0001000" Addr Pin Voltage 0 0.7 V
VADDR-2 "0001001" Addr Pin Voltage 1.3 1.7 V
VADDR-3 "0001010" Addr Pin Voltage 2.3 2.7 V
VADDR-4 "0001011" Addr Pin Voltage 3.3 5 V
LNBH21
12/20
THERMAL DESIGN NOTES
During normal operation, the LNBH21 device dissipates some power. At maximum rated output current
(750mA), the voltage drop on the linear regulator lead to a total dissipated power that is typically 1.65W.
The heat generated requires a suitable heatsink to keep the junction temperature below the over
temperature protection threshold. Assuming a 45°C temperature inside the Set-Top-Box case, the total
Rthj-amb has to be less than 48°C/W.
While this can be easily achieved using a through-hole power package that can be attached to a small
heatsink or to the metallic frame of the receiver, a surface mount power package must rely on PCB
solutions whose thermal efficiency is often limited. The simplest solution is to use a large, continuous
copper area of the GND layer to dissipate the heat coming from the IC body.
GivenanR
thj-case equal to 2°C/W, a maximum of 46°C/W are left to the PCB heatsink. This figure is
achieved if a minimum of 6.5cm2copper area is placed just below the IC body. This area can be the inner
GND layer of a multi-layer PCB, or, in a dual layer PCB, an unbroken GND area even on the oppositeside
where the IC is placed. In figure 4, it is shown a suggested layout for the PSO-20 package with a dual
layer PCB, where the IC exposed pad connected to GND and the square dissipating area are thermally
connected through 32 vias holes, filled by solder. Thisarrangement, when L=25mm, achieves an Rthc-amb
of about 32°C/W.
Different layouts are possible, too. Basic principles, however, suggest to keep the IC and its ground
exposed pad approximately in the middle of the dissipating area; to provide as many vias as possible; to
design a dissipating area having a shape as square as possible and not interrupted by other copper
traces.
Figure 4 : PowerSO-20 SUGGESTED PCB HEATSINK LAYOUT
LNBH21
13/20
TYPICAL CHARACTERISTICS (unless otherwise specified Tj=25°C)
Figure 5 : Output Voltage vs Temperature
Figure 6 : Output Voltage vs Temperature
Figure 7 : Output Voltage vs Temperature
Figure 8 : Load Regulation vs Temperature
Figure 9 : Load Regulation vs Temperature
Figure 10 : Supply Current vs Temperature
LNBH21
14/20
Figure 11 : Supply Current vs Temperature
Figure 12 : Supply Current vs Temperature
Figure 13 : Dynamic Overload Protection ON
Time vs Temperature
Figure 14 : Dynamic Overload Protection OFF
Time vs Temperature
Figure 15 : Output Current Limiting vs
Temperature
Figure 16 : Output Current Limiting vs
Temperature
LNBH21
15/20
Figure 17 : Tone Frequency vs Temperature
Figure 18 : Tone Amplitude vs Temperature
Figure 19 : Tone Duty Cycle vs Temperature
Figure 20 : Tone Rise Time vs Temperature
Figure 21 : Tone Fall Time vs Temperature
Figure 22 : Undervoltage Lockout Threshold vs
Temperature
LNBH21
16/20
Figure 23 : Output Backward Current vs
Temperature
Figure 24 : DC/DC Converter Efficiency vs
Temperature
Figure 25 : Current Limit Sense Voltage vs
Temperature
Figure 26 : 22kHz Tone Waveform
Figure 27 : DSQIN Tone Enable Transient
Response
Figure 28 : DSQIN Tone Enable Transient
Response
VCC=12V, IO=50mA, EN=TEN=1
VCC=12V, IO=50mA, EN=1, Tone enabled by DSQIN Pin
VCC=12V, IO=50mA, EN=1, Tone enabled by DSQIN Pin
LNBH21
17/20
Figure 29 : DSQIN Tone Disable Transient
Response
VCC=12V, IO=50mA, EN=1, Tone enabled by DSQIN Pin
LNBH21
18/20
DIM. mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 3.60 0.1417
a1 0.10 0.30 0.0039 0.0118
a2 3.30 0.1299
a3 0 0.10 0 0.0039
b 0.40 0.53 0.0157 0.0209
c 0.23 0.32 0.0090 0.0013
D (1) 15.80 16.00 0.6220 0.630
E 13.90 14.50 0.5472 0.5710
e 1.27 0.0500
e3 11.43 0.4500
E1 (1) 10.90 11.10 0.4291 0.4370
E2 2.90 0.1141
G 0 0.10 0.0000 0.0039
h 1.10 0.0433
L 0.80 1.10 0.0314 0.0433
N
0˚
10˚
S0˚ 8˚0˚ 8˚
T 10.0 0.3937
PowerSO-20 MECHANICAL DATA
0056635
e
a2 A
E
a1
PSO20MEC
DETAIL A
T
D
110
1120
E1
E2
h x 45˚
DETAIL A
lead
slug
a3
S
Gage Plane 0.35
L
DETAIL B
R
DETAIL B
(COPLANARITY)
GC
-C-
SEATING PLANE
e3
b
c
NN
(1) “D and E1” do not include mold flash or protusions - Mold flash or protusions shall not exceed 0.15mm (0.006”)
1
LNBH21
19/20
DIM. mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 330 12.992
C 12.8 13.2 0.504 0.519
D 20.2 0.795
N 60 2.362
T 30.4 1.197
Ao 15.1 15.3 0.594 0.602
Bo 16.5 16.7 0.650 0.658
Ko 3.8 4.0 0.149 0.157
Po 3.9 4.1 0.153 0.161
P 23.9 24.1 0.941 0.949
W 23.7 24.3 0.933 0.957
Tape & Reel PowerSO-20 MECHANICAL DATA
LNBH21
20/20
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
conseq uences of use o f suc h info rmat ion n or for any in fringeme nt of paten ts or oth er righ ts of third part ies whic h may resul t from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
All other names are the property of their respective owners
© 2004 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.
http://www.st.com
