ICS1572M-301 - Integrated Device Technology

ICS1572-101 Pinout

ICS1572-301 Pinout

CRYSTAL

OSCILLATOR / R PHASE-

FREQUENCY

DETECTOR

CHARGE

PUMP

LOOP

FILTER

VCO

PRESCALER

/ A

/ M

MUX

/ 2

/ 4

/ N1 MUX DRIVER

DIFF.

OUTPUT

DRIVER

/ N2

PROGRAMMING

INTERFACE

CLK+

CLK−

LOAD

LD/N2

XTAL1

XTAL2

FEEDBACK DIVIDER

EXTFBK

BLANK (-30 1 only)







N.C. 1 20 N.C.

AD0 2 19 AD1

XTAL1 3 18 AD2

XTAL2 4 17 VDD

STROBE 5 16 VDD

VSS 6 15 VDDO

VSS 7 14 IPRG

LOAD 8 13 CLK+

LD/N2 9 12 CLK-

N.C. 10 11 N.C.

Description

The ICS1572 is a high performance monolithic phase-locked

loop (PLL) frequency synthesizer. Utilizing ICS’s advanced

CMOS mixed-mode technology, the ICS1572 provides a low

cost solution for high-end video clock generation in worksta-

tions a nd hi gh-e nd PC ap p li cat ion s.

The ICS1572 has differential video clock outputs (CLK+ and

CLK-) that are compatible with industry standard video DACs.

Anot her c lo ck output , LOAD, is p rovi de d wh ose fre quenc y is

derived from the main clock by a programmable divider. An

additional clock output is available, LD/N2, which is derived

from the LOAD frequency and whose modulus may also be

programmed.

Operating frequencies are fully programmable with direct con-

trol provided for reference divider, pre-scaler , feedback divider

and post -scal er.

Reset of the pipeline delay on Brooktree RAMDACs may

be performed under register control. Outputs may a lso be set

to desired states to facilitate circuit board testing.

Features

•Supports high-resolution graphics - CLK output to

180 MHz

•El iminate s nee d for mu ltip le ECL o utpu t crys tal osci lla tors

•Fully programmable synthesizer capability - not just a

cl ock mu ltiplier

•Avail able in 2 0-pin 300 -mil wi de body SOI C package

•Available in both parallel (101) and serial (301)

programming versions

•Circuit included for reset of Brooktree RAMDAC pipeline

delay

Applications

•Workstations

•AutoCa d Ac cel er ators

•Hig h-e nd PC gr ap hic s syste ms

User Programmable Differential Output Graphics Clock Generator

ICS1572

Figure 1

ICS1572RevC093094 RAMDAC is a trademark of Brooktree Corporation.

Integrated

Circuit

S y stems, Inc.

N.C. 1 20 N.C.

AD0 2 19 AD1

XTAL1 3 18 AD2

XTAL2 4 17 VDD

STROBE 5 16 VDD

VSS 6 15 VDDO

VSS 7 14 IPRG

LOAD 8 13 CLK+

LD/N2 9 12 CLK-

N.C. 10 11 N.C.

DATA SHEET

ICS1572

IDT™ / ICS™ User Programmable Differential Output Graphics Clock Generator ICS1572

User Programmable Differential

Output Graphics Clock Generator

Overview

The ICS1572 is ideally suited to provide the graphics system

clock signals required by high-performance video DACs.

Ful ly pr ogram m able fe edba ck a nd r efer en ce di vi de r cap ab ilit y

allow virtually any frequency to be generated, not just simple

multiples of the reference frequency. The ICS1572 uses the

latest ge nerati on of frequency synthesis techniques develope d

by ICS and is completely suitable for the most demanding

vi de o applic at ion s.

PLL Synthesizer Description -

Ratiometric Mode

The ICS1572 generates its output frequencies using phase-

locked loop techniques. The phase-locked loop (or PLL) is a

closed-loop feedback system that drives the output frequency

to be ratiometrically related to the reference frequency pro-

vided to the PLL (see Figure 1). The reference frequency is

generated by an on-chip crystal oscillator or the reference

frequency may be applied to the ICS1572 from an external

frequency source.

The phase-frequency detector shown in the block diagram

drives the voltage-controlled oscillator , or VCO, to a frequency

that will cause the two inputs to the phase-frequency detector

to be ma tc hed in fre quency a nd phase. T hi s occurs when:

F(XTAL1) . Fe edback Di vider

F(VCO): = Refere nce Divide r

This expression is exact; that is, the accuracy of the output

fre quen cy de pends sole ly on t he re fere nce freq uenc y provi de d

to the part (assuming correctly programmed dividers).

The VCO gain is programmable , which permits the ICS1572 to

be optimized for be st performanc e at all operating frequencies.

The reference divider may be programmed for any modulus

fro m 1 t o 128 in steps of one .

The feedback divider may be programmed for any modulus

fro m 37 throug h 391 in steps of one. Any eve n mo dul us from

392 through 782 can also be achieved by setting the “double”

bit whic h double s the fe edba ck di vider modul us. The fee dback

divider makes use of a dual-modulus prescaler technique tha t

allows the programmable counters to operate at low speed

without sacrificing resolution. This is an improvement over

conventional fixed prescaler architectures that typically im-

pose a facto r -of- four penal ty (or lar ger) in this respect .

T able 1 perm its the derivation of “A” & “M” counter program-

ming d ire c tl y from desi r ed mod ulus.

PLL Post-Scaler

A programmable post-scaler may be inserted between the VCO

and the CLK+ and CLK- outputs of the ICS1572. This is useful

in generating of lower frequencies, as the VCO has been

opt imi zed fo r hig h-fr eq ue nc y ope ra tion.

The post-scaler allows the selection of:

•VCO fre que nc y

•VCO fre que nc y di vi ded by 2

•VCO fre que nc y di vi ded by 4

•Inter na l regi ster bit (AUXCL K) va lue

Load Clock Divider

The ICS1572 has an additional programmable divider

(referred to in Figure 1 as the N1 divider) that is used to

generate the LOAD clock freque ncy for t he video DAC. The

modulus of this div ider may be set t o 3, 4, 5, 6, 8, or 10 un de r

duty factor to be 50/50, even when an odd modulus is selected.

The input frequency to this divider is the output of the PLL

post-scaler described above.

Digital Inputs - ICS1572-101 Option

The AD0-AD3 pins and the STROBE pin are used to load all

cont rol re gist ers of t he ICS1572 (-101 option). The AD0- AD3

and STROBE pins ar e each equipped with a pull-up and wil l

be at a logic HIGH level when not connected. They may be

dri ven wit h sta nda rd TTL or CMOS log ic fam il ies.

The address of the register to be loaded is latched from the

AD0-AD3 pins by a negat ive e dge on the STROBE pin . Th e

data for that register is l atched from the AD0-AD3 pins by a

positive edge on the STROBE pin. See Figure 2 for a timing

diag ra m. After power-up, th e ICS1572-101 requires 32 re gis-

ter writes for new programming to become effective. Since

onl y 13 registe rs are used at present, the program ming syste m

can perform 19 “dummy” writes to address 13 or 14 to com-

p lete the se q ue nce.

ICS1572

User Programmable Differential Output Graphics Clock Generator TSD

IDT™ / ICS™ User Programmable Differential Output Graphics Clock Generator ICS1572

Digital Inputs - ICS1572-301 Option

The programming of the ICS1572-301 is performed serially

by using the DATCLK, DATA, and HOLD~pins to load an

internal shift register.

DATA is shifted into the register on the rising edge of

DATCL K. T he log ic va lue on the HOL D~ pi n is la tc hed a t the

same time. When HOLD~ is low, the shift register may be

loaded without disturbing the operation of the ICS1572. When

high, the shift register outputs are transferred to the control

registers, and the new programming information becomes ac-

tive . Ordina rily, a high le ve l should be plac e d on th e HOLD~

pin when the last data bit is presented. See Figure 3 for the

pro gra m ming sequenc e .

An addit ional control pin on the ICS1572-301, BLANK can

perform either of two functions. It may be used to disable the

pha se-fre quen cy det ect or in li ne-l oc ked app lica tion s. Alter na-

tively, t h e BLANK pin may be used as a synchronous enable

for VRAM shift clock generation. See sections on Line-Locked

Opera tions a nd VRAM shif t clock gen erat ion for detail s.

Output Description

The differential output drivers, CLK+ and CLK, are current-

mode and are designed to drive resistive terminations in a

complem entary fashion. The outputs are current-sinking only,

with the amount of sink current programmable via the IPRG

pin. The sink current, which is steered to either CLK+ or CLK-,

is approximately four times the current suppli ed to the IPRG

pin. For most appl ications, a resist or from VDDO to I PRG will

set the current to the necessary precision. See Figure 6 for

out put character istics.

The LOAD output is a high-current CMOS type drive whose

frequency is controlled by a programmable divider that may be

selected for a modulus of 3, 4, 5, 6, 8, or 10. It may also be

suppr esse d under re gi ste r cont rol .

The LD/N2 output is high-current CMOS type drive whose

frequ ency is de rived fro m t he LOAD output . The progr amm a-

bl e modu lus m ay r an ge f rom 1 to 512 in steps of on e.

Pipeline Delay Reset Function

The ICS1572 implements the clocking sequence required to

reset the pipeline delay on Brooktree RAMDACs. This se-

quence can be generated by setting th e appropriate register bit

(DACRST) to a logic 1 and then resetting to logic 0.

When changing frequencies, it is advisable to a llow 500 mi-

croseconds after the new frequency is selected to activat e the

re set functi on. The out put frequency of the s y nthesizer sh ould

be stable enough at th at point for the video DAC to correct ly

execut e its reset sequence. See Figure 4 for a diagram of the

pipeline delay reset sequence.

This all ows the synth esize r to be com ple t ely programme d for

the desired frequency before it is made active. Once the part

has bee n “u nlo ck ed ” by the 32 write s, progr am min g be co me s

effect ive imm e di at e ly.

ALL registers identifi ed in the data sheet (0-9, 11, 12 & 15)

MUST be written upon initial programming. The programming

registers are not initialized upon power-up, but the latched

outputs of those registers are. The latch is made transparent

afte r 32 register writes. If any register has not been written, the

state upon power-up (random) will become effective. Registers

13 & 14 physically do not exi st. Re gi ste r 10 doe s exi st , but is

reserved for future expansion. To insure compatibility with

possible future modifications to the database, ICS recommends

that all thre e u nuse d loca tions be writ ten wi th ze ro.

Figure 2

DATCLK

DATA

HOLD

DATA_1 DATA_2 DATA_56

ICS1572-301 Register Loading

Figure 3

Pipeline Delay Reset Timing

STROBE

DATCLK

CLK+

LOAD

9 11

TCLK

Figure 4

DATA VALIDADDRESS VALID

AD0-AD3

STROBE

ICS1572-101 Register Loading

ICS1572

User Programmable Differential Output Graphics Clock Generator TSD

IDT™ / ICS™ User Programmable Differential Output Graphics Clock Generator ICS1572

Reference Oscillator and Crystal

Selection

The ICS1572 has circuitry on-board to implement a Pierce

osc il la tor wi th t he ad dit ion of only one exte rn al co mp onent, a

quartz crystal. Pierce oscillators operate the crystal in anti-

(also called parallel-) resonant mode. See the AC Charac-

teristics for the effective capacitive loading to specify when

or deri ng cr ysta l s.

Series-resonan t crystals may also be used with the ICS1572.

Be aware that the oscillati on f requency will be slightly higher

than the frequency that is stamped on the can (typically 0.025-

0.05%).

As th e e nt ire op erat io n o f t he ph ase -lo cked l oop d epen ds on

having a stable referenc e frequency, we recommend that the

crysta l be mounted a s clo sely a s possibl e to t he package . Avoid

routing digital signals or the ICS1572 outputs underneath or

near these traces. It is also des irable to ground the crystal can

to the ground plan e, if pos sible.

If an exte rnal refe renc e fr eque ncy sour ce is to be used wit h the

ICS1572, it is important that it be jitter-free. The rising and

fall in g edge s of t ha t sig na l should b e fast a nd f re e of n oise fo r

be st re sult s.

The loop phase is locked to the falling edges of the XTAL1

input signals.

Line-Locked Operation

The ICS1572 supports line-locked clock applications by al-

lowing the LOAD (N1) and N2 divider chains to act as the

fe e dba c k div ide r fo r the PL L.

The N1 and N2 d ivide r cha in s al low a muc h lar ger modul us to

be achieved than the PLL ’s own feedback divider. Additionally,

the output of the N2 counter is accessibl e off-chip for perfo rm-

ing horizontal reset of the graphics system, where necessary.

This mode is set under register control (ALTLOOP bit). Th e

re fe renc e di vid er (R co unt er) is set to di vid e by 1 in thi s mode ,

and the HSYNC s ignal of t he externa l vi deo wi ll be supp lied

to the XTAL1 input. The output frequency of the synth esizer

wi ll t hen be:

F(CLK) : = F (XTAL1) . N1 . N2.

By using the phase-detector hardware dis able mode, the PLL

can be m ade t o f ree- run a t the be gin nin g o f t he v er ti cal in ter v a l

of the external video, and ca n be reactiva te d a t i ts com ple tion.

ICS1572-101 The ICS1572-101 supports phase detector

disable via a special control mode. When the

PDRSTE N (p ha se dete ctor rese t enab le ) bit is

set, a high level on AD3 will disable PLL

locking.

ICS1572-301 The ICS1572-301 supports phase detector

disable via the BLANK pin. When the

PDRSTEN bit is set, a high level on the

BLANK inp ut wi ll disa ble PL L locki ng.

External Feedback Operation

The ICS1572-301 option also supports the inclusion of an

exte rnal co unter as the fe edba ck div ider o f th e PLL. This m ode

is useful in graphic systems that must be “genlocked” to

extern al video sources.

Whe n the EXTFBEN bi t is set to logi c 1, the ph ase -fr eq ue nc y

detector will use the EXTFBK pin as its f eedback input. The

loop phase will be locked to the rising edges of the signal

appl ie d to t he EXT FBK input .

VRAM Shift Clock Generation

The ICS1572-301 option supports VRAM shift clock genera-

tion and interruption. By programming the N2 counter to divide

by 1, the LD/N2 output becomes a duplicate of the LOAD

output. When the SCEN bit is set, the LD/N2 output may be

synchronously started and stopped via the blank pin. When

BL ANK is high, the LD/ N2 wil l be fre e -run nin g an d in ph ase

with LOAD. When BLANK is taken l ow , the LD/ N2 output is

stopped at a low level. See Figure 5 for a diagram of the

sequence. Note that this use of the BLANK pin precludes its use

for phase comparator disabl e (see Line-Lock ed O pera tion).

VRAM Shift Clock Control

BLANK

LOAD

LD/N2

Figure 5

ICS1572

User Programmable Differential Output Graphics Clock Generator TSD

IDT™ / ICS™ User Programmable Differential Output Graphics Clock Generator ICS1572

Power-On Initialization

The ICS1572 has an internal power-on reset circuit that per-

for ms the fo llowin g func t ion s:

1) Set s the mu lt iplexe r to pass the re ference frequency

to the C LK+ a nd CL K- out put s.

2) Sele ct s the mo dul us of the N1 di vid er (for t he

LOAD clo ck) to be four.

These functions should allow initialization of most graphics

system s tha t can not immedi ately prov ide for register program -

ming upon system power-up.

Bec ause the powe r -o n reset circ uit is on th e VDD supply, and

be cause that supply is filtered, care must be taken to a llow the

reset to de-assert before programming. A safe guideline is to

all ow 20 mic rose c onds a fter the VDD supply r eac he s 4 vol ts.

Programming Note s

•VCO Frequency R ange: Use the post-div ider to ke ep the

VCO frequency as high as possible within its operating

range.

•Div ide r Ra nge: For be st result s in norm al si tu at ions (i.e. ,

pi xel cloc k gene ra ti on for hi-re s d isplay s), ke ep t he refe r-

enc e di vi der m od ulus as short a s p os si ble (for a f reque nc y

at the output of the refe rence divider in the few hundred

kHz to several MHz range). If you need to go to a lower

phase comparator reference frequency (usually required

for incr ea se d freq uency accuracy), that is acceptable, but

jit ter perfo rm an ce wil l suffer some wha t.

•VCO Gain Programming: Use the minimum gain which

can reliably achieve the VCO frequ ency d esired, as shown

here:

VCO GAIN MAX FREQUENCY

4 1 20 MH z

5 2 00 MH z

6 2 30 MH z

* SPECIAL APPL ICATION. Co ntact factory fo r custom produ ct ab ove

230 MHz.

•Pha se Detec tor Gain : For most gra phics appl ica ti ons and

divider ranges, set P[1,0] = 10 and set P[2] = 1. Under

some circumstanc es, set ting the P[2] bit “on” can reduc e

jitter. During 1572 operation at exact multiples of the

crysta l fre quency, P[2] bit = 0 may provide the best jitter

performance.

Board Test Support

It is often desirable to stati cally co ntrol the leve ls of the output

pi ns for ci rc ui t b oa rd t e st . T he ICS1572 su ppor ts this throug h

a register programmable mode, AUXEN. When this mode is

set, two register bits directly control the logic levels of the

CLK+/ CLK- pins and the LOAD pin. This mode is ac tiva ted

when the S[0] and S[1] bits are both set to logic 1. See Register

Ma ppi ng for deta il s.

Power Supplies and Decoupling

The ICS1572 has two VSS pins to reduce the effects of package

inductance. Both pins are connected to the same potential on

the die (the ground bus). BOTH of these pins should connect

to the ground plane of the video board as close to the package

as is possible.

The ICS1572 has a VDDO pin which is the supply of +5 volt

power to all output drivers. This pin should be connected to the

power plane (or bus) using standard high-frequency decou-

pling practice. That is, capacitors should have low series induc-

ta nc e an d be mounte d c lo se to t he ICS1572.

The VDD pin is the po wer suppl y pin for the PLL synthe siz er

circuitry a n d ot her lower current digit al func tions. We recom -

mend that RC decoupling or zener regul ation be provided for

t his p in (as shown in the recommende d application circuit ry).

This will allow the PLL to “track” through power supply

fluctuations without visible effects. See Figure 7 for typical

external circui try.

Figure 6

ICS1572

User Programmable Differential Output Graphics Clock Generator TSD

IDT™ / ICS™ User Programmable Differential Output Graphics Clock Generator ICS1572

1 N.C. N.C 20

2AD0 AD1 19

3XTAL1 AD2 18

4XTAL2 AD3 17

5 STROBE VDD 16

6 VSS VDDO 15

7 VSS IPRG 14

8LOAD CLK+ 13

9 LD/N2 CLK- 12

10 N.C. N.C. 11

+5V

RAMDAC

120

390390

DATA BUS









SELECT

Figure 3

ICS1572 Typical Interface

ICS1572

User Programmable Differential Output Graphics Clock Generator TSD

IDT™ / ICS™ User Programmable Differential Output Graphics Clock Generator ICS1572

NOTE: IT IS NOT NECESSARY TO UNDERSTAND THE FUNCTION OF THESE BITS TO USE THE ICS1572. PC SOFTWARE IS AVAILABLE

FROM ICS TO AUTOMATICALLY GENERATE ALL REGISTER VALUES BASED ON REQUIREMENTS. CONTACT FACTORY FOR DETAILS.

REG# BIT(S) BIT REF. DESCRIPTION

0 0-3 R[0] ..R[ 3] Refe re nc e divi de r modul us con tro l bits

1 0-2 R[4]..R[ 6] Modul us = value + 1

2 0-3 A[0]..A[3] Cont rols A coun te r. When set to zero, mo dulus=7. Otherwise,

mo dul us=7 for “ va lue ” underflows of the pre sca ler, and mo dul us=6

there a fter until M count e r unde rf lows.

3 0-3 M[0]..M[3] M cou nter c ontrol bits

4 0-1 M[4]..M[5] Modulus = val ue + 1

4 3 DBL FRE Q Doubl es modu lus of du al -m odu lus pre sc ale r (fro m 6/7 to 12/1 4).

5 0-2 N1[0]..N1[ 2] Sets N1 modulus acco rding to thi s table . The s e bit s are set to im ple-

ment a divide -by- four on power -up .

6 0-3 N2[0]..N2[ 3] Sets t he mo dulus of the N2 di vider. Modul us = va lue + 1

7 0-3 N2[4] ..N2[ 7] The input of the N2 divi de r is the out put of the N1 divi de r in all cloc k

mode s except AUXEN.

8 3 N2[8]

8 0-2 V[0]. .V[1] Sets the gain o f the VC O.

N1[2] N1[1] N1[0] RATIO

0003

0014

0104

0115

1006

1018

1108

11110

V[2] V[1] V[0] VCO GAIN

(MHz/VOLT)

100 30

101 45

110 60

111 80

ICS1572

User Programmable Differential Output Graphics Clock Generator TSD

IDT™ / ICS™ User Programmable Differential Output Graphics Clock Generator ICS1572

REG# BIT(S) BIT REF. DESCRIPTION

9 0-1 P[0]. . P[1] Set s the gain of t he pha se de t ect or a cc or din g to this ta bl e .

9 3 [P2] Phase de tec to r tuning bit. Norma lly shoul d be set t o one.

1 1 0-1 S[0]. . S[1] PLL post-sc a ler/ test m ode sel ect bits

11 2 AUX_CL K When in the AUXEN cloc k mode, this bit control s the diffe rent ial

outputs.

1 1 3 AUX_N1 When i n the AUXEN c lock mode , this bit contr ols t he LOAD outp ut

(and c onse que nt ly t he N2 o utp ut ac co rdi ng to its pro gra m ming) .

12 0 RESERVED Must be set t o zer o.

12 1 JAMPLL Tristate s pha se dete cto r outputs; re sets ph ase detec tor logic, and

resets R, A, M, and N2 counters.

12 2 DACRST Set to ze ro for n orm a l opera t ion . When set to one, th e CLK+ ou tpu t is

ke pt hi gh a nd t he CLK- outp ut i s kept low. (Al l other devic e func t ion s are

una f fe c te d. ) Whe n re turned to z e ro, the CL K+ a nd CLK- out put s wil l

resu me to ggl ing on a rising e dg e of the LD output (+ /- 1 CLK peri od).

To initiate a RAMDAC r ese t seque nc e , simply wri te a one to

thi s reg iste r bi t fo ll owe d by a ze ro.

12 3 SELXTAL When set to log ic 1, passe s the r ef er ence frequency to th e post-sc al e r.

15 0 ALTL O OP Cont rol s substit ut ion of N1 an d N2 div ide rs in to fe e dba c k lo op of PL L .

When this bit is a logic 1, the N1 and N2 dividers are used.

15 3 PDRSTEN Phase-d et ect or rese t ena bl e co ntr ol bit. Whe n thi s bit is set, the AD3

pin becomes a transparent reset input to the phase detector .

See LINE-LOCKED CLOCK GENERATION section for more

de ta ils o n the ope ra t ion of thi s function.

P[1] P[ 0] GAIN (uA/radi an )

00 0.05

01 0.15

10 0.5

11 1.5

S[1] S[0] DESCRIPTION

0 0 Post-scaler=1. F(CLK)=F(PLL). The output of the N1 divider drives

the L OAD out put whic h, in t urn , drive s the N2 di vid er.

0 1 Post-scaler=2. F(CLK)=F(PLL)/2. The output of the N1 divider

drive s the LOAD outp ut whi ch, i n turn, dri ves the N2 divide r.

1 0 Post-scaler=4. F(CLK)=F(PLL)/4. The output of the N1 divider

drive s the LOAD outp ut whi ch, i n turn, dri ves the N2 divide r.

1 1 AUXEN CLOCK MODE . The AUXCLK bit dr ives the dif fe rentia l

outputs CLK+ and CLK- and the AUXN1 bit drives the LOAD

ou tpu t which, in turn, driv es the N2 divi de r.

ICS1572

User Programmable Differential Output Graphics Clock Generator TSD

IDT™ / ICS™ User Programmable Differential Output Graphics Clock Generator ICS1572

NOTE: IT IS NOT NECESSARY TO UNDERSTAND THE FUNCTION OF THESE BITS TO USE THE ICS1572. PC SOFTWARE IS AVAILABLE

FROM ICS TO AUTOMATICALLY GENERATE ALL REGISTER VALUES BASED ON REQUIREMENTS. CONTACT FACTORY FOR DETAILS.

BIT(S) BIT REF. DESCRIPTION

1-3 N1[0].. N1[2] Sets N1 modulus acco rding to thi s table . The s e bit s are set to im plement

a di vide -by- four on power -up .

N1[2] N1[1] N1[0] RATIO

0003

0014

0104

0115

1006

1018

1108

11110

4 RESERVE D Set to z ero.

5 RESERVE D MUST be set t o zer o.If th is bit is ever progr amm e d for a log ic one, devic e

ope ra ti on wi ll c e a se and further se ria l dat a l oa d in to t he r eg isters will be

inhibi ted un til a powe r -of f/ powe r -o n sequ ence .

6 JAMPLL Tri sta tes p hase dete c to r out put s, re set s p ha se de te c tor log ic, and rese ts

R, A, M, a nd N 2 counters.

7 DACRST Set to z ero for n ormal operations. Whe n set to one, the CL K+ output is

ke pt hi gh a nd t he CLK- outp ut i s kept low. (Al l other devic e func t ion s are

una f fe c te d. ) Whe n re turned to z e ro, the CL K+ a nd CLK- out put s wil l

resu me to ggl ing on a rising ed g e of t he LD ou tpu t (+/ −1 CL K p er i od).

To initiate a RAMDAC r ese t seque nc e , simply wri te a one to this reg iste r

bit followed by a z ero.

8 SELXTAL When set to log ic 1, p asse s the r ef eren ce fre qu en cy to the po st-sc ale r.

9 ALTL OO P Control s substit ut ion of N1 an d N2 div ide rs in to fe e dba c k lo op of PL L .

When this bit is a logic 1, the N1 and N2 dividers are used.

10 SCEN VRAM shift cloc k enable bit. When l ogi c 1, the BLANK pin ca n be use d

to disable the LD/N2 output.

1 1 EXTFBKE N Externa l PLL feedba c k sel e ct. W hen l ogi c 1, the EXTFBK pin is used for

the phase-frequency det e ct or fe e dba c k in put .

12 PDRST EN Phase dete c tor reset ena ble control bit. When thi s bit i s se t, a high level

on the BLANK in put will disabl e PLL lock ing . See LINE -LOCKED

CL OCK GENE RATION se ct io n for m ore de tai ls on the op er at io n of

this function.

ICS1572

User Programmable Differential Output Graphics Clock Generator TSD

IDT™ / ICS™ User Programmable Differential Output Graphics Clock Generator ICS1572

BIT(S) BIT REF. DESCRIPTION

13-14 S[0]..S[1] PLL post-scaler/test mode select bits.

S[1] S[0] DESCRIPTION

0 0 Post-scaler=1. F(CLK)=F(PLL). The output of the N1 divider drives

the LOAD out put wh ich, in turn, dri ve s the N2 divide r.

0 1 Post-scaler=2. F(CLK)=F(PLL)/2. The output of the N1 divider

dri ves the LOAD ou tpu t whi ch, in tur n, d riv es th e N2 divi de r.

1 0 Post-scaler=4. F(CLK)=F(PLL)/4. The output of the N1 divider

dri ves the LOAD ou tpu t whi ch, in tur n, d riv es th e N2 divi de r.

1 1 AUXEN CLOCK MODE . The AUXCL K bit dri ves the dif fere ntial

outputs CLK+ and CLK- and the AUXN1 bit drives the LOAD

out put which, in turn, drives the N2 divider.

15 AUX_CL K When in t he AUXEN clock mode, thi s bit control s the differentia l outputs.

16 AUX_N1 When i n the AUXEN c lo ck mo de , this bit co ntr ols the N1 out put (and

conseq ue ntl y the N2 ou tpu t accor din g to its prog ra mm ing).



17-24 N2[0]..N2[7] Sets the mo dulus of the N2 di vid er. T he in put of the N2 di vi der is the

28 N2[8] out put of the N1 divider in a ll c lock mo des except AUXEN.

25-2 7 V[0].. V[2] Set s the gain of VCO.

V[2] V[1] V[0] VCO GAIN

(MHz/VOLT)

100 30

101 45

110 60

111 80

29-3 0 P[0].. P[1] Sets the ga in of the phase de t ec t or a ccording to this ta bl e .

P[1] P[0] GAIN (uA/ra dia n)

00 0.05

01 0.15

10 0.5

11 1.5

31 RESERVE D Set to zero.

32 P[2] Pha se dete cto r tun ing bit. Should norm a lly be set to one.

ICS1572

User Programmable Differential Output Graphics Clock Generator TSD

IDT™ / ICS™ User Programmable Differential Output Graphics Clock Generator ICS1572

BIT(S) BIT REF. DESCRIPTION

33-38 M[0]..M[5] M counter control bits

Modulus = val ue + 1

39 RESERVE D Set to zero.

40 DBL FRE Q Doubl es modu lus of du al -m odu lus pre sc ale r (fro m 6/7 to 12/1 4).

41-44 A[0]..A[3] Controls A coun te r. When set to zero, modulus= 7. Otherwise,

mo dul us=7 for “ va lue ” underflows of the pre sca ler, and mo dul us=6

there a fter until M count e r unde rf lows.

45-4 8 RESERVED Set to zero.

49-5 5 R[0]..R[ 6] Re fere nc e divi de r modul us control bits

Modulus = val ue + 1

56 RESERVE D Set to zero.

ICS1572

User Programmable Differential Output Graphics Clock Generator TSD

IDT™ / ICS™ User Programmable Differential Output Graphics Clock Generator ICS1572

Table 1 - “A” & “M” Divider Programming

Feedback Divider Modulus Table

A[2]..A[0]- 001 010 011 100 101 110 111 000

M[5]..M[0]

000000 7

000001 13 14

000010 19 20 21

000011 25 26 27 28

000100 31 32 33 34 35

000101 37 38 39 40 41 42

000110 43 44 45 46 47 48 49

000111 49 50 51 52 53 54 55 56

001000 55 56 57 58 59 60 61 63

001001 61 62 63 64 65 66 67 70

001010 67 68 69 70 71 72 73 77

001011 73 74 75 76 77 78 79 84

001100 79 80 81 82 83 84 85 91

001101 85 86 87 88 89 90 91 98

001110 91 92 93 94 95 96 97 105

001111 97 98 99 100 101 102 103 112

010000 103 104 105 106 107 108 109 119

010001 109 110 111 112 113 114 115 126

010010 115 116 117 118 119 120 121 133

010011 121 122 123 124 125 126 127 140

010100 127 128 129 130 131 132 133 147

010101 133 134 135 136 137 138 139 154

010110 139 140 141 142 143 144 145 161

010111 145 146 147 148 149 150 151 168

011000 151 152 153 154 155 156 157 175

011001 157 158 159 160 161 162 163 182

011010 163 164 165 166 167 168 169 189

011011 169 170 171 172 173 174 175 196

011100 175 176 177 178 179 180 181 203

011101 181 182 183 184 185 186 187 210

011110 187 188 189 190 191 192 193 217

011111 193 194 195 196 197 198 199 224

A[2]..A[0]- 001 010 011 100 101 110 111 000

M[5]..M[0]

100000 199 200 201 202 203 204 205 231

100001 205 206 207 208 209 210 211 238

100010 211 212 213 214 215 216 217 245

100011 217 218 219 220 221 222 223 252

100100 223 224 225 226 227 228 229 259

100101 229 230 231 232 233 234 235 266

100110 235 236 237 238 239 240 241 273

100111 241 242 243 244 245 246 247 280

101000 247 248 249 250 251 252 253 287

101001 253 254 255 256 257 258 259 294

101010 259 260 261 262 263 264 265 301

101011 265 266 267 268 269 270 271 308

101100 271 272 273 274 275 276 277 315

101101 277 278 279 280 281 282 283 322

101110 283 284 285 286 287 288 289 329

101111 289 290 291 292 293 294 295 336

110000 295 296 297 298 299 300 301 343

110001 301 302 303 304 305 306 307 350

110010 307 308 309 310 311 312 313 357

110011 313 314 315 316 317 318 319 364

110100 319 320 321 322 323 324 325 371

110101 325 326 327 328 329 330 331 378

110110 331 332 333 334 335 336 337 385

110111 337 338 339 340 341 342 343 392

111000 343 344 345 346 347 348 349 399

111001 349 350 351 352 353 354 355 406

111010 355 356 357 358 359 360 361 413

111011 361 362 363 364 365 366 367 420

111100 367 368 369 370 371 372 373 427

111101 373 374 375 376 377 378 379 434

111110 379 380 381 382 383 384 385 441

111111 385 386 387 388 389 390 391 448

Notes:

To use t hi s tab le , find t he de sired modul us in t he table. Fol lo w the c ol um n up t o fi nd t he A divi der progra m mi ng va l ue s.

Fol low the row to the l eft to fin d the M div ider pr ogra m m ing . Some feed ba ck d ivisors ca n be a chie ve d with two or three

com binatio ns of di vi der setti ngs. Any are a cce pt a ble f or u se .

The formula fo r the ef fectiv e fe e dba c k modulus is: N = [(M +1 ) . 6] +A

exc ep t whe n A=0, then : N=(M +1) . 7

Unde r all circ um sta nc e s: A ≤ M

ICS1572

User Programmable Differential Output Graphics Clock Generator TSD

IDT™ / ICS™ User Programmable Differential Output Graphics Clock Generator ICS1572

Pin Descriptions - ICS1572-101

PIN# NAME DESCRIPTION

13 CLK+ Clock out (non-inverted)

12 CLK−Clock out (inverted)

8 LOAD Lo ad outp ut. This out put is normall y a t the CL K fre qu ency div ide d b y N1.

3 XTAL 1 Qua rtz crystal c on ne ct io n 1/e xt e rna l re fe re nc e fre que nc y i nput

4 XTAL2 Quartz crystal connection 2

2 AD0 Address/Da ta Bit 0 (L SB)

19 AD1 Address/Da ta Bit 1

18 AD2 Address/Data Bi t 2

17 AD3 Address/Da ta Bit 3 (MSB)

9 LD/ N2 Divi ded L OAD outp ut. Se e tex t.

5 STROBE Control for address/da ta latch

16 VD D PLL system power (+5V. See a pplicati on diagram. )

15 VDDO Output stage powe r (+5V)

14 IPRG Output stage c urrent set

6,7 VSS Device ground. Both pins must be c onnected to the same ground potent ial.

1,10, 11,20 NC Not conn ec t ed

Pin Descriptions - ICS1572-301

PIN# NAME DESCRIPTION

13 CLK+ Clock out (non-inverted)

12 CLK−Clock out (inverted)

8 LOAD Lo ad outp ut. This out put is normall y a t the CL K fre qu ency div ide d b y N1.

3 XTAL 1 Qua rtz crystal c on ne ct io n 1/e xt e rna l re fe re nc e fre que nc y i nput

4 XTAL2 Quartz crystal connection 2

5 DATCLK Data Clock (Input)

19 DATA Ser ial Regi ste r Da ta (Inp ut)

18 HOLD~ HOLD (I nput)

17 BLA NK Blanking (Input). See Text.

9 LD/ N2 Divide d LOAD output/ shif t clock. See tex t.

2 EXTFBK External feedback conne ction for PLL (input). See text.

16 VD D PLL system power (+5V. See a pplicati on diagram. )

15 VDDO Output stage powe r (+5V)

14 IPRG Output stage c urrent set

6,7 VSS Devic e groun d. Both pins mu st be con nect ed.

1,10, 11,20 NC Not conn ec t ed

ICS1572

User Programmable Differential Output Graphics Clock Generator TSD

IDT™ / ICS™ User Programmable Differential Output Graphics Clock Generator ICS1572

Absolute Maximum Ratings

VDD, VDDO (mea sure d to VSS) . . . . . . . . . . . . . . . . . . . . . . 7.0V

Digit al Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS-0. 5 to VDD + 0.5V

Digit al Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS-0. 5 to VDDO + 0.5V

Am bie nt Ope ra ti ng T empe ra t ure. . . . . . . . . . . . . . . . . . . . . . . -55 t o 125°C

Sto ra ge T e m pe ra tur e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C

Junc tion T e mper at ure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175°C

Soldering Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

Recommended Operating Conditions

VDD, VDDO (mea sure d to VSS) . . . . . . . . . . . . . . . . . . . . . . 4.75 to 5 .25V

Operating Temperature (Ambient). . . . . . . . . . . . . . . . . . . . . . 0 to 70°C

DC Characteristics

TTL-Compatible Inputs

101 Option - (AD0-AD3, STROBE),

301 Option - (DATCLK, DATA, HOLD, BLANK, EXT F B K)

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS

Input Hi gh Voltage Vih 2.0 VDD+0.5 V

Input Low Vol ta ge Vil VSS-0.5 0.8 V

Input Hig h Curren t Iih Vih =VDD - 10 uA

Input Low Curr en t I il Vil =0.0 - 150 u A

Input Capa c itan ce Cin -8pF

XTAL1 In put

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS

Input Hi gh Voltage Vxh 3.75 VDD+0.5 V

Input Low Vol ta ge Vxl VSS-0.5 1.25

CLK+, CLK- Outputs

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS

Differe nt ia l Output Voltage 0.6 - V

LOAD, LD/N2 Outputs

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS

Outp ut High Vol ta ge (I oh= 4. 0m A) 2.4 - V

Output Low Volta ge (I ol=8. 0m A) - 0.4 V

ICS1572

User Programmable Differential Output Graphics Clock Generator TSD

IDT™ / ICS™ User Programmable Differential Output Graphics Clock Generator ICS1572

SYMBOL PARAMETER MIN TYP MAX UNITS

Fvco VC O Fr eq ue nc y (see Not e 1) 20 160 MHz

Fxtal Crystal Fre quency 5 20 MHz

Cpar Crystal Oscil la t or L oa din g Ca pa ci tance 20 p F

Fload LOAD Fre que nc y 80 MHz

Txhi XTAL1 High Time (whe n drive n ext e rna lly) 8 ns

Txlo XTAL1 Low TIm e (whe n driven exte rna l ly) 8 ns

Thigh Differential Clock Output Duty Cycle

(se e Note 2) 45 55 %

Jclk Differential Clock Output Cumulative

Ji tt er (see Note 3) <0.06 pixel

Tlock PL L Acq uire T ime (to withi n 1 %) 50 0 µs

Idd VDD Supply Curre nt 15 t.b. d. mA

Iddo VDDO Supply Curren t (excluding CLK+/-

termination) 20 t.b.d. mA

DIGITAL INPUTS - ICS1572-1 01

1 Address Se t up Time 10 ns

2 Address Hold Time 10 ns

3 Data Setup T ime 10 ns

4 Data Hold T ime 10 ns

5 ST R O BE Pu lse W idth (Thi or Tlo)20 ns

DIGITAL OUTPUTS - ICS1572- 301

6 DATA/HOLD~ Setup T i me 10 ns

7 DATA/HOLD~Hold Time 10 ns

8 DATCL K Pul se Width ( Thi or Tlo)20 ns

PI PELINE DE LAY RE SET

9 Reset Activatio n T ime 2*Tclk ns

10 R ese t Duratio n 4 *T loa d ns

11 R est ar t De lay 2*T load ns

12 Rest ar t Matc hi ng -1 *Tclk +1.5*Tclk ns

DIGITAL OUTPUTS

13 CLK+ / CL K- Clo ck Rat e 180 MHz

14 LOAD To LD/N2 Ske w (Sh ift Cloc k Mode) -2 0 +2 ns

Note 1: Use of the post-divider is required for frequencies lower than 20 MHz on CLK+ & CLK- outputs. Use of the post-divider

is recommended for output frequencies lower than 65 MHz.

Note 2: Using l oad circ uit of Figur e 6. Duty cycl e mea sure d at zero crossing s of dif fe re nce volt age betwe en CLK+ and CLK-.

Note 3: Cumula tive jitter is define d a s the maxim um error (in the tim e doma in) of any CLK edge, at any point in time, c om pa re d

wit h th e e qui va lent ed ge generat e d by a n ideal fr equency sourc e .

ICS laborator y te sting indi c at e s that the ty pic a l va l ue shown ab ove ca n be tr ea ted as a ma ximum ji tte r sp ec i fic a ti on i n

virtually all applications. Jitter performance can depend somewhat on circuit board layout, decoupling, and register

programming.

AC Characteristics

ICS1572

User Programmable Differential Output Graphics Clock Generator TSD

IDT™ / ICS™ User Programmable Differential Output Graphics Clock Generator ICS1572

NOTES

ICS1572

User Programmable Differential Output Graphics Clock Generator TSD

IDT™ / ICS™ User Programmable Differential Output Graphics Clock Generator ICS1572

Output Circuitry

The do t cloc k signa ls CLK a nd CLK- a re typic ally the highe st

frequency signals present in the workstation. To minimize

problems with EMI, crosstalk, and capacitive loading extra

ca re shou l d be tak en in lay in g ou t t his are a of th e P C bo ard .

The ICS1572 is packaged in a 0.3”-wide 20-pin SOIC package.

This permits the clock generator, crystal, and rel ated compo-

ne nt s to be lai d ou t in a n are a t he size of a postage sta m p. The

ICS1572 s hould be placed as close as possible to the RAM-

DAC. The CLK and CLK- pins are running at VHF frequen-

cies; one should minimize the length of PCB trace connecting

them to the RAMDAC so that they don’t b ecome radiators of

RF ene r gy.

At the frequencies that the ICS1572 i s capabl e of, PC board

traces may be long enough to be a significant portion of a

wavelength of that frequency. PC traces for CLK and CLK-

should be treated as transmission lines, not just interconnecting

wires. T hese lines can take two form s: mi crostri p a nd stri pline .

A micro st ri p line i s shown be low:

Essentially, the microstrip is a copper trace on a PCB over a

ground plane. Typically, the dielectric is G10 glass epoxy. It

differs from a standard PCB trace in that its width is calculated

to have a characteristic impedance. To calculate the charac-

teristic impedance of a microstrip line one must know the width

and thickness of the trace, and the thickness and dielectric

constant of the dielectric. For G10 glass epoxy, the dielectric

consta nt (er) is abo ut 5. Propag ation d ela y is strictl y a function

of dielectric constant. For G10 propagation, delay is calculated

t o be 1.77 ns/ft.

Str ipl ine i s the ot her f orm a PCB tr an smi ssion l ine c an take . A

buried trace between ground planes (or be tween a power plane

and a groun d plane ) is com m on in m ul ti-l ay er boa rds.

Attempting to create a workstation design without the use of

multi-layer boards would be adv enturous to say the least, the

issue would more likely be whethe r to place the interconnect

on the surface or between layers. The between layer approach

would work better from an EMI standpoint, but would be more

dif fic ul t to lay out . A stri pline is sh own b elow:

Using 1oz. copper (0.0015 ” thick) and 0.040” thickness G10,

a 0.010” t race will e xhibit a characteristic impedance of 75Ω

in a stripline confi guration.

Typically, RAMDACS require a Vih of VAA-1.0 Volts as a

guaranteed logical “1” and a Vil of VAA-1. 6 as a guarant eed

lo gic a l “0. ” Worst c a se input ca pa c it a nc e is 10 p F.

Output circuitry for the ICS1572 is shown in the following

diagram. It consists of a 4/1 curre nt mirror, and two open drain

out put FETs alon g wit h inv er ti ng buf f er s to a lt er na te ly en ab le

eac h c urr en t-si nking drive r. Both CL K an d CL K- outputs are

connected to the respective CLOCK and CLOCK* inputs of

the RAMDAC with transmission line s and te rm in at e d in the i r

eq uiv al ent i mpe danc es by the Thevenin equival ent impedances

of R1 a nd R2 or R1 ’ and R2 ’.

ICS1572 Ap p licatio n I nfo rmation

Output Circuit Considerations for the ICS1572

ICS1572

User Programmable Differential Output Graphics Clock Generator TSD

IDT™ / ICS™ User Programmable Differential Output Graphics Clock Generator ICS1572

The ICS1572 i s incapable of sourcin g current, so Vih must be

set by the ratios of these resistors for ea ch of these lines. R1

and R2 are electrically in parallel from an AC standpoint

beca use Vdd is bypassed to ground through bypass-capacitor

networ k Cb. I f we p icke d a target impe danc e of 7 5Ω for our

trans mis sio n line impeda nce, a v alue o f 91Ω for R1 and R1’

and a value of 430Ω for R 2 a nd R2’ wou ld y ield a Thev inin

equivalent ch aract eristic im pedance of 75.1W and a Vih val ue

of VAA-.873 Volts, a margin of 0.127Volts. This may be

adequate; however, at higher frequencies one must contend

with the 10 pF input capacitance of t h e RAMDAC. Values of

82Ω for R1 and R1’ and 820Ω for R2 and R2 ’ woul d give us a

cha ract eristic impedanc e of 7 4.5 Ω and a Vih value of VAA-.45.

With a .55 Volt margin on Vih, this voltage level might be safer .

To set a value for Vil, we must determine a value for Iprg that

wil l cause the output FET’s to sink an appr opriate c u rrent. We

desire V il to be VAA-1.6 or greater . VAA-2 would seem to be a

saf e valu e. Setti ng up a sin k cur rent of 25 mil liampe res woul d

guarantee this through our 82Ω pull-up resistors. As this is

controlled by a 4/1 current mirror , 7 mA into Iprg should set this

curre nt pro perly. A 510 Ω re sistor fr om V dd to Iprg should wor k

fine.

Resistors Rt and Rt’ are shown as s eries terminating resistors

at the ICS1572 end of the transmission lines. These are not

required for operation, but may be useful for meeting EMI

r equir em ents . Their int ent is to in teract with th e inpu t capaci-

tance of the RAMDAC and the distributed capacitance of the

transmission line to soften up rise and fall times and conse-

quently cut some of the high-order harmonic content that is

more likely to radiate RF energy. In actual usage they would

most li ke ly be 10 t o 20Ω resistors or possibly ferrite beads.

Cb is shown as multip le c apacitors. Typica lly, a 22 µF tantalum

should be used with separate .1 µF and 220pf capacitors placed

as close to the pins as possible. This provides low series

inductance capacitors right at the source of high frequency

energy. Rd is u sed to isolate the c ircui try from external sources

of no ise . Five t o ten oh ms shoul d be ad equa te .

Great care must be used when evaluating high frequency

circuits to achieve meaningful results. The 10 pf input capaci-

tance and long ground lead of an ordinary scope probe will

make any measurements made with it meaningless. A low

capacitance FET probe with a ground connection directly

connected to the shield at the tip will be required. A 1GHz

bandwidth scope will be barely adequate, try to find a faster

unit.

ICS1572 Ap plicat io n No te

IC S1572 Output Ci rcuitry

ICS1572

User Programmable Differential Output Graphics Clock Generator TSD

IDT™ / ICS™ User Programmable Differential Output Graphics Clock Generator ICS1572

LEAD COUNT 1 4L 16 L 18L 20L 24L 28L 32L

DIMENSION L 0.354 0.4 04 0.454 0.504 0.604 0. 704 0. 804

Ordering Information

ICS1572M-101 or ICS1572M-301

Example:

ICS XXX X M -XXX

Patte rn Numbe r (2 or 3 digit numbe r for parts wi th RO M code patter ns )

Package Type

M=SOIC

Devic e Typ e (cons ist s of 3 o r 4 digi t numbe rs )

Prefix

ICS , AV=Stan da rd De vice ; GSP=Genloc k Device

SOIC Packages (wide body)

ICS1572

User Programmable Differential Output Graphics Clock Generator TSD

IDT™ / ICS™ User Programmable Differential Output Graphics Clock Generator ICS1572

Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered

trademarks used to identify products or services of their respective owners.

Printed in USA

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Corporate Headquarters

Integrated Device Technology, Inc.

6024 Silver Creek Valley Road

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+408 284 8200 (outside U.S.)

Asia Pacific and Japan

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Reg. No. 199707558G

435 Orchard Road

#20-03 Wisma Atria

Singapore 238877

+65 6 887 5505

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+44 1372 363 339

For Sales

800-345-7015

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Fax: 408-284-2775

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User Programmable Differential Output Graphics Clock Generator TSD