MD1711 High-Speed Integrated Ultrasound Driver IC Features General Description * * * * * * * * * * The MD1711 is a two-channel logic controller circuit with low-impedance MOSFET gate drivers. It is intended to be used with external FETs as a five-level high-voltage and high-speed transmitter. The MD1711 is designed for medical ultrasound imaging applications but can also be used for metal flaw detection, NDT and for driving piezoelectric transducers. Drives Two Ultrasound Transducer Channels Generates a Five-Level Waveform Drives 12 High-Voltage MOSFETs 2A Source-and-Sink Peak Currents Up to 20 MHz Output Frequency 12 V/ns Slew Rate 3 ns Matched Delay Times Less than -40 dB Second Harmonic Two Separate Gate Drive Voltages 1.8V to 3.3V CMOS Logic Interface Applications * * * * * Medical Ultrasound Imaging Piezoelectric Transducer Drivers Non-Destructive Testing (NDT) Metal Flaw Detection Sonar Transmitter The MD1711 has two sets of control logic inputs, one for Channel A and one for Channel B. Each channel consists of three pairs of MOSFET gate drivers. These drivers are designed to match the drive requirements of the TC6320. One MD1711 drives six TC6320s. Each driver consists of an N-channel and a P-channel MOSFET. They are designed to have the same impedance and can provide peak currents of 2 amps. Package Types 48-lead LQFP (Top view) 48-lead QFN (Top view) 48 1 48 1 See Table 2-1 for pin information. 2019 Microchip Technology Inc. DS20005740A-page 1 MD1711 Functional Block Diagram +100V 1.0F DV DD 2 10nF DVDD1 DV DD 2 DVDD2 10nF -100V AVDD1 1.0F +100V DV DD 1 Piezoelectric Transducer A 1.0F 10nF DV DD 1 POSA/POS1A 10nF -100V NEGA/NEG1A 1.0F HVEN1A/POS2A HVEN2A/NEG2A CLAMPA VSS DV DD 1 VLL SEL EN Control Logic and Level Translate +100V 1.0F DV DD 2 10nF DV DD 2 POSB/POS1B 10nF -100V NEGB/NEG1B 1.0F HVEN1B/POS2B HVEN2B/NEG2B +100V DV DD 1 Piezoelectric Transducer B 1.0F CLAMP 10nF DV DD 1 10nF -100V 1.0F AVSS DVSS AGND DGND VSS DV DD 1 MD1711 DS20005740A-page 2 TC6320 2019 Microchip Technology Inc. MD1711 Typical Application Circuit +10V +5.0V 0.22F 0.22F +10V -10V 0.22F +10V 0.22F 40 33 35 45 43 DVDD2 DVDD2 DGND DVDD1 DVSS DGND FB 6 36 SEL POSA / POS1A HVEN1A / POS2A ClampA +3.3V Control Logic & Level Translator 1 3 HVEN2A / NEG2A OUTPA1 39 47 2 VPP1 1F DVDD2 13 NEGA / NEG1A +100V DVDD1 DVDD1 30 DGND AVDD1 0.1F EN 0.22F 31 42 10nF DVDD2 OUTNA1 37 10nF VNN1 1F -100V +50V VPP2 4 1F DVDD1 5 46 OUTPA2 MD1711 VLL 41 (1/2 of I/O) 0.1F OUTNA2 34 48 10nF DVDD1 10nF VNN2 AVSS -50V 0.1F 1F Transducer 0V 0.1F 14 15 AVSS SUB OUTPA3 AVSS 44 VSS DVDD1 OUTNA3 32 -10V AGND DGND DVDD1 DVSS DVDD2 DVDD1 DGND DVDD2 18 7 19 16 21 28 0 26 TC6320 0.22F +10V 2019 Microchip Technology Inc. 0V 25 0 -10V +10V +5.0V DS20005740A-page 3 MD1711 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Logic Supply Voltage, VLL ....................................................................................................................... -0.5V to +5.5V Positive Gate Drive Supply, AVDD1, DVDD1, DVDD2 ..................................................................................-0.5V to +15V Negative Gate Drive Supply, AVSS, DVSS .................................................................................................-15V to +0.5V Operating Junction Temperature, TJ ........................................................................................................ 0C to +125C Storage Temperature, TS ..................................................................................................................... -65C to +150C Power Dissipation (48-lead LQFP) ....................................................................................................................... 1.92W Power Dissipation (48-lead QFN) ......................................................................................................................... 5.55W Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. OPERATING SUPPLY VOLTAGES AND CURRENTS Electrical Specifications: Over operating conditions unless otherwise specified, AVDD1 = DVDD1 = DVDD2 = 10V, AVSS = DVSS = -10V, VLL = 3.3V, TA = 25C. Parameter Sym. Min. Typ. VLL 1.8 3.3 5 V Positive Drive Bias Supply AVDD1 8 10 12.6 V Positive Gate Drive Supply DVDD1 4.75 -- 12.6 V Positive Gate Drive Supply DVDD2 4.75 -- 12.6 V Logic Supply Max. Unit Conditions AVSS, DVSS -12 -10 -8 V Logic Supply Current IVLL -- 2 -- mA Positive Bias Current IAVDD1 -- 5 -- mA IAVSS, IDVSS -- 20 -- All channels on at 5 MHz, mA no load Positive Drive Current 1 IDVDD1 -- 55 -- mA Positive Drive Current 2 IDVDD2 -- 13 -- mA VAVDD1 Quiescent Current IAVDD1Q -- 2 -- mA Negative Gate Drive and Bias Supply Negative Drive and Bias Supply Currents VAVSS Quiescent Current IAVSSQ -- 0.75 -- mA VDVDD1 Quiescent Current IDVDD1Q -- -- 10 A VDVDD2 Quiescent Current IDVDD2Q -- -- 10 A IVLLQ -- 1 -- mA Logic Supply Current DS20005740A-page 4 All channels on at 5 MHz, DVDD2 = 5V, no load EN = low, all inputs low or high 2019 Microchip Technology Inc. MD1711 DC ELECTRICAL CHARACTERISTICS Electrical Specifications: Over operating conditions unless otherwise specified, AVDD1 = DVDD1 = DVDD2 = 10V, AVSS = DVSS = -10V, VLL = 3.3V, TA = 0C to 70C. Parameter Sym. Min. Typ. Max. Unit Conditions -- 6 ISINK = 100 mA P-CHANNEL AND N-CHANNEL GATE DRIVER OUTPUTS Output Sink Resistance Output Source resistance Peak Output Sink Current Peak Output Source Current P-Channel N-Channel P-Channel N-Channel P-Channel N-Channel P-Channel N-Channel RSINK RSOURCE ISINK ISOURCE -- -- -- 10 ISINK = 100 mA -- -- 6 ISOURCE = 100 mA ISOURCE = 100 mA -- -- 10 -- 2 -- A -- 1.5 -- A -- 2 -- A -- 1.5 -- A LOGIC INPUTS Input Logic High Voltage VIH 0.8 VLL -- VLL V Input Logic Low Voltage VIL 0 -- 0.2 VLL V Input Logic High Current IIH -- -- 1 A Input Logic Low Current IIL -1 -- -- A AC ELECTRICAL CHARACTERISTICS Electrical Specifications: Over operating conditions unless otherwise specified, AVDD1 = DVDD1 = DVDD2 = 10V, AVSS = DVSS = -10V, VLL = 3.3V, TA = 0C to 70C. Parameter Sym. Min. Typ. Max. Unit Conditions Output Frequency Range fOUT -- -- 20 MHz Propagation Delay when Output is from Low to High tPH -- 19 -- ns No load (See Timing Waveforms.) Propagation Delay when Output is from High to Low tPL -- 19 -- ns No load (See Timing Waveforms.) Output Rise Time tr -- 8 -- ns 1000 pF load (See Timing Waveforms.) Output Fall Time tf -- 8 -- ns 1000 pF load (See Timing Waveforms.) tDM -- -- 3 ns No load, from device to device tDLAY -- 30 -- ps Standard deviation of tD samples (1 kHz) SR -- 12 -- HD2 -- -40 -- Delay Time Matching Output Jitter Output Slew Rate Second Harmonic Distortion 2019 Microchip Technology Inc. V/ns Measured at TC6320 outdB put with 100 load DS20005740A-page 5 MD1711 TEMPERATURE SPECIFICATIONS Parameter Sym. Min. Typ. Max. Unit Operating Junction Temperature TJ 0 -- +125 C Storage Temperature TS -65 -- +150 C 48-lead LQFP JA -- 52 -- C/W 48-lead QFN JA -- 18 -- C/W Conditions TEMPERATURE RANGE PACKAGE THERMAL RESISTANCE DS20005740A-page 6 2019 Microchip Technology Inc. MD1711 Timing Waveforms VLL HVEN1A/POS2A 0V VLL HVEN2A/NEG2A 0V VLL POSA/POS1A 0V VLL NEGA/NEG1A 0V fOUT VPP1 VPP2 HVOUTA 0V VNN2 VNN1 tr1, rise time from 0.9VNN1 to 0.9VPP1 tf1, fall time from 0.9VPP1 to 0.9VNN1 tr2, rise time from 0.9VNN2 to 0.9VPP2 tf2, fall time from 0.9VPP2 to 0.9VNN2 3.3V 50% IN 0V 50% tPH tPL 10V 90% 90% OUT 0V 2019 Microchip Technology Inc. 10% 10% tr t DS20005740A-page 7 MD1711 2.0 PIN DESCRIPTION Functional descriptions for the pins are listed in Table 2-1. See Package Types for the location of pins. TABLE 2-1: PIN FUNCTION TABLE Pin Number Pin Name 1 POSA/POS1A Logic input control for Channel A. When SEL = L, the pin is POSA. When SEL = H, the pin is POS1A. 2 NEGA/NEG1A Logic input control for Channel A. When SEL = L, the pin is NEGA. When SEL = H, the pin is NEG1A. 3 HVEN1A/POS2A Logic input control for Channel A. When SEL = L, the pin is HVEN1A. When SEL = H, the pin is POS2A. 4 HVEN2A/NEG2A Logic input control for Channel A. When SEL = L, the pin is HVEN2A. When SEL = H, the pin is NEG2A. 5 CLAMPA Used with SEL = H. Logic input control for OUT-PA3 and OUT-NA3. Connect to ground when SEL = L. 6 AVDD1 Supplies analog circuitry portion of the gate driver. Should be at the same potential as DVDD1. 7 AGND Analog Ground 8 CLAMPB Used with SEL = H. Logic input control for OUT-PB3 and OUT-NB3. Connect to ground when SEL = L. 9 HVEN2B/NEG2B Logic input control for Channel B. When SEL = L, the pin is HVEN2B. When SEL = H, the pin is NEG2B. 10 HVEN1B/POS2B Logic input control for Channel B. When SEL = L, the pin is HVEN1B. When SEL = H, the pin is POS2B. 11 NEGB/NEG1B Logic input control for Channel B. When SEL = L, the pin is NEGB. When SEL = H, the pin is NEG1B. 12 POSB/POS1B Logic input control for Channel B. When SEL = L, the pin is POSB. When SEL = H, the pin is POS1B. 13 SEL 14 Description Logic input select. See Table 3-2 for SEL = L and Table 3-3 for SEL = H. AVSS Negative driver supply for OUT-PA3, OUT-PB3 and bias circuits. It is also connected to the IC substrate. It should be connected to the most negative potential. 16 DVSS Gate drive supply voltage for OUT-PA3 and OUT-PB3. Supplies digital circuitry portion and the main output stage. Should be at the same potential as AVSS. 17 OUT-PB3 18 DGND Digital Ground 19 DVDD1 Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main output stage for OUT-PA2, OUT-NA2, OUT-NA3, OUT-PB2, OUT-NB2 and OUT-NB3. Should be at the same potential as AVDD1. 20 Out-PB2 Output P-channel gate driver for Channel B 21 DVDD2 Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main output stage for OUT-PA1, OUT-NA1, OUT-PB1 and OUT-NB1. Can be at a different potential compared to DVDD1. 22 Out-PB1 Output P-channel gate driver for Channel B 23 N/C 24 Out-NB1 15 DS20005740A-page 8 Output P-channel gate driver for Channel B No connect Output N-channel gate driver for Channel B 2019 Microchip Technology Inc. MD1711 TABLE 2-1: PIN FUNCTION TABLE Pin Number Pin Name Description 25 DVDD2 Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main output stage for OUT-PA1, OUT-NA1, OUT-PB1 and OUT-NB1. Can be at a different potential compared to DVDD1. 26 DGND Digital Ground 27 Out-NB2 Output N-channel gate driver for Channel B 28 DVDD1 Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main output stage for OUT-PA2, OUT-NA2, OUT-NA3, OUT-PB2, OUT-NB2 and OUT-NB3. Should be at the same potential as AVDD1. 29 Out-NB3 Output N-channel gate driver for Channel B 30 DGND Digital Ground 31 DVDD1 Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main output stage for OUT-PA2, OUT-NA2, OUT-NA3, OUT-PB2, OUT-NB2 and OUT-NB3. Should be at the same potential as AVDD1. 32 OUT-NA3 33 DVDD1 Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main output stage for OUT-PA2, OUT-NA2, OUT-NA3, OUT-PB2, OUT-NB2 and OUT-NB3. Should be at the same potential as AVDD1. 34 Out-NA2 Output N-Channel gate drivers for Channel A 35 DGND Digital Ground 36 DVDD2 Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main output stage for OUT-PA1, OUT-NA1, OUT-PB1 and OUT-NB1. Can be at a different potential compared to DVDD1. 37 Out-NA1 Output N-channel gate drivers for Channel A 38 N/C 39 Out-PA1 Output P-channel gate drivers for Channel A 40 DVDD2 Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main output stage for OUT-PA1, OUT-NA1, OUT-PB1 and OUT-NB1. Can be at a different potential compared to DVDD1. 41 OUT-PA2 42 DVDD1 Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main output stage for OUT-PA2, OUT-NA2, OUT-NA3, OUT-PB2, OUT-NB2 and OUT-NB3. Should be at the same potential as AVDD1. 43 DGND Digital Ground 44 Out-PA3 45 DVSS 46 VLL Logic supply voltage 47 EN Logic input enable control. When EN = L, all P-channel output drivers are high and all N-channel output drivers are low. 48 AVSS Negative driver supply for OUT-PA3, OUT-PB3 and bias circuits. It is also connected to the IC substrate. It should be connected to the most negative potential. Center Pad AVSS For the QFN package, the center pad is at AVSS potential. It should be externally connected to AVSS. 2019 Microchip Technology Inc. Output N-channel gate drivers for Channel A No connect Output P-channel gate drivers for Channel A Output P-channel gate drivers for Channel A Gate drive supply voltage for OUT-PA3 and OUT-PB3. Supplies digital circuitry portion and the main output stage. Should be at the same potential as AVSS. DS20005740A-page 9 MD1711 3.0 DETAILED DESCRIPTION TABLE 3-1: POWER-UP SEQUENCE Step Connection 1 AVSS, DVSS 2 VLL, AVDD1, DVDD1 and DVDD2 Description Negative gate drive supply and substrate bias Logic supply, positive gate drive supply and bias 1/2 of MD1711 3x TC6320 DVDD2 OUT-PA1 10nF +100V VPP1 GPA1 +10V AVDD1 HVOUTPA1 +10V DVDD1 DVDD2 +10VDVDD2 OUT-NA1 10nF GNA1 HVOUTA RLOAD 100 HVOUTNA1 +3.3V VLL VNN1 -100V EN +50V POSA/POS1A NEGA/NEG1A HVEN1A/POS2A HVEN2A/NEG2A Channel A Control Logic and Level Translation DVDD1 OUT-PA2 10nF VPP2 GPA2 HVOUTPA2 DVDD1 OUT-NA2 10nF GNA2 CLAMPA HVOUTNA2 VNN2 SEL -50V AGND VPP3 DGND OUT-PA3 AVSS GPA3 HVOUTPA3 DVSS DVDD1 DVSS -10V OUT-NA3 GNA3 HVOUTNA3 VNN3 FIGURE 3-1: DS20005740A-page 10 Test Circuit for Channel A. 2019 Microchip Technology Inc. MD1711 TABLE 3-2: TRUTH FUNCTION TABLE FOR CHANNELS A AND B (FOR SEL = L) VPP1 to VNN1 Output Logic Control Inputs SEL EN HVEN1/ POS2 HVEN2/ NEG2 Clamp POS/ POS1 NEG/ NEG1 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X 2019 Microchip Technology Inc. 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X HVOUTP1 1 VPP2 to VNN2 Output HVOUTN1 HVOUTP2 OFF VPP3 to VNN3 Output HVOUTN2 HVOUTP3 OFF 1 HVOUTN3 ON ON ON ON ON ON OFF OFF 0 1 OFF 0 OFF 1 0 OFF 1 OFF 0 1 OFF OFF ON ON OFF ON OFF OFF ON OFF OFF OFF OFF OFF OFF OFF 0 1 OFF 0 1 0 OFF 0 OFF OFF 1 OFF ON ON OFF 1 OFF OFF OFF OFF ON ON OFF OFF OFF OFF OFF OFF 0 1 0 OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF 1 0 1 0 1 0 1 0 1 X DS20005740A-page 11 MD1711 TABLE 3-3: TRUTH FUNCTION TABLE FOR CHANNELS A AND B (FOR SEL = H) VPP1 to VNN1 Output Logic Control Inputs SEL EN HVEN1/ POS2 HVEN2/ NEG2 Clamp POS/ POS1 NEG/ NEG1 HVOUTP1 1 1 0 0 0 0 0 OFF OFF ON 1 1 0 0 0 1 0 ON OFF ON ON 1 1 0 0 1 0 0 OFF OFF OFF ON 1 1 0 0 1 1 0 ON OFF ON ON 1 1 0 1 0 0 0 OFF OFF OFF ON 1 1 0 1 0 1 0 ON OFF 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 1 1 1 1 1 1 HVOUTN1 HVOUTP2 ON ON 1 0 1 1 0 0 OFF OFF OFF ON 1 1 0 1 1 1 0 ON OFF 1 1 1 1 1 1 0 0 0 1 1 1 0 0 0 0 1 ON ON 0 OFF OFF OFF ON 0 ON OFF 1 0 0 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 0 0 OFF OFF ON 0 ON OFF ON ON 0 OFF OFF OFF ON 0 ON OFF 1 0 0 1 1 1 1 1 1 ON OFF 1 1 1 1 ON 0 1 1 1 1 0 1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 0 1 0 0 0 0 1 1 1 ON ON 1 1 1 1 1 0 0 OFF OFF OFF ON 1 1 1 1 1 1 0 ON OFF ON ON X X X X OFF OFF 1 1 1 1 1 0 DS20005740A-page 12 1 1 X 1 1 1 1 0 1 1 1 VPP3 to VNN3 Output HVOUTN2 HVOUTP3 HVOUTN3 OFF 1 1 VPP2 to VNN2 Output OFF OFF OFF OFF ON OFF ON OFF OFF ON ON OFF OFF OFF ON OFF ON ON ON OFF ON ON ON ON OFF OFF OFF 2019 Microchip Technology Inc. MD1711 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 48-lead LQFP XXXXXX XXXXXXX e3 YYWW NNN Legend: XX...X Y YY WW NNN e3 * Note: Example MD 1711FG e3 1930 525 48-lead QFN Example XXXXXXXX e3 YYWWNNN MD1711K6 e3 1914325 Product Code or Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC(R) designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for product code or customer-specific information. Package may or not include the corporate logo. 2019 Microchip Technology Inc. DS20005740A-page 13 MD1711 48-Lead LQFP Package Outline (FG) 7.00x7.00mm body, 1.60mm height (max), 0.50mm pitch D D1 E1 E Note 1 (Index Area D1/4 x E1/4) 48 1 e b Top View View B L2 A A2 Seating Plane L L1 A1 Gauge Plane Seating Plane View B Side View Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging. Note: 1. $3LQLGHQWLHUPXVWEHORFDWHGLQWKHLQGH[DUHDLQGLFDWHG7KH3LQLGHQWLHUFDQEHDPROGHGPDUNLGHQWLHUDQHPEHGGHGPHWDOPDUNHURU a printed indicator. Symbol A A1 A2 b D D1 E E1 MIN Dimension NOM (mm) MAX 1.40* 0.05 1.35 0.17 8.80* 6.80* 8.80* 6.80* - - 1.40 0.22 9.00 7.00 9.00 7.00 1.60 0.15 1.45 0.27 9.20* 7.20* 9.20* 7.20* e L L1 L2 1.00 REF 0.25 BSC 0O 0.45 0.50 BSC 0.60 0.75 3.5O 7O JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001. 7KLVGLPHQVLRQLVQRWVSHFLHGLQWKH-('(&GUDZLQJ Drawings are not to scale. S # S Q G DS20005740A-page 14 2019 Microchip Technology Inc. MD1711 48-Lead QFN Package Outline (K6) 7.00x7.00mm body, 1.00mm height (max), 0.50mm pitch D2 D 48 48 Note 1 (Index Area D/2 x E/2) 1 1 Note 1 (Index Area D/2 x E/2) e E E2 b View B Top View Bottom View Note 3 A3 A L Seating Plane L1 Note 2 A1 View B Side View Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging. Notes: 1. $3LQLGHQWLHUPXVWEHORFDWHGLQWKHLQGH[DUHDLQGLFDWHG7KH3LQLGHQWLHUFDQEHDPROGHGPDUNLGHQWLHUDQHPEHGGHGPHWDOPDUNHURU a printed indicator. 2. 'HSHQGLQJRQWKHPHWKRGRIPDQXIDFWXULQJDPD[LPXPRIPPSXOOEDFN / PD\EHSUHVHQW 3. 7KHLQQHUWLSRIWKHOHDGPD\EHHLWKHUURXQGHGRUVTXDUH Symbol Dimension (mm) A A1 MIN 0.80 0.00 NOM 0.90 0.02 MAX 1.00 0.05 A3 0.20 REF b D D2 E E2 0.18 6.85* 1.25 6.85* 1.25 0.25 7.00 - 7.00 - 0.30 7.15* 5.45 7.15* 5.45 e 0.50 BSC L L1 0.30 0.00 0O 0.40 - - 0.50 0.15 14O JEDEC Registration MO-220, Variation VKKD-6, Issue K, June 2006. 7KLVGLPHQVLRQLVQRWVSHFLHGLQWKH-('(&GUDZLQJ 7KLVGLPHQVLRQGLIIHUVIURPWKH-('(&GUDZLQJ Drawings are not to scale. 2019 Microchip Technology Inc. DS20005740A-page 15 MD1711 NOTES: DS20005740A-page 16 2019 Microchip Technology Inc. MD1711 APPENDIX A: REVISION HISTORY Revision A (April 2019) * Converted Supertex Doc# DSFP-MD1711 to Microchip DS20005740A * Changed package marking formats * Changed the quantity of the 48-lead LQFP FG M931 media type from 3000/Reel to 1000/Reel * Changed the quantity of the 48-lead VQFN K6 package from 250/Tray to 260/Tray * Changed the quantity of the 48-lead VQFN K6 M933 media type from 2000/Reel to 3000/Reel * Made minor text changes throughout the document 2019 Microchip Technology Inc. DS20005740A-page 17 MD1711 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office. XX PART NO. - Package Options Device X - Environmental X Media Type Device: MD1711 = High-Speed Integrated Ultrasound Driver IC Packages: FG = 48-lead LQFP K6 = 48-lead VQFN Environmental: G = Lead (Pb)-free/RoHS-compliant Package Media Types: (blank) = 250/Tray for an FG Package = 260/Tray for a K6 Package M931 = 1000/Reel for an FG Package M933 = 3000/Reel for a K6 Package DS20005740A-page 18 Examples: a) MD1711FG-G: High-Speed Integrated Ultrasound Driver IC, 48-lead LQFP, 250/Tray b) MD1711FG-G-M931: High-Speed Integrated Ultrasound Driver IC, 48-lead LQFP, 1000/Reel c) MD1711K6-G: High-Speed Integrated Ultrasound Driver IC, 48-lead VQFN, 260/Tray d) MD1711K6-G-M933: High-Speed Integrated Ultrasound Driver IC, 48-lead VQFN, 3000/Reel 2019 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." 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Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2019, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-4413-8 == ISO/TS 16949 == 2019 Microchip Technology Inc. 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