2019 Microchip Technology Inc. DS20005740A-page 1
MD1711
Features
• Drives Two Ultrasound Transducer Channels
• Generates a Five-Level Waveform
• Drives 12 High-Voltage MOSFETs
• ±2A Source-and-Sink Peak Currents
• Up to 20 MHz Output Frequency
• 12 V/ns Slew Rate
• ±3 ns Matched Delay Times
• Less than –40 dB Second Harmonic
• Two Separate Gate Drive Voltages
• 1.8V to 3.3V CMOS Logic Interface
Applications
• Medical Ultrasound Imaging
• Piezoelectric Transducer Drivers
• Non-Destructive Testing (NDT)
• Metal Flaw Detection
• Sonar Transmitter
General Description
The MD1711 is a two-channel logic controller circuit
with low-impedance MOSFET gate drivers. It is
intended to be used with external FETs as a five-level
high-voltage and high-speed transmitter. The MD1711
is designed for medical ultrasound imaging
applications but can also be used for metal flaw
detection, NDT and for driving piezoelectric
transducers.
The MD1711 has two sets of control logic inputs, one
for Channel A and one for Channel B. Each channel
consists of three pairs of MOSFET gate drivers. These
drivers are designed to match the drive requirements of
the TC6320. One MD1711 drives six TC6320s. Each
driver consists of an N-channel and a P-channel
MOSFET. They are designed to have the same
impedance and can provide peak currents of 2 amps.
Package Types
48-lead LQFP
(Top view)
See Table 2-1 for pin information.
48-lead QFN
(Top view)
1
48
1
48
High-Speed Integrated Ultrasound Driver IC
MD1711
DS20005740A-page 2 2019 Microchip Technology Inc.
Functional Block Diagram
10nF
10nF
+100V
1.0µF
DVDD1
10nF
10nF
10nF
10nF
10nF
10nF
TC6320
DVDD2
AVDD1
VLL
SEL
EN
AVSS
DVSS
AGND
DGND
POSA/POS1A
CLAMPA
NEGA/NEG1A
HVEN1A/POS2A
HVEN2A/NEG2A
POSB/POS1B
CLAMP
NEGB/NEG1B
HVEN1B/POS2B
HVEN2B/NEG2B
DV
DD
1
V
SS
Piezoelectric
Transducer A
Control
Logic
and
Level
Translate
MD1711
-100V
1.0µF
+100V
1.0µF
-100V
1.0µF
+100V
1.0µF
-100V
1.0µF
+100V
1.0µF
-100V
1.0µF
DV
DD
1
DV
DD
1
DV
DD
2
DV
DD
2
DV
DD
1
DV
DD
1
V
SS
DV
DD
1
DV
DD
2
DV
DD
2
Piezoelectric
Transducer B
2019 Microchip Technology Inc. DS20005740A-page 3
MD1711
Typical Application Circuit
VNN1
TC6320
+100V
-100V
+50V
-50V
0V
0V
30
32
34
44
39
41
37
DVDD2
VSS
DVSS
-10V
DVDD1 DVDD2
16
19 21
+10V
VLL
+3.3V
AVSS
48
14
15
AVSS
SEL
POSA / POS1A
EN
DGNDAGND
0
MD1711
(1/2 of I/O)
SUB
718
AVSS
33
36
28 25
31
DGND
35
40 42
43
DVSS
45
FB
AVDD1
6
0
46
47
13
1
2
3
4
5
OUTPA1
OUTNA1
OUTPA2
OUTNA2
OUTPA3
OUTNA3
DGND
DGND
+5.0V
DVDD1
+10V
DVDD2
+5.0V
+10V
+10V
26
DGND
+10V
-10V
-10V
DVDD2DVDD1
DVDD1
Transducer
0.22µF
Control Logic
& Level
Translator
NEGA / NEG1A
HVEN1A / POS2A
HVEN2A / NEG2A
ClampA
0.1µF
0.1µF
0.1µF
0.22µF
0.22µF
0.22µF
0.22µF
0.22µF
0.1µF
10nF
10nF
10nF
10nF
1µF
1µF
1µF
1µF
VNN2
VPP2
VPP1
DVDD2
DVDD1
DVDD1
DVDD1
DVDD2 DVDD1
MD1711
DS20005740A-page 4 2019 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
Logic Supply Voltage, VLL ....................................................................................................................... –0.5V to +5.5V
Positive Gate Drive Supply, AVDD1, DVDD1, DVDD2 ..................................................................................–0.5V to +15V
Negative Gate Drive Supply, AVSS, DVSS .................................................................................................–15V to +0.5V
Operating Junction Temperature, TJ........................................................................................................ 0°C to +125°C
Storage Temperature, TS ..................................................................................................................... –65°C to +150°C
Power Dissipation (48-lead LQFP) ....................................................................................................................... 1.92W
Power Dissipation (48-lead QFN) ......................................................................................................................... 5.55W
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
OPERATING SUPPLY VOLTAGES AND CURRENTS
Electrical Specifications: Over operating conditions unless otherwise specified, AVDD1 = DVDD1 = DVDD2 = 10V,
AVSS = DVSS = –10V, VLL = 3.3V, TA = 25°C.
Parameter Sym. Min. Typ. Max. Unit Conditions
Logic Supply VLL 1.8 3.3 5 V
Positive Drive Bias Supply AVDD1 8 10 12.6 V
Positive Gate Drive Supply DVDD1 4.75 — 12.6 V
Positive Gate Drive Supply DVDD2 4.75 — 12.6 V
Negative Gate Drive and Bias Supply AVSS, DVSS –12 –10 –8 V
Logic Supply Current IVLL — 2 — mA
All channels on at 5 MHz,
no load
Positive Bias Current IAVDD1 — 5 — mA
Negative Drive and Bias Supply
Currents IAVSS, IDVSS — 20 — mA
Positive Drive Current 1 IDVDD1 — 55 — mA
Positive Drive Current 2 IDVDD2 — 13 — mA All channels on at 5 MHz,
DVDD2 = 5V, no load
VAVDD1 Quiescent Current IAVDD1Q — 2 — mA
EN = low, all inputs low or
high
VAVSS Quiescent Current IAVSSQ — 0.75 — mA
VDVDD1 Quiescent Current IDVDD1Q — — 10 µA
VDVDD2 Quiescent Current IDVDD2Q — — 10 µA
Logic Supply Current IVLLQ — 1 — mA
2019 Microchip Technology Inc. DS20005740A-page 5
MD1711
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Over operating conditions unless otherwise specified, AVDD1 = DVDD1 = DVDD2 = 10V,
AVSS = DVSS = –10V, VLL = 3.3V, TA = 0°C to 70°C.
Parameter Sym. Min. Typ. Max. Unit Conditions
P-CHANNEL AND N-CHANNEL GATE DRIVER OUTPUTS
Output Sink Resistance P-Channel RSINK
— — 6 Ω ISINK = 100 mA
N-Channel — — 10 Ω ISINK = 100 mA
Output Source resistance P-Channel RSOURCE
— — 6 Ω ISOURCE = 100 mA
N-Channel — — 10 Ω ISOURCE = 100 mA
Peak Output Sink Current P-Channel ISINK
— 2 — A
N-Channel — 1.5 — A
Peak Output Source Current P-Channel ISOURCE
— 2 — A
N-Channel — 1.5 — A
LOGIC INPUTS
Input Logic High Voltage VIH 0.8 VLL — VLL V
Input Logic Low Voltage VIL 0 — 0.2 VLL V
Input Logic High Current IIH — — 1 µA
Input Logic Low Current IIL –1 — — µA
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Over operating conditions unless otherwise specified, AVDD1 = DVDD1 = DVDD2 = 10V,
AVSS = DVSS = –10V, VLL = 3.3V, TA = 0°C to 70°C.
Parameter Sym. Min. Typ. Max. Unit Conditions
Output Frequency Range fOUT — — 20 MHz
Propagation Delay when Output
is from Low to High tPH — 19 — ns No load
(See Timing Waveforms.)
Propagation Delay when Output
is from High to Low tPL — 19 — ns No load
(See Timing Waveforms.)
Output Rise Time tr— 8 — ns 1000 pF load
(See Timing Waveforms.)
Output Fall Time tf— 8 — ns 1000 pF load
(See Timing Waveforms.)
Delay Time Matching ΔtDM — — ±3 ns No load, from device to
device
Output Jitter ΔtDLAY — 30 — ps Standard deviation of tD
samples (1 kHz)
Output Slew Rate SR — 12 — V/ns Measured at TC6320 out-
put with 100Ω load
Second Harmonic Distortion HD2 — –40 — dB
MD1711
DS20005740A-page 6 2019 Microchip Technology Inc.
TEMPERATURE SPECIFICATIONS
Parameter Sym. Min. Typ. Max. Unit Conditions
TEMPERATURE RANGE
Operating Junction Temperature TJ0 — +125 °C
Storage Temperature TS–65 — +150 °C
PACKAGE THERMAL RESISTANCE
48-lead LQFP JA — 52 — °C/W
48-lead QFN JA — 18 — °C/W
2019 Microchip Technology Inc. DS20005740A-page 7
MD1711
Timing Waveforms
POSA/POS1A
NEGA/NEG1A
0V
VLL
HVEN2A/NEG2A
VPP1
VNN1
VPP2
VNN2
HVOUTA
tr1, rise time from
0.9VNN1 to 0.9VPP1
fOUT
0V
3.3V
IN
tPH
10%
90%
50%
0V
10V
50%
OUT
tPL
tr
90%
10%
t
tf1, fall time from
0.9VPP1 to 0.9VNN1
tr2, rise time from
0.9VNN2 to 0.9VPP2
tf2, fall time from
0.9VPP2 to 0.9VNN2
VLL
VLL
VLL
0V
0V
0V
0V
HVEN1A/POS2A
MD1711
DS20005740A-page 8 2019 Microchip Technology Inc.
2.0 PIN DESCRIPTION
Functional descriptions for the pins are listed in
Table 2-1. See Package Types for the location of pins.
TABLE 2-1: PIN FUNCTION TABLE
Pin Number Pin Name Description
1 POSA/POS1A Logic input control for Channel A. When SEL = L, the pin is POSA.
When SEL = H, the pin is POS1A.
2 NEGA/NEG1A Logic input control for Channel A. When SEL = L, the pin is NEGA.
When SEL = H, the pin is NEG1A.
3 HVEN1A/POS2A Logic input control for Channel A. When SEL = L, the pin is HVEN1A.
When SEL = H, the pin is POS2A.
4 HVEN2A/NEG2A Logic input control for Channel A. When SEL = L, the pin is HVEN2A.
When SEL = H, the pin is NEG2A.
5 CLAMPA Used with SEL = H. Logic input control for OUT–PA3 and OUT–NA3. Connect to
ground when SEL = L.
6 AVDD1 Supplies analog circuitry portion of the gate driver. Should be at the same poten-
tial as DVDD1.
7 AGND Analog Ground
8 CLAMPB Used with SEL = H. Logic input control for OUT–PB3 and OUT–NB3.
Connect to ground when SEL = L.
9 HVEN2B/NEG2B Logic input control for Channel B. When SEL = L, the pin is HVEN2B.
When SEL = H, the pin is NEG2B.
10 HVEN1B/POS2B Logic input control for Channel B. When SEL = L, the pin is HVEN1B.
When SEL = H, the pin is POS2B.
11 NEGB/NEG1B Logic input control for Channel B. When SEL = L, the pin is NEGB.
When SEL = H, the pin is NEG1B.
12 POSB/POS1B Logic input control for Channel B. When SEL = L, the pin is POSB.
When SEL = H, the pin is POS1B.
13 SEL Logic input select. See Table 3-2 for SEL = L and Table 3-3 for SEL = H.
14 AVSS Negative driver supply for OUT–PA3, OUT–PB3 and bias circuits. It is also con-
nected to the IC substrate. It should be connected to the most negative potential.
15
16 DVSS Gate drive supply voltage for OUT–PA3 and OUT–PB3. Supplies digital circuitry
portion and the main output stage. Should be at the same potential as AVSS.
17 OUT-PB3 Output P-channel gate driver for Channel B
18 DGND Digital Ground
19 DVDD1
Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and
the main output stage for OUT–PA2, OUT–NA2, OUT–NA3, OUT–PB2,
OUT–NB2 and OUT–NB3. Should be at the same potential as AVDD1.
20 Out-PB2 Output P-channel gate driver for Channel B
21 DVDD2
Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and
the main output stage for OUT–PA1, OUT–NA1, OUT–PB1 and OUT–NB1.
Can be at a different potential compared to DVDD1.
22 Out-PB1 Output P-channel gate driver for Channel B
23 N/C No connect
24 Out-NB1 Output N-channel gate driver for Channel B
2019 Microchip Technology Inc. DS20005740A-page 9
MD1711
25 DVDD2
Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and
the main output stage for OUT–PA1, OUT–NA1, OUT–PB1 and OUT–NB1. Can
be at a different potential compared to DVDD1.
26 DGND Digital Ground
27 Out-NB2 Output N-channel gate driver for Channel B
28 DVDD1
Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and
the main output stage for OUT–PA2, OUT–NA2, OUT–NA3, OUT–PB2,
OUT–NB2 and OUT–NB3. Should be at the same potential as AVDD1.
29 Out-NB3 Output N-channel gate driver for Channel B
30 DGND Digital Ground
31 DVDD1
Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and
the main output stage for OUT–PA2, OUT–NA2, OUT–NA3, OUT–PB2,
OUT–NB2 and OUT–NB3. Should be at the same potential as AVDD1.
32 OUT-NA3 Output N-channel gate drivers for Channel A
33 DVDD1
Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and
the main output stage for OUT–PA2, OUT–NA2, OUT–NA3, OUT–PB2,
OUT–NB2 and OUT–NB3. Should be at the same potential as AVDD1.
34 Out-NA2 Output N-Channel gate drivers for Channel A
35 DGND Digital Ground
36 DVDD2
Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and
the main output stage for OUT–PA1, OUT–NA1, OUT–PB1 and OUT–NB1. Can
be at a different potential compared to DVDD1.
37 Out-NA1 Output N-channel gate drivers for Channel A
38 N/C No connect
39 Out-PA1 Output P-channel gate drivers for Channel A
40 DVDD2
Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and
the main output stage for OUT–PA1, OUT–NA1, OUT–PB1 and OUT–NB1. Can
be at a different potential compared to DVDD1.
41 OUT-PA2 Output P-channel gate drivers for Channel A
42 DVDD1
Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and
the main output stage for OUT–PA2, OUT–NA2, OUT–NA3, OUT–PB2,
OUT–NB2 and OUT–NB3. Should be at the same potential as AVDD1.
43 DGND Digital Ground
44 Out-PA3 Output P-channel gate drivers for Channel A
45 DVSS Gate drive supply voltage for OUT–PA3 and OUT–PB3. Supplies digital circuitry
portion and the main output stage. Should be at the same potential as AVSS.
46 VLL Logic supply voltage
47 EN Logic input enable control. When EN = L, all P-channel output drivers are high
and all N-channel output drivers are low.
48 AVSS Negative driver supply for OUT–PA3, OUT–PB3 and bias circuits. It is also con-
nected to the IC substrate. It should be connected to the most negative potential.
Center Pad AVSS For the QFN package, the center pad is at AVSS potential. It should be externally
connected to AVSS.
TABLE 2-1: PIN FUNCTION TABLE
Pin Number Pin Name Description
MD1711
DS20005740A-page 10 2019 Microchip Technology Inc.
3.0 DETAILED DESCRIPTION
FIGURE 3-1: Test Circuit for Channel A.
TABLE 3-1: POWER-UP SEQUENCE
Step Connection Description
1 AVSS, DVSS Negative gate drive supply and substrate bias
2 VLL, AVDD1, DVDD1 and DVDD2 Logic supply, positive gate drive supply and bias
DVDD2
GPA1
HVOUTPA1
OUT-NA3
RLOAD
100
HVOUTA
10nF
10nF
+10V AVDD1
+10V DVDD1
+10VDVDD2
+3.3V VLL
EN
POSA/POS1A
NEGA/NEG1A
HVEN1A/POS2A
HVEN2A/NEG2A
CLAMPA
SEL
AGND
DGND
AVSS
DVSS
-10V
+100V
-100V
+50V
-50V
1/2 of MD1711 3x TC6320
Channel A
Control
Logic and
Level
Translation
DVDD2
DVDD1
DVDD1
DVDD1
DVSS
VPP1
VPP2
VNN1
VNN2
OUT-PA3
OUT-NA2
OUT-PA2
OUT-NA1
OUT-PA1
10nF
10nF
HVOUTNA1
HVOUTPA2
HVOUTNA2
HVOUTPA3
HVOUTNA3
GNA1
GPA2
GNA2
GPA3
GNA3
VPP3
VNN3
2019 Microchip Technology Inc. DS20005740A-page 11
MD1711
TABLE 3-2: TRUTH FUNCTION TABLE FOR CHANNELS A AND B (FOR SEL = L)
Logic Control Inputs VPP1 to VNN1
Output
VPP2 to VNN2
Output
VPP3 to VNN3
Output
SEL EN HVEN1/
POS2
HVEN2/
NEG2 Clamp POS/
POS1
NEG/
NEG1 HVOUTP1 HVOUTN1 HVOUTP2 HVOUTN2 HVOUTP3 HVOUTN3
0100000
OFF OFF
ON ON
0100001 ON ON
0100010 ON ON
0100011 OFF OFF
0100100
OFF OFF OFF
0100101
0100110
0100111
0101000
OFF
OFF OFF ON ON
0101001 OFF ON OFF OFF
0101010 ON OFF OFF OFF
0101011 OFF OFF OFF OFF
0101100
OFF OFF OFF
0101101
0101110
0101111
0110000OFF OFF
OFF
ON ON
0110001OFF ON OFF OFF
0110010ON OFF OFF OFF
0110011OFF OFF OFF OFF
0110100
OFF OFF OFF
0110101
0110110
0110111
0111000
OFF OFF OFF
0111001
0111010
0111011
0111100
OFF OFF OFF
0111101
0111110
0111111
0 0 X X X X X OFF OFF OFF
MD1711
DS20005740A-page 12 2019 Microchip Technology Inc.
TABLE 3-3: TRUTH FUNCTION TABLE FOR CHANNELS A AND B (FOR SEL = H)
Logic Control Inputs VPP1 to VNN1
Output
VPP2 to VNN2
Output
VPP3 to VNN3
Output
SEL EN HVEN1/
POS2
HVEN2/
NEG2 Clamp POS/
POS1
NEG/
NEG1 HVOUTP1 HVOUTN1 HVOUTP2 HVOUTN2 HVOUTP3 HVOUTN3
1100000OFF OFF
OFF OFF OFF
1100001OFF ON
1100010ON OFF
1100011ON ON
1100100OFF OFF
OFF ON OFF
1100101OFF ON
1100110ON OFF
1100111ON ON
1101000OFF OFF
ON OFF OFF
1101001OFF ON
1101010ON OFF
1101011ON ON
1101100OFF OFF
ON ON OFF
1101101OFF ON
1101110ON OFF
1101111ON ON
1110000OFF OFF
OFF OFF ON
1110001OFF ON
1110010ON OFF
1110011ON ON
1110100OFF OFF
OFF ON ON
1110101OFF ON
1110110ON OFF
1110111ON ON
1111000OFF OFF
ON OFF ON
1111001OFF ON
1111010ON OFF
1111011ON ON
1111100OFF OFF
ON ON ON
1111101OFF ON
1111110ON OFF
1111111ON ON
1 0 X X X X X OFF OFF OFF OFF OFF
2019 Microchip Technology Inc. DS20005740A-page 13
MD1711
4.0 PACKAGING INFORMATION
4.1 Package Marking Information
48-lead LQFP Example
NNN
YYWW
XXXXXXX
XXXXXX
e3
525
1930
1711FG
MD
e3
48-lead QFN
XXXXXXXX
YYWWNNN
e3
Example
MD1711K6
1914325
e3
Legend: XX...X Product Code or Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available characters
for product code or customer-specific information. Package may or not include
the corporate logo.
3
e
3
e
MD1711
DS20005740A-page 14 2019 Microchip Technology Inc.
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
2019 Microchip Technology Inc. DS20005740A-page 15
MD1711
48-Lead QFN Package Outline (K6)
7.00x7.00mm body, 1.00mm height (max), 0.50mm pitch
Symbol A A1 A3 b D D2 E E2 e L L1 ș
Dimension
(mm)
MIN 0.80 0.00 0.20
REF
0.18 6.85* 1.25 6.85* 1.25 0.50
BSC
0.30
†
0.00 0
O
NOM 0.90 0.02 0.25 7.00 - 7.00 - 0.40
†
--
MAX 1.00 0.05 0.30 7.15* 5.45 7.15* 5.45 0.50
†
0.15 14
O
JEDEC Registration MO-220, Variation VKKD-6, Issue K, June 2006.
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7KLVGLPHQVLRQGLIIHUVIURPWKH-('(&GUDZLQJ
Drawings are not to scale.
Notes:
1. $3LQLGHQWL¿HUPXVWEHORFDWHGLQWKHLQGH[DUHDLQGLFDWHG7KH3LQLGHQWL¿HUFDQEHDPROGHGPDUNLGHQWL¿HUDQHPEHGGHGPHWDOPDUNHURU
a printed indicator.
2. 'HSHQGLQJRQWKHPHWKRGRIPDQXIDFWXULQJDPD[LPXPRIPPSXOOEDFN/PD\EHSUHVHQW
3. 7KHLQQHUWLSRIWKHOHDGPD\EHHLWKHUURXQGHGRUVTXDUH
Seating
Plane
Top View
Side View
Bottom View
A
A1
D
E
D2
b
E2
A3
L
L1
View B
View B
1
Note 3
Note 2
Note 1
(Index Area
D/2 x E/2)
Note 1
(Index Area
D/2 x E/2)
e
48
1
48
θ
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
MD1711
DS20005740A-page 16 2019 Microchip Technology Inc.
NOTES:
2019 Microchip Technology Inc. DS20005740A-page 17
MD1711
APPENDIX A: REVISION HISTORY
Revision A (April 2019)
• Converted Supertex Doc# DSFP-MD1711 to
Microchip DS20005740A
• Changed package marking formats
• Changed the quantity of the 48-lead LQFP FG
M931 media type from 3000/Reel to 1000/Reel
• Changed the quantity of the 48-lead VQFN K6
package from 250/Tray to 260/Tray
• Changed the quantity of the 48-lead VQFN K6
M933 media type from 2000/Reel to 3000/Reel
• Made minor text changes throughout the docu-
ment
MD1711
DS20005740A-page 18 2019 Microchip Technology Inc.
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
Examples:
a) MD1711FG-G: High-Speed Integrated
Ultrasound Driver IC,
48-lead LQFP, 250/Tray
b) MD1711FG-G-M931: High-Speed Integrated
Ultrasound Driver IC,
48-lead LQFP, 1000/Reel
c) MD1711K6-G: High-Speed Integrated
Ultrasound Driver IC,
48-lead VQFN, 260/Tray
d) MD1711K6-G-M933: High-Speed Integrated
Ultrasound Driver IC,
48-lead VQFN, 3000/Reel
PART NO.
Device
Device: MD1711 = High-Speed Integrated Ultrasound Driver IC
Packages: FG = 48-lead LQFP
K6 = 48-lead VQFN
Environmental: G = Lead (Pb)-free/RoHS-compliant Package
Media Types: (blank) = 250/Tray for an FG Package
= 260/Tray for a K6 Package
M931 = 1000/Reel for an FG Package
M933 = 3000/Reel for a K6 Package
XX
Package
- X - X
Environmental
Media Type
Options
2019 Microchip Technology Inc. DS20005740A-page 19
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo,
JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo,
SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity,
JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon,
QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O,
SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2019, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-4413-8
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITYMANAGEMENTSYSTEM
CERTIFIEDBYDNV
== ISO/TS16949==
DS20005740A-page 20 2019 Microchip Technology Inc.
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08/15/18