(R) Using Selectable I/O Standards in APEX 20KE, APEX 20KC & MAX 7000B Devices October 2001, ver. 2.1 Introduction Application Note 117 High-performance, low-voltage I/O standards have been introduced to keep pace with increasing clock speeds, higher data rates, and new low-voltage devices. These I/O standards are used to interface with memory, microprocessors, backplanes, and peripheral devices. Designers who want to use these new standards with programmable logic need flexible, high-performance, multi-standard I/O buffers. Altera's revolutionary APEXTM 20KE and APEX 20KC devices offer the highest density, highest performance programmable logic solution with the necessary I/O standards for the communication and computer industries. Altera(R) MAX(R) 7000B devices are the product-term leader in I/O standard support: MAX 7000B devices are the only macrocell-based devices to support GTL+, 2.5-V SSTL-2, and 3.3-V SSTL-3. With the new programmable I/O standards supported by APEX 20KE and MAX 7000B devices, a single device can simultaneously support multiple I/O standards, as well as interface with high-speed, low-voltage memory buses and backplanes. These I/O standards include LVDS, which supports data rates up to 840 megabits per second (Mbps). Embedding I/O standard support in programmable logic devices (PLDs) simplifies board design. Dedicated circuitry like LVDS transceivers is integrated into PLDs, saving board space, reducing pin usage, and improving performance. This application note provides guidelines for designing with selectable I/O standards in Altera devices and covers the following topics: Overview of I/O Standards & Applications Altera Corporation A-AN-117-2.1 Overview of I/O standards and applications APEX 20KE, APEX 20KC and MAX 7000B I/O standard support Operating conditions Board termination schemes APEX 20K family I/O standard software support The ability for PLDs to support industry I/O standards gives customers a quick time-to-market design solution. This section provides an overview of typical applications for the selectable I/O standards supported by Altera devices. The specifications for each I/O standard are listed in this section. 1 AN 117: Using Selectable I/O Standards In APEX 20KE, APEX 20KC & MAX 7000B Devices LVTTL The LVTTL standard is a single-ended, general-purpose standard for 3.3-V applications. The LVTTL interface is defined by JEDEC Standard JESD 8-A, Interface Standard for Nominal 3.0 V/3.3 V Supply Digital Integrated Circuits. The LVTTL output buffer is a push-pull driver. This standard requires the output buffer to drive to 2.4 V (minimum VOH = 2.4 V). It does not require the use of input reference voltages or termination. APEX 20K, APEX 20KE, and MAX 7000B devices are compliant with this standard. The maximum recommended input voltage for APEX and MAX 7000B devices is 4.1 V, which exceeds the 3.9-V requirement of this specification. LVCMOS The LVCMOS standard is defined in JEDEC Standard JESD 8-A, Interface Standard for Nominal 3.0 V/3.3 V Supply Digital Integrated Circuits. LVCMOS is a single-ended general-purpose standard also used for 3.3-V applications. The input buffer requirements are the same as the LVTTL requirements, and the output buffer is required to drive to the rail (minimum VOH = VCCIO - 0.2 V). This standard requires a 3.3-V I/O supply voltage (VCCIO), but not the use of input reference voltages or termination. APEX 20K, APEX 20KE, APEX 20KC and MAX 7000B devices are compliant with the LVCMOS standard. 2.5 V The 2.5-V I/O standard is documented by JEDEC Standard JESD 8-5, 2.5 V 0.2 V (Normal Range) and 1.7 V to 2.7 V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit. This standard is similar to LVCMOS but is used for 2.5-V power supply levels. APEX 20K, APEX 20KE, APEX 20KC and MAX 7000B devices are compliant with this standard, which requires a 2.5-V VCCIO, but not the use of input reference voltages or termination. 1.8 V The 1.8-V I/O standard is documented by JEDEC Standard JESD 8-7, 1.8 V 0.15 V (Normal Range) and 1.2 V to 1.95 V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit. This standard is similar to LVCMOS but is used for 1.8-V power supply levels and reduced input and output thresholds. APEX 20K, APEX 20KE, APEX 20KC and MAX 7000B devices are compliant with this standard, which requires a 1.8-V VCCIO, but not the use of input reference voltages or termination. 2 Altera Corporation AN 117: Using Selectable I/O Standards In APEX 20KE, APEX 20KC & MAX 7000B Devices 3.3-V PCI APEX 20K, APEX 20KE and APEX 20KC devices are compliant with PCI Local Bus Specification, Revision 2.2 for 3.3-V operation. At 3.3 V, the PCI standard supports up to 64-bit bus width operation at 33 or 66 MHz. This standard uses LVTTL-type input and output buffers and requires a 3.3-V VCCIO , but not the use of input reference voltages or termination. MAX 7000B devices are compliant with all aspects of this standard except that they do not offer clamps to VCCIO. PCI-X The PCI-X standard is an enhanced version of the PCI standard that can support higher average bandwidth and has more stringent requirements. The APEX 20KE and APEX 20KC I/O drivers meet the requirements for PCI-X. In the Quartus IITM software, set the buffer setting to PCI to support PCI-X requirements, including the overshoot clamp. A future version of the Quartus II software will include the ability to choose PCI-X as an I/O standard. LVDS The LVDS I/O standard is used for very high-performance, low-power-consumption data transfer. Two key industry standards define LVDS: IEEE 1596.3 SCI-LVDS and ANSI/TIA/EIA-644. Both standards have similar key features, but the IEEE standard supports a maximum data transfer of 250 Mbps. APEX 20KE devices are designed to meet the ANSI/TIA/EIA-644 requirements at up to 840 Mbps. The LVDS standard requires a 3.3-V VCCIO and a 100-3/4 termination resistor between the two traces at the input buffer. No input reference voltage is required. f For more information on LVDS, see the Altera web site at http://www.altera.com. LVPECL The LVPECL standard is a differential I/O standard that is similar to LVDS. APEX 20KE devices can support LVPECL I/O standard by using the I/O pins in LVDS mode with an external resistor network. Altera Corporation 3 AN 117: Using Selectable I/O Standards In APEX 20KE, APEX 20KC & MAX 7000B Devices GTL+ The GTL+ standard is a high-speed bus standard first used by Intel Corporation for interfacing with the Pentium Pro processor and is often used for processor interfacing or communication across a backplane. GTL+ is a voltage-referenced standard requiring a 1.0-V input reference voltage (VREF) and board termination voltage (VTT) of 1.5 V. The GTL+ standard is an open-drain standard that requires a minimum VCCIO supply voltage of 3.0 V. APEX 20KE and MAX 7000B devices are compliant with this standard. SSTL-2 Class I & II The SSTL-2 standard, specified by JEDEC Standard JESD 8-9, Stub-Series Terminated Logic for 2.5 Volts (SSTL-2), is a voltage-referenced standard requiring a 1.25-V VREF, a 2.5-V VCCIO, and a 1.25-V VTT. SSTL-2 is used for high-speed SDRAM interfaces. APEX 20KE, APEX 20KC and MAX 7000B devices are compliant with this standard. SSTL-3 Class I & II The SSTL-3 standard, specified by JEDEC Standard JESD 8-8, Stub-Series Terminated Logic for 3.3 Volts (SSTL-3), is a voltage-referenced standard requiring a 1.5-V VREF, a 3.3-V VCCIO, and a 1.5-V VTT. SSTL-3 is used for high-speed SDRAM interfaces. APEX 20KE, APEX 20KC and MAX 7000B devices are compliant with this standard. HSTL Class I The HSTL standard, specified by JEDEC Standard JESD 8-6, High-Speed Transceiver Logic (HSTL), is a 1.5 V output buffer supply voltage based interface standard for digital integrated circuits. HSTL is a voltage-referenced standard requiring a 0.75-V VREF, a 1.5-V VCCIO, and a 0.75-V VTT. APEX 20KE and APEX 20KC devices support HSTL Class I operation with a VCCIO voltage of 1.8 V. APEX 20KE and APEX 20KC devices drive compliant VOH and VOL levels with VCCIO at 1.8 V. AGP The AGP standard is specified by the Advanced Graphics Port Interface Specification Revision 2.0 introduced by Intel Corporation for graphics applications. AGP is a voltage-referenced standard requiring a 1.32-V VREF and a 3.3-V VCCIO . AGP does not require termination. APEX 20KE and APEX 20KC devices support the AGP interface. 4 Altera Corporation AN 117: Using Selectable I/O Standards In APEX 20KE, APEX 20KC & MAX 7000B Devices CTT The CTT standard is specified by JEDEC Standard JESD 8-4, Center-Tap-Terminated (CTT) Low-Level, High-Speed Interface Standard for Digital Integrated Circuits. CTT is a voltage-referenced standard requiring a 1.5-V VREF, a 3.3-V VCCIO, and a 1.5-V VTT. The CTT standard is a superset of LVTTL and LVCMOS. CTT receivers are compatible with LVCMOS and LVTTL standards. CTT drivers, when unterminated, are compatible with the AC and DC specifications for LVCMOS and LVTTL. APEX 20KE & MAX 7000B I/O Standards Support The APEX 20KE I/O blocks support 16 I/O standards and are the only PLDs in the industry with LVDS. MAX 7000B devices provide support for GTL+, SSTL-2, and SSTL-3, a unique feature among product-term-based PLDs. The programmable input/output element (IOE) blocks in both APEX 20KE and MAX 7000B devices have individual power supplies with separate I/O supply voltage (VCCIO) pins for each I/O block. The VCCIO supply supports 3.3-V, 2.5-V, and 1.8-V levels. APEX 20KE & MAX 7000B I/O Standards The APEX 20KE and MAX 7000B I/O buffers meet the voltage, drive strength, and AC characteristics necessary to comply with the I/O standards listed in Table 1. Altera Corporation 5 AN 117: Using Selectable I/O Standards In APEX 20KE, APEX 20KC & MAX 7000B Devices Table 1. APEX 20KE & MAX 7000B Supported I/O Standards I/O Standard Device Type Input Output Supply Board Reference Voltage Termination Voltage (VCCIO) (V) (1) Voltage (VREF) (V) (1) (VTT) (V) (1) APEX 20KE MAX 7000B LVTTL v v Single-ended N/A 3.3 N/A LVCMOS v v Single-ended N/A 3.3 N/A 2.5 V v v Single-ended N/A 2.5 N/A 1.8 V v v Single-ended N/A 1.8 N/A PCI v v(2) Single-ended N/A 3.3 N/A PCI-X v Single-ended N/A 3.3 N/A LVDS v Differential N/A N/A N/A LVPECL v Differential N/A 3.3 N/A GTL+ v v Voltage-referenced 1.0 N/A 1.5 SSTL-2 Class I and II v v Voltage-referenced 1.25 2.5 1.25 SSTL-3 Class I and II v v Voltage-referenced 1.5 3.3 1.5 HSTL Class I v Voltage-referenced 0.75 1.8 (3) 0.75 AGP v Voltage-referenced 1.32 3.3 N/A CTT v Voltage-referenced 1.5 3.3 1.5 Notes: (1) (2) (3) The values shown for VREF, VCCIO, and VTT are typical values. MAX 7000B devices do not have the PCI diode clamp to V CCIO. These devices comply with all other 64-bit/66-MHz 3.3-V PCI specifications. APEX 20KE devices drive HSTL-compliant signal levels with V CCIO corrected to a 1.8-V supply. f Each I/O standard has different VREF, VTT, and VCCIO requirements. For more information, refer to "Board Termination Schemes" on page 14. APEX 20KE I/O Standards The I/O banks in the APEX 20KE devices support 16 I/O standards and are the first programmable logic devices (PLDs) in the industry with dedicated LVDS circuitry. APEX 20KE devices in BGA and FineLine BGATM packages have eight programmable I/O banks and two LVDS I/O blocks (one transmitter block and one receiver block) within two of the I/O banks. The programmable input/output element (IOE) banks in APEX 20KE devices have individual power planes with separate I/O supply voltage (VCCIO) pins for each I/O bank. The VCCIO supply supports 3.3-V, 2.5-V, and 1.8-V levels. 6 Altera Corporation AN 117: Using Selectable I/O Standards In APEX 20KE, APEX 20KC & MAX 7000B Devices APEX 20KE devices in FineLine BGA packages have eight programmable I/O blocks and two LVDS I/O blocks. Figure 1 shows the representation of the I/O blocks. For APEX 20KE designs that do not use LVDS, the LVDS I/O blocks can be used for any other standard. Figure 1. APEX 20KE I/O Blocks I/O Bank 1 I/O Bank 8 LVDS Output Block (2) (1) I/O Bank 2 I/O Bank 3 Regular I/O Banks Support LVTTL LVCMOS 2.5 V 1.8 V 3.3 V PCI PCI-X GTL+ SSTL-2 Class I and II SSTL-3 Class I and II CTT AGP HSTL (1) LVDS Input Block (2) I/O Bank 4 Individual Power Bus I/O Bank 7 I/O Bank 6 I/O Bank 5 Note: (1) (2) The first two I/O pins that border the LVDS blocks can only be used for input to maintain an acceptable noise level on the VCCIO supply. If the LVDS input and output blocks are not used for LVDS, they can support all of the I/O standards and can be used as input, output, or bidirectional pins with VCCIO set to 3.3 V, 2.5 V, or 1.8 V. MAX 7000B I/O Standards Each MAX 7000B device has two programmable I/O blocks. Each I/O block can be configured independently to utilize any of the I/O standards supported by MAX 7000B devices. Additionally, you can use I/O standards with common VCCIO voltages simultaneously within a single block. Each programmable I/O block has its own power supply with separate VCCIO pins and support for 3.3-V, 2.5-V, and 1.8-V voltage levels. Figure 2 shows a representation of the MAX 7000B programmable I/O blocks. Altera Corporation 7 AN 117: Using Selectable I/O Standards In APEX 20KE, APEX 20KC & MAX 7000B Devices Figure 2. MAX 7000B I/O Banks Notes (1), (2), (3) Programmable I/O Banks LVTTL LVCMOS 2.5 V 1.8 V 3.3-V PCI GTL+ SSTL-2 Class I and II SSTL-3 Class I and II Individual Power Bus Notes: (1) (2) (3) Operating Conditions Any input pin can be referenced to one of the two available VREF levels. MAX 7000B devices have two VREF pins that can be referenced by any I/O pin in both I/O blocks. The output drivers are dependent on VCCIO. The VCCIO pins for each I/O block can be powered to a different voltage. Tables 2 through 17 list the DC operating specifications for the supported I/O standards. These tables list minimal specifications only. APEX 20KE and MAX 7000B devices may exceed these specifications. Consult individual device data sheets for details. Table 2. LVTTL I/O Specifications Symbol Parameter VCCIO Output supply voltage Conditions Minimum Maximum Units 3.0 3.6 V V VI H High-level input voltage 2.0 VCCIO + 0.3 VIL Low-level input voltage -0.3 0.8 V II Input pin leakage current VIN = 0 V or 3.3 V -5 10 A VOH High-level output voltage IOH = -4 mA 2.4 VOL Low-level output voltage IOL = 4 mA 0.4 V 8 V Altera Corporation AN 117: Using Selectable I/O Standards In APEX 20KE, APEX 20KC & MAX 7000B Devices Table 3. LVCMOS I/O Specifications Symbol Parameter Conditions Minimum Maximum Units VCCIO Power supply voltage range 3.0 3.6 V VIH High-level input voltage 2.0 VCCIO + 0.3 V VIL Low-level input voltage -0.3 0.8 V II Input pin leakage current VIN = 0 V or 3.3 V -10 10 A VOH High-level output voltage VCCIO = 3.0 V IOH = -0.1 mA VOL Low-level output voltage VCCIO = 3.0 V IOL = 0.1 mA VCCIO - 0.2 V 0.2 V Maximum Units Table 4. 2.5-V I/O Specifications Symbol Parameter Conditions Minimum VCCIO Output supply voltage 2.375 VIH High-level input voltage 1.7 VIL Low-level input voltage II Input pin leakage current VOH High-level output voltage VOL Low-level output voltage -0.3 VIN = 0 V or 3.3 V -10 2.625 V VCCIO + 0.3 V 0.7 10 V A IOH = -0.1 mA 2.1 V IOH = -1 mA 2.0 V IOH = -2 mA 1.7 V IOL = 0.1 mA 0.2 V IOH = 1 mA 0.4 V IOH = 2 mA 0.7 V Table 5. 1.8-V I/O Specifications Symbol Parameter Conditions Minimum Maximum 1.7 1.9 Units VCCIO Output supply voltage VI H High-level input voltage 0.65 x VCCIO VCCIO + 0.3 V VIL Low-level input voltage 0.35 x VCCIO V II Input pin leakage current VIN = 0 V or 3.3 V 10 A VOH High-level output voltage IOH = -2 mA VOL Low-level output voltage IOL = 2 mA Altera Corporation -10 VCCIO - 0.45 V V 0.45 V 9 AN 117: Using Selectable I/O Standards In APEX 20KE, APEX 20KC & MAX 7000B Devices Table 6. 3.3-V PCI Specifications Symbol Parameter VCCIO I/O supply voltage VIH High-level input voltage Conditions Minimum Typical 3.0 3.3 Maximum Units 3.6 V 0.5 x VCCIO VCCIO + 0.5 V -0.5 0.3 x VCCIO V 0 < VIN < VCCIO -10 10 A High-level output voltage IOUT = -500 A 0.9 x VCCIO Low-level output voltage IOUT = 1,500 A VIL Low-level input voltage II Input pin leakage current VOH VOL V 0.1 x VCCIO V Table 7. 3.3-V PCI-X Specifications Symbol Parameter VCCIO Output supply voltage Conditions Minimum Typical Maximum Units 3.0 3.3 3.6 V VI H High-level input voltage 0.5 x VCCIO VCCIO + 0.5 V VIL Low-level input voltage -0.5 0.35 x VCCIO V VIPU Input pull-up voltage IIL Input pin leakage current 0 < VIN < VCCIO 10.0 A 0.7 x VCCIO VOH High-level output voltage Iout = -500 A VOL Low-level output voltage Iout = 1500 A Lpin Pin Inductance V -10.0 0.9 x VCCIO V 0.1 x VCCIO V 15.0 nH Units Table 8. 3.3-V LVDS I/O Specifications Symbol Parameter Conditions VCCIO I/O supply voltage VOD Differential output voltage RL = 100 3/4 y VOD Change in VOD between high and low RL = 100 3/4 VOS Output offset voltage RL = 100 3/4 y VOS Change in VOS between high and low RL = 100 3/4 VTH Differential input threshold VCM = 1.2 V VIN RL 10 Minimum Typical Maximum 3.135 3.3 3.465 V 450 mV 50 mV 250 1.125 1.25 1.375 V 50 mV -100 100 mV Receiver input voltage range 0.0 2.4 V Receiver differential input resistor (external to APEX devices) 90 110 3/4 100 Altera Corporation AN 117: Using Selectable I/O Standards In APEX 20KE, APEX 20KC & MAX 7000B Devices Table 9. GTL+ I/O Specifications Symbol Parameter Conditions Minimum Typical Maximum Units VTT Termination voltage 1.35 1.5 1.65 V VREF Reference voltage 0.88 1.0 1.12 V VREF - 0.1 V 0.65 V Units VIH High-level input voltage VIL Low-level input voltage VOL Low-level output voltage VREF + 0.1 V IOL = 36 mA Table 10. SSTL-2 Class I Specifications Symbol Parameter VCCIO I/O supply voltage VTT Termination voltage VREF Reference voltage Conditions Minimum Typical Maximum 2.375 2.5 2.625 V VREF - 0.04 VREF VREF + 0.04 V 1.15 1.25 1.35 V VIH High-level input voltage VREF + 0.18 VCCIO + 0.3 V VIL Low-level input voltage -0.3 VREF - 0.18 V VOH High-level output voltage IOH = -7.6 mA VOL Low-level output voltage IOL = 7.6 mA VTT - 0.57 V Altera Corporation VTT + 0.57 V 11 AN 117: Using Selectable I/O Standards In APEX 20KE, APEX 20KC & MAX 7000B Devices Table 11. SSTL-2 Class II Specifications Symbol Parameter VCCIO I/O supply voltage VTT Termination voltage VREF Reference voltage VIH High-level input voltage Conditions VIL Low-level input voltage VOH High-level output voltage IOH = -15.2 mA VOL Low-level output voltage IOL = 15.2 mA Minimum Typical Maximum Units 2.375 2.5 2.625 V VREF - 0.04 VREF VREF + 0.04 V 1.15 1.25 1.35 V VREF + 0.18 VCCIO + 0.3 V -0.3 VREF - 0.18 VTT + 0.76 V V VTT - 0.76 V Maximum Units Table 12. SSTL-3 Class I Specifications Symbol Parameter VCCIO I/O Supply voltage VTT Termination voltage VREF Reference voltage VIH High-level input voltage Conditions VIL Low-level input voltage VOH High-level output voltage IOH = -8 mA VOL Low-level output voltage IOL = 8 mA Minimum Typical 3.0 3.3 3.6 V VREF - 0.05 VREF VREF + 0.05 V 1.3 1.5 1.7 V VREF + 0.2 VCCIO + 0.3 V -0.3 VREF - 0.2 VTT + 0.6 V V VTT - 0.6 V Units Table 13. SSTL-3 Class II Specifications Symbol Parameter Conditions VCCIO I/O Supply voltage VTT Termination voltage VREF Reference voltage VIH High-level input voltage VIL Low-level input voltage VOH High-level output voltage IOH = -16 mA VOL Low-level output voltage IOL = 16 mA 12 Minimum Typical Maximum 3.0 3.3 3.6 V VREF - 0.05 VREF VREF + 0.05 V 1.3 1.5 1.7 V VREF + 0.2 VCCIO + 0.3 V -0.3 VREF - 0.2 V VT T + 0.8 V VTT - 0.8 V Altera Corporation AN 117: Using Selectable I/O Standards In APEX 20KE, APEX 20KC & MAX 7000B Devices Table 14. HSTL Class I I/O Specifications Symbol Parameter Conditions VCCIO I/O Supply voltage VTT Termination voltage VREF Reference voltage VIH High-level input voltage VIL Low-level input voltage VOH High-level output voltage IOH = -8 mA VOL Low-level output voltage IOL = 8 mA Minimum Typical Maximum Units 1.71 1.8 1.89 V VREF - 0.05 VREF VREF + 0.05 V 0.68 0.75 0.90 V VREF + 0.1 VCCIO + 0.3 V -0.3 VREF - 0.1 V VCCIO - 0.4 V 0.4 V Table 15. LVPECL Specifications Minimum Typical Maximum Units VCCIO Symbol Output Supply Voltage Parameter 3.135 3.3 3.465 V VIL Low-level input voltage 1300 1700 mV VIH High-level input voltage 2100 2600 mV VOL Low-level output voltage 1450 1650 mV VOH High-level output voltage 2275 2420 mV VID Input Voltage Differential 400 600 950 mV VOD Output Voltage Differential 625 800 950 mV tr, tf Rise/Fall Time (20 to 80%) 85 tDSKEW Differential Skew tO Output Load 150 3/4 RL Receiver differential input resistor 100 3/4 325 ps 25 ps Table 16. 3.3-V AGP I/O Specifications Symbol Parameter Conditions Minimum Typical 3.3 Maximum Units VCCIO I/O supply voltage 3.15 3.45 V VREF Reference voltage 0.39 x VCCIO 0.41 x VCCIO V 0.5 x VCCIO VCCIO + 0.5 V 0.3 x VCCIO V VIH High-level input voltage VIL Low-level input voltage VOH High-level output voltage IOUT = -500 A VOL Low-level output voltage IOUT = 1500 A II Input pin leakage current 0 < VI N < VCCIO Altera Corporation 0.9 x VCCIO -10 3.6 V 0.1 x VCCIO V 10 A 13 AN 117: Using Selectable I/O Standards In APEX 20KE, APEX 20KC & MAX 7000B Devices Table 17. CTT I/O Specifications Symbol VCCIO Parameter Conditions Minimum Typical Maximum Units I/O supply voltage 3.0 3.3 3.6 V VTT/VREF (1) Termination and reference voltage 1.35 1.5 1.65 V VREF - 0.2 V 10 A VIH High-level input voltage VIL Low-level input voltage VREF + 0.2 II Input pin leakage current 0 < VIN < VCCIO VOH High-level output voltage IOH = -8 mA VOL Low-level output voltage IOL = 8 mA IO Output leakage current (when output is high Z) V -10 VREF + 0.4 GND VOUT VCCIO V -10 VREF - 0.4 V 10 A Note: (1) VREF specifies center point of switching range. Board Termination Schemes The various I/O standards supported by APEX 20KE and MAX 7000B devices require specific termination schemes to achieve their high speeds. Each I/O standard has an individual termination scheme. The diagram in Figure 3 shows the series and parallel termination resistors that are used with the I/O standards. Figure 3. Board Termination Diagram Driving Device Receiving Device VTT VTT RT1 RT2 Z = 50 RS VREF The LVDS I/O standard requires a termination resistor between the signals at the receiving device as shown in Figure 4. The termination resistor should match the differential load impedance of the bus ranging from 90 to 110 3/4, but typically 100 3/4. 14 Altera Corporation AN 117: Using Selectable I/O Standards In APEX 20KE, APEX 20KC & MAX 7000B Devices Figure 4. LVDS Board Termination at the Receiver Transmitting Device 100 Receiving Device + - Table 18 shows the board termination values and reference voltages that each APEX 20KE I/O standard uses. Table 18. Board Termination Values I/O Standard Output Driver RS (3/4) RT1 (3/4) RT2 (3/4) VREF (V) VTT (V) GTL+ Open-drain - 50 50 1.0 1.5 SSTL-2 Class I Push-pull 25 - 50 1.25 1.25 SSTL-2 Class II Push-pull 25 50 50 1.25 1.25 SSTL-3 Class I Push-pull 25 - 50 1.5 1.5 SSTL-3 Class II Push-pull 25 50 50 1.5 1.5 HSTL Class I Push-pull - - 50 0.75 0.75 AGP Push-pull - - - 1.32 - CTT Push-pull - - 50 1.5 1.5 MAX 7000B Software Support Software Support for MAX 7000B Devices Selectable I/O standards are programmable on a per pin basis for both APEX 20KE and MAX 7000B devices. APEX 20KE devices have a total of 10 I/O blocks, including two LVDS blocks. The LVDS I/O blocks can also be used for any of the other I/O standards when not used for LVDS. MAX 7000B devices have two I/O blocks; I/O standards supported by MAX 7000B devices are shown in Table 1 on page 6. The QuartusTM II and MAX+PLUS(R) II software tools define the I/O standard used for each I/O block. Software support for MAX 7000B devices selectable I/O standards is provided in the MAX+PLUS II software version 9.4 and higher. This document explains the Quartus II software's support for selectable I/O standards. For information on how the MAX+PLUS II software supports these standards, contact Altera Applications. Altera Corporation 15 AN 117: Using Selectable I/O Standards In APEX 20KE, APEX 20KC & MAX 7000B Devices APEX 20K Family I/O Standard Software Support This section shows how to implement and view the selectable I/O standards for the APEX 20K family in the Quartus II software and gives placement and assignment guidelines. The following topics will be discussed: Device and Pin Options dialog box Pin Assignments dialog box Representation of I/O banks and I/O standards in the floorplan editor Automatic placement & verification of selectable I/O standards with the Quartus II software Guidelines for selectable I/O standards I/O and VREF pin placement guidelines Device & Pin Options Dialog Box The Voltage tab in the Device & Pin Options dialog box (Compiler Settings dialog box) contains a Default I/O Standard drop-down menu, which is used to set the default I/O standard for a device. All I/O pins without a specific I/O standard assignment will default to the I/O standard specified in this drop-down menu. The drop-down menu has the following options for APEX 20KE devices: LVTTL (default setting) LVCMOS 2.5 V 1.8 V PCI PCI-X (supported in a future version of the Quartus II software) LVDS LVPECL (supported in a future version of the Quartus II software) GTL+ SSTL-2 Class I & II SSTL-3 Class I & II HSTL Class I (supported in a future version) AGP CTT The options available for APEX 20K devices in the drop-down menu are as follows: 16 LVTTL LVCMOS (default setting) 3.3-V PCI 2.5 V 1.8 V Altera Corporation AN 117: Using Selectable I/O Standards In APEX 20KE, APEX 20KC & MAX 7000B Devices Figure 5 shows the Device & Pin Options dialog box (Compiler Settings dialog box) when targeting an APEX 20KE device. Figure 5. Device & Pin Options Dialog Box for APEX 20KE Devices Pin Assignments Dialog Box In the Pin Assignments dialog box, designers can make pin assignments, specify I/O standards, VREF assignments, and view the settings made to each pin. Altera Corporation 17 AN 117: Using Selectable I/O Standards In APEX 20KE, APEX 20KC & MAX 7000B Devices Figure 6 shows the Pin Assignments dialog box. The Number column corresponds with the pin number on the specified package. The Name column contains the user-specified pin name in the design. There are two relevant columns to note: I/O Bank and I/O Standard. The Type column in the Available Pins & Existing Assignments list box displays the following pin types: Row I/O, Column I/O, VREF, Reserved, and dual-purpose pin names. The list box is sortable on any column by clicking on the column heading. There are drop-down menus for making I/O standard and reserved pin assignments on a pin-by-pin basis. VREF pins are assigned the same way as reserved pins. To select the I/O standard for I/O and VREF pins, choose an I/O standard from the I/O standard drop-down menu. To assign a pin to be a VREF, enter a pin name (reserve pin names are not declared in the design file), check the Reserve pin box, and select reserve as VREF from the drop-down menu. Figure 6. Pin Assignments Dialog Box Follow the steps below to make pin assignments, designate I/O standard types, and reserve pins. Designers should reserve I/O pins that may be needed in the future. 18 Altera Corporation AN 117: Using Selectable I/O Standards In APEX 20KE, APEX 20KC & MAX 7000B Devices 1. If you have not already done so, open or create the project that you want to modify. 2. Choose Compiler Settings (Processing menu). 3. Click the Chips & Devices tab. 4. Select the target device in the Available devices list. 5. Click Assign Pins. 6. In the Pin Assignments dialog box, to show the pins for which you cannot assign a node name in the Available pins & existing assignments list, select Show no connect pins. 7. In the Available pins & existing assignments list, select the pin number for the pin to which you want to assign, change, or delete a node name assignment. 8. To delete the node name assignment from the pin, under Assignment, click Delete. 9. To assign a new node name to the pin, or change the existing node name assignment for the pin, under Assignment, type a node name in the Pin name box or Copy the node name to the Pin Assignments dialog box with the Node Finder. 10. If you added or changed the node name assignment for the pin and you want to assign an I/O Standard to the pin, under Assignment, select a standard from the I/O Standard list. 11. If you added or changed the node name assignment or I/O standard and you want to reserve the pin for future use, under Assignment, turn on Reserve pin (even if it does not exist in the design file), and select As input tri-stated, As output driving ground, As output driving an unspecified signal, or As VREF from the list. 12. To save a new assignment and add the assignment to the Available pins & existing assignments list, under Assignment, click Add. 13. To save the changed assignment and add the assignment to the Available pins & existing assignments list, under Assignment, click Change. 14. Repeat steps 7 to 13 for each additional assignment you want to make, change, or delete. 15. Click OK. Altera Corporation 19 AN 117: Using Selectable I/O Standards In APEX 20KE, APEX 20KC & MAX 7000B Devices Representation of I/O Banks & Standards in the Floorplan Editor The Floorplan Editor supports many features in APEX 20KE devices, including multiple I/O standards, PLLs, and the LVDS transmitter and receiver block. The Floorplan Editor shows membership in I/O banks by using a unique background fill color around each pin for each I/O bank. In addition, the bank number is shown. The Floorplan editor has two package views (Package Top and Package Bottom) and three internal views (Interior MegaLABTM, Interior LABs and Interior Cells). In the package views the I/O bank number is labeled above the pin for pin-grid array (PGA) and BGA packages, or on the inside of the device for quad flat pack (QFP) packages. In the interior views, the I/O is outside the package as a background around the pin name. Only I/O and VCCIO pins have the colored background; GNDINT, GNDIO, and VCCINT pins do not, as they are not specific to a particular I/O bank. Figure 7 shows the coloring in the Floorplan Editor for the EP20K600E device (1,020-pin FineLine BGA device package) in package view. Figure 7. Package View with Show I/O Banks On 20 Altera Corporation AN 117: Using Selectable I/O Standards In APEX 20KE, APEX 20KC & MAX 7000B Devices Under the View pull-down menu in the Floorplan Editor, the Show I/O Banks option controls and displays the I/O bank colors. This command also turns on the display of both the I/O bank colors and bank numbers in the three interior views. The Floorplan Editor Color Legend, located under the View pull-down menu, has an entry for each I/O bank color, as shown in Figure 8. The output clock and feedback pins for PLL1 and PLL2 reside in I/O Bank 9 and I/O Bank 10 and can support any of the I/O standards supported for APEX 20KE devices. Figure 8. Pin Color Legend Window for the Floorplan Editor Figure 9 shows a portion of the package view of two EP20K100E device I/O Banks of a 240-pin plastic quad flat pack (PQFP) package in the Floorplan Editor. In the PQFP packages, the eight I/O banks have been merged into 4 merged I/O banks. The VCCIO planes on merged I/O banks are internally connected in the PQFP packages. The naming convention for merged I/O banks lists the real I/O bank that the pin belongs to, and then lists the I/O bank with which it shares VCCIO. The I/O bank and Bank6 (Bank7) share the VCCIO with Bank7 (and Bank6), but has a different VREF bus. This allows Bank6 (and Bank7) to be used for one voltage-referenced I/O standard and Bank7 (and Bank6) for another because they have separate VREF buses, as long as those two standards use the same VCC level. For example, Bank6 (and Bank7) can implement GTL+ while Bank7 (and Bank6) implements SSTL-3 Class I. Altera Corporation 21 AN 117: Using Selectable I/O Standards In APEX 20KE, APEX 20KC & MAX 7000B Devices Figure 9. Top View of the 240-Pin PQFP Package Figure 10 shows the internal cells view of the APEX 20KE device's PLL support. The diamond next to the dedicated clocks indicates that the PLL is used. 22 Altera Corporation AN 117: Using Selectable I/O Standards In APEX 20KE, APEX 20KC & MAX 7000B Devices Figure 10. View of Internal Cells in Floorplan Editor The dedicated clock pins (CLK1p, CLK2p, CLK3p, CLK4p) support LVDS and have optional dual-purpose negative polarity pins associated with them. The PLL feedback pins (CLKLK_FB1p, CLKLK_FB2p) and the PLL output pins (CLKLK_OUT1p, CLKLK_OUT2p) also support LVDS following the same convention as the dedicated clock pins. Figure 11 shows the LVDS receiver in the Floorplan Editor. The receiver data channel, represented by LVDSRX01p and LVDSRX01n, feeds the dedicated serial-to-parallel converter. The LVDS clock (LVDSRXINCLK1p, LVDSINCLK1n) clocks the serial-to-parallel converter. The serial-to-parallel converter is shown by the filled rectangle adjacent to the IOE register associated with each positive polarity LVDS data and clock pin. Altera Corporation 23 AN 117: Using Selectable I/O Standards In APEX 20KE, APEX 20KC & MAX 7000B Devices Figure 11. Internal Cells View of LVDS Receiver Guidelines for Selectable I/O Standards The following guidelines should be used when designing for the selectable I/O standards in APEX 20KE devices. The guidelines define which standards are compatible based on input, output, and bidirectional types within an I/O bank. 24 No two input pins can be placed in the same I/O bank if their I/O standards require a different VREF voltage. However, non-voltage-referenced standards can coexist with voltage-referenced standards; e.g., one bank can support GTL+ and LVTTL. For PQFP packages, the two merged I/O banks still support separate VREF inputs for each bank. For example, if Bank1 and Bank8 are merged together, bank 1 can support GTL+ while Bank8 can support SSTL-3. No two push-pull standard output pins can be placed in the same I/O bank if they require a different VCCIO voltage level. All output pins have the same VCCIO level for merged I/O banks in the PQFP packages. GTL+ is an open-drain I/O standard and therefore can be assigned to I/O banks with a 2.5-V or 3.3-V VCCIO level. Altera Corporation AN 117: Using Selectable I/O Standards In APEX 20KE, APEX 20KC & MAX 7000B Devices The clamp diode affects input tolerance. When the PCI clamp diode is turned on, an I/O pin is clamped to VCCIO. For example, a 2.5-V VCCIO bank without the clamp diode is tolerant to 3.3-V inputs. However, when the clamp is turned on, the 2.5-V VCCIO bank is not 3.3-V tolerant. An LVTTL input that does not have its clamp diode turned on can be placed in a bank that has a 2.5-V VCCIO level. Bidirectional pins have to satisfy both input and output guidelines. All output drivers between two GNDIO pins should not sink more current than 273 mA in total. Pins using the 1.8-V standard are not current limited. The current requirement for I/O standards with 3.3-V and 2.5-V VCCIO levels are defined as follows: - - - - - Altera Corporation For VCCIO = 3.3 V, [(# of GTL+ x 36) + (# of LVTTL x ILVTTL) + (# of PCI x 1.5) + (# of LVCMOS x ILVCMOS) + (# of SSTL-3 class I x 8) + (SSTL-3 class II x 16) + (# of LVDS x 4.5) + (# of AGP x 1.5) + (# of CTT x 8)] mA 273 mA Where ILVTTL (4-mA default value) and I LVCMOS (0.1 mA default value) are the current sink on the LVTTL and LVCMOS pins, respectively. If your system requires higher ICC for LVTTL or LVCMOS pins (for example, due to termination) then adjust the equation accordingly. For VCCIO = 2.5 V, ((# of 2.5V x 2) + (# of SSTL-2 class I x 7.6) + (# of SSTL-2 class II x 15.2) mA 273 mA In practice, this rule applies only to SSTL-2 Class II, SSTL-3 Class II, GTL+, and LVCMOS and LVTTL pins which can sink more than 14 mA per output pin. For other standards, every pin can be used without violating this requirement. The APEX 20K Programmable Logic Device Family Data Sheet shows the relationship of I/O pins to GNDIO pins to enable correct pin placement. This is also shown in the Quartus II software's Floorplan Editor and in Quartus II Help. When placing VREF pins, follow these guidelines. Output pins that can switch while an input is using a VREF have to be placed a distance of two pads away from the VREF pin, or a distance of one pad away from the VREF pin if the pad between them is a power (VCC or GND) pad. Figure 12 shows both cases. Multiple VREF pins may be used in an I/O bank of the same standards. Further VREF guidelines are discussed in the "I/O & VREF Placement Guidelines" on page 27. 25 AN 117: Using Selectable I/O Standards In APEX 20KE, APEX 20KC & MAX 7000B Devices Figure 12. Examples of VREF Placement One VREF for 16 input pins VREF Power Max 8 I/P Max 8 I/P Multiple VREF pins should be considered per I/O bank VREF Power Max 8 I/P Max 8 I/P VREF O/P Max 8 I/P Max 8 I/P Automatic Placement & Verification of Selectable I/O Standards With Quartus II Software The Quartus II software verifies correct placement of all I/O and VREF pins, following the same rules outlined in the "Guidelines for Selectable I/O Standards" on page 24. 26 Designers must assign VREF pins for all voltage-referenced I/O pins. The Quartus software automatically places I/O pins of different VREF standards without pin assignments in separate I/O banks. The Quartus software verifies that no two voltage-referenced I/O pins requiring different VREF or LVDS pin levels are placed in one bank. The Quartus software ensures that an I/O pin requiring a VREF pin is no more than 16 pins from a VREF pin. All 16 voltage-referenced I/O pins may be placed on only one side of the VREF pin or staggered on both sides of the VREF pin. The Quartus II software reports an error message if the current limitation is exceeded between GNDIO pins. It uses the equations documented in the "Guidelines for Selectable I/O Standards" on page 24. The Quartus II software ensures that no more than 16 voltage referenced I/O standard pins are using a single VREF. Altera Corporation AN 117: Using Selectable I/O Standards In APEX 20KE, APEX 20KC & MAX 7000B Devices The Quartus II software does not allow you to place an output pin within two pins of a VREF if a power pin does not separate them. To view pad orientation, use the Show Pads view in the Floorplan Editor. The Quartus II software will reserve the unused LVDS channels in the LVDS transmitter and receiver blocks when any of the LVDS channels are being used. It will also reserve the two I/O pins adjacent to the LVDS blocks that share a VCCIO pin with the LVDS blocks. The Quartus II software will not allow placement of non-LVDS output pins in or within two I/O pins (with a common VCCIO pin) of the LVDS blocks. I/O & VREF Placement Guidelines This section discusses VREF and I/O pin placement guidelines when designing with I/O buses. Each VREF pin can support up to eight voltage-referenced input pins on each side, or 16 input pins in total, as shown in Figure 13. The Quartus II software will give an error message if a voltage-referenced input pin is placed more than 16 pads from a VREF pin. Figure 13. Each VREF Can Support 16 Input Pins V REF Output pins should be placed two or more pins away from VREF pins, except when the VREF is next to a power pin. In that case the power pin isolates the VREF pin from the switching output. Output pins can be placed on the other side of the power pin, as shown in Figure 14. Altera Corporation 27 AN 117: Using Selectable I/O Standards In APEX 20KE, APEX 20KC & MAX 7000B Devices Figure 14. VREF Pin Placement Guidelines VREF Inputs Inputs or Ouputs VREF VCC or GND pad Voltage-referenced bidirectional buses that share a single tri-state control signal can be placed around the VREF pin, as shown in Figure 15. This works because the bus is only operating in one direction at a time. When the bidirectional pins are driving out, no inputs are using the VREF pin. When the bidirectional pins are accepting input signals, there are no output pins that would interfere with the input pins' ability to use the VREF level. Figure 15. Placement of Bidirectional Buses with Single OE Control VREF OK VREF OK Output pins can be placed outside the bus without affecting the use of VREF in the bidirectional bus, as shown in Figure 16. Furthermore, an unrelated output pin may be placed within a voltage-referenced bidirectional bus if the output pin is more than two pads from the VREF pin or separated by a power pin. 28 Altera Corporation AN 117: Using Selectable I/O Standards In APEX 20KE, APEX 20KC & MAX 7000B Devices Figure 16. Placement of Output Pins Outside the Bidirectional Buses VREF Not OK These outputs affect the inputs & bidirectional pins VREF OK Output pins can also be placed inside the bus if they are more than two pins away from the VREF pin, as shown in Figure 17. Figure 17. Output Pin Placement in a Bidirectional Bus VREF Not OK This output affects input and bidirectional pins when it is within two pins of the VREF pin unless separated by a power or GND VREF OK Place outputs two or more pins from VREF Altera Corporation 29 AN 117: Using Selectable I/O Standards In APEX 20KE, APEX 20KC & MAX 7000B Devices Conclusion The advanced programmable I/O features and standards simplify board design by minimizing the number of devices used to interface with memory, microprocessors, and backplanes. The APEX 20KE devices, which are 64-bit, 66-MHz PCI compliant, support 16 programmable I/O standards, allowing customization for a wide variety of applications. Input, output, and bidirectional pins of different I/O standards can be intermixed with I/O banks by following the guidelines in this document. APEX 20KE devices also offer increased I/O performance with new standards and features like LVDS (840 Mbps data transfer). References Revision History 30 Interface Standard for Nominal 3 V/3.3 V Supply Digital Integrated Circuits, JESD8-A, Electronic Industries Association, June 1994. Stub-Series Terminated Logic for 3.3 Volts (SSTL-3), EIA/JESD8-8, Electronic Industries Association, August 1996. Stub-Series Terminated Logic for 2.5 Volts (SSTL-2), EIA/JESD8-9, Electronic Industries Association, September 1998. Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits, ANSI/TIA/EIA-644, American National Standards Institute/Telecommunication Industry Association/Electronic Industries Association. 2.5 V 0.2 V (Normal Range) and 1.7 V to 2.7 V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit, EIA/JESD8-5, Electronic Industries Association, October 1995. 1.8 V 0.15 V (Normal Range) and 1.2 V to 1.95 V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit, EIA/JESD8-7, Electronic Industries Association, February 1997. PCI Local Bus Specification, Revision 2.2, PCI Special Interest Group, December 1998. The information contained in Application Note 117 (Using Selectable I/OStandards in APEX 20KE, APEX 20KC & MAX 7000B Devices) version 2.1 supersedes information published in previous versions. Application Note 117 (Using Selectable I/OStandards in APEX 20KE, APEX 20KC & MAX 7000B Devices) version 2.1 contains the folllowing change: The title has been changed throughout the document. Altera Corporation AN 117: Using Selectable I/O Standards In APEX 20KE, APEX 20KC & MAX 7000B Devices 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Literature Services: lit_req@altera.com 31 Copyright (c) 2001 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. 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