®
Alt er a Cor pora t ion 1
Using Selectable I/O
Standards in APEX 20KE,
APEX 20KC & MAX 7000B Devices
October 2 001 , ver. 2.1 Applic a ti on Not e 117
A-AN-117-2.1
Introduction High-performance, low-voltage I/O standards have been introduced to
keep pac e with increasing clo ck speeds, high er data rates, an d new
low-vol tage d evic es. These I/O standards are used to interface with
memory , micropro cessors, ba ckplanes, a nd periphe ral devices . Designe rs
who want to use these new standards with programmable logic need
flexible, high-performance, multi-standard I/O buffers.
Altera’s revolutionary APEX TM 20KE and APEX 20KC devices offer the
highest density, highest performance programmable logic solution with
the necessary I/O standards for the communication and computer
industries. Altera® MAX®7000B devices are the product-term leader in
I/O standard support: MAX 7000B devices are the only macrocell-based
devices to support GTL+, 2.5-V SSTL-2, and 3.3-V SSTL-3.
With the new programmable I/O standards supported by APEX 20KE
and MAX 7000B devices, a single device can simultaneously support
multiple I/O standar ds, as we ll as in terface wi th high -speed, low-voltage
memory buses and backplanes. These I/O standards include LVDS,
which supports data rates up to 840 megabits per second (Mbps).
Embeddi ng I/O standard sup port in prog rammable logic d evices (PLDs)
simplifies board design. Dedicated circuitry like LVDS transceivers is
integrated into PLDs, saving board space, reducing pin usage, and
improving performa nce .
This application note provides guidelines for designing with selectable
I/O standards in Altera devices and covers the following topics:
■Overview of I/O standards and applications
■APEX 20KE, APEX 20KC and MAX 7000B I/O standard support
■Operating conditions
■Board termination schemes
■APEX 20K family I/O standard software support
Overview of I/O
Standards &
Applications
The abilit y for PL Ds to supp ort in dustry I /O standar ds gives cu stomer s a
quick time-to-market design solution. This section provides an overview
of typical applications for the selectable I/O standards supported by
Altera devices. The specifications for each I/O standard are listed in this
section.
2Altera Corporation
AN 117: Us ing Sel ectab l e I/O Standards In A PEX 20KE, APEX 20K C & MA X 7000B Devic es
LVTTL
The LVTTL standard is a single-ended, general-purpose standard for
3.3-V applications. The LVTTL interface is defined by JEDEC Standard
JESD 8-A, Inter face Stan dard for Nomi nal 3.0 V/3.3 V Supply Digital
Integrated Circuits. The LVTTL output buffer is a push-pull driver. This
standard requires the output buffer to drive to 2.4 V (minimum VOH =
2.4 V). It does not require the use of input reference voltages or
termina tio n . APEX 20K, APEX 20KE, and MAX 7000B de v ices are
compliant with this standard. The maximum recommended input vol tage
for APEX and MAX 7000B devices is 4.1 V, wh ich exceeds the 3.9-V
requirement of this specification.
LVCMOS
The LVCMOS standard is defined in JEDEC Standard JESD 8-A, Interface
St andard for Nom i nal 3.0 V/3.3 V Supply Digital Integ rated Circuits .
LVCMOS is a single -en ded genera l-pur p ose standard als o used for 3. 3-V
applications. The input buffer requirements are the same as the LVTTL
requirements, and the output buffer is required to drive to the rail
(minimum VOH = VCCIO – 0.2 V). This standard requires a 3.3-V I/O
supply voltage (VCCIO), but not the use of input reference voltages or
termination. APEX 20K, APEX 20KE, APEX 20KC and MAX 7000B devices
are compliant with the LVCMOS standard.
2.5 V
The 2.5-V I/O standard is documented by JEDEC Standard JESD 8-5,
2.5 V ± 0.2 V (Normal Range) and 1.7 V to 2.7 V (Wide Range) Power Supply
Voltage and Interface Standard for Nonterminated Digital Integrated Circuit.
This standard is similar to LVCMOS but is used for 2.5-V power supply
levels. APEX 20K, APEX 20KE, APEX 20KC and MAX 7000B devices are
compliant with this standard, which requires a 2.5-V VCCIO, but not the
use of input reference voltages or termination.
1.8 V
The 1.8-V I/O standard is documented by JEDEC Standard JESD 8-7,
1.8 V ± 0.15 V (Norm al Range) and 1. 2 V to 1. 95 V (W ide Rang e) Powe r Supp ly
Voltage and Interface Standard for Nonterminated Digital Integrated Circuit.
This standard is similar to LVCMOS but is used for 1.8-V power supply
levels an d re duce d inpu t a nd output thr e sholds . APE X 2 0K, APE X 20 KE,
APEX 20KC and MA X 70 00B devices are compli ant with this standard,
whic h re quires a 1.8-V VCCIO, but not the use of input reference voltages
or termination.
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3.3-V PCI
APEX 20K, APEX 20KE and APEX 20KC devices are compliant with PCI
Local Bus Specification, Revision 2.2 for 3.3-V operation. At 3.3 V, the PCI
standard supports up to 64-bit bus width operation at 33 or 66 MHz. This
standard uses LVTTL-type input and output buffers and requires a 3.3-V
VCCIO, but not the use of input reference voltages or termination.
MAX 700 0B device s ar e comp lian t w ith all as pects of t his standa rd e xcept
that they do not offer clamps to VCCIO.
PCI-X
The PCI-X standard is an enhanced version of the PCI standard that can
supp ort hig her ave rage b and width and has mo re str ingent r equire men ts.
The APEX 20KE and APEX 20KC I/O drivers meet the requirements for
PCI-X. In the Quartus IITM software, set the buffer setting to PCI to support
PCI-X requirements, including the overshoot clamp. A future version of
the Quartu s I I softw are will incl ud e the a b ility to choose P CI-X a s an I/ O
standard.
LVDS
The LVDS I/O standard is used for very high-performance,
low-power-consumption data transfer. Two key industry standards
define LVD S: IEEE 1596.3 SCI-LVDS and ANSI/TIA/ EIA-644. Both
standards have similar key features, but the IEEE standard supports a
maximum data transfer of 250 Mbps. APEX 20KE devices are designed to
meet the AN SI/TI A/EIA -644 requ ireme nts at up to 840 M bps. The L VDS
standard requires a 3.3-V VCCIO and a 100-¾ termination resistor between
the two traces at the inp ut bu ffer. No input r eference voltage is requ ired .
fFor more informat i o n on LVDS, see the Altera we b site at
http://www.altera.com.
LVPECL
The LVPECL standard is a different ial I/O stan dard that is similar to
LVDS. APEX 20KE devi ce s can sup port LVPECL I/O stan dard by using
the I/O pins in LVDS mode with an ex te rnal r esi stor net work .
4Altera Corporation
AN 117: Us ing Sel ectab l e I/O Standards In A PEX 20KE, APEX 20K C & MA X 7000B Devic es
GTL+
The GTL+ standard is a high-speed bus standard first used by Intel
Corporation for interfacing with the Pentium Pro processor and is often
used for processor interfacing or communication across a backplane.
GTL+ is a voltage-referenced standard requiring a 1.0-V input reference
voltage (VREF) and board termination voltage (VTT) of 1.5 V. The GTL+
standard is an open-drain standard that requires a minimum VCCIO
supply voltage of 3.0 V. APEX 20KE and MAX 7000B devices ar e
compliant with this standard.
SSTL- 2 Cl as s I & II
The SSTL - 2 s tandard, specifie d by JEDEC Standard JESD 8-9, Stub-Series
Terminated Logic for 2.5 Volts (SSTL-2), is a voltage-referenced standard
requiring a 1.25-V VREF, a 2. 5-V VCCIO, and a 1.25-V VTT. SSTL-2 is used
for high-speed SDRAM interfaces. APEX 20KE, APEX 20KC and
MAX 7000B devices are compliant with this standard.
SSTL- 3 Cl as s I & II
The SSTL - 3 s tandard, specifie d by JEDEC Standard JESD 8-8, Stub-Series
Terminated Logic for 3.3 Volts (SSTL-3), is a voltage-referenced standard
requiring a 1.5-V VREF, a 3.3-V VCCIO, and a 1.5-V VTT. SSTL-3 is used for
high- spee d SD RAM i nterf aces . AP EX 20KE, AP EX 20 KC and MA X 7000 B
devices are compliant with this standard.
HSTL Class I
The HSTL standard, specified by JEDEC Sta ndard JESD 8-6, High-Speed
Transceiver Logic (HSTL), is a 1.5 V output buffer supply voltage based
interface standard for digital integrated circuits. HSTL is a
volt age-re feren ced sta ndard re quir ing a 0.75 -V VREF, a 1.5-V VCCIO, and a
0.75-V VTT. APEX 20KE and APEX 2 0KC devices support HS TL Cl ass I
operation with a VCCIO voltage of 1.8 V. APEX 20KE and APEX 20KC
devices driv e compliant VOH an d VOL levels with VCCIO at 1.8 V.
AGP
The AGP standard is specified by the Advanced Graphics Port Interface
Specification Revision 2.0 introduced by Intel Corporation for graphics
applications. AGP is a voltage-referenced standard requiring a 1.32-V
VREF and a 3.3-V VCCIO. AGP does not require termination. APEX 20KE
and APEX 20KC devices support the AGP interface.
Altera Corporation 5
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CTT
The CTT standard is specified by JEDEC Standard JESD 8-4,
Center-Tap-Terminated (CTT) Low-Level, High-Speed Interface Standard for
Digital Integrated Circuits. CTT is a volta ge- refer enc ed sta nda rd r equir ing
a 1.5-V VREF, a 3.3-V VCCIO, and a 1.5-V VTT. The CTT standard is a
superset of LVTTL and LVCMOS. CTT receivers are compatible with
LVCMOS and LVTTL standards . CTT drivers, when untermin at ed, are
compatible with the AC and DC specifications for LVCMOS and LVTTL.
APEX 20KE &
MAX 7000B
I/O Sta ndar ds
Support
The APEX 20KE I/O blocks support 16 I/O standards and are the only
PLDs in the industry with LVD S. MAX 7000B devic es provide suppo rt for
GTL+, SSTL-2, and SSTL-3, a unique feature among product-term-based
PLDs.
The programmable input/output element (IOE) blocks in both
APEX 20KE and MAX 7000B devices have individual power supplies with
separate I/O supply voltage (VCCIO) pins for each I/O block. The VCCIO
supply suppo r ts 3.3-V , 2.5-V, and 1.8-V levels.
APEX 20KE & MAX 7000B I/O Standards
The APEX 20KE and MAX 7000B I/O buffers meet th e voltage, drive
str ength, and AC charac teri stics neces sary to co mply with the I/O
standards listed in Table 1.
6Altera Corporation
AN 117: Us ing Sel ectab l e I/O Standards In A PEX 20KE, APEX 20K C & MA X 7000B Devic es
Notes:
( 1) The values s hown for VREF, VCCIO, and VTT ar e t ypica l v a lu es .
(2) MAX 7000B devices do not have the PCI diode clamp to VCCIO. These devices comply with all other 64-bit/66-MHz
3.3-V PCI specifications.
(3) AP E X 20 K E de v ices d r iv e HSTL- c o mpliant s ignal level s with VCCIO cor rec ted t o a 1.8 -V sup pl y.
fEach I/O standard has different VREF, VTT, and VCCIO requirements. For
more information, refer to “Board Termination Schemes” on page 14.
APEX 20KE I/ O Standar ds
The I/O bank s in the A PEX 20 KE devic es suppor t 16 I/ O stand ar ds and
are the first programmable logic devices (PLDs) in the industry with
dedic at ed LVDS circuitry. APEX 20KE devices in BGA and Fi neLine
BGATM packages have eight programmable I/O banks and two LVDS I/O
blocks (one transmitter block and one receiver block) within two of the
I/O banks. The programmable input/output element (IOE) banks in
APEX 20KE devices have individual power planes with separate I/O
supply voltage (VCCIO) pins for each I/O bank. The VCCIO supply
supports 3.3-V, 2.5-V, and 1.8-V levels.
Table 1. APEX 20KE & MAX 7000B Supported I /O Standards
I/O Standard Device Type Input
Reference
Voltage
(VREF) (V) (1)
Output Supply
Voltage
(VCCIO) (V) (1)
Board
Termination
Voltage
(VTT) (V) (1)
APEX 20KE MAX 7000 B
LVTTL vv
Single-ended N/A 3.3 N/A
LVCMOS vv
Single-ended N/A 3.3 N/A
2.5 V vv
Single-ended N/A 2.5 N/A
1.8 V vv
Single-ended N/A 1.8 N/A
PCI vv(2) Single-ended N/A 3.3 N/A
PCI-X vSingle-ended N/A 3.3 N/A
LVDS vDifferential N/A N/A N/A
LVPECL vDifferential N/A 3.3 N/A
GTL+ vv
Voltage-referenced 1.0 N/A 1.5
SSTL-2
Class I and II vv
Voltage-referenced 1.25 2.5 1.25
SSTL-3
Class I and II vv
Voltage-referenced 1.5 3.3 1.5
HSTL Class I vVoltage-referenced 0.75 1.8 (3) 0.75
AGP vVoltage-referenced 1.32 3.3 N/A
CTT vVoltage-referenced 1.5 3.3 1.5
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APEX 20KE devices in FineLine BGA packages have eight programmable
I/O blocks and two LVDS I/O blocks. Figure 1 shows the repre sentatio n
of the I/O blocks. For APEX 20KE designs that do not use LVDS, the
LVDS I/O blocks can be used for any other standard.
Figure 1. APEX 20KE I/O Blo cks
Note:
(1) The first two I/O pins that border the LVDS blocks can only be used for input to
main t a in a n ac c e p table noise leve l on the VCCIO supply.
(2) If the LVDS input and output blocks are not used for LVDS, they ca n support all of
the I/O st an d ard s an d can be use d as inpu t, ou tpu t , or bidi r ect ional pins with
VCCIO set to 3.3 V, 2.5 V, or 1.8 V.
MAX 7000B I/O Standards
Each MAX 7000B device has two programmable I/O blocks. Each I/O
block c an be configured indepe ndently to ut ilize any of the I/O standa rds
supported by MAX 7000B devices. Additionally, you can use I/O
standards with common VCCIO voltages simultaneously within a single
block. Each programmable I/O block has its own power supply with
separate VCCIO pins and support for 3.3-V, 2.5-V, and 1.8-V voltage levels.
Figure 2 shows a representation of the MAX 7000B programmable I/O
blocks.
LVDS Inpu
t
Block (2)
(1)
LVDS Output
Block (2)
(1)
Individual
Power Bus
I/O Bank 8
I/O Bank 1 I/O Bank 2
I/O Bank 3
I/O Bank 4
I/O Bank 5I/O Bank 6
I/O Bank 7
Regular I/O Banks Support
■
LVTTL
■
LVCMOS
■
2.5 V
■
1.8 V
■
3.3 V PCI
■
PCI-X
■
GTL+
■
SSTL-2 Class I and II
■
SSTL-3 Class I and II
■
CTT
■
AGP
■
HSTL
8Altera Corporation
AN 117: Us ing Sel ectab l e I/O Standards In A PEX 20KE, APEX 20K C & MA X 7000B Devic es
Figure 2. MA X 7000B I /O Banks Notes (1), (2), (3)
Notes:
(1) Any input pin can be referenced to one of the two available VREF level s .
(2) MAX 7000B devices have two VREF pins t hat can b e refe r enced by any I /O pi n in
both I/O blocks.
(3) The output drivers are dependent on VCCIO. The VCCIO pins f or each I/O block can
be powered to a different voltage.
Operating
Conditions
Tables 2 through 17 list the DC ope rating specific ations for t he suppo rted
I/O standards. These tables list minimal specifications only. APEX 20KE
and MAX 7000B devices may exceed these specifications. Consult
indivi dual device data sheets for details.
Individual
Power Bus
Programmable I/O Banks
■
LVTTL
■
LVCMOS
■
2.5 V
■
1.8 V
■
3.3-V PCI
■
GTL+
■
SSTL-2 Class I and II
■
SSTL-3 Class I and II
Table 2. LVTTL I/O Specificat ions
Symbol Parameter Conditions Minimum Maximum Units
VCCIO Outpu t supply vo lta ge 3.0 3.6 V
VIH High-level input voltage 2.0 VCCIO + 0.3 V
VIL Low-level input voltage –0.3 0.8 V
IIInput pin leak age current VIN = 0 V or 3. 3 V –5 1 0 µA
VOH High-level output voltage IOH = –4 mA 2.4 V
VOL Low-level output voltage IOL = 4 mA 0.4 V
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Table 3. LVCMOS I/O Specifications
Symbol Parameter Conditions Minimum Maximum Units
VCCIO Power supply vo ltag e range 3.0 3.6 V
VIH High -lev el input voltage 2.0 VCCIO + 0.3 V
VIL Low -lev el input voltage –0.3 0.8 V
IIInput pin leaka ge c urrent VIN = 0 V or 3.3 V –10 10 µA
VOH High -lev el out put vo lta ge VCCIO = 3.0 V
IOH = –0.1 mA VCCIO – 0.2 V
VOL Low -lev el out put vo lta ge VCCIO = 3.0 V
IOL = 0.1 mA 0.2 V
Table 4 . 2.5-V I/O Specifica tions
Symbol Parameter Conditions Minimum Maximum Units
VCCIO Output supply voltage 2.375 2.625 V
VIH High -lev el input voltage 1.7 VCCIO + 0.3 V
VIL Low -lev el input voltage –0.3 0.7 V
IIInput pin leaka ge c urrent VIN = 0 V or 3.3 V –10 10 µA
VOH High -lev el out put vo lta ge IOH = –0. 1 mA 2.1 V
IOH = –1 mA 2.0 V
IOH = –2 mA 1.7 V
VOL Low -lev el out put vo lta ge IOL = 0.1 mA 0.2 V
IOH = 1 mA 0.4 V
IOH = 2 mA 0.7 V
Table 5 . 1.8-V I/O Specifica tions
Symbol Parameter Conditions Minimum Maximum Units
VCCIO Output supply voltage 1.7 1.9 V
VIH High -lev el input voltage 0.6 5 × VCCIO VCCIO + 0. 3 V
VIL Low -lev el input voltage 0.35 × VCCIO V
IIInput pin leaka ge c urrent VIN = 0 V or 3.3 V –10 10 µA
VOH High -lev el out put vo lta ge IOH = –2 m A VCCIO – 0.45 V
VOL Low -lev el out put vo lta ge IOL = 2 mA 0.45 V
10 Altera Corporation
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Table 6. 3.3-V PCI Specificatio ns
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O supp ly volt age 3.0 3.3 3.6 V
VIH High-level input voltage 0.5 × VCCIO VCCIO + 0.5 V
VIL Low-level input voltage –0.5 0.3 × VCCIO V
IIInput pin leak age current 0 < VIN < VCCIO –10 10 µA
VOH High-level output voltage IOUT = –500 µA 0.9 × VCCIO V
VOL Low-level output voltage IOUT = 1,5 00 µA 0.1 × VCCIO V
Table 7. 3.3- V PCI-X Spe cificati ons
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO Output supply voltage 3.0 3.3 3.6 V
VIH Hig h-lev el input voltage 0. 5 × VCCIO VCCIO + 0.5 V
VIL Low -lev el input voltage –0.5 0.35 ×
VCCIO
V
VIPU Inp ut pu ll-up v olt age 0.7 × VCCIO V
IIL Inp ut pin leak age c urrent 0 < VIN < VCCIO –10.0 10.0 µA
VOH Hig h-lev el output voltage Iout = –500 µA 0.9 × VCCIO V
VOL Low -lev el out put voltage Iout = 1500 µA 0.1 × VCCIO V
Lpin Pin In duc ta nc e 15.0 nH
Table 8. 3.3-V LVDS I/O Specifications
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O supp ly volt age 3.135 3.3 3.465 V
VOD Differe nt ial out put vol tag e RL = 100 ¾ 250 450 mV
ý V OD C hange in VOD between
high and low RL = 100 ¾ 50 m V
VOS Outpu t offset vo lta ge RL = 100 ¾ 1.1 25 1.25 1.375 V
ý V OS C hange in VOS between
high and low RL = 100 ¾ 50 mV
VTH Differe nt ial input th res hold VCM = 1.2 V –100 100 mV
VIN Receiv er input voltage
range 0.0 2.4 V
RLReceiv er dif fe rent ial input
resistor (external to APEX
devices)
90 100 110 ¾
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Table 9 . GTL+ I/O Specifications
Symbol Parameter Conditions Minimum Typical Maximum Units
VTT Termination volta ge 1.35 1.5 1.65 V
VREF Reference voltage 0.88 1.0 1.12 V
VIH High -lev el input voltage VREF + 0.1 V
VIL Low -lev el input voltage VREF – 0.1 V
VOL Low -lev el out put vo lta ge IOL = 36 mA 0.65 V
Table 10. SSTL-2 Class I Specifications
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I / O sup ply voltage 2.375 2.5 2.625 V
VTT Termination volta ge VREF – 0.04 VREF VREF + 0.04 V
VREF Reference voltage 1.15 1.25 1.35 V
VIH High -lev el input voltage VREF + 0.18 VCCIO + 0.3 V
VIL Low -lev el input voltage –0.3 VREF – 0.18 V
VOH High -lev el out put vo lta ge IOH = –7.6 mA VTT + 0.57 V
VOL Low -lev el out put vo lta ge IOL = 7.6 mA VTT – 0.57 V
12 Altera Corporation
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Table 11. SSTL-2 Cl ass II Speci f ica t ions
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O supp ly volt age 2.37 5 2.5 2.625 V
VTT Termination voltage VREF – 0.04 VREF VREF + 0.04 V
VREF Referenc e v olt age 1.15 1.2 5 1.3 5 V
VIH High-level input voltage VREF + 0.18 VCCIO + 0.3 V
VIL Low-level input voltage –0.3 VREF – 0.18 V
VOH High-level output voltage IOH = –15.2 mA VTT + 0.76 V
VOL Low-level output voltage IOL = 15.2 mA VTT – 0.76 V
Table 12 . SSTL-3 Class I Specifications
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O Supply voltage 3.0 3.3 3.6 V
VTT Ter min at ion v olt age VREF – 0. 05 VREF VREF + 0.05 V
VREF Reference volta ge 1.3 1. 5 1.7 V
VIH Hig h-lev el input voltage VREF + 0.2 VCCIO + 0 . 3 V
VIL Low -lev el input voltage –0.3 VREF – 0.2 V
VOH Hig h-lev el out put voltage IOH = –8 mA VTT + 0. 6 V
VOL Low -lev el out put voltage IOL = 8 mA VTT – 0.6 V
Table 13. SSTL-3 Cl ass II Speci f ica t ions
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O Supply vo lta ge 3.0 3.3 3.6 V
VTT Termination voltage VREF – 0. 05 VREF VREF + 0.05 V
VREF Referenc e v olt age 1.3 1.5 1.7 V
VIH High-level input voltage VREF + 0.2 VCCIO + 0 . 3 V
VIL Low-level input voltage –0.3 VREF – 0. 2 V
VOH High-level output voltage IOH = –16 mA VTT + 0.8 V
VOL Low-level output voltage IOL = 16 mA VTT – 0.8 V
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Table 14. HSTL Class I I/O Specifications
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O Supply voltage 1.71 1.8 1.89 V
VTT Terminat ion v olt age VREF – 0.05 VREF V
REF + 0.05 V
VREF Re fe renc e vo lta ge 0.6 8 0.75 0.90 V
VIH High-level input voltage VREF + 0.1 VCCIO + 0.3 V
VIL Low-level input voltage –0. 3 VREF – 0 .1 V
VOH High-level output voltage IOH = –8 mA VCCIO – 0. 4 V
VOL Low-level output voltage IOL = 8 mA 0.4 V
Table 15. LVPECL Spe cification s
Symbol Parameter Minimum Typical Maximum Units
VCCIO Output Supply Volt age 3.135 3.3 3.465 V
VIL Low- lev el input vo lta ge 1300 1700 mV
VIH High- lev el input vo lta ge 2100 2600 mV
VOL Low- lev el out put vol tag e 1450 1650 mV
VOH High- lev el out put vo ltag e 2275 2420 mV
VID Input Volt age Differential 400 600 950 mV
VOD Outp ut Vo lta ge D ifferential 625 800 950 mV
tr, tfRise /Fall Time (20 to 80%)85325ps
tDSKEW Dif fer ent ial Sk ew 25 ps
tOOutput Lo ad 150 ¾
RLReceiv er dif f erent ial input resistor 100 ¾
Table 16. 3.3-V AGP I/O Specifications
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O supply voltage 3.15 3.3 3.45 V
VREF Reference voltage 0.39 × VCCIO 0.41 × VCCIO V
VIH High -lev el input voltage 0.5 × VCCIO VCCIO + 0.5 V
VIL Low -lev el input voltage 0.3 × VCCIO V
VOH High -lev el out put vo lta ge IOUT = –500 µA 0.9 × VCCIO 3.6 V
VOL Low -lev el out put vo lta ge IOUT = 1500 µA 0.1 × VCCIO V
IIInput pin leaka ge c urrent 0 < VIN < VCCIO –10 10 µA
14 Altera Corporation
AN 117: Us ing Sel ectab l e I/O Standards In A PEX 20KE, APEX 20K C & MA X 7000B Devic es
Note:
(1) VREF spec ifies c enter po int of sw it ching rang e.
Board
Termination
Schemes
The various I/O standards supported by APEX 20KE and MAX 7000B
devices re quire specific terminati on scheme s to achieve t heir high spee ds.
Each I/O standard has an individual termination scheme. The diagram in
Figure 3 shows the series and parallel termination resistors that are used
with the I/O sta nd ard s.
Fig ure 3. Boa r d Terminat i on Diag r am
The LVDS I/O stan dard require s a termination resisto r between the
si gnals at th e receiv ing de vice as sh own i n Figure 4. The termination
resistor should match the differential load impedance of the bus ranging
from 90 to 110 ¾, but typically 100 ¾.
Table 17. CTT I/O Specifications
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O supply vo lta ge 3.0 3.3 3.6 V
VTT/VREF (1) Term inat ion and
reference v olt age 1.35 1.5 1.65 V
VIH High-level input voltage VREF + 0.2 V
VIL Low-level input voltage VREF – 0.2 V
III nput pin leak age c urrent 0 < VIN < VCCIO –10 10 µA
VOH High-level output voltage IOH = –8 mA VREF + 0.4 V
VOL Low-level output voltage IOL = 8 mA VREF – 0.4 V
IOOutput leak age current
(when output is high Z)GND ð VOUT ð
VCCIO
–10 10 µA
Driving Device Receiving Device
VTT
RS
RT1
VREF
VTT
RT2
Z = 50
Altera Corporation 15
AN 117: Usin g Se le ctab l e I/O Stan d ar d s In APE X 20K E, APEX 20KC & MA X 7000B Devices
Figure 4. LVDS Board Terminati on at the Receiv er
Table 18 shows the board termination values and reference voltages that
eac h APEX 20KE I/O sta ndar d uses .
MAX 7000B
Software
Support
Softw are Support fo r MAX 7000B Devices
Selectable I/O standards are programmable on a per pin basis for both
APEX 20KE and MAX 7000B devices. APEX 20KE devices have a total of
10 I/O block s, incl uding tw o LVDS b locks. T he LVDS I/O blocks can a lso
be used for any of the other I/O standards when not used for LVDS.
MAX 7000B devices have two I/O blocks; I/O standards supported by
MAX 700 0B de vice s ar e sho wn i n Table 1 on page 6. The QuartusTM II and
MAX+PLUS® II softw are tools define the I/O sta ndard used for each I/O
block.
Software support for MAX 7000B devices selectable I/O standards is
provided in the MAX+PLUS II software version 9.4 and higher. This
document explains the Quartus II software’s support for selectable I/O
standards. For information on how the MAX+PLUS II software supports
these standards, contact Altera Applications.
T
ransmitting
Device Receivin
g
Device
+
–
100 Ω
Table 18. Board Termination Values
I/O Standard Output Driver RS (¾) RT1 (¾) RT2 (¾) VREF (V) VTT (V)
GTL+ Open-drain – 50 50 1.0 1.5
SSTL -2 Cla ss I Push-pull 25 – 5 0 1.25 1.2 5
SSTL -2 Cla ss II Push-pull 25 50 5 0 1.25 1.25
SSTL -3 Cla ss I Push-pull 25 – 5 0 1.5 1. 5
SSTL -3 Cla ss II Push-pull 25 50 50 1.5 1.5
HSTL Cl as s I Push-pull – – 50 0.75 0.75
AGP Push-pull – – – 1.32 –
CTT Push-pull – – 50 1.5 1.5
16 Altera Corporation
AN 117: Us ing Sel ectab l e I/O Standards In A PEX 20KE, APEX 20K C & MA X 7000B Devic es
A PEX 20K
Family I/O
Standard
Software
Support
This section shows how to implement and view the selectable I/O
standards for the APEX 20K family in the Quartus II software and gives
placement and assignment guidelines. The following topics will be
discussed:
■Device and Pin Options dialog box
■Pin Assignments dialog box
■Representation of I/O banks and I/O standards in the floorplan
editor
■Automatic place ment & verif icati on of sele ctab le I/O standar ds wit h
the Quartus II software
■Guidelines for selectable I/O standards
■I/O and VREF pin placement guidelines
Device & Pin Options Dialog Box
The Voltage tab in th e De vic e & Pin Options dialog box (Compiler
Settings dialog box) contains a Default I/O Standa r d drop-down menu,
which is used to set the default I/O standard for a device. All I/O pins
without a specific I/O standard assignment will default to the I/O
standard specified in this drop-down menu. The drop-down menu has
the following options for APEX 20KE devices:
■LVTTL (default setting)
■LVCMOS
■2.5 V
■1.8 V
■PCI
■PCI-X (supported in a future version of the Quartus II software)
■LVDS
■LVPECL (supported in a future version of the Quartus II software)
■GTL+
■SSTL-2 Class I & II
■SSTL-3 Class I & II
■HSTL Class I (supported in a future version)
■AGP
■CTT
The options available for APEX 20K devices in the drop-down menu are
as follows:
■LVTTL
■LVCMOS (default setting)
■3.3-V PCI
■2.5 V
■1.8 V
Altera Corporation 17
AN 117: Usin g Se le ctab l e I/O Stan d ar d s In APE X 20K E, APEX 20KC & MA X 7000B Devices
Figure 5 shows t he D evice & Pin Options dialog box (Compiler Settings
dialog box) when targeting an APEX 20KE device.
Figure 5. Device & P i n Options D ialog Box for APEX 20KE De vi ces
Pin Assignments Dialog Box
In the Pin As si g nme nts dia log box, desig ners ca n make pin as signme nts,
specify I/O standar ds, VREF assignments, and view the se ttings made to
each pin .
18 Altera Corporation
AN 117: Us ing Sel ectab l e I/O Standards In A PEX 20KE, APEX 20K C & MA X 7000B Devic es
Figure 6 shows the Pin Assignments dialog box. The Number column
corresponds with the pin number on the specified package. The Name
colu m n c o nta i ns the u s er - sp ecified pin name in th e d es i gn . T he r e ar e two
relevant colu mns to n ote : I/O Ban k and I/O Standard . The Type c olumn
in the Availab le Pins & Existin g Assignments list box displays the
following pin types: Row I/O, Column I/O, VREF, Reserved, and
dual-purpose pin names. The list box is sortable on any column by
clicking on the column heading .
There are drop-down menus for making I/O standard and reserved pin
assignments on a pin-by-pin basis. VREF pins are assigned the same way
as reserved pins. To select the I/O standard for I/O and VREF pins, ch oose
an I /O st anda rd f rom th e I/O standard drop- down m enu. To a ssign a pin
to be a VREF, enter a pin name (reserve pin names are not declared in the
design file), check the Reserve pin box, and select reserve as VREF from the
drop-d own m enu .
Figure 6. Pin Assignments Dialog Box
Follow the ste ps below to make pin assig nments, designate I/O stan dard
types, and reserve pins. Designers should reserve I/O pins that may be
need ed in th e futu r e .
Altera Corporation 19
AN 117: Usin g Se le ctab l e I/O Stan d ar d s In APE X 20K E, APEX 20KC & MA X 7000B Devices
1. If you have not already done so, open or create the project that you
want to mod ify.
2. Choose Compiler Settings (Processing menu).
3. Click the Chips & Devices tab.
4. Sele ct the target devi ce in the Available devices list.
5. Click Assi gn Pins.
6. In the Pin Assignments dialog box, to show the pins for which you
cannot assign a node name in the Available pin s & existing
assignments list, select Show no con nect pins.
7. In the Available pins & existing assignments list, select the pin
number for the pin to which you want to assign, change, or delete a
node name assignment.
8. To delete the node name assignment from the pin, under
Assignment, click Delete.
9. To assign a new node name to the pin, or change the existing node
name assignment for the pin , under Assignment, type a node name
in the Pin name box or Copy the node name to the Pin Assignments
dialog box with the Node Finder.
10. If you added or changed the node name assignment for the pin and
you want to assign an I/O Standard to the pin, under Assignment,
select a standard from the I/O Standa rd list.
11. If you added or changed the node name assignment or I/O standard
and you wan t to reserve the pi n for fu ture use, under Assignment,
tur n on Reserve pin (even if it does not exist in the design file), and
select As input tri-stated, As output driving ground, As output
driving an unspecified signal, or As VREF from the list.
12. To save a new assignment and add the assignment to the Available
pins & existing assignments list, under Assignment, click Add.
13. To save the changed assignment and add the assignment to the
Available pins & existing assignments list, under Assignment,
click Change.
14. Repeat steps 7 to 13 for each additi onal assignment you want to
make, change, or delete.
15. Click OK.
20 Altera Corporation
AN 117: Us ing Sel ectab l e I/O Standards In A PEX 20KE, APEX 20K C & MA X 7000B Devic es
Representation of I/O Banks & Standards in the Floorplan Editor
The Floorplan Editor supports many features in APEX 20KE devices,
including multiple I/O standards, PLLs, and the LVDS transmitter and
receiver block.
The Floo rplan E ditor s hows me mbe rship in I/O b anks by using a uni que
backgro und fill c olor arou nd each pin for eac h I /O bank . In a ddi tion, the
bank number is shown. The Floorplan editor has two package views
(Package Top and Package Bottom) and three internal views (Interior
MegaLABTM, Interior LABs and Interior Cells). In the package views the
I/O bank number is labeled above the pin for pin-grid array (PGA) and
BGA packages, or on the inside of the device for quad flat pack (QFP)
packages. In the interior views, the I/O is outside the package as a
background around the pin name.
Only I/O and VCCIO pins ha ve the colored ba ckground; GNDINT, GNDIO,
and VCCINT pins do not, as they are not specific to a particular I/O bank.
Figure 7 shows the coloring in the Floorplan Editor for the EP20K600E
device (1,020-pin FineLine BGA device package) in package view.
Figure 7. Pa ckage View w ith Show I/O Banks On
Altera Corporation 21
AN 117: Usin g Se le ctab l e I/O Stan d ar d s In APE X 20K E, APEX 20KC & MA X 7000B Devices
Under the View pull-down menu in the Floorplan Editor, the Show I/ O
Banks option controls and displays the I/O bank colors. This command
also turns on the display of both the I/O bank colors and bank numbers
in the three interior views.
The Floorplan Editor Color Legend, l ocat ed under the V iew pu ll-down
menu, has an entry for each I/O bank color, as shown in Figure 8. The
output clock and feedback pins for PLL 1 and PLL2 reside in I/O Bank 9
and I /O Bank 10 and ca n suppor t any of the I/ O stand ards sup ported for
APEX 20KE devices.
Figure 8. Pin Color Legend Window for the Floorplan Editor
Figure 9 shows a portion of the package view of two EP20K100E device
I/O B ank s of a 24 0-pi n plastic quad flat pack (PQFP) pa cka ge in the
Floorp lan Editor.
In the PQFP packages, the eight I/O banks have been merged into
4 merged I/O banks. The VCCIO planes on merged I/O banks are
internally connected in the PQFP packages. The naming convention for
mer ged I/O b anks lists t he real I/O ba nk that the pin belo ngs to, and the n
lists the I/O bank with which it shares VCCIO. The I/O bank and Bank6
(Bank7) share the VCCIO with Bank7 (and Ban k6), but has a diff erent VREF
bus. This allows Bank6 (and Bank7) to be used for one voltage-referenced
I/O standard and Bank7 (and Bank6) for another because they have
separate VREF buses, as long as those two standards use the same VCC
leve l. For exam ple, Bank 6 (and Bank7) ca n implem ent GTL+ wh ile Bank7
(and Bank6) implements SSTL-3 Class I.
22 Altera Corporation
AN 117: Us ing Sel ectab l e I/O Standards In A PEX 20KE, APEX 20K C & MA X 7000B Devic es
Figure 9. Top View of t he 240-Pin PQFP Package
Figure 10 shows the internal cells view of the APEX 20KE device’s PLL
suppor t. T he d iam on d ne xt to the d e di cat ed clocks ind ica te s that the PL L
is used.
Altera Corporation 23
AN 117: Usin g Se le ctab l e I/O Stan d ar d s In APE X 20K E, APEX 20KC & MA X 7000B Devices
Figure 10. View of In tern al Cells in Floorplan Edito r
The dedi ca ted clock pi ns ( CLK1p, CLK2p, CLK3p, CLK4p) support LVDS
and have optional dual-pu rpose ne gative po larity pins as soci ated with
them. The PLL feedb ack pi ns (CLKLK_FB1p, CLKLK_FB2p) and the PLL
output pins (CLKLK_OUT1p, CLKLK_OUT2p) also support LVDS
following the same convention as the dedicated clock pins.
Figure 11 shows the LVDS receiver in the Floorplan Editor. The receiver
data channel, repr e sented by LVDSRX01p and LVDSRX01n, feeds the
dedicated serial-to-parallel converter. The LVDS clock (LVDSRXINCLK1p,
LVDSINCLK1n) clocks the serial-to-parallel converter. The
ser ial -to-p aral lel c onve rte r is sh own by th e fil led recta ng le ad jacent to t he
IOE register assoc iated wi th each positive polari ty LVDS da ta a nd clock
pin.
24 Altera Corporation
AN 117: Us ing Sel ectab l e I/O Standards In A PEX 20KE, APEX 20K C & MA X 7000B Devic es
Figure 11. Internal Cells View of LVDS Receiver
Guidel ines for Se lec table I/O Sta ndards
The following guidelines should be used when designing for the
selectable I/O standards in APEX 20KE devices. The guidelines define
which st anda rds are compatib le based on input, ou tput, and bidir ection al
types within an I/O bank.
■No two input pins can be placed in the same I/O bank if their I/O
standa rds require a different VREF voltage. However,
non-voltage-referenced standards can coexist with
voltage-referenced standards; e.g., one bank can support GTL+ and
LVTTL. Fo r PQFP pac kag es, the tw o me rge d I/O ba nk s st ill s upport
separ ate VREF inputs for each bank. For example, if Bank1 and Bank8
are merged together, bank 1 can support GTL+ while Bank8 can
support SSTL-3.
■No two push-pull standard output pins can be placed in the same I/O
bank if they require a different VCCIO voltage level. All output pins
have the same VCCIO level for merged I/O banks in the PQFP
packages. GT L+ is an open-drain I/ O standard and the r efore can be
assigned to I/O banks with a 2.5-V or 3.3-V VCCIO level.
Altera Corporation 25
AN 117: Usin g Se le ctab l e I/O Stan d ar d s In APE X 20K E, APEX 20KC & MA X 7000B Devices
■The clamp diode affects input tolerance. When the PCI clamp diode
is turned on, an I/O pin is clamped to VCCIO. For exam ple, a 2.5-V
VCCIO bank without the clamp diode is tolerant to 3.3-V inputs.
Howe v er, wh en the cla mp is tur ne d on, th e 2.5-V VCCIO bank is not
3.3-V toler ant . An LVTTL input that does not have its clamp diode
turned on can be pl aced in a bank that has a 2.5-V VCCIO level.
■Bidirectional pins have to satisfy both input and output guidelines.
■All output driv ers betw ee n two GNDIO pins should not sink more
current than 273 mA in total. Pins using the 1.8-V standard are not
current limited. The current requirement for I/O standards with
3.3-V and 2.5-V VCCIO leve ls a re de fine d as f ol lo ws :
–For VCCIO = 3.3 V,
[(# of GTL+ × 36) + (# of LVTTL × ILVTTL) + (# of PCI × 1.5) + (#
of LVCMOS × ILVCMOS) + (# of SSTL-3 class I × 8) + (SS TL - 3
class II × 16) + (# of LVDS × 4.5) + (# of AGP × 1. 5) + (# of CT T ×
8) ] mA ð 273 mA
–Where I
LVTTL (4-mA default value) and I LVCMOS (0.1 mA default
value) are the current sink on the LVTTL and LVCMOS pins,
respectively. If your system requires higher ICC for LVTTL or
LVCMOS pins (for example, due to termination) then adjust the
equation acc ord ingl y.
–For VCCIO = 2.5 V,
((# of 2.5V × 2) + (# of SSTL-2 class I × 7.6) + (# of SSTL -2 class II
× 15.2) mA ð 273 mA
– In practice, this rule applies only to SSTL-2 Class II, SSTL-3
Class II, GTL+, and LVCMOS and LVTTL pins whi ch can sink
more than 14 mA per output pin. For other standards, every pin
can be used without violating this requirement.
–The APEX 20K Programmable Logic Device Family Data Sheet
shows the relationship of I/O pins to GNDIO pins to enable
correct pin placement. This is also shown in the Quartus II
software’s Floorplan Editor and in Quartus II Help.
■When placing VREF pins, follow these guidelines. Output pins that
can switch while an input is using a VREF have to be placed a distance
of two pads away from the VREF pin, or a distance of one pad away
from the VREF pin if the pad between them is a po wer (VCC or GND)
pad. Figure 12 shows both ca se s. M ult iple VREF pins may be used in
an I/O bank of the same standards. Further VREF guideline s are
discusse d i n the “I/O & VRE F Placement Guidel ines” on page 27.
26 Altera Corporation
AN 117: Us ing Sel ectab l e I/O Standards In A PEX 20KE, APEX 20K C & MA X 7000B Devic es
Figu re 12. Examp l es of VREF Placement
Auto matic Place men t & Verific at ion of Selectable I/O Standard s
Wi th Q uar tus II Softwa re
The Quartus II software v e r ifies correct placement of all I/O an d VREF
pins, following the same rules outlined in the “Gui delin es for Selectable
I/O Stan dards” on page 24.
■Designers must assign VREF pin s fo r all volt age- ref erence d I /O p ins.
The Quartus software automatically places I/O pins of different
VREF standards without pin assignments in separate I/O banks.
■The Quartus software verifies that no two voltage-referenced I/O
pins requiring different VREF or LVDS pin levels are placed in one
bank.
■The Quartus software ensures that an I/O pin requiring a VREF pin
is no more than 16 pins from a VREF pin. All 16 voltage-referenced
I/O pins may be placed on only one s ide of the VREF pi n or stagg ered
on both sides of the VREF pin.
■The Quartus II software reports an error message if the curren t
limitation is exceede d between GNDIO pins. It uses the equations
documented in the “Guidelines for Selectable I/O Standards” on
page 24 .
■The Quartus II software ensures that no more than 16 voltage
referenced I/O standard pins are using a single VREF.
Max 8 I/P Max 8 I/P
Max 8 I/P
Power
Power
V
REF
V
REF
Max 8 I/P Max 8 I/P
V
REF
Max 8 I/P
O/P
O
ne V for 16 input pins
REF
M
ultiple V pins should be considered per I/O bank
REF
Altera Corporation 27
AN 117: Usin g Se le ctab l e I/O Stan d ar d s In APE X 20K E, APEX 20KC & MA X 7000B Devices
■The Quartus II software does not allow you to place an output pin
within two pins of a VREF if a power pin doe s no t se parate them. To
view pad orientation, use the Show Pads view in the Floorplan
Editor.
■The Quartus II software will reserve the unused LVDS channels in the
LVDS transmitter and receiver blocks when any of the LVDS
chann els a re being us ed. It will a lso reserve the two I/O p ins adjace nt
to the LVDS blocks that share a VCCIO pin w ith the LVDS blocks.
■The Quartus II software will not allow placement of non-LVDS
output pins in or within tw o I/O pins (with a common VCCIO pin) of
the LVDS blocks .
I/O & VREF Placement Guidelines
This section discusses VREF and I/O pin placeme nt gu idelin es when
designing with I/O buses. Each VREF pin can support up to eight
voltage-referenced input pins on each side, or 16 input pins in total, as
show n in Figure 13. The Q ua r tus I I sof tw are will gi ve an er ro r m e ssa ge if
a voltage-referenced input pin is placed more than 16 pads from a VREF
pin.
Figure 13. Ea ch VREF Ca n Suppor t 16 In put Pins
Output pins should be placed two or more pins away from VREF pins,
except wh en the VREF is next to a power pin. In that case the power pin
isolates the VREF pin from the switching output. Output pins can be
placed on the other side of the power pin, as shown in Figure 14.
V
REF
28 Altera Corporation
AN 117: Us ing Sel ectab l e I/O Standards In A PEX 20KE, APEX 20K C & MA X 7000B Devic es
Fig ur e 14 . VRE F Pin Pl acem en t Gu i de li n es
Voltag e-ref erence d bidirec tional bu ses that sha re a single tri-sta te control
si gnal can be plac ed around the VREF pin, as shown in Figure 15. This
works because the bus is only operating in one direction at a time. When
the bidirectional pins are driving out, no inputs are using the VREF pin.
When the bidi r e ctional p ins are accepti ng in put si gnals, th ere are no
output pins that would interfere with the input pins’ ability to use the
VREF level.
Figure 15. Placement of Bidirectional Buses with Single OE Control
Output pins can be placed outside the bus without affecting the use of
VREF in th e bidirection al bus , as shown in Figure 16. Fu rthe rm o re , a n
unrelated output pin may be placed within a voltage-referenced
bidirectional bus if the output pin is more than two pads from the VREF
pin or separated by a power pin.
VREF
Inputs Input
s
or
Oupu
ts
VCC or GND pad
VREF
O
K
O
K
V
REF
V
REF
Altera Corporation 29
AN 117: Usin g Se le ctab l e I/O Stan d ar d s In APE X 20K E, APEX 20KC & MA X 7000B Devices
Figure 16. Pla cement of Output Pins Outsi de th e Bidirec t i onal Buses
Output pins can also be placed inside the bus if they are more than two
pins away from the VREF pin, as shown in Figure 17.
Figure 17. Output Pin Placement in a Bidirectional Bus
These outputs affect the inputs & bidirectional pins
Not
OK
O
K
VREF
VREF
VREF
VREF
This output affects input and bidirectional pins
when it is within two pins of the VREF pin unless
separated by a power or GND
Place outputs two or more pins from VREF
Not O
K
OK
30 Altera Corporation
AN 117: Us ing Sel ectab l e I/O Standards In A PEX 20KE, APEX 20K C & MA X 7000B Devic es
Conclusion The a dv anced pr og r am mab l e I /O fe atures and standa r ds sim plify b oar d
design by minimizing the number of devices used to interface with
memory, microprocessors, and backplanes. The APEX 20KE devices,
which are 64-bit, 66-MHz PCI compliant, support 16 programmable I/O
standards, allowing customization for a wide variety of applications.
Input, output, and bidirectional pins of different I/O standards can be
intermix ed with I/O banks by followi ng the guidelin es in this document.
APEX 20KE devices also offer increased I/O performance with new
standards and features like LVDS (840 Mbps data transfer).
References ■Interface Standard for Nominal 3 V/3.3 V Supply Digital Integrated
Circuits, JESD8-A, Electronic Industries Association, June 1994.
■Stub-Series Terminated Logic for 3.3 Volts (SSTL-3), EIA/JESD8-8,
Electr onic Ind ustrie s Ass o cia tion , August 199 6.
■Stub-Series Terminated Logic for 2.5 Volts (SSTL-2), EIA/JESD8-9,
Electr onic Ind ustrie s Ass o cia tion , Septem ber 1998.
■Electrical Characteristics of Low Voltage Differential Signaling (LVDS)
Interface Circuits, ANS I/TIA/ EIA- 644, Ameri can N atio nal Sta ndar ds
Institute/Telecommunication Industry Association/Electronic
Industries Association.
■2.5 V ±0.2 V (Normal Range) and 1.7 V to 2.7 V (Wide Range) Power
Supply Voltage and Interface Standard for Nonterminated Digital
Integrated Circuit, EIA/JESD8-5, Electronic Industries Associ at i on,
Octob e r 19 95.
■1.8 V ±0.15 V (Normal Range) and 1.2 V to 1.95 V (Wide Range) Power
Supply Voltage and Interface Standard for Nonterminated Digital
Integrated Circuit, EIA/JESD8-7, Electronic Industries Associ at i on,
Februa r y 19 97.
■PCI Local Bus Specification, Revision 2.2, PCI Special Interest
Grou p, De cemb e r 19 98.
Revision
History
The information contained in Application Note 117 (Using Selectable
I/OSta ndards in APEX 20KE, APEX 20KC & MAX 7000B Devices) version
2.1 supersedes information published in previous versions. Application
Note 117 (Using Selectable I/OStan dards in APEX 20KE, APEX 20KC &
MAX 7000B Devices) version 2.1 contains the folllowing change: The title
has been changed throughout the document.
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ttp://www.altera.com
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AN 117: Using Sel ectable I/O Stan da rds I n A PEX 20KE, APE X 20K C & MAX 7000B De vi ces
31 Altera Corporation
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